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Fixed broken link to RISC-V documentation

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Sandra Polifroni
2024-09-03 17:09:46 -04:00
parent 73d9fb01ab
commit 0c19e2da62
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RELEASE.md
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@@ -989,7 +989,7 @@ on GitHub for more information.
* `Zihintntl` extension version was upgraded to 1.0 and is no longer experimental.
* Intrinsics were added for `Zk*`, `Zbb`, and `Zbc`. See
[Scalar Bit Manipulation Extension Intrinsics](https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#scalar-bit-manipulation-extension-intrinsics) in the RISC-V C API specification.
[Scalar Bit Manipulation Extension Intrinsics](https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#scalar-bit-manipulation-extension-intrinsics) in the RISC-V C API specification.
* Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64.