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https://github.com/ROCm/ROCm.git
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The initial code merge of Nvidia Hopper features support. Please be aware that the code merge is not finished yet and the trouble-shooting is still ongoing. The new hardware features (GMMA, TMA, STMATRIX etc.) and automatic warp-specialization are experimental for now and turned off by default. It is recommended for a trial when version 3.0 is released. The work is contributed by: ben-zhang-609, bealwang, donproc, qliu93, jsh20, allatit23, LyricZhao, ivanyinwz, goostavz & yangjunpro from Nvidia, in cooperation with: ptillet, Jokeren, ThomasRaoux & zahimoud from OpenAI. Co-authored-by: Goostav Zhu <gzhu@nvidia.com>
218 lines
8.9 KiB
C++
218 lines
8.9 KiB
C++
/*
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* Copyright (c) 2023 NVIDIA Corporation & Affiliates. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "BarrierOpToLLVM.h"
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using namespace mlir;
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using namespace mlir::triton;
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// --------------------------------------------------------------------------
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// -- MBarrier related Ops lowering, to be moved to a seperate file ---------
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// --------------------------------------------------------------------------
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struct AllocMBarrierOpConversion : public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::AllocMBarrierOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::AllocMBarrierOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::AllocMBarrierOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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Value smemBase = getSharedMemoryBase(loc, rewriter, op.getResult());
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auto resultTy = op.getType();
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auto resultTensorTy = resultTy.dyn_cast<RankedTensorType>();
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Type elemPtrTy;
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if (resultTensorTy) {
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auto llvmElemTy =
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getTypeConverter()->convertType(resultTensorTy.getElementType());
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elemPtrTy = ptr_ty(llvmElemTy, 3);
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} else {
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elemPtrTy = getTypeConverter()->convertType(resultTy);
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}
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smemBase = bitcast(smemBase, elemPtrTy);
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auto threadId = getThreadId(rewriter, loc);
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auto pred = icmp_eq(threadId, i32_val(0));
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int numMBarriers = 1;
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if (resultTensorTy) {
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assert(resultTensorTy.getRank() == 1 &&
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"unexpected rank for AllocMBarrierOp");
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numMBarriers = resultTensorTy.getShape()[0];
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}
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for (int i = 0; i < numMBarriers; ++i) {
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Value smem = smemBase;
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if (i > 0) {
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smem = gep(elemPtrTy, smem, i32_val(i));
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}
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rewriter.create<triton::nvgpu::MBarrierInitOp>(loc, smem, pred,
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op.getCount());
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}
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if (resultTensorTy) {
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auto smemObj = SharedMemoryObject(smemBase, resultTensorTy.getShape(),
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{0}, loc, rewriter);
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auto retVal = getStructFromSharedMemoryObject(loc, smemObj, rewriter);
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rewriter.replaceOp(op, retVal);
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} else {
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rewriter.replaceOp(op, smemBase);
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}
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return success();
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}
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};
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struct MBarrierArriveOpConversion : public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::MBarrierArriveOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::MBarrierArriveOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::MBarrierArriveOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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auto mbarrier = adaptor.getMbarrier();
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bool trackAsyncOp = op.getTrackAsyncOp();
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triton::nvgpu::MBarriveType type = triton::nvgpu::MBarriveType::normal;
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uint32_t txCount = op.getTxCount();
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auto remoteCtaId = adaptor.getRemoteCtaId();
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if (trackAsyncOp) {
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type = triton::nvgpu::MBarriveType::cp_async;
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} else if (remoteCtaId) {
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assert(txCount == 0 &&
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"remote arrive of transaction mbarrier is not implemented yet");
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type = triton::nvgpu::MBarriveType::remote;
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} else if (txCount > 0) {
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type = triton::nvgpu::MBarriveType::expect_tx;
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}
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Value pred = adaptor.getPred();
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if (pred == nullptr) {
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pred = int_val(/*width*/ 1, 1);
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}
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rewriter.replaceOpWithNewOp<triton::nvgpu::MBarrierArriveOp>(
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op, mbarrier, pred, remoteCtaId, type, txCount);
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return success();
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}
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};
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struct MBarrierWaitOpConversion : public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::MBarrierWaitOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::MBarrierWaitOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::MBarrierWaitOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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rewriter.replaceOpWithNewOp<triton::nvgpu::MBarrierWaitOp>(
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op, adaptor.getMbarrier(), adaptor.getPhase());
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return success();
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}
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};
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struct ExtractMBarrierOpConversion
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: public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::ExtractMBarrierOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::ExtractMBarrierOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::ExtractMBarrierOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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auto elemTy =
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op.getTensor().getType().cast<RankedTensorType>().getElementType();
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auto tensorStruct = adaptor.getTensor();
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auto index = adaptor.getIndex();
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auto ptrTy =
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LLVM::LLVMPointerType::get(getTypeConverter()->convertType(elemTy), 3);
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auto basePtr =
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extract_val(ptrTy, tensorStruct, rewriter.getDenseI64ArrayAttr(0));
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Value result = gep(ptrTy, basePtr, index);
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rewriter.replaceOp(op, result);
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return success();
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}
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};
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struct NamedBarrierArriveOpConversion
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: public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::NamedBarrierArriveOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::NamedBarrierArriveOp>::
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ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::NamedBarrierArriveOp op,
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OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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rewriter.replaceOpWithNewOp<triton::nvgpu::NamedBarrierArriveOp>(
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op, adaptor.getBar(), adaptor.getNumThreads());
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return success();
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}
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};
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struct NamedBarrierWaitOpConversion
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: public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::NamedBarrierWaitOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::NamedBarrierWaitOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::NamedBarrierWaitOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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rewriter.replaceOpWithNewOp<triton::nvgpu::NamedBarrierWaitOp>(
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op, adaptor.getBar(), adaptor.getNumThreads());
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return success();
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}
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};
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struct FenceAsyncSharedOpConversion
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: public ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::FenceAsyncSharedOp> {
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using ConvertTritonGPUOpToLLVMPattern<
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triton::nvidia_gpu::FenceAsyncSharedOp>::ConvertTritonGPUOpToLLVMPattern;
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LogicalResult
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matchAndRewrite(triton::nvidia_gpu::FenceAsyncSharedOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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rewriter.replaceOpWithNewOp<triton::nvgpu::FenceAsyncSharedOp>(
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op, adaptor.getBCluster());
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return success();
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}
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};
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void populateBarrierOpToLLVMPatterns(
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TritonGPUToLLVMTypeConverter &typeConverter, RewritePatternSet &patterns,
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int numWarps, ModuleAxisInfoAnalysis &axisInfoAnalysis,
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ModuleAllocation &allocation, PatternBenefit benefit) {
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patterns.add<AllocMBarrierOpConversion>(typeConverter, allocation, benefit);
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patterns.add<MBarrierArriveOpConversion>(typeConverter, allocation, benefit);
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patterns.add<MBarrierWaitOpConversion>(typeConverter, allocation, benefit);
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patterns.add<ExtractMBarrierOpConversion>(typeConverter, allocation, benefit);
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patterns.add<NamedBarrierArriveOpConversion>(typeConverter, allocation,
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benefit);
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patterns.add<NamedBarrierWaitOpConversion>(typeConverter, allocation,
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benefit);
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patterns.add<FenceAsyncSharedOpConversion>(typeConverter, allocation,
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benefit);
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}
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