Michael Melesse 6efc013e46 ROCM IFU: fix AtomicCASOpConversion segfault

2023-12-12 17:40:31 -06:00

..

Analysis

[BACKEND] Remove ttg.cmp and ttg.select and replace by arith op (#2526)

2023-10-23 19:35:46 -07:00

Conversion

Merge branch 'triton-mlir' into ifu-231117

2023-12-12 14:24:11 -06:00

lib

upgrade llvm to b1115f8c (NFC) (#2403)

2023-10-16 16:38:49 -07:00

LLVMIR

[BACKEND] Add LLVM pre-processing pass to break struct types (#2285)

2023-09-13 10:03:29 -07:00

NVGPU

upgrade llvm to b1115f8c (NFC) (#2403)

2023-10-16 16:38:49 -07:00

Triton

[BACKEND] Remove ttg.cmp and ttg.select and replace by arith op (#2526)

2023-10-23 19:35:46 -07:00

TritonGPU

ROCM IFU: fix AtomicCASOpConversion segfault

2023-12-12 17:40:31 -06:00

TritonNvidiaGPU

[FRONTEND][BACKEND] dd memory synchronization scope parameter to atomic ops. (#2562)

2023-10-30 19:18:27 -07:00

CMakeLists.txt

[TESTS] Now using downloaded FileCheck directly without copying it (#1293)

2023-03-07 09:11:08 -08:00

lit.cfg.py

Reformat Python code with yapf. (#2589)

2023-11-02 20:44:17 -07:00

lit.site.cfg.py.in

Merge triton-mlir branch - Complete rewrite of the backend from scratch (#1004)

2022-12-21 01:30:50 -08:00