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ROCm/docs/reference/gpu-arch-specs.rst
Sam Wu a3a6c17b3d Merge roc-6.1.x into docs/6.1.0 (#3055)
* update manifest file for ROCm6.1 (#3024)

Co-authored-by: Wang, Yanyao <yanyao.wang@amd.com>

* Add ROCm version 6.1.0 to version list (#3023) (#3025)

* Merge develop into roc-6.1.x (#3048)

* Add ROCm version 6.1.0 to version list (#3023)

* Update CHANGELOG.md

Added GitHub links to Changelog

* Update CHANGELOG.md

* Update manifest for ROCm 6.1.0 (#3022)

* Reorganize default.xml by group and alphabetically

* Add rocDecode to default.xml

* Add rocDecode to included names in tag script

* update tag to 6.1.0

---------

Co-authored-by: Young Hui - AMD <145490163+yhuiYH@users.noreply.github.com>

* Update CHANGELOG.md

Updated ROCm Compiler with fixed issue

* docs(tools/autotag/README.md): Add additional note to avoid duplicating data in changelog template (#3018)

* Bump rocm-docs-core from 0.38.1 to 1.0.0 in /docs/sphinx

Bumps [rocm-docs-core](https://github.com/RadeonOpenCompute/rocm-docs-core) from 0.38.1 to 1.0.0.
- [Release notes](https://github.com/RadeonOpenCompute/rocm-docs-core/releases)
- [Changelog](https://github.com/ROCm/rocm-docs-core/blob/develop/CHANGELOG.md)
- [Commits](https://github.com/RadeonOpenCompute/rocm-docs-core/compare/v0.38.1...v1.0.0)

---
updated-dependencies:
- dependency-name: rocm-docs-core
  dependency-type: direct:production
  update-type: version-update:semver-major
...

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* Use Ubuntu 22.04 and Python 3.10 in RTD config

* Update README.md (#3043)

* Update README.md

Fix rocSPARSE build link

* Update link to just general page, instead of anchor

* Add 'JAX for ROCm' link to index.md (#3034)

* Add JAX for ROCm link to index.md

* Reorder third-party libraries installation guides in index

* Update links to rocAL component (#3033)

* Update links to rocAL component

* Change absolute rocm docs links to relative

* Update compatibility/precision-support links (#3030)

* Change links to component data type support pages from absolute to relative

* Fix rocPRIM data type support links

* Empty commit to trigger demo rebuild.

* Update excluded and included projects

* Separate templates into a module; Fix MIVisionX template

* Add hipfort changelog processor

* Add rpp custom processor

* Add custom processor for rvs

* update the code-owner list (#3046)

* Update default.xml (#3038)

* Remove HIPCC from default.xml

HIPCC moved into llvm-project

* Remove ROCm-Device-Libs from default.xml

ROCm-Device-Libs was moved into llvm-project

* Remove ROCm-CompilerSupport from default.xml

ROCm-CompilerSupport was moved into llvm-project

* Add rocprofiler-register to default.xml

Added in 6.1 manifest

* Apply mathlibs group to projects in manifest

* Bump rocm-docs-core from 0.38.1 to 1.0.0 in /docs/sphinx (#3047)

* Bump rocm-docs-core from 0.38.1 to 1.0.0 in /docs/sphinx

Bumps [rocm-docs-core](https://github.com/RadeonOpenCompute/rocm-docs-core) from 0.38.1 to 1.0.0.
- [Release notes](https://github.com/RadeonOpenCompute/rocm-docs-core/releases)
- [Changelog](https://github.com/ROCm/rocm-docs-core/blob/develop/CHANGELOG.md)
- [Commits](https://github.com/RadeonOpenCompute/rocm-docs-core/compare/v0.38.1...v1.0.0)

---
updated-dependencies:
- dependency-name: rocm-docs-core
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>

* Set Ubuntu 22.04 and Python 3.10 in ReadtheDocs config

---------

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Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Co-authored-by: Sam Wu <22262939+samjwu@users.noreply.github.com>

* Add 6.1.0.md template

* Add AMD SMI to 6.1.0 template

* Add ROCm Compiler to 6.1.0 template

* Add RDC to 6.1.0 template

* Add ROCgdb to 6.1.0 template

* Add ROCm SMI to 6.1.0 template

* Add ROCProfiler to 6.1.0 template

* Add MI200 SR-IOV known issue to 6.1.0 template

* Add MI300 RAS fixed defect to 6.1.0 template

* docs(6.1.0.md): Add more changelog notes for 6.1.0

* Update 6.1.0.md

Added links to GitHub for known issues and ROCm Compiler fixed defect

* Test autotag script

* Add ck template

* Add HIPIFY to included names for tag script

* Remove rocprofiler from tag_script

* Remove RVS template

Determine cause of missing later

* Add HIPIFY to template for 6.1.0

* Add extra line to topp of template for formatting changelog

* Update 5.7.1.md

Fixing the broken link for rocBLAS programmer's guide in 5.7.1 Changelog.

* Regenerate changelog with new 5.7.1 link fix

* Add note for tag_script included_names

* Improve readability of GPU architecture hardware specs (#3009)

* move units of measurement to table headers

* add glossary explaining table headers

* add missed units and update h1

* toc listing to say indicate Accelerators & GPUs

* fix typo

* update meta description and keywords

* Update title in toc to fit in sidebar

* update title, toc, and filename

* Fix broken link to HIP programming guide

* Revert "update title, toc, and filename"

This reverts commit 6b9e687805.

* Revert glossary; slight fixes

* Change 'Pro' to 'PRO' for consistency

* Add references to programming and hardware architecture guides

* Change 'warp' to 'wavefront'

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Co-authored-by: amitkumar-amd <120512306+amitkumar-amd@users.noreply.github.com>

---------

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: Yanyao Wang <yanywang@amd.com>
Co-authored-by: Wang, Yanyao <yanyao.wang@amd.com>
Co-authored-by: Roopa Malavally <56051583+Rmalavally@users.noreply.github.com>
Co-authored-by: Young Hui - AMD <145490163+yhuiYH@users.noreply.github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
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2024-04-22 14:38:25 -06:00

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This file contains invisible Unicode characters
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.. meta::
:description: AMD Instinct™ accelerator, AMD Radeon PRO™, and AMD Radeon™ GPU architecture information
:keywords: Instinct, Radeon, accelerator, CDNA, GPU, architecture, VRAM, Compute Units, Cache, Registers, LDS, Register File
Accelerator and GPU hardware specifications
######################################################
The following tables provide an overview of the hardware specifications for AMD Instinct™ accelerators, and AMD Radeon™ PRO and Radeon™ GPUs.
.. tab-set::
.. tab-item:: AMD Instinct accelerators
.. list-table::
:header-rows: 1
:name: instinct-arch-spec-table
*
- Model
- Architecture
- LLVM target name
- VRAM (GiB)
- Compute Units
- Wavefront Size
- LDS (KiB)
- L3 Cache (MiB)
- L2 Cache (MiB)
- L1 Vector Cache (KiB)
- L1 Scalar Cache (KiB)
- L1 Instruction Cache (KiB)
- VGPR File (KiB)
- SGPR File (KiB)
*
- MI300X
- CDNA3
- gfx941 or gfx942
- 192
- 304
- 64
- 64
- 256
- 32
- 32
- 16 per 2 CUs
- 64 per 2 CUs
- 512
- 12.5
*
- MI300A
- CDNA3
- gfx940 or gfx942
- 128
- 228
- 64
- 64
- 256
- 24
- 32
- 16 per 2 CUs
- 64 per 2 CUs
- 512
- 12.5
*
- MI250X
- CDNA2
- gfx90a
- 128
- 220 (110 per GCD)
- 64
- 64
-
- 16 (8 per GCD)
- 16
- 16 per 2 CUs
- 32 per 2 CUs
- 512
- 12.5
*
- MI250
- CDNA2
- gfx90a
- 128
- 208
- 64
- 64
-
- 16 (8 per GCD)
- 16
- 16 per 2 CUs
- 32 per 2 CUs
- 512
- 12.5
*
- MI210
- CDNA2
- gfx90a
- 64
- 104
- 64
- 64
-
- 8
- 16
- 16 per 2 CUs
- 32 per 2 CUs
- 512
- 12.5
*
- MI100
- CDNA
- gfx908
- 32
- 120
- 64
- 64
-
- 8
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256 VGPR and 256 AccVGPR
- 12.5
*
- MI60
- GCN5.1
- gfx906
- 32
- 64
- 64
- 64
-
- 4
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
*
- MI50 (32GB)
- GCN5.1
- gfx906
- 32
- 60
- 64
- 64
-
- 4
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
*
- MI50 (16GB)
- GCN5.1
- gfx906
- 16
- 60
- 64
- 64
-
- 4
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
*
- MI25
- GCN5.0
- gfx900
- 16 
- 64
- 64
- 64 
-
- 4 
- 16 
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
*
- MI8
- GCN3.0
- gfx803
- 4
- 64
- 64
- 64
-
- 2
- 16
- 16 per 4 CUs
- 32 per 4 CUs
- 256
- 12.5
*
- MI6
- GCN4.0
- gfx803
- 16
- 36
- 64
- 64
-
- 2
- 16
- 16 per 4 CUs
- 32 per 4 CUs
- 256
- 12.5
.. tab-item:: AMD Radeon PRO GPUs
.. list-table::
:header-rows: 1
:name: radeon-pro-arch-spec-table
*
- Model
- Architecture
- LLVM target name
- VRAM (GiB)
- Compute Units
- Wavefront Size
- LDS (KiB)
- Infinity Cache (MiB)
- L2 Cache (MiB)
- Graphics L1 Cache (KiB)
- L0 Vector Cache (KiB)
- L0 Scalar Cache (KiB)
- L0 Instruction Cache (KiB)
- VGPR File (KiB)
- SGPR File (KiB)
*
- Radeon PRO W7900
- RDNA3
- gfx1100
- 48
- 96
- 32
- 128
- 96
- 6
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon PRO W7800
- RDNA3
- gfx1100
- 32
- 70
- 32
- 128
- 64
- 6
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon PRO W7700
- RDNA3
- gfx1101
- 16
- 48
- 32
- 128
- 64
- 4
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon PRO W6800
- RDNA2
- gfx1030
- 32
- 60
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon PRO W6600
- RDNA2
- gfx1032
- 8
- 28
- 32
- 128
- 32
- 2
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon PRO V620
- RDNA2
- gfx1030
- 32
- 72
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon Pro W5500
- RDNA
- gfx1012
- 8
- 22
- 32
- 128
-
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon Pro VII
- GCN5.1
- gfx906
- 16
- 60
- 64
- 64
-
- 4
-
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
.. tab-item:: AMD Radeon GPUs
.. list-table::
:header-rows: 1
:name: radeon-arch-spec-table
*
- Model
- Architecture
- LLVM target name
- VRAM (GiB)
- Compute Units
- Wavefront Size
- LDS (KiB)
- Infinity Cache (MiB)
- L2 Cache (MiB)
- Graphics L1 Cache (KiB)
- L0 Vector Cache (KiB)
- L0 Scalar Cache (KiB)
- L0 Instruction Cache (KiB)
- VGPR File (KiB)
- SGPR File (KiB)
*
- Radeon RX 7900 XTX
- RDNA3
- gfx1100
- 24
- 96
- 32
- 128
- 96
- 6
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon RX 7900 XT
- RDNA3
- gfx1100
- 20
- 84
- 32
- 128
- 80
- 6
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon RX 7900 GRE
- RDNA3
- gfx1100
- 16
- 80
- 32
- 128
- 64
- 6
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon RX 7800 XT
- RDNA3
- gfx1101
- 16
- 60
- 32
- 128
- 64
- 4
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon RX 7700 XT
- RDNA3
- gfx1101
- 12
- 54
- 32
- 128
- 48
- 4
- 256
- 32
- 16
- 32
- 384
- 20
*
- Radeon RX 7600
- RDNA3
- gfx1102
- 8
- 32
- 32
- 128
- 32
- 2
- 256
- 32
- 16
- 32
- 256
- 20
*
- Radeon RX 6950 XT
- RDNA2
- gfx1030
- 16
- 80
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6900 XT
- RDNA2
- gfx1030
- 16
- 80
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6800 XT
- RDNA2
- gfx1030
- 16
- 72
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6800
- RDNA2
- gfx1030
- 16
- 60
- 32
- 128
- 128
- 4
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6750 XT
- RDNA2
- gfx1031
- 12
- 40
- 32
- 128
- 96
- 3
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6700 XT
- RDNA2
- gfx1031
- 12
- 40
- 32
- 128
- 96
- 3
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6700
- RDNA2
- gfx1031
- 10
- 36
- 32
- 128
- 80
- 3
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6650 XT
- RDNA2
- gfx1032
- 8
- 32
- 32
- 128
- 32
- 2
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6600 XT
- RDNA2
- gfx1032
- 8
- 32
- 32
- 128
- 32
- 2
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon RX 6600
- RDNA2
- gfx1032
- 8
- 28
- 32
- 128
- 32
- 2
- 128
- 16
- 16
- 32
- 256
- 20
*
- Radeon VII
- GCN5.1
- gfx906
- 16
- 60
- 64
- 64 per CU
-
- 4
-
- 16
- 16 per 3 CUs
- 32 per 3 CUs
- 256
- 12.5
For more information on the terms used here, see the :ref:`specific documents and guides <gpu-arch-documentation>`, the :doc:`conceptual overview of the HIP programming model<hip:understand/programming_model>`, or the :doc:`HIP reference guide<hip:reference/programming_model>`.