Thomas Raoux cda298fae7 [Pipeliner] Allocate less shared memory when possible (#2466) ...

The pipeliner was overallocating shared memory for the inputs
for current schedule. This reduces the shared memory usage to only
what is needed.
Note that improving membar analysis could allow taking advantage of
allocating extra buffers to remove barriers.

2023-10-12 12:10:06 -07:00

..

Analysis

[OPTIMIZER] Calculate a proper divisibility for ExpandDims (#2397)

2023-09-27 23:10:01 -07:00

Conversion

[BACKEND] Allow reduce with sliced 3D layout as input (#2480)

2023-10-10 15:19:11 -07:00

lib

[BACKEND] Clean up code (#1768)

2023-06-12 17:40:33 -07:00

LLVMIR

[BACKEND] Add LLVM pre-processing pass to break struct types (#2285)

2023-09-13 10:03:29 -07:00

NVGPU

[BACKEND] Fix multiple bugs in WGMMA (#2457)

2023-10-06 17:59:28 -07:00

Triton

[TOOLS] Enable per-pass IR printing in triton-translate (#2449)

2023-10-05 13:23:46 -07:00

TritonGPU

[Pipeliner] Allocate less shared memory when possible (#2466)

2023-10-12 12:10:06 -07:00

TritonNvidiaGPU

[FRONTEND][BACKEND] Add flag to control accumulation for fp8 (#2300)

2023-09-15 18:42:54 -07:00

CMakeLists.txt

[TESTS] Now using downloaded FileCheck directly without copying it (#1293)

2023-03-07 09:11:08 -08:00

lit.cfg.py

[BACKEND] Add LLVM pre-processing pass to break struct types (#2285)

2023-09-13 10:03:29 -07:00

lit.site.cfg.py.in

Merge triton-mlir branch - Complete rewrite of the backend from scratch (#1004)

2022-12-21 01:30:50 -08:00