Alexander Efimov a944811b6d Replace inline assembly in commonShflSync with intrinsics (#418) ...

Inline assembly does not take into account instructions around,
and in general can not avoid data hazards.
Replacing inline asm with intrinsics solves this problem.
This particular code behaved incorrectly in one of mfma dot tests:

Code generated with help of inline assembly:

```
  v_mfma_f32_4x4x4f16 v[4:7], v[4:5], v[6:7], 0
  ds_swizzle_b32 v3, v4, offset:swizzle(SWAP:4)
```

Correct code generated with intrinsics:

```
  v_mfma_f32_4x4x4f16 v[4:7], v[4:5], v[6:7], 0
  s_nop 4
  ds_swizzle_b32 v3, v4, offset:swizzle(SWAP:4)
```

2023-12-11 16:41:39 +01:00

..

Analysis

upgrade llvm to b1115f8c (NFC) (#2403)

2023-10-16 16:38:49 -07:00

Conversion

Replace inline assembly in commonShflSync with intrinsics (#418)

2023-12-11 16:41:39 +01:00

lib

upgrade llvm to b1115f8c (NFC) (#2403)

2023-10-16 16:38:49 -07:00

LLVMIR

[BACKEND] Add LLVM pre-processing pass to break struct types (#2285)

2023-09-13 10:03:29 -07:00

NVGPU

upgrade llvm to b1115f8c (NFC) (#2403)

2023-10-16 16:38:49 -07:00

Triton

[TOOLS] Enable per-pass IR printing in triton-translate (#2449)

2023-10-05 13:23:46 -07:00

TritonGPU

Merge commit '721897fcc4f942aa97d2e9ba3787a5e213758177' into ifu-231108

2023-11-08 18:51:23 +00:00

TritonNvidiaGPU

[FRONTEND][BACKEND] Add flag to control accumulation for fp8 (#2300)

2023-09-15 18:42:54 -07:00

CMakeLists.txt

[TESTS] Now using downloaded FileCheck directly without copying it (#1293)

2023-03-07 09:11:08 -08:00

lit.cfg.py

[BACKEND] Add LLVM pre-processing pass to break struct types (#2285)

2023-09-13 10:03:29 -07:00

lit.site.cfg.py.in

Merge triton-mlir branch - Complete rewrite of the backend from scratch (#1004)

2022-12-21 01:30:50 -08:00