From 0982753437eaa0a1015e56cd4d8fdd16a1310d63 Mon Sep 17 00:00:00 2001
From: Sleigh-InSPECtor <sleighinspector@outlook.com>
Date: Mon, 20 May 2024 14:13:49 +0930
Subject: [PATCH] AArch32: fixed vmvn

* fixed incorrect shift offset (bytes given in place of bits) and double word order
---
 Ghidra/Processors/ARM/data/languages/ARMneon.sinc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
index a6b2e4e94c..888c5b91e4 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
@@ -4816,7 +4816,7 @@ vmlDmA: Dm_4^"["^thv_M5^"]"	is TMode=1 & thv_c2021=2 & Dm_4 & thv_M5											{
 	tmp2:8 = Qm(8);
 	tmp1 = ~ tmp1;
 	tmp2 = ~ tmp2;
-	Qd = (zext(tmp1) << 8) | zext(tmp2);
+	Qd = (zext(tmp2) << 64) | zext(tmp1);
 }
 
 define pcodeop FloatVectorNeg;