Instructions:
  SLL rd_ptr = 68, rs1_ptr = 40, rs2 = 8, rs2_as = 0

APC advantage:
  - Main columns: 53 -> 14 (3.79x reduction)
  - Bus interactions: 24 -> 10 (2.40x reduction)
  - Constraints: 76 -> 1 (76.00x reduction)

Symbolic machine using 14 unique main columns:
  from_state__timestamp_0
  reads_aux__0__base__prev_timestamp_0
  reads_aux__0__base__timestamp_lt_aux__lower_decomp__0_0
  writes_aux__base__prev_timestamp_0
  writes_aux__base__timestamp_lt_aux__lower_decomp__0_0
  writes_aux__prev_data__0_0
  writes_aux__prev_data__1_0
  writes_aux__prev_data__2_0
  writes_aux__prev_data__3_0
  a__1_0
  a__2_0
  a__3_0
  b__3_0
  is_valid

// Bus 0 (EXECUTION_BRIDGE):
mult=is_valid * -1, args=[0, from_state__timestamp_0]
mult=is_valid * 1, args=[4, from_state__timestamp_0 + 3]

// Bus 1 (MEMORY):
mult=is_valid * -1, args=[1, 40, a__1_0, a__2_0, a__3_0, b__3_0, reads_aux__0__base__prev_timestamp_0]
mult=is_valid * 1, args=[1, 40, a__1_0, a__2_0, a__3_0, b__3_0, from_state__timestamp_0]
mult=is_valid * -1, args=[1, 68, writes_aux__prev_data__0_0, writes_aux__prev_data__1_0, writes_aux__prev_data__2_0, writes_aux__prev_data__3_0, writes_aux__base__prev_timestamp_0]
mult=is_valid * 1, args=[1, 68, 0, a__1_0, a__2_0, a__3_0, from_state__timestamp_0 + 2]

// Bus 3 (VARIABLE_RANGE_CHECKER):
mult=is_valid * 1, args=[reads_aux__0__base__timestamp_lt_aux__lower_decomp__0_0, 17]
mult=is_valid * 1, args=[15360 * reads_aux__0__base__prev_timestamp_0 + 15360 * reads_aux__0__base__timestamp_lt_aux__lower_decomp__0_0 + 15360 - 15360 * from_state__timestamp_0, 12]
mult=is_valid * 1, args=[writes_aux__base__timestamp_lt_aux__lower_decomp__0_0, 17]
mult=is_valid * 1, args=[15360 * writes_aux__base__prev_timestamp_0 + 15360 * writes_aux__base__timestamp_lt_aux__lower_decomp__0_0 - (15360 * from_state__timestamp_0 + 15360), 12]

// Algebraic constraints:
is_valid * (is_valid - 1) = 0