From 135eda01d4f465f278ea68541e978e37973e6827 Mon Sep 17 00:00:00 2001
From: chriseth <chris@ethereum.org>
Date: Wed, 5 Apr 2023 16:29:51 +0200
Subject: [PATCH] Fix riscv asm parser.

---
 src/riscv/riscv_asm.lalrpop | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/riscv/riscv_asm.lalrpop b/src/riscv/riscv_asm.lalrpop
index cbc524210..d7e93b478 100644
--- a/src/riscv/riscv_asm.lalrpop
+++ b/src/riscv/riscv_asm.lalrpop
@@ -69,7 +69,7 @@ Register: Register = {
     r"s[2-9]" => Register(16 + <>[1..].parse::<u8>().unwrap()),
     r"s1[0-1]" => Register(16 + <>[1..].parse::<u8>().unwrap()),
     r"t[0-2]" => Register(5 + <>[1..].parse::<u8>().unwrap()),
-    r"t[3-6]" => Register(28 + <>[1..].parse::<u8>().unwrap()),
+    r"t[3-6]" => Register(25 + <>[1..].parse::<u8>().unwrap()),
 }
 
 OffsetRegister: Argument = {