From 6ca34e980dde5ef3462671ed71999bab91a8cf2c Mon Sep 17 00:00:00 2001
From: Lucas Clemente Vella <lucas.vella@ethereum.org>
Date: Fri, 12 May 2023 11:42:38 +0100
Subject: [PATCH] Fixed a couple of signed instructions bugs.

---
 riscv/src/compiler.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv/src/compiler.rs b/riscv/src/compiler.rs
index 0410819d8..477ec5ea7 100644
--- a/riscv/src/compiler.rs
+++ b/riscv/src/compiler.rs
@@ -463,7 +463,7 @@ pil{
     { Y_7bit } in { seven_bit };
 }
 
-// Input is a 32 but unsined number (0 <= Y < 2**32) interpreted as a two's complement numbers.
+// Input is a 32 but unsigned number (0 <= Y < 2**32) interpreted as a two's complement numbers.
 // Returns a signed number (-2**31 <= X < 2**31).
 instr to_signed Y -> X {
     // wrap_bit is used as sign_bit here.
@@ -780,7 +780,7 @@ fn process_instruction(instr: &str, args: &[Argument]) -> Vec<String> {
             let (rd, rs, imm) = rri(args);
             vec![
                 format!("tmp1 <=X= to_signed({rs});"),
-                format!("{rd} <=Y= is_positive({imm} - tmp1);"),
+                format!("{rd} <=Y= is_positive({} - tmp1);", imm as i32),
             ]
         }
         "sltiu" => {
@@ -810,7 +810,7 @@ fn process_instruction(instr: &str, args: &[Argument]) -> Vec<String> {
             let (r1, label) = rl(args);
             vec![
                 format!("tmp1 <=X= to_signed({r1});"),
-                format!("branch_if_positive {r1} + 1, {label};"),
+                format!("branch_if_positive tmp1 + 1, {label};"),
             ]
         }
         "bltu" => {