Georg Wiese 2832ff108b Fix second stage witgen (#2173) ...

Builds on #2169

With this PR, second-stage witness generation works for the bus used in
the RISC-V machine 🎉

This is an end-to-end test:
```bash
cargo run -r --bin powdr-rs compile riscv/tests/riscv_data/sum-o output --max-degree-log 15 --field gl
cargo run -r pil output/sum.asm -o output -f --field gl --prove-with mock --linker-mode bus -i 1,1,1
```

What's needed is two small changes to `VmProcessor`:
- The degree is now passed by the caller (`DynamicMachine` or
`SecondStageMachine`). That way, `SecondStageMachine` can set it to the
actual final size, instead of the maximum allowed degree.
- I disabled loop detection for second-stage witness generation for now.

2024-11-29 18:16:02 +00:00

..

src

Fix second stage witgen (#2173)

2024-11-29 18:16:02 +00:00

Cargo.toml

Introduce workspace-level lints (#2166)

2024-11-29 14:02:53 +00:00