diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/README.md b/backends/tfhe-hpu-backend/config_store/u55c_gf64/README.md deleted file mode 100644 index 2fbe5df9f..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/README.md +++ /dev/null @@ -1,6 +0,0 @@ -# Fpga version - -Built with the following command: (i.e. xrt/run_syn_hpu_msplit_3parts_64b.sh) -``` -just zaxl-build hpu_msplit_3parts 3 "0:300" "-F TOP_MSPLIT TOP_MSPLIT_1 -F TOP_BATCH TOP_BATCH_TOPhpu_BPBS8_TPBS32 -F TOP_PCMAX TOP_PCMAX_pem2_glwe1_bsk8_ksk8 -F TOP_PC TOP_PC_pem2_glwe1_bsk4_ksk4 -F APPLICATION APPLI_msg2_carry2 -F NTT_MOD NTT_MOD_goldilocks -F NTT_CORE_ARCH NTT_CORE_ARCH_gf64 -F NTT_CORE_R_PSI NTT_CORE_R2_PSI16 -F NTT_CORE_RDX_CUT NTT_CORE_RDX_CUT_n5c5c1 -F NTT_CORE_DIV NTT_CORE_DIV_1 -F BSK_SLOT_CUT BSK_SLOT8_CUT4 -F KSK_SLOT_CUT KSK_SLOT8_CUT4 -F KSLB KSLB_x2y32z3 -F HPU_PART HPU_PART_gf64 -F AXI_DATA_W AXI_DATA_W_512" "1:${PROJECT_DIR}/hw/output/micro_code/ucore_fw.elf" 'D:MEMORY_FILE_PATH=\\\"${PROJECT_DIR}/hw/\\\"' | tee build_out.log -``` diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_0.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_0.asm deleted file mode 100644 index 838beed9e..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_0.asm +++ /dev/null @@ -1,15 +0,0 @@ -# CUST_0 -# Simple IOp to check the xfer between Hpu/Cpu -# Construct constant in dest slot -> 249 (0xf9) -SUB R0 R0 R0 -ADDS R0 R0 1 -ST TD[0].0 R0 -SUB R1 R1 R1 -ADDS R1 R1 2 -ST TD[0].1 R1 -SUB R2 R2 R2 -ADDS R2 R2 3 -ST TD[0].2 R2 -SUB R3 R3 R3 -ADDS R3 R3 3 -ST TD[0].3 R3 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_1.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_1.asm deleted file mode 100644 index 3679e2c5f..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_1.asm +++ /dev/null @@ -1,11 +0,0 @@ -# CUST_1 -# Simple IOp to check the xfer between Hpu/Cpu -# Dest <- Src_a -LD R0 TS[0].0 -LD R1 TS[0].1 -LD R2 TS[0].2 -LD R3 TS[0].3 -ST TD[0].0 R0 -ST TD[0].1 R1 -ST TD[0].2 R2 -ST TD[0].3 R3 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_10.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_10.asm deleted file mode 100644 index f591d66b3..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_10.asm +++ /dev/null @@ -1,25 +0,0 @@ -; CUST_8 -; Simple IOp to check the ALU operation -; Dst[0].0 <- Src[0].0 + Src[1].0 -LD R1 TS[0].0 -LD R2 TS[1].0 -ADD R0 R1 R2 -ST TD[0].0 R0 - -; Dst[0].1 <- Src[0].1 + Src[1].1 -LD R5 TS[0].1 -LD R6 TS[1].1 -ADD R4 R5 R6 -ST TD[0].2 R4 - -; Dst[0].2 <- Src[0].2 + Src[1].2 -LD R9 TS[0].2 -LD R10 TS[1].2 -ADD R8 R9 R10 -ST TD[0].2 R8 - -; Dst[0].3 <- Src[0].3 + Src[1].3 -LD R13 TS[0].3 -LD R14 TS[1].3 -ADD R12 R13 R14 -ST TD[0].3 R0 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_16.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_16.asm deleted file mode 100644 index 0b4cfe80f..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_16.asm +++ /dev/null @@ -1,6 +0,0 @@ -# CUST_16 -# Simple IOp to check PBS behavior -# Dest <- PBSNone(Src_a.0) -LD R0 TS[0].0 -PBS_F R0 R0 PbsNone -ST TD[0].0 R0 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_17.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_17.asm deleted file mode 100644 index bdb6711a7..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_17.asm +++ /dev/null @@ -1,15 +0,0 @@ -# CUST_17 -# Simple IOp to check PBS behavior -# Dest <- PBSNone(Src_a) -LD R0 TS[0].0 -PBS R0 R0 PbsNone -ST TD[0].0 R0 -LD R1 TS[0].1 -PBS R1 R1 PbsNone -ST TD[0].1 R1 -LD R2 TS[0].2 -PBS R2 R2 PbsNone -ST TD[0].2 R2 -LD R3 TS[0].3 -PBS_F R3 R3 PbsNone -ST TD[0].3 R3 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_18.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_18.asm deleted file mode 100644 index c4b9a46a0..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_18.asm +++ /dev/null @@ -1,23 +0,0 @@ -; CUST_18 -; Simple IOp to check extraction pattern -; Correct result: -; * Dst[0,1] <- Src[0][0,1] -; * Dst[2,3] <- Src[1][0,1] - -; Pack Src[0][0,1] with a Mac and extract Carry/Msg in Dst[0][0,1] -LD R0 TS[0].0 -LD R1 TS[0].1 -MAC R3 R1 R0 4 -PBS R4 R3 PbsMsgOnly -PBS R5 R3 PbsCarryInMsg -ST TD[0].0 R4 -ST TD[0].1 R5 - -; Pack Src[1][0,1] with a Mac and extract Carry/Msg in Dst[0][2,3] -LD R10 TS[1].0 -LD R11 TS[1].1 -MAC R13 R11 R10 4 -PBS R14 R13 PbsMsgOnly -PBS R15 R13 PbsCarryInMsg -ST TD[0].2 R14 -ST TD[0].3 R15 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_19.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_19.asm deleted file mode 100644 index 0974347fa..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_19.asm +++ /dev/null @@ -1,19 +0,0 @@ -; CUST_19 -; Simple IOp to check PbsMl2 -; Correct result: -; * Dst[0][0] <- Src[0][0] -; * Dst[0][1] <- 0 -; * Dst[0][2] <- Src[0][0] +1 -; * Dst[0][3] <- 0 -; i.e Cust_19(0x2) => 0x32 - -; Construct a 0 for destination padding -SUB R16 R16 R16 - -; Apply PbsMl2 on Src[0] result goes in dest[0][0-3] (0-padded) -LD R0 TS[0].0 -PBS_ML2_F R0 R0 PbsTestMany2 -ST TD[0].0 R0 -ST TD[0].1 R16 -ST TD[0].2 R1 -ST TD[0].3 R16 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_2.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_2.asm deleted file mode 100644 index bc8e0175e..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_2.asm +++ /dev/null @@ -1,11 +0,0 @@ -# CUST_2 -# Simple IOp to check the xfer between Hpu/Cpu -# Dest <- Src_b -LD R0 TS[1].0 -LD R1 TS[1].1 -LD R2 TS[1].2 -LD R3 TS[1].3 -ST TD[0].0 R0 -ST TD[0].1 R1 -ST TD[0].2 R2 -ST TD[0].3 R3 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_20.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_20.asm deleted file mode 100644 index 5f29f8ee5..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_20.asm +++ /dev/null @@ -1,22 +0,0 @@ -; CUST_20 -; Simple IOp to check PbsMl4 -; Correct result: -; * Dst[0][0] <- Src[0][0] -; * Dst[0][1] <- Src[0][0] +1 -; * Dst[0][2] <- Src[0][0] +2 -; * Dst[0][3] <- Src[0][0] +3 -; i.e Cust_20(0x0) => 0xe4 - -SUB R16 R16 R16 -ST TD[0].0 R0 -ST TD[0].1 R0 -ST TD[0].2 R0 -ST TD[0].3 R0 - -; Apply PbsMl4 on Src[0] result goes in dest[0][0-3] -LD R0 TS[0].0 -PBS_ML4_F R0 R0 PbsTestMany4 -ST TD[0].0 R0 -ST TD[0].1 R1 -ST TD[0].2 R2 -ST TD[0].3 R3 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_21.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_21.asm deleted file mode 100644 index 5a601bbe6..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_21.asm +++ /dev/null @@ -1,24 +0,0 @@ -; CUST_21 -; Simple IOp to check PbsMl8 -; WARN: This operation required 16b ct width -; Correct result: -; * Dst[0][0] <- Src[0][0] -; * Dst[0][1] <- Src[0][0] +1 -; * Dst[0][2] <- Src[0][0] +2 -; * Dst[0][3] <- Src[0][0] +3 -; * Dst[0][4] <- Src[0][0] +4 -; * Dst[0][5] <- Src[0][0] +5 -; * Dst[0][6] <- Src[0][0] +6 -; * Dst[0][7] <- Src[0][0] +7 - -; Apply PbsMl8 on Src[0] result goes in dest[0][0-7] -LD R0 TS[0].0 -PBS_ML8_F R0 R0 PbsTestMany8 -ST TD[0].0 R0 -ST TD[0].1 R1 -ST TD[0].2 R2 -ST TD[0].3 R3 -ST TD[0].4 R4 -ST TD[0].5 R5 -ST TD[0].6 R6 -ST TD[0].7 R7 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_3.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_3.asm deleted file mode 100644 index d13ca243c..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_3.asm +++ /dev/null @@ -1,16 +0,0 @@ -# CUST_3 -# Simple IOp to check isc behavior -# Generate obvious deps and check that isc correctly issued the dop -# Correct result must bu Dest <- Src[0] -LD R0 TS[0].0 -LD R1 TS[0].1 -LD R2 TS[0].2 -LD R3 TS[0].3 -PBS R4 R0 PbsNone -ST TD[0].0 R4 -PBS R4 R1 PbsNone -ST TD[0].1 R4 -PBS R4 R2 PbsNone -ST TD[0].2 R4 -PBS_F R4 R3 PbsNone -ST TD[0].3 R4 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_8.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_8.asm deleted file mode 100644 index c02eee9cd..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_8.asm +++ /dev/null @@ -1,19 +0,0 @@ -; CUST_8 -; Simple IOp to check the ALU operation -; Dst[0].0 <- Src[0].0 + Src[1].0 -LD R1 TS[0].0 -LD R2 TS[1].0 -ADD R0 R1 R2 -ST TD[0].0 R0 - -; Dst[0].1 <- Src[0].1 - Src[1].1 -LD R5 TS[0].1 -LD R6 TS[1].1 -SUB R4 R5 R6 -ST TD[0].1 R4 - -; Dst[0].2 <- Src[0].2 + (Src[1].2 *4) -LD R9 TS[0].2 -LD R10 TS[1].2 -MAC R8 R9 R10 4 -ST TD[0].2 R8 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_9.asm b/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_9.asm deleted file mode 100644 index 5e5cc4129..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/custom_iop/cust_9.asm +++ /dev/null @@ -1,21 +0,0 @@ -; CUST_9 -; Simple IOp to check the ALU Scalar operation -; Dst[0].0 <- Src[0].0 + Imm[0].0 -LD R1 TS[0].0 -ADDS R0 R1 TI[0].0 -ST TD[0].0 R0 - -; Dst[0].1 <- Src[0].1 - Imm[0].1 -LD R5 TS[0].1 -SUBS R4 R5 TI[0].1 -ST TD[0].1 R4 - -; Dst[0].2 <- Imm[0].2 - Src[0].2 -LD R9 TS[0].2 -SSUB R8 R9 TI[0].2 -ST TD[0].2 R8 - -; Dst[0].3 <- Src[0].3 * Imm[0].3 -LD R13 TS[0].3 -MULS R12 R13 TI[0].3 -ST TD[0].3 R12 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_config.toml b/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_config.toml deleted file mode 100644 index b5d460a1a..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_config.toml +++ /dev/null @@ -1,98 +0,0 @@ - -[fpga] - regmap=["${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core.toml"] - polling_us=10 -[fpga.ffi.Xrt] - id= 0 - kernel= "hpu_msplit_3parts_1in3" - xclbin="${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_msplit_3parts.xclbin" - -[rtl] - bpip_use = true - bpip_use_opportunism = true - bpip_timeout = 100_000 - -[board] - ct_mem = 4096 - ct_pc = [ - {Hbm= {pc=10}}, - {Hbm= {pc=11}}, - ] - heap_size = 3584 - - lut_mem = 256 - lut_pc = {Hbm={pc=12}} - - fw_size= 65536 - fw_pc = {Hbm={pc=1}} - - bsk_pc = [ - {Hbm={pc=2}}, - {Hbm={pc=3}}, - {Hbm={pc=4}}, - {Hbm={pc=5}}, - {Hbm={pc=6}}, - {Hbm={pc=7}}, - {Hbm={pc=8}}, - {Hbm={pc=9}} - ] - - ksk_pc = [ - {Hbm={pc=24}}, - {Hbm={pc=25}}, - {Hbm={pc=26}}, - {Hbm={pc=27}}, - {Hbm={pc=28}}, - {Hbm={pc=29}}, - {Hbm={pc=30}}, - {Hbm={pc=31}} - ] - - trace_pc = {Hbm={pc=0}} - trace_depth = 4 # In MB - -[firmware] - implementation = "Llt" - integer_w=[4,6,8,10,12,14,16,32,64,128] - min_batch_size = 6 - kogge_cfg = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/kogge_cfg.toml" - custom_iop.'IOP[0]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_0.asm" - custom_iop.'IOP[1]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_1.asm" - custom_iop.'IOP[2]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_2.asm" - custom_iop.'IOP[3]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_3.asm" - custom_iop.'IOP[8]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_8.asm" - custom_iop.'IOP[9]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_9.asm" - custom_iop.'IOP[16]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_16.asm" - custom_iop.'IOP[17]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_17.asm" - custom_iop.'IOP[18]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_18.asm" - custom_iop.'IOP[19]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_19.asm" - custom_iop.'IOP[20]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_20.asm" - custom_iop.'IOP[21]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_21.asm" - -[firmware.op_cfg.default] - fill_batch_fifo = true - min_batch_size = false - use_tiers = false - flush_behaviour = "Patient" - flush = true - -[firmware.op_cfg.by_op.MUL] - fill_batch_fifo = false - min_batch_size = false - use_tiers = false - flush_behaviour = "Patient" - flush = true - -[firmware.op_cfg.by_op.MULS] - fill_batch_fifo = false - min_batch_size = false - use_tiers = false - flush_behaviour = "Patient" - flush = true - -[firmware.op_cfg.by_op.ERC_20] - fill_batch_fifo = false - min_batch_size = true - use_tiers = true - flush_behaviour = "Patient" - flush = true diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin b/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin deleted file mode 100644 index 604d76461..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:35ad67cf9760e37256a6c92cf29ea67334690b724fd3b7b859919ee9b0bde6d3 -size 78194785 diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.info b/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.info deleted file mode 100644 index cbaa8cba5..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.info +++ /dev/null @@ -1,1550 +0,0 @@ - -============================================================================== -XRT Build Version: 2.16.0 (Vitis) - Build Date: 2023-07-13 16:00:55 - Hash ID: 157faa07876c55bb8aa8ec51b28608a6a0f6638e -============================================================================== -xclbin Information ------------------- - Generated by: v++ (2024.1) on 2024-05-20-23:21:20 - Version: 2.16.0 - Kernels: hpu_msplit_3parts_3in3, hpu_msplit_3parts_2in3, hpu_msplit_3parts_1in3 - Signature: - Content: Bitstream - UUID (xclbin): d0bcc1ed-d380-c9cf-175f-c059794490d4 - UUID (IINTF): b7ac1abe1e3e1cb686d5a81232452676 - Sections: BITSTREAM, MEM_TOPOLOGY, IP_LAYOUT, CONNECTIVITY, - CLOCK_FREQ_TOPOLOGY, BUILD_METADATA, - EMBEDDED_METADATA, SYSTEM_METADATA, - PARTITION_METADATA, GROUP_CONNECTIVITY, GROUP_TOPOLOGY -============================================================================== -Hardware Platform (Shell) Information -------------------------------------- - Vendor: xilinx - Board: u55c - Name: gen3x16_xdma_3 - Version: 202210.1 - Generated Version: Vivado 2022.1 (SW Build: 3513633) - Created: - Fri Apr 1 11:16:28 2022 FPGA Device: xcu55c - Board Vendor: xilinx.com - Board Name: xilinx.com:au55c:1.0 - Board Part: xilinx.com:au55c:part0:1.0 - Platform VBNV: xilinx_u55c_gen3x16_xdma_3_202210_1 - Static UUID: b7ac1abe-1e3e-1cb6-86d5-a81232452676 - Feature ROM TimeStamp: 0 - -Scalable Clocks ---------------- - Name: hbm_aclk - Index: 0 - Type: SYSTEM - Frequency: 450 MHz - - Name: KERNEL_CLK - Index: 1 - Type: KERNEL - Frequency: 500 MHz - - Name: DATA_CLK - Index: 2 - Type: DATA - Frequency: 300 MHz - -System Clocks ------- - Name: ulp_ucs_aclk_kernel_00 - Type: SCALABLE - Default Freq: 300 MHz - Requested Freq: 300 MHz - Achieved Freq: 300 MHz - - Name: ulp_ucs_aclk_kernel_01 - Type: SCALABLE - Default Freq: 500 MHz - Requested Freq: 500 MHz - Achieved Freq: 500 MHz - - Name: _bd_top_blp_s_aclk_freerun_ref_00 - Type: FIXED - Default Freq: 100 MHz - -Memory Configuration --------------------- - Name: HBM[0] - Index: 0 - Type: MEM_HBM - Base Address: 0x0 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[1] - Index: 1 - Type: MEM_DRAM - Base Address: 0x20000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[2] - Index: 2 - Type: MEM_DRAM - Base Address: 0x40000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[3] - Index: 3 - Type: MEM_DRAM - Base Address: 0x60000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[4] - Index: 4 - Type: MEM_DRAM - Base Address: 0x80000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[5] - Index: 5 - Type: MEM_DRAM - Base Address: 0xa0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[6] - Index: 6 - Type: MEM_DRAM - Base Address: 0xc0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[7] - Index: 7 - Type: MEM_DRAM - Base Address: 0xe0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[8] - Index: 8 - Type: MEM_DRAM - Base Address: 0x100000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[9] - Index: 9 - Type: MEM_DRAM - Base Address: 0x120000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[10] - Index: 10 - Type: MEM_DRAM - Base Address: 0x140000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[11] - Index: 11 - Type: MEM_DRAM - Base Address: 0x160000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[12] - Index: 12 - Type: MEM_DRAM - Base Address: 0x180000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[13] - Index: 13 - Type: MEM_DRAM - Base Address: 0x1a0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[14] - Index: 14 - Type: MEM_DRAM - Base Address: 0x1c0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[15] - Index: 15 - Type: MEM_DRAM - Base Address: 0x1e0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[16] - Index: 16 - Type: MEM_DRAM - Base Address: 0x200000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[17] - Index: 17 - Type: MEM_DRAM - Base Address: 0x220000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[18] - Index: 18 - Type: MEM_DRAM - Base Address: 0x240000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[19] - Index: 19 - Type: MEM_DRAM - Base Address: 0x260000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[20] - Index: 20 - Type: MEM_DRAM - Base Address: 0x280000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[21] - Index: 21 - Type: MEM_DRAM - Base Address: 0x2a0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[22] - Index: 22 - Type: MEM_DRAM - Base Address: 0x2c0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[23] - Index: 23 - Type: MEM_DRAM - Base Address: 0x2e0000000 - Address Size: 0x20000000 - Bank Used: No - - Name: HBM[24] - Index: 24 - Type: MEM_DRAM - Base Address: 0x300000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[25] - Index: 25 - Type: MEM_DRAM - Base Address: 0x320000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[26] - Index: 26 - Type: MEM_DRAM - Base Address: 0x340000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[27] - Index: 27 - Type: MEM_DRAM - Base Address: 0x360000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[28] - Index: 28 - Type: MEM_DRAM - Base Address: 0x380000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[29] - Index: 29 - Type: MEM_DRAM - Base Address: 0x3a0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[30] - Index: 30 - Type: MEM_DRAM - Base Address: 0x3c0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: HBM[31] - Index: 31 - Type: MEM_DRAM - Base Address: 0x3e0000000 - Address Size: 0x20000000 - Bank Used: Yes - - Name: PLRAM[0] - Index: 32 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: PLRAM[1] - Index: 33 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: PLRAM[2] - Index: 34 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: PLRAM[3] - Index: 35 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: PLRAM[4] - Index: 36 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: PLRAM[5] - Index: 37 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: HOST[0] - Index: 38 - Type: MEM_DRAM - Base Address: 0x0 - Address Size: 0x0 - Bank Used: No - - Name: dc_0 - Index: 39 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_1 - Index: 40 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_2 - Index: 41 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_3 - Index: 42 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_4 - Index: 43 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_5 - Index: 44 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_6 - Index: 45 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_7 - Index: 46 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_8 - Index: 47 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_9 - Index: 48 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_10 - Index: 49 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_11 - Index: 50 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_12 - Index: 51 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_13 - Index: 52 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_14 - Index: 53 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_15 - Index: 54 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_16 - Index: 55 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_17 - Index: 56 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_18 - Index: 57 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_19 - Index: 58 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_20 - Index: 59 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_21 - Index: 60 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_22 - Index: 61 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_23 - Index: 62 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_24 - Index: 63 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_25 - Index: 64 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_26 - Index: 65 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_27 - Index: 66 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes - - Name: dc_28 - Index: 67 - Type: MEM_STREAMING_CONNECTION - Base Address: 0x0 - Address Size: 0x0 - Bank Used: Yes -============================================================================== -Kernel: hpu_msplit_3parts_3in3 - -Definition ----------- - Signature: hpu_msplit_3parts_3in3 (void* M_AXI_BSK_0_PTR, void* M_AXI_BSK_1_PTR, void* M_AXI_BSK_2_PTR, void* M_AXI_BSK_3_PTR, void* M_AXI_BSK_4_PTR, void* M_AXI_BSK_5_PTR, void* M_AXI_BSK_6_PTR, void* M_AXI_BSK_7_PTR, void* axis_p2_p3_batch, void* axis_p2_p3_bsk_c, void* axis_p2_p3_proc_c, void* axis_p2_p3_proc_d0, void* axis_p2_p3_proc_d1, void* axis_p2_p3_proc_d2, void* axis_p2_p3_proc_d3, void* axis_p3_p2_bsk_c, void* axis_p3_p2_proc_c, void* axis_p3_p2_proc_d0, void* axis_p3_p2_proc_d1, void* axis_p3_p2_proc_d2, void* axis_p3_p2_proc_d3, void* axis_p3_p2_side) - -Ports ------ - Port: axis_p2_p3_batch - Mode: read_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p2_p3_bsk_c - Mode: read_only - Range (bytes): - Data Width: 520 bits - Port Type: stream - - Port: axis_p2_p3_proc_c - Mode: read_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p3_proc_d0 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d1 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d2 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d3 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_bsk_c - Mode: write_only - Range (bytes): - Data Width: 8 bits - Port Type: stream - - Port: axis_p3_p2_proc_c - Mode: write_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p3_p2_proc_d0 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d1 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d2 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d3 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_side - Mode: write_only - Range (bytes): - Data Width: 256 bits - Port Type: stream - - Port: m_axi_bsk_0 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_1 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_2 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_3 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_4 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_5 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_6 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_bsk_7 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: s_axil - Mode: slave - Range (bytes): 0x10000 - Data Width: 32 bits - Port Type: addressable - --------------------------- -Instance: hpu_msplit_3parts_3in3_1 - Base Address: 0x1000000 - - Argument: M_AXI_BSK_0_PTR - Register Offset: 0x10 - Port: m_axi_bsk_0 - Memory: HBM[2] (MEM_DRAM) - - Argument: M_AXI_BSK_1_PTR - Register Offset: 0x14 - Port: m_axi_bsk_1 - Memory: HBM[3] (MEM_DRAM) - - Argument: M_AXI_BSK_2_PTR - Register Offset: 0x18 - Port: m_axi_bsk_2 - Memory: HBM[4] (MEM_DRAM) - - Argument: M_AXI_BSK_3_PTR - Register Offset: 0x1c - Port: m_axi_bsk_3 - Memory: HBM[5] (MEM_DRAM) - - Argument: M_AXI_BSK_4_PTR - Register Offset: 0x20 - Port: m_axi_bsk_4 - Memory: HBM[6] (MEM_DRAM) - - Argument: M_AXI_BSK_5_PTR - Register Offset: 0x24 - Port: m_axi_bsk_5 - Memory: HBM[7] (MEM_DRAM) - - Argument: M_AXI_BSK_6_PTR - Register Offset: 0x28 - Port: m_axi_bsk_6 - Memory: HBM[8] (MEM_DRAM) - - Argument: M_AXI_BSK_7_PTR - Register Offset: 0x2c - Port: m_axi_bsk_7 - Memory: HBM[9] (MEM_DRAM) - - Argument: axis_p2_p3_batch - Register Offset: 0x0 - Port: axis_p2_p3_batch - Memory: dc_15 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_bsk_c - Register Offset: 0x0 - Port: axis_p2_p3_bsk_c - Memory: dc_16 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_c - Register Offset: 0x0 - Port: axis_p2_p3_proc_c - Memory: dc_17 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d0 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d0 - Memory: dc_18 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d1 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d1 - Memory: dc_19 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d2 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d2 - Memory: dc_20 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d3 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d3 - Memory: dc_21 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_bsk_c - Register Offset: 0x0 - Port: axis_p3_p2_bsk_c - Memory: dc_22 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_c - Register Offset: 0x0 - Port: axis_p3_p2_proc_c - Memory: dc_23 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d0 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d0 - Memory: dc_24 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d1 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d1 - Memory: dc_25 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d2 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d2 - Memory: dc_26 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d3 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d3 - Memory: dc_27 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_side - Register Offset: 0x0 - Port: axis_p3_p2_side - Memory: dc_28 (MEM_STREAMING_CONNECTION) -Kernel: hpu_msplit_3parts_2in3 - -Definition ----------- - Signature: hpu_msplit_3parts_2in3 (void* axis_p1_p2_batch, void* axis_p1_p2_bsk_c, void* axis_p1_p2_ldg_c, void* axis_p1_p2_ldg_d, void* axis_p1_p2_mmacc_side, void* axis_p1_p2_mmfeed_c, void* axis_p1_p2_mmfeed_d0, void* axis_p1_p2_mmfeed_d1, void* axis_p1_p2_mmsxt_c, void* axis_p2_p1_bsk_c, void* axis_p2_p1_mmacc_c, void* axis_p2_p1_mmacc_d0, void* axis_p2_p1_mmacc_side, void* axis_p2_p1_mmsxt_d0, void* axis_p2_p1_side, void* axis_p2_p3_batch, void* axis_p2_p3_bsk_c, void* axis_p2_p3_proc_c, void* axis_p2_p3_proc_d0, void* axis_p2_p3_proc_d1, void* axis_p2_p3_proc_d2, void* axis_p2_p3_proc_d3, void* axis_p3_p2_bsk_c, void* axis_p3_p2_proc_c, void* axis_p3_p2_proc_d0, void* axis_p3_p2_proc_d1, void* axis_p3_p2_proc_d2, void* axis_p3_p2_proc_d3, void* axis_p3_p2_side) - -Ports ------ - Port: axis_p1_p2_batch - Mode: read_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p1_p2_bsk_c - Mode: read_only - Range (bytes): - Data Width: 520 bits - Port Type: stream - - Port: axis_p1_p2_ldg_c - Mode: read_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p1_p2_ldg_d - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmacc_side - Mode: read_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_c - Mode: read_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_d0 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_d1 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmsxt_c - Mode: read_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p2_p1_bsk_c - Mode: write_only - Range (bytes): - Data Width: 8 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_c - Mode: write_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_d0 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_side - Mode: write_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p1_mmsxt_d0 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p1_side - Mode: write_only - Range (bytes): - Data Width: 256 bits - Port Type: stream - - Port: axis_p2_p3_batch - Mode: write_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p2_p3_bsk_c - Mode: write_only - Range (bytes): - Data Width: 520 bits - Port Type: stream - - Port: axis_p2_p3_proc_c - Mode: write_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p3_proc_d0 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d1 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d2 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p3_proc_d3 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_bsk_c - Mode: read_only - Range (bytes): - Data Width: 8 bits - Port Type: stream - - Port: axis_p3_p2_proc_c - Mode: read_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p3_p2_proc_d0 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d1 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d2 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_proc_d3 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p3_p2_side - Mode: read_only - Range (bytes): - Data Width: 256 bits - Port Type: stream - --------------------------- -Instance: hpu_msplit_3parts_2in3_1 - Base Address: not_used - - Argument: axis_p1_p2_batch - Register Offset: 0x0 - Port: axis_p1_p2_batch - Memory: dc_0 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_bsk_c - Register Offset: 0x0 - Port: axis_p1_p2_bsk_c - Memory: dc_1 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_ldg_c - Register Offset: 0x0 - Port: axis_p1_p2_ldg_c - Memory: dc_2 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_ldg_d - Register Offset: 0x0 - Port: axis_p1_p2_ldg_d - Memory: dc_3 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmacc_side - Register Offset: 0x0 - Port: axis_p1_p2_mmacc_side - Memory: dc_4 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_c - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_c - Memory: dc_5 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_d0 - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_d0 - Memory: dc_6 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_d1 - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_d1 - Memory: dc_7 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmsxt_c - Register Offset: 0x0 - Port: axis_p1_p2_mmsxt_c - Memory: dc_8 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_bsk_c - Register Offset: 0x0 - Port: axis_p2_p1_bsk_c - Memory: dc_9 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_c - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_c - Memory: dc_10 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_d0 - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_d0 - Memory: dc_11 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_side - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_side - Memory: dc_12 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmsxt_d0 - Register Offset: 0x0 - Port: axis_p2_p1_mmsxt_d0 - Memory: dc_13 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_side - Register Offset: 0x0 - Port: axis_p2_p1_side - Memory: dc_14 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_batch - Register Offset: 0x0 - Port: axis_p2_p3_batch - Memory: dc_15 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_bsk_c - Register Offset: 0x0 - Port: axis_p2_p3_bsk_c - Memory: dc_16 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_c - Register Offset: 0x0 - Port: axis_p2_p3_proc_c - Memory: dc_17 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d0 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d0 - Memory: dc_18 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d1 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d1 - Memory: dc_19 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d2 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d2 - Memory: dc_20 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p3_proc_d3 - Register Offset: 0x0 - Port: axis_p2_p3_proc_d3 - Memory: dc_21 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_bsk_c - Register Offset: 0x0 - Port: axis_p3_p2_bsk_c - Memory: dc_22 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_c - Register Offset: 0x0 - Port: axis_p3_p2_proc_c - Memory: dc_23 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d0 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d0 - Memory: dc_24 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d1 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d1 - Memory: dc_25 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d2 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d2 - Memory: dc_26 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_proc_d3 - Register Offset: 0x0 - Port: axis_p3_p2_proc_d3 - Memory: dc_27 (MEM_STREAMING_CONNECTION) - - Argument: axis_p3_p2_side - Register Offset: 0x0 - Port: axis_p3_p2_side - Memory: dc_28 (MEM_STREAMING_CONNECTION) -Kernel: hpu_msplit_3parts_1in3 - -Definition ----------- - Signature: hpu_msplit_3parts_1in3 (void* M_AXI_UCORE_PTR, void* M_AXI_TRC_PTR, void* M_AXI_PEM_0_PTR, void* M_AXI_PEM_1_PTR, void* M_AXI_GLWE_0_PTR, void* M_AXI_KSK_0_PTR, void* M_AXI_KSK_1_PTR, void* M_AXI_KSK_2_PTR, void* M_AXI_KSK_3_PTR, void* M_AXI_KSK_4_PTR, void* M_AXI_KSK_5_PTR, void* M_AXI_KSK_6_PTR, void* M_AXI_KSK_7_PTR, void* axis_p1_p2_batch, void* axis_p1_p2_bsk_c, void* axis_p1_p2_ldg_c, void* axis_p1_p2_ldg_d, void* axis_p1_p2_mmacc_side, void* axis_p1_p2_mmfeed_c, void* axis_p1_p2_mmfeed_d0, void* axis_p1_p2_mmfeed_d1, void* axis_p1_p2_mmsxt_c, void* axis_p2_p1_bsk_c, void* axis_p2_p1_mmacc_c, void* axis_p2_p1_mmacc_d0, void* axis_p2_p1_mmacc_side, void* axis_p2_p1_mmsxt_d0, void* axis_p2_p1_side) - -Ports ------ - Port: axis_p1_p2_batch - Mode: write_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p1_p2_bsk_c - Mode: write_only - Range (bytes): - Data Width: 520 bits - Port Type: stream - - Port: axis_p1_p2_ldg_c - Mode: write_only - Range (bytes): - Data Width: 32 bits - Port Type: stream - - Port: axis_p1_p2_ldg_d - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmacc_side - Mode: write_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_c - Mode: write_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_d0 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmfeed_d1 - Mode: write_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p1_p2_mmsxt_c - Mode: write_only - Range (bytes): - Data Width: 64 bits - Port Type: stream - - Port: axis_p2_p1_bsk_c - Mode: read_only - Range (bytes): - Data Width: 8 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_c - Mode: read_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_d0 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p1_mmacc_side - Mode: read_only - Range (bytes): - Data Width: 16 bits - Port Type: stream - - Port: axis_p2_p1_mmsxt_d0 - Mode: read_only - Range (bytes): - Data Width: 2048 bits - Port Type: stream - - Port: axis_p2_p1_side - Mode: read_only - Range (bytes): - Data Width: 256 bits - Port Type: stream - - Port: m_axi_glwe_0 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_0 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_1 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_2 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_3 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_4 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_5 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_6 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_ksk_7 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_pem_0 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_pem_1 - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 512 bits - Port Type: addressable - - Port: m_axi_trc - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 32 bits - Port Type: addressable - - Port: m_axi_ucore - Mode: master - Range (bytes): 0xFFFFFFFF - Data Width: 32 bits - Port Type: addressable - - Port: s_axil - Mode: slave - Range (bytes): 0x10000 - Data Width: 32 bits - Port Type: addressable - --------------------------- -Instance: hpu_msplit_3parts_1in3_1 - Base Address: 0x800000 - - Argument: M_AXI_UCORE_PTR - Register Offset: 0x10 - Port: m_axi_ucore - Memory: HBM[1] (MEM_DRAM) - - Argument: M_AXI_TRC_PTR - Register Offset: 0x14 - Port: m_axi_trc - Memory: HBM[0] (MEM_HBM) - - Argument: M_AXI_PEM_0_PTR - Register Offset: 0x18 - Port: m_axi_pem_0 - Memory: HBM[10] (MEM_DRAM) - - Argument: M_AXI_PEM_1_PTR - Register Offset: 0x1c - Port: m_axi_pem_1 - Memory: HBM[11] (MEM_DRAM) - - Argument: M_AXI_GLWE_0_PTR - Register Offset: 0x20 - Port: m_axi_glwe_0 - Memory: HBM[12] (MEM_DRAM) - - Argument: M_AXI_KSK_0_PTR - Register Offset: 0x24 - Port: m_axi_ksk_0 - Memory: HBM[24] (MEM_DRAM) - - Argument: M_AXI_KSK_1_PTR - Register Offset: 0x28 - Port: m_axi_ksk_1 - Memory: HBM[25] (MEM_DRAM) - - Argument: M_AXI_KSK_2_PTR - Register Offset: 0x2c - Port: m_axi_ksk_2 - Memory: HBM[26] (MEM_DRAM) - - Argument: M_AXI_KSK_3_PTR - Register Offset: 0x30 - Port: m_axi_ksk_3 - Memory: HBM[27] (MEM_DRAM) - - Argument: M_AXI_KSK_4_PTR - Register Offset: 0x34 - Port: m_axi_ksk_4 - Memory: HBM[28] (MEM_DRAM) - - Argument: M_AXI_KSK_5_PTR - Register Offset: 0x38 - Port: m_axi_ksk_5 - Memory: HBM[29] (MEM_DRAM) - - Argument: M_AXI_KSK_6_PTR - Register Offset: 0x3c - Port: m_axi_ksk_6 - Memory: HBM[30] (MEM_DRAM) - - Argument: M_AXI_KSK_7_PTR - Register Offset: 0x40 - Port: m_axi_ksk_7 - Memory: HBM[31] (MEM_DRAM) - - Argument: axis_p1_p2_batch - Register Offset: 0x0 - Port: axis_p1_p2_batch - Memory: dc_0 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_bsk_c - Register Offset: 0x0 - Port: axis_p1_p2_bsk_c - Memory: dc_1 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_ldg_c - Register Offset: 0x0 - Port: axis_p1_p2_ldg_c - Memory: dc_2 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_ldg_d - Register Offset: 0x0 - Port: axis_p1_p2_ldg_d - Memory: dc_3 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmacc_side - Register Offset: 0x0 - Port: axis_p1_p2_mmacc_side - Memory: dc_4 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_c - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_c - Memory: dc_5 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_d0 - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_d0 - Memory: dc_6 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmfeed_d1 - Register Offset: 0x0 - Port: axis_p1_p2_mmfeed_d1 - Memory: dc_7 (MEM_STREAMING_CONNECTION) - - Argument: axis_p1_p2_mmsxt_c - Register Offset: 0x0 - Port: axis_p1_p2_mmsxt_c - Memory: dc_8 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_bsk_c - Register Offset: 0x0 - Port: axis_p2_p1_bsk_c - Memory: dc_9 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_c - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_c - Memory: dc_10 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_d0 - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_d0 - Memory: dc_11 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmacc_side - Register Offset: 0x0 - Port: axis_p2_p1_mmacc_side - Memory: dc_12 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_mmsxt_d0 - Register Offset: 0x0 - Port: axis_p2_p1_mmsxt_d0 - Memory: dc_13 (MEM_STREAMING_CONNECTION) - - Argument: axis_p2_p1_side - Register Offset: 0x0 - Port: axis_p2_p1_side - Memory: dc_14 (MEM_STREAMING_CONNECTION) -============================================================================== -Generated By ------------- - Command: v++ - Version: 2024.1 - 2024-05-20-23:21:20 (SW BUILD: 5074859) - Command Line: v++ --config /projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/cfg/hpu_msplit_3parts.cfg --connectivity.nk hpu_msplit_3parts_1in3:1 --connectivity.nk hpu_msplit_3parts_2in3:1 --connectivity.nk hpu_msplit_3parts_3in3:1 --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_bsk_c --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_c --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmsxt_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmsxt_c --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_c --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_d:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_d --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d0:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d0 --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d1:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d1 --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmacc_side:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmacc_side --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_batch:hpu_msplit_3parts_2in3_1.axis_p1_p2_batch --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_d0 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_c --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_bsk_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_bsk_c --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_side --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmsxt_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmsxt_d0 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_side --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d0:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d0 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d1:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d1 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d2:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d2 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d3:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d3 --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_c --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_bsk_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_bsk_c --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_batch:hpu_msplit_3parts_3in3_1.axis_p2_p3_batch --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d0:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d0 --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d1:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d1 --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d2:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d2 --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d3:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d3 --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_c --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_bsk_c --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_side:hpu_msplit_3parts_2in3_1.axis_p3_p2_side --connectivity.slr hpu_msplit_3parts_1in3_1:SLR0 --connectivity.slr hpu_msplit_3parts_2in3_1:SLR1 --connectivity.slr hpu_msplit_3parts_3in3_1:SLR2 --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_trc:HBM[0] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ucore:HBM[1] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_pem_0:HBM[10] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_pem_1:HBM[11] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_glwe_0:HBM[12] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_0:HBM[2] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_1:HBM[3] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_2:HBM[4] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_3:HBM[5] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_4:HBM[6] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_5:HBM[7] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_6:HBM[8] --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_7:HBM[9] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_0:HBM[24] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_1:HBM[25] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_2:HBM[26] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_3:HBM[27] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_4:HBM[28] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_5:HBM[29] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_6:HBM[30] --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_7:HBM[31] --debug --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo --kernel_frequency 0:300 --link --optimize 0 --output /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin --platform xilinx_u55c_gen3x16_xdma_3_202210_1 --report_level 0 --save-temps --target hw --temp_dir /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin --vivado.param project.writeIntermediateCheckpoints=1 --vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/constraints/hpu_msplit_3parts_impl_opt_design_pre.xdc --vivado.prop run.synth_1.STEPS.SYNTH_DESIGN.ARGS.NO_SRLEXTRACT=true --vivado.prop run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-hier_fanout_limit 1024} --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high --vivado.prop run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AlternateCLBRouting - Options: --config /projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/cfg/hpu_msplit_3parts.cfg - --connectivity.nk hpu_msplit_3parts_1in3:1 - --connectivity.nk hpu_msplit_3parts_2in3:1 - --connectivity.nk hpu_msplit_3parts_3in3:1 - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_bsk_c - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_c - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmsxt_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmsxt_c - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_c - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_d:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_d - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d0:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d0 - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d1:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d1 - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_mmacc_side:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmacc_side - --connectivity.sc hpu_msplit_3parts_1in3_1.axis_p1_p2_batch:hpu_msplit_3parts_2in3_1.axis_p1_p2_batch - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_d0 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_c - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_bsk_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_bsk_c - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_side - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmsxt_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmsxt_d0 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_side - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d0:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d0 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d1:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d1 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d2:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d2 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d3:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d3 - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_c - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_bsk_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_bsk_c - --connectivity.sc hpu_msplit_3parts_2in3_1.axis_p2_p3_batch:hpu_msplit_3parts_3in3_1.axis_p2_p3_batch - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d0:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d0 - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d1:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d1 - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d2:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d2 - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d3:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d3 - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_c - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_bsk_c - --connectivity.sc hpu_msplit_3parts_3in3_1.axis_p3_p2_side:hpu_msplit_3parts_2in3_1.axis_p3_p2_side - --connectivity.slr hpu_msplit_3parts_1in3_1:SLR0 - --connectivity.slr hpu_msplit_3parts_2in3_1:SLR1 - --connectivity.slr hpu_msplit_3parts_3in3_1:SLR2 - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_trc:HBM[0] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ucore:HBM[1] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_pem_0:HBM[10] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_pem_1:HBM[11] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_glwe_0:HBM[12] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_0:HBM[2] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_1:HBM[3] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_2:HBM[4] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_3:HBM[5] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_4:HBM[6] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_5:HBM[7] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_6:HBM[8] - --connectivity.sp hpu_msplit_3parts_3in3_1.m_axi_bsk_7:HBM[9] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_0:HBM[24] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_1:HBM[25] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_2:HBM[26] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_3:HBM[27] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_4:HBM[28] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_5:HBM[29] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_6:HBM[30] - --connectivity.sp hpu_msplit_3parts_1in3_1.m_axi_ksk_7:HBM[31] - --debug - --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo - --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo - --input_files /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo - --kernel_frequency 0:300 - --link - --optimize 0 - --output /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin - --platform xilinx_u55c_gen3x16_xdma_3_202210_1 - --report_level 0 - --save-temps - --target hw - --temp_dir /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin - --vivado.param project.writeIntermediateCheckpoints=1 - --vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/constraints/hpu_msplit_3parts_impl_opt_design_pre.xdc - --vivado.prop run.synth_1.STEPS.SYNTH_DESIGN.ARGS.NO_SRLEXTRACT=true - --vivado.prop run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-hier_fanout_limit 1024} - --vivado.prop run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high - --vivado.prop run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AlternateCLBRouting -============================================================================== -User Added Key Value Pairs --------------------------- - -============================================================================== diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.link_summary b/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.link_summary deleted file mode 100644 index 3d71a76a6..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_msplit_3parts.xclbin.link_summary +++ /dev/null @@ -1,1377 +0,0 @@ - -{ - "thisFile": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin.link_summary", - "connectId": "", - "serverToken": "", - "timestamp": "0" -} - - -{ - "type": "ET_CmdStep", - "dateTimestamp": "Tue Mar 25 21:43:59 2025", - "timestampMillis": "1742935439546", - "buildStep": { - "cmdId": "e88f97ad-c344-46ae-84b0-dceb8646f1dd", - "name": "v++", - "logFile": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/link.steps.log", - "commandLine": "/opt/xilinx/Vitis/2024.1/bin/unwrapped/lnx64.o/v++ --vivado.prop \"run.__KERNEL__.{STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS}={-directive sdx_optimization_effort_high}\" --advanced.misc \"report=type report_timing_summary name impl_report_timing_summary_route_design_summary steps {route_design} runs {impl_1} options {-max_paths 10}\" --advanced.misc \"report=type report_timing_summary name impl_report_timing_summary_post_route_phys_opt_design_summary steps {post_route_phys_opt_design} runs {impl_1} options {-max_paths 10}\" -l -g -t hw --platform xilinx_u55c_gen3x16_xdma_3_202210_1 --save-temps --temp_dir /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin -o /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin --config /projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/cfg/hpu_msplit_3parts.cfg --vivado.prop run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/constraints/hpu_msplit_3parts_impl_opt_design_pre.xdc --kernel_frequency 0:300 /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo ", - "args": [ - "-l", - "-g", - "-t", - "hw", - "--platform", - "xilinx_u55c_gen3x16_xdma_3_202210_1", - "--save-temps", - "--temp_dir", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin", - "-o", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin", - "--config", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/cfg/hpu_msplit_3parts.cfg", - "--vivado.prop", - "run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/constraints/hpu_msplit_3parts_impl_opt_design_pre.xdc", - "--kernel_frequency", - "0:300", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo" - ], - "iniFiles": [ - { - "path": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/kernel/xilinx_u55c_gen3x16_xdma_3_202210_1/cfg/hpu_msplit_3parts.cfg", - "content": "# General configuration knobs\n# equivalent of --platform knob\n# platform=\n# equivalent of --log_dir knob\n# logdir=\n# equivalent of --report_dir knob\n# report_dir=\n# equivalent of --target knob\n#target=hw\n\n# Enable debug mode\ndebug=1\nsave-temps=1\n\n# Enable link mode\n# link=1\n\n# Vivado properties\n[vivado]\nparam=project.writeIntermediateCheckpoints=1\nprop=run.synth_1.STEPS.SYNTH_DESIGN.ARGS.NO_SRLEXTRACT=true\nprop=run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-hier_fanout_limit 1024}\nprop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high\nprop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AlternateCLBRouting\n\n[connectivity]\n# Number of CU per xo\nnk=hpu_msplit_3parts_1in3:1\nnk=hpu_msplit_3parts_2in3:1\nnk=hpu_msplit_3parts_3in3:1\n\n# SLR assignement\nslr=hpu_msplit_3parts_1in3_1:SLR0\nslr=hpu_msplit_3parts_2in3_1:SLR1\nslr=hpu_msplit_3parts_3in3_1:SLR2\n\n# Axi4 memory connection\nsp=hpu_msplit_3parts_1in3_1.m_axi_trc:HBM[0]\n# Note that if the following is modified, do not forget to change the ucore config\nsp=hpu_msplit_3parts_1in3_1.m_axi_ucore:HBM[1]\n\nsp=hpu_msplit_3parts_1in3_1.m_axi_pem_0:HBM[10]\nsp=hpu_msplit_3parts_1in3_1.m_axi_pem_1:HBM[11]\nsp=hpu_msplit_3parts_1in3_1.m_axi_glwe_0:HBM[12]\n\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_0:HBM[2]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_1:HBM[3]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_2:HBM[4]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_3:HBM[5]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_4:HBM[6]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_5:HBM[7]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_6:HBM[8]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_7:HBM[9]\n\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_0:HBM[24]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_1:HBM[25]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_2:HBM[26]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_3:HBM[27]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_4:HBM[28]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_5:HBM[29]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_6:HBM[30]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_7:HBM[31]\n\n\n# AXI stream\n# part1 -\u003e part2\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_bsk_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmsxt_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmsxt_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_d:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_d\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d0:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d0\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d1:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d1\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmacc_side:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmacc_side\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_batch:hpu_msplit_3parts_2in3_1.axis_p1_p2_batch\n\n# part2 -\u003e part1\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_bsk_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_bsk_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_side\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmsxt_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmsxt_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_side\n\n# part2 -\u003e part3\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d0:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d1:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d1\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d2:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d2\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d3:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d3\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_bsk_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_bsk_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_batch:hpu_msplit_3parts_3in3_1.axis_p2_p3_batch\n# part3 -\u003e part2\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d0:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d0\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d1:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d1\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d2:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d2\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d3:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d3\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_c\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_bsk_c\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_side:hpu_msplit_3parts_2in3_1.axis_p3_p2_side\n" - } - ], - "cwd": "/projects/baroux/Fpga/fpga_u55c_syn/xrt" - } -} - - -{ - "type": "ET_Status", - "dateTimestamp": "Tue Mar 25 21:43:59 2025", - "timestampMillis": "1742935439546", - "status": { - "cmdId": "e88f97ad-c344-46ae-84b0-dceb8646f1dd", - "state": "CS_RUNNING" - } -} - - -{ - "type": "ET_FlowMetaData", - "dateTimestamp": "Tue Mar 25 21:44:03 2025", - "timestampMillis": "1742935443837", - "buildSummary": { - "hardwarePlatform": "xilinx_u55c_gen3x16_xdma_3_202210_1.xpfm", - "hardwareDsa": "", - "platformDirectory": "/opt/xilinx/platforms/xilinx_u55c_gen3x16_xdma_3_202210_1", - "runtime": "OpenCL", - "systemConfig": "Linux", - "flow": "BF_LINK", - "target": "TT_HW", - "binaryContainer": { - "base": { - "type": "BT_UKNOWN", - "name": "hpu_msplit_3parts", - "file": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts.xclbin", - "reports": [], - "uuid": "" - }, - "kernels": [] - }, - "kernels": [ - { - "base": { - "type": "KERNEL", - "name": "hpu_msplit_3parts_1in3", - "file": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo", - "reports": [], - "uuid": "" - }, - "sources": [], - "psSources": [], - "cuNames": [ - "hpu_msplit_3parts_1in3_1" - ], - "type": "RTL", - "frequency": 0, - "freqUnits": "" - }, - { - "base": { - "type": "KERNEL", - "name": "hpu_msplit_3parts_2in3", - "file": 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SW Build 5074859 on 2024-05-20-23:21:20" - } -} - - -{ - "type": "ET_SubCmdStep", - "dateTimestamp": "Tue Mar 25 21:44:03 2025", - "timestampMillis": "1742935443951", - "buildStep": { - "cmdId": "33b1fc21-fde3-4a78-8553-b2ccdebcbbf2", - "name": "system_link", - "logFile": "", - "commandLine": "system_link --xo /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo --xo /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo --xo /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo -keep --config /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/syslinkConfig.ini --xpfm /opt/xilinx/platforms/xilinx_u55c_gen3x16_xdma_3_202210_1/xilinx_u55c_gen3x16_xdma_3_202210_1.xpfm --target hw --output_dir /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int --temp_dir /projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/sys_link", - "args": [ - "--xo", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_1in3.xo", - "--xo", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_2in3.xo", - "--xo", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/hpu_msplit_3parts_3in3.xo", - "-keep", - "--config", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/syslinkConfig.ini", - "--xpfm", - "/opt/xilinx/platforms/xilinx_u55c_gen3x16_xdma_3_202210_1/xilinx_u55c_gen3x16_xdma_3_202210_1.xpfm", - "--target", - "hw", - "--output_dir", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int", - "--temp_dir", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/sys_link" - ], - "iniFiles": [ - { - "path": "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/syslinkConfig.ini", - "content": "nk=hpu_msplit_3parts_1in3:1\nnk=hpu_msplit_3parts_2in3:1\nnk=hpu_msplit_3parts_3in3:1\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_bsk_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmsxt_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmsxt_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_c:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_c\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_ldg_d:hpu_msplit_3parts_2in3_1.axis_p1_p2_ldg_d\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d0:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d0\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmfeed_d1:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmfeed_d1\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_mmacc_side:hpu_msplit_3parts_2in3_1.axis_p1_p2_mmacc_side\nsc=hpu_msplit_3parts_1in3_1.axis_p1_p2_batch:hpu_msplit_3parts_2in3_1.axis_p1_p2_batch\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_bsk_c:hpu_msplit_3parts_1in3_1.axis_p2_p1_bsk_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_side\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmsxt_d0:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmsxt_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p1_mmacc_side:hpu_msplit_3parts_1in3_1.axis_p2_p1_mmacc_side\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d0:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d0\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d1:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d1\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d2:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d2\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_d3:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_d3\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_proc_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_proc_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_bsk_c:hpu_msplit_3parts_3in3_1.axis_p2_p3_bsk_c\nsc=hpu_msplit_3parts_2in3_1.axis_p2_p3_batch:hpu_msplit_3parts_3in3_1.axis_p2_p3_batch\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d0:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d0\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d1:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d1\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d2:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d2\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_d3:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_d3\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_proc_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_proc_c\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_bsk_c:hpu_msplit_3parts_2in3_1.axis_p3_p2_bsk_c\nsc=hpu_msplit_3parts_3in3_1.axis_p3_p2_side:hpu_msplit_3parts_2in3_1.axis_p3_p2_side\nsp=hpu_msplit_3parts_1in3_1.m_axi_trc:HBM[0]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ucore:HBM[1]\nsp=hpu_msplit_3parts_1in3_1.m_axi_pem_0:HBM[10]\nsp=hpu_msplit_3parts_1in3_1.m_axi_pem_1:HBM[11]\nsp=hpu_msplit_3parts_1in3_1.m_axi_glwe_0:HBM[12]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_0:HBM[2]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_1:HBM[3]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_2:HBM[4]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_3:HBM[5]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_4:HBM[6]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_5:HBM[7]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_6:HBM[8]\nsp=hpu_msplit_3parts_3in3_1.m_axi_bsk_7:HBM[9]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_0:HBM[24]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_1:HBM[25]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_2:HBM[26]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_3:HBM[27]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_4:HBM[28]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_5:HBM[29]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_6:HBM[30]\nsp=hpu_msplit_3parts_1in3_1.m_axi_ksk_7:HBM[31]\nslr=hpu_msplit_3parts_1in3_1:SLR0\nslr=hpu_msplit_3parts_2in3_1:SLR1\nslr=hpu_msplit_3parts_3in3_1:SLR2\n\n" - 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"args": [ - "-sdsl", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/sdsl.dat", - "-rtd", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/cf2sw.rtd", - "-nofilter", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/cf2sw_full.rtd", - "-xclbin", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/xclbin_orig.xml", - "-o", - "/projects/baroux/Fpga/fpga_u55c_syn/xrt/output/hw/_tmp_vitis_xclbin/link/int/xclbin_orig.1.xml" - ], - "iniFiles": [], - "cwd": "/projects/baroux/Fpga/fpga_u55c_syn/xrt" - } -} - - -{ - "type": "ET_Status", - "dateTimestamp": "Tue Mar 25 21:44:26 2025", - "timestampMillis": "1742935466923", - "status": { - "cmdId": "b848552b-dd20-45da-819c-c68595e8a991", - "state": "CS_RUNNING" - } -} - - -{ - "type": "ET_Status", - "dateTimestamp": "Tue Mar 25 21:44:38 2025", - "timestampMillis": "1742935478613", - "status": { - "cmdId": "b848552b-dd20-45da-819c-c68595e8a991", - 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"cmdId": "" - } -} - diff --git a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_regif_core.toml b/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_regif_core.toml deleted file mode 100644 index bdfc2b104..000000000 --- a/backends/tfhe-hpu-backend/config_store/u55c_gf64/hpu_regif_core.toml +++ /dev/null @@ -1,622 +0,0 @@ -# This is a sample example of register-map definition - -module_name="hpu_regif_core" -description="Hpu top-level register interface. Used by the host to retrieved RTL information, configure it and issue commands." -word_size_b = 32 -offset = 0x00 -range = 0x10000 -ext_pkg = ["axi_if_common_param_pkg", "axi_if_shell_axil_pkg"] - -# ===================================================================================================================== -[section.Xrt] -description="Vitis Required registers" -offset= 0x0 - - # Currently not in used -> Placeholder only -[section.Xrt.register.reserved] - description="Xrt reserved" - default={Cst=0x00} - owner="User" - read_access="Read" - write_access="Write" - -# ===================================================================================================================== -[section.info] -description="Contain all the RTL parameters used that have impact on associated SW" -offset= 0x10 - -[section.info.register.version] - description="RTL version" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="VERSION"} - -[section.info.register.ntt_architecture] - description="NTT architecture" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="NTT_CORE_ARCH"} - -[section.info.register.ntt_structure] - description="NTT structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.radix = { size_b=8, offset_b=0 , default={Param="R"}, description="NTT radix"} - field.psi = { size_b=8, offset_b=8 , default={Param="PSI"}, description="NTT psi"} - field.div = { size_b=8, offset_b=16, default={Param="BWD_PSI_DIV"}, description="NTT backward div"} - field.delta = { size_b=8, offset_b=24, default={Param="DELTA"}, description="NTT network delta (for wmm arch)"} - -[section.info.register.ntt_rdx_cut] - description="NTT radix cuts, in log2 unit (for gf64 arch)" - owner="Parameter" - read_access="Read" - write_access="None" - field.radix_cut0 = { size_b=4, offset_b=0 , default={Param="NTT_RDX_CUT_S_0"}, description="NTT radix cut #0"} - field.radix_cut1 = { size_b=4, offset_b=4 , default={Param="NTT_RDX_CUT_S_1"}, description="NTT radix cut #1"} - field.radix_cut2 = { size_b=4, offset_b=8 , default={Param="NTT_RDX_CUT_S_2"}, description="NTT radix cut #2"} - field.radix_cut3 = { size_b=4, offset_b=12, default={Param="NTT_RDX_CUT_S_3"}, description="NTT radix cut #3"} - field.radix_cut4 = { size_b=4, offset_b=16, default={Param="NTT_RDX_CUT_S_4"}, description="NTT radix cut #4"} - field.radix_cut5 = { size_b=4, offset_b=20, default={Param="NTT_RDX_CUT_S_5"}, description="NTT radix cut #5"} - field.radix_cut6 = { size_b=4, offset_b=24, default={Param="NTT_RDX_CUT_S_6"}, description="NTT radix cut #6"} - field.radix_cut7 = { size_b=4, offset_b=28, default={Param="NTT_RDX_CUT_S_7"}, description="NTT radix cut #7"} - -[section.info.register.ntt_pbs] - description="Maximum number of PBS in the NTT pipeline" - owner="Parameter" - read_access="Read" - write_access="None" - field.batch_pbs_nb = { size_b=8, offset_b=0 , default={Param="BATCH_PBS_NB"}, description="Maximum number of PBS in the NTT pipe"} - field.total_pbs_nb = { size_b=8, offset_b=8 , default={Param="TOTAL_PBS_NB"}, description="Maximum number of PBS stored in PEP buffer"} - -[section.info.register.ntt_modulo] - description="Code associated to the NTT prime" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="MOD_NTT_NAME"} - -[section.info.register.application] - description="Code associated with the application" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="APPLICATION_NAME"} - -[section.info.register.ks_structure] - description="Key-switch structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.x = { size_b=8, offset_b=0 , default={Param="LBX"}, description="Number of coefficients on X dimension"} - field.y = { size_b=8, offset_b=8 , default={Param="LBY"}, description="Number of coefficients on Y dimension"} - field.z = { size_b=8, offset_b=16, default={Param="LBZ"}, description="Number of coefficients on Z dimension"} - -[section.info.register.ks_crypto_param] - description="Key-switch crypto parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.mod_ksk_w = { size_b=8, offset_b=0 , default={Param="MOD_KSK_W"}, description="Width of KSK modulo"} - field.ks_l = { size_b=8, offset_b=8 , default={Param="KS_L"}, description="Number of KS decomposition level"} - field.ks_b = { size_b=8, offset_b=16, default={Param="KS_B_W"}, description="Width of KS decomposition base"} - -[section.info.register.regf_structure] - description="Register file structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.reg_nb = { size_b=8, offset_b=0 , default={Param="REGF_REG_NB"}, description="Number of registers in regfile"} - field.coef_nb = { size_b=8, offset_b=8 , default={Param="REGF_COEF_NB"}, description="Number of coefficients at regfile interface"} - -[section.info.register.isc_structure] - description="Instruction scheduler structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.depth = { size_b=8, offset_b=0 , default={Param="ISC_DEPTH"}, description="Number of slots in ISC lookahead buffer."} - field.min_iop_size = { size_b=8, offset_b=8 , default={Param="MIN_IOP_SIZE"}, description="Minimum number of DOp per IOp to prevent sync_id overflow."} - -[section.info.register.pe_properties] - description="Processing elements parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.alu_nb = { size_b=8, offset_b=24 , default={Param="PEA_ALU_NB"}, description="Number of coefficients processed in parallel in pe_alu"} - field.pep_regf_period = { size_b=8, offset_b=16 , default={Param="PEP_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEP and regfile"} - field.pem_regf_period = { size_b=8, offset_b=8 , default={Param="PEM_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEM and regfile"} - field.pea_regf_period = { size_b=8, offset_b=0 , default={Param="PEA_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEA and regfile"} - -[section.info.register.bsk_structure] - description="BSK manager structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.bsk_cut_nb = { size_b=8, offset_b=8 , default={Param="BSK_CUT_NB"}, description="BSK cut nb"} - -[section.info.register.ksk_structure] - description="KSK manager structure parameters" - owner="Parameter" - read_access="Read" - write_access="None" - field.ksk_cut_nb = { size_b=8, offset_b=8 , default={Param="KSK_CUT_NB"}, description="KSK cut nb"} - -[section.info.register.hbm_axi4_nb] - description="Number of AXI4 connections to HBM" - owner="Parameter" - read_access="Read" - write_access="None" - field.bsk_pc = { size_b=8, offset_b=0 , default={Param="BSK_PC"}, description="Number of HBM connections for BSK"} - field.ksk_pc = { size_b=8, offset_b=8, default={Param="KSK_PC"}, description="Number of HBM connections for KSK"} - field.pem_pc = { size_b=8, offset_b=16, default={Param="PEM_PC"}, description="Number of HBM connections for ciphertexts (PEM)"} - field.glwe_pc = { size_b=8, offset_b=24, default={Param="GLWE_PC"}, description="Number of HBM connections for GLWE"} - -[section.info.register.hbm_axi4_dataw_pem] - description="Ciphertext HBM AXI4 connection data width" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="AXI4_PEM_DATA_W"} - -[section.info.register.hbm_axi4_dataw_glwe] - description="GLWE HBM AXI4 connection data width" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="AXI4_GLWE_DATA_W"} - -[section.info.register.hbm_axi4_dataw_bsk] - description="BSK HBM AXI4 connection data width" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="AXI4_BSK_DATA_W"} - -[section.info.register.hbm_axi4_dataw_ksk] - description="KSK HBM AXI4 connection data width" - owner="Parameter" - read_access="Read" - write_access="None" - default={Param="AXI4_KSK_DATA_W"} - -# ===================================================================================================================== -[section.bpip] -offset= 0x200 -description="BPIP configuration" - -[section.bpip.register.use] - description="(1) Use BPIP mode, (0) use IPIP mode (default)" - owner="User" - read_access="Read" - write_access="Write" - field.use_bpip = { size_b=1, offset_b=0 , default={Cst=1}, description="use"} - field.use_opportunism = { size_b=1, offset_b=1 , default={Cst=0}, description="use opportunistic PBS flush"} - -[section.bpip.register.timeout] - description="Timeout for BPIP mode" - owner="User" - read_access="Read" - write_access="Write" - default={Cst=0xffffffff} - -# ===================================================================================================================== -[section.hbm_axi4_addr_1in3] -offset= 0x400 -description="HBM AXI4 connection address offset" - -[section.hbm_axi4_addr_1in3.register.ct] - description="Address offset for each ciphertext HBM AXI4 connection" - owner="User" - read_access="Read" - write_access="Write" - duplicate=["_pc0_lsb", "_pc0_msb","_pc1_lsb", "_pc1_msb"] - -[section.hbm_axi4_addr_1in3.register.glwe] - description="Address offset for each GLWE HBM AXI4 connection" - owner="User" - read_access="Read" - write_access="Write" - duplicate=["_pc0_lsb", "_pc0_msb"] - - -[section.hbm_axi4_addr_1in3.register.ksk] - description="Address offset for each KSK HBM AXI4 connection" - owner="User" - read_access="Read" - write_access="Write" - duplicate=["_pc0_lsb", "_pc0_msb", "_pc1_lsb", "_pc1_msb", "_pc2_lsb", "_pc2_msb", "_pc3_lsb", "_pc3_msb", "_pc4_lsb", "_pc4_msb", "_pc5_lsb", "_pc5_msb", "_pc6_lsb", "_pc6_msb", "_pc7_lsb", "_pc7_msb"] - - [section.hbm_axi4_addr_1in3.register.trc] - description="Address offset for each trace HBM AXI4 connection" - owner="User" - read_access="Read" - write_access="Write" - duplicate=["_pc0_lsb", "_pc0_msb"] - - -# ===================================================================================================================== -[section.hbm_axi4_addr_3in3] -description="HBM AXI4 connection address offset" - -[section.hbm_axi4_addr_3in3.register.bsk] - description="Address offset for each BSK HBM AXI4 connection" - owner="User" - read_access="Read" - write_access="Write" - duplicate=["_pc0_lsb", "_pc0_msb", "_pc1_lsb", "_pc1_msb", "_pc2_lsb", "_pc2_msb", "_pc3_lsb", "_pc3_msb", "_pc4_lsb", "_pc4_msb", "_pc5_lsb", "_pc5_msb", "_pc6_lsb", "_pc6_msb", "_pc7_lsb", "_pc7_msb"] - - -# ===================================================================================================================== -[section.status_1in3] -description="HPU status of part 1in3" -offset= 0x800 - -[section.status_1in3.register.error] - description="Error register (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - field.pbs = { size_b=32, offset_b=0 , default={Cst=0}, description="HPU error part 1in3"} - -# ===================================================================================================================== -[section.status_3in3] -description="HPU status of parts 2in3 and 3in3" - -[section.status_3in3.register.error] - description="Error register (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - field.pbs = { size_b=32, offset_b=0 , default={Cst=0}, description="HPU error part 3in3"} - -# ===================================================================================================================== -[section.ksk_avail] -description="KSK availability configuration" -offset= 0x1000 - -[section.ksk_avail.register.avail] - description="KSK available bit" - owner="User" - read_access="Read" - write_access="Write" - field.avail = { size_b=1, offset_b=0 , default={Cst=0}, description="avail"} - -[section.ksk_avail.register.reset] - description="KSK reset sequence" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - field.request = { size_b=1, offset_b=0 , default={Cst=0}, description="request"} - field.done = { size_b=1, offset_b=31 , default={Cst=0}, description="done"} - -# ===================================================================================================================== -[section.bsk_avail] -description="BSK availability configuration" - -[section.bsk_avail.register.avail] - description="BSK available bit" - owner="User" - read_access="Read" - write_access="Write" - field.avail = { size_b=1, offset_b=0 , default={Cst=0}, description="avail"} - -[section.bsk_avail.register.reset] - description="BSK reset sequence" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - field.request = { size_b=1, offset_b=0 , default={Cst=0}, description="request"} - field.done = { size_b=1, offset_b=31 , default={Cst=0}, description="done"} - -# ===================================================================================================================== -[section.runtime_1in3] -description="Runtime information" -offset= 0x2000 - -[section.runtime_1in3.register.pep_cmux_loop] - description="PEP: CMUX iteration loop number" - owner="Kernel" - read_access="Read" - write_access="None" - field.br_loop = { size_b=15, offset_b=0 , default={Cst=0}, description="PBS current BR-loop"} - field.br_loop_c = { size_b=1, offset_b=15 , default={Cst=0}, description="PBS current BR-loop parity"} - field.ks_loop = { size_b=15, offset_b=16 , default={Cst=0}, description="KS current KS-loop"} - field.ks_loop_c = { size_b=1, offset_b=31 , default={Cst=0}, description="KS current KS-loop parity"} - -[section.runtime_1in3.register.pep_pointer_0] - description="PEP: pointers (part 1)" - owner="Kernel" - read_access="Read" - write_access="None" - field.pool_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP pool_rp"} - field.pool_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP pool_wp"} - field.ldg_pt = { size_b=8, offset_b=16 , default={Cst=0}, description="PEP ldg_pt"} - field.ldb_pt = { size_b=8, offset_b=24 , default={Cst=0}, description="PEP ldb_pt"} - -[section.runtime_1in3.register.pep_pointer_1] - description="PEP: pointers (part 2)" - owner="Kernel" - read_access="Read" - write_access="None" - field.ks_in_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP ks_in_rp"} - field.ks_in_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP ks_in_wp"} - field.ks_out_rp = { size_b=8, offset_b=16 , default={Cst=0}, description="PEP ks_out_rp"} - field.ks_out_wp = { size_b=8, offset_b=24 , default={Cst=0}, description="PEP ks_out_wp"} - -[section.runtime_1in3.register.pep_pointer_2] - description="PEP: pointers (part 3)" - owner="Kernel" - read_access="Read" - write_access="None" - field.pbs_in_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP pbs_in_rp"} - field.pbs_in_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP pbs_in_wp"} - field.ipip_flush_last_pbs_in_loop = { size_b=16, offset_b=16 , default={Cst=0}, description="PEP IPIP flush last pbs_in_loop"} - -[section.runtime_1in3.register.isc_latest_instruction] - description="ISC: 4 latest instructions received ([0] is the most recent)" - owner="Kernel" - read_access="Read" - write_access="None" - duplicate=["_0","_1","_2","_3"] - -[section.runtime_1in3.register.pep_seq_bpip_batch_cnt] - description="PEP: BPIP batch counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_bpip_batch_flush_cnt] - description="PEP: BPIP batch triggered by a flush counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_bpip_batch_timeout_cnt] - description="PEP: BPIP batch triggered by a timeout counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_bpip_waiting_batch_cnt] - description="PEP: BPIP batch that waits the trigger counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_bpip_batch_filling_cnt] - description="PEP: Count batch with filled with a given number of CT (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - duplicate=["_1","_2","_3","_4","_5","_6","_7","_8","_9","_10","_11","_12","_13","_14","_15","_16"] - -[section.runtime_1in3.register.pep_seq_ld_ack_cnt] - description="PEP: load BLWE ack counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_cmux_not_full_batch_cnt] - description="PEP: not full batch CMUX counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_seq_ipip_flush_cnt] - description="PEP: IPIP flush CMUX counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_ldb_rcp_dur] - description="PEP: load BLWE reception max duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_ldg_req_dur] - description="PEP: load GLWE request max duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_ldg_rcp_dur] - description="PEP: load GLWE reception max duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_load_ksk_rcp_dur] - description="PEP: load KSK slice reception max duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - duplicate=["_pc0","_pc1","_pc2","_pc3","_pc4","_pc5","_pc6","_pc7","_pc8","_pc9","_pc10","_pc11","_pc12","_pc13","_pc14","_pc15"] - - -[section.runtime_1in3.register.pep_mmacc_sxt_rcp_dur] - description="PEP: MMACC SXT reception duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_mmacc_sxt_req_dur] - description="PEP: MMACC SXT request duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_mmacc_sxt_cmd_wait_b_dur] - description="PEP: MMACC SXT command wait for b duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_inst_cnt] - description="PEP: input instruction counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pep_ack_cnt] - description="PEP: instruction acknowledge counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pem_load_inst_cnt] - description="PEM: load input instruction counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pem_load_ack_cnt] - description="PEM: load instruction acknowledge counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pem_store_inst_cnt] - description="PEM: store input instruction counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pem_store_ack_cnt] - description="PEM: store instruction acknowledge counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pea_inst_cnt] - description="PEA: input instruction counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pea_ack_cnt] - description="PEA: instruction acknowledge counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.isc_inst_cnt] - description="ISC: input instruction counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.isc_ack_cnt] - description="ISC: instruction acknowledge counter (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.runtime_1in3.register.pem_load_info_0] - description="PEM: load first data)" - owner="Kernel" - read_access="Read" - write_access="None" - duplicate=["_pc0_0","_pc0_1","_pc0_2","_pc0_3","_pc1_0","_pc1_1","_pc1_2","_pc1_3"] - -[section.runtime_1in3.register.pem_load_info_1] - description="PEM: load first address" - owner="Kernel" - read_access="Read" - write_access="None" - duplicate=["_pc0_lsb","_pc0_msb","_pc1_lsb","_pc1_msb"] - -[section.runtime_1in3.register.pem_store_info_0] - description="PEM: store info 0)" - owner="Kernel" - read_access="Read" - write_access="None" - field.cmd_vld = { size_b=1, offset_b=0 , default={Cst=0}, description="PEM_ST cmd vld"} - field.cmd_rdy = { size_b=1, offset_b=1 , default={Cst=0}, description="PEM_ST cmd rdy"} - field.pem_regf_rd_req_vld = { size_b=1, offset_b=2 , default={Cst=0}, description="PEM_ST pem_regf_rd_req_vld"} - field.pem_regf_rd_req_rdy = { size_b=1, offset_b=3 , default={Cst=0}, description="PEM_ST pem_regf_rd_req_rdy"} - field.brsp_fifo_in_vld = { size_b=4, offset_b=4 , default={Cst=0}, description="PEM_ST brsp_fifo_in_vld"} - field.brsp_fifo_in_rdy = { size_b=4, offset_b=8 , default={Cst=0}, description="PEM_ST brsp_fifo_in_rdy"} - field.rcp_fifo_in_vld = { size_b=4, offset_b=12 , default={Cst=0}, description="PEM_ST rcp_fifo_in_vld"} - field.rcp_fifo_in_rdy = { size_b=4, offset_b=16 , default={Cst=0}, description="PEM_ST rcp_fifo_in_rdy"} - field.r2_axi_vld = { size_b=4, offset_b=20 , default={Cst=0}, description="PEM_ST r2_axi_vld"} - field.r2_axi_rdy = { size_b=4, offset_b=24 , default={Cst=0}, description="PEM_ST r2_axi_rdy"} - field.c0_enough_location = { size_b=4, offset_b=28 , default={Cst=0}, description="PEM_ST c0_enough_location"} - -[section.runtime_1in3.register.pem_store_info_1] - description="PEM: store info 1" - owner="Kernel" - read_access="Read" - write_access="None" - field.s0_cmd_vld = { size_b=4, offset_b=0 , default={Cst=0}, description="PEM_ST s0_cmd_vld"} - field.s0_cmd_rdy = { size_b=4, offset_b=4 , default={Cst=0}, description="PEM_ST s0_cmd_rdy"} - field.m_axi_bvalid = { size_b=4, offset_b=8 , default={Cst=0}, description="PEM_ST m_axi_bvalid"} - field.m_axi_bready = { size_b=4, offset_b=12 , default={Cst=0}, description="PEM_ST m_axi_bready"} - field.m_axi_wvalid = { size_b=4, offset_b=16 , default={Cst=0}, description="PEM_ST m_axi_wvalid"} - field.m_axi_wready = { size_b=4, offset_b=20 , default={Cst=0}, description="PEM_ST m_axi_wready"} - field.m_axi_awvalid = { size_b=4, offset_b=24 , default={Cst=0}, description="PEM_ST m_axi_awvalid"} - field.m_axi_awready = { size_b=4, offset_b=28 , default={Cst=0}, description="PEM_ST m_axi_awready"} - -[section.runtime_1in3.register.pem_store_info_2] - description="PEM: store info 2" - owner="Kernel" - read_access="Read" - write_access="None" - field.c0_free_loc_cnt = { size_b=16, offset_b=0 , default={Cst=0}, description="PEM_ST c0_free_loc_cnt"} - field.brsp_bresp_cnt = { size_b=16, offset_b=16 , default={Cst=0}, description="PEM_ST brsp_bresp_cnt"} - -[section.runtime_1in3.register.pem_store_info_3] - description="PEM: store info 3" - owner="Kernel" - read_access="Read" - write_access="None" - field.brsp_ack_seen = { size_b=16, offset_b=0 , default={Cst=0}, description="PEM_ST brsp_ack_seen"} - field.c0_cmd_cnt = { size_b=8, offset_b=16 , default={Cst=0}, description="PEM_ST c0_cmd_cnt"} - - -# ===================================================================================================================== -[section.runtime_3in3] -description="Runtime information" - -[section.runtime_3in3.register.pep_load_bsk_rcp_dur] - description="PEP: load BSK slice reception max duration (Could be reset by user)" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - duplicate=["_pc0","_pc1","_pc2","_pc3","_pc4","_pc5","_pc6","_pc7","_pc8","_pc9","_pc10","_pc11","_pc12","_pc13","_pc14","_pc15"] - -[section.runtime_3in3.register.pep_bskif_req_info_0] - description="PEP: BSK_IF: requester info 0" - owner="Kernel" - read_access="Read" - write_access="None" - field.req_br_loop_rp = { size_b=16, offset_b=0 , default={Cst=0}, description="PEP BSK_IF requester BSK read pointer"} - field.req_br_loop_wp = { size_b=16, offset_b=16 , default={Cst=0}, description="PEP BSK_IF requester BSK write pointer"} - -[section.runtime_3in3.register.pep_bskif_req_info_1] - description="PEP: BSK_IF: requester info 0" - owner="Kernel" - read_access="Read" - write_access="None" - field.req_prf_br_loop = { size_b=16, offset_b=0 , default={Cst=0}, description="PEP BSK_IF requester BSK prefetch pointer"} - field.req_parity = { size_b=1, offset_b=16 , default={Cst=0}, description="PEP BSK_IF requester BSK pointer parity"} - field.req_assigned = { size_b=1, offset_b=31 , default={Cst=0}, description="PEP BSK_IF requester assignment"} - -# ===================================================================================================================== -[section.WorkAck] -description="Purpose of this section" -offset= 0x8000 - -[section.WorkAck.register.workq] - description="Insert work in workq and read status" - owner="Kernel" - read_access="Read" - write_access="WriteNotify" - -[section.WorkAck.register.ackq] - description="Pop ack from in ackq" - owner="Kernel" - read_access="ReadNotify" - write_access="None" diff --git a/backends/tfhe-hpu-backend/src/ffi/mod.rs b/backends/tfhe-hpu-backend/src/ffi/mod.rs index 94b4bdfac..cb370cc35 100644 --- a/backends/tfhe-hpu-backend/src/ffi/mod.rs +++ b/backends/tfhe-hpu-backend/src/ffi/mod.rs @@ -2,7 +2,7 @@ //! The aim is to completely hide underlying specificities and enable compile-time //! swapping. //! -//! Mainly replacing Xrt(u55c)/V80 by a simulation interface to ease CI +//! Mainly replacing V80 by a simulation interface to ease CI use crate::interface::FFIMode; diff --git a/setup_hpu.sh b/setup_hpu.sh index 5eac1f64d..d90a9cbe4 100644 --- a/setup_hpu.sh +++ b/setup_hpu.sh @@ -8,7 +8,6 @@ HPU_MOCKUP_DIR=$CUR_SCRIPT_DIR/mockups/tfhe-hpu-mockup # Default default bitstream # Available options are: # * sim: use with the mockup (i.e simulation) -# * u55c: use with u55c (latest bitstream with gf64 config) # * v80: use with v80 (i.e should specify pcie-dev flag [zamav80: 01, srvzama: 21] HPU_CONFIG="sim" @@ -35,7 +34,7 @@ do case "$1" in -h|--help) echo "Available options are:" - echo " * --config: target configuration [sim, u55c_gf64, v80]" + echo " * --config: target configuration [sim, v80]" echo " * --rust-log: Specify rust verbosity [Cf. tracing]" echo " * --pcie-dev: target pcie device [Warn: v80 only]" return 0 @@ -111,15 +110,6 @@ if [[ "$HPU_CONFIG" == sim* ]]; then export HPU_MOCKUP_DIR fi -# U55c specific init ########################################################### -if [[ "$HPU_CONFIG" == u55c* ]]; then - # Setup Xrt for low-level xfer with u55c - XRT_SETUP=/opt/xilinx/xrt/setup.sh - if [[ -f $XRT_SETUP ]]; then - source $XRT_SETUP - fi -fi - # V80 specific init ########################################################### if [[ "$HPU_CONFIG" == v80* ]]; then export V80_PCIE_DEV diff --git a/tfhe/tests/hpu.rs b/tfhe/tests/hpu.rs index cc891391c..a1cd98237 100644 --- a/tfhe/tests/hpu.rs +++ b/tfhe/tests/hpu.rs @@ -88,9 +88,6 @@ mod hpu_test { (std::sync::Mutex::new(hpu_device), cks, key_seed) } - // NB: Currently u55c didn't check for workq overflow. - // -> Use default value < queue depth to circumvent this limitation - // NB': This is only for u55c, on V80 user could set HPU_TEST_ITER to whatever value he want const DEFAULT_TEST_ITER: usize = 32; macro_rules! hpu_testbundle {