mirror of
https://github.com/zama-ai/tfhe-rs.git
synced 2026-01-09 22:57:59 -05:00
chore(hpu): Remove all references to U55C, which is not supported anymore.
This commit is contained in:
JJ-hw
@@ -1,6 +0,0 @@
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# Fpga version
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Built with the following command: (i.e. xrt/run_syn_hpu_msplit_3parts_64b.sh)
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```
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just zaxl-build hpu_msplit_3parts 3 "0:300" "-F TOP_MSPLIT TOP_MSPLIT_1 -F TOP_BATCH TOP_BATCH_TOPhpu_BPBS8_TPBS32 -F TOP_PCMAX TOP_PCMAX_pem2_glwe1_bsk8_ksk8 -F TOP_PC TOP_PC_pem2_glwe1_bsk4_ksk4 -F APPLICATION APPLI_msg2_carry2 -F NTT_MOD NTT_MOD_goldilocks -F NTT_CORE_ARCH NTT_CORE_ARCH_gf64 -F NTT_CORE_R_PSI NTT_CORE_R2_PSI16 -F NTT_CORE_RDX_CUT NTT_CORE_RDX_CUT_n5c5c1 -F NTT_CORE_DIV NTT_CORE_DIV_1 -F BSK_SLOT_CUT BSK_SLOT8_CUT4 -F KSK_SLOT_CUT KSK_SLOT8_CUT4 -F KSLB KSLB_x2y32z3 -F HPU_PART HPU_PART_gf64 -F AXI_DATA_W AXI_DATA_W_512" "1:${PROJECT_DIR}/hw/output/micro_code/ucore_fw.elf" 'D:MEMORY_FILE_PATH=\\\"${PROJECT_DIR}/hw/\\\"' | tee build_out.log
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```
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@@ -1,15 +0,0 @@
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# CUST_0
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# Simple IOp to check the xfer between Hpu/Cpu
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# Construct constant in dest slot -> 249 (0xf9)
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SUB R0 R0 R0
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ADDS R0 R0 1
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ST TD[0].0 R0
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SUB R1 R1 R1
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ADDS R1 R1 2
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ST TD[0].1 R1
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SUB R2 R2 R2
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ADDS R2 R2 3
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ST TD[0].2 R2
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SUB R3 R3 R3
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ADDS R3 R3 3
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ST TD[0].3 R3
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@@ -1,11 +0,0 @@
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# CUST_1
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# Simple IOp to check the xfer between Hpu/Cpu
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# Dest <- Src_a
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LD R0 TS[0].0
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LD R1 TS[0].1
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LD R2 TS[0].2
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LD R3 TS[0].3
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ST TD[0].0 R0
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ST TD[0].1 R1
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ST TD[0].2 R2
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ST TD[0].3 R3
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@@ -1,25 +0,0 @@
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; CUST_8
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; Simple IOp to check the ALU operation
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; Dst[0].0 <- Src[0].0 + Src[1].0
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LD R1 TS[0].0
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LD R2 TS[1].0
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ADD R0 R1 R2
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ST TD[0].0 R0
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; Dst[0].1 <- Src[0].1 + Src[1].1
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LD R5 TS[0].1
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LD R6 TS[1].1
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ADD R4 R5 R6
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ST TD[0].2 R4
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; Dst[0].2 <- Src[0].2 + Src[1].2
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LD R9 TS[0].2
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LD R10 TS[1].2
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ADD R8 R9 R10
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ST TD[0].2 R8
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; Dst[0].3 <- Src[0].3 + Src[1].3
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LD R13 TS[0].3
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LD R14 TS[1].3
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ADD R12 R13 R14
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ST TD[0].3 R0
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@@ -1,6 +0,0 @@
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# CUST_16
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# Simple IOp to check PBS behavior
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# Dest <- PBSNone(Src_a.0)
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LD R0 TS[0].0
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PBS_F R0 R0 PbsNone
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ST TD[0].0 R0
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@@ -1,15 +0,0 @@
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# CUST_17
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# Simple IOp to check PBS behavior
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# Dest <- PBSNone(Src_a)
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LD R0 TS[0].0
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PBS R0 R0 PbsNone
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ST TD[0].0 R0
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LD R1 TS[0].1
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PBS R1 R1 PbsNone
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ST TD[0].1 R1
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LD R2 TS[0].2
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PBS R2 R2 PbsNone
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ST TD[0].2 R2
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LD R3 TS[0].3
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PBS_F R3 R3 PbsNone
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ST TD[0].3 R3
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@@ -1,23 +0,0 @@
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; CUST_18
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; Simple IOp to check extraction pattern
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; Correct result:
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; * Dst[0,1] <- Src[0][0,1]
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; * Dst[2,3] <- Src[1][0,1]
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; Pack Src[0][0,1] with a Mac and extract Carry/Msg in Dst[0][0,1]
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LD R0 TS[0].0
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LD R1 TS[0].1
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MAC R3 R1 R0 4
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PBS R4 R3 PbsMsgOnly
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PBS R5 R3 PbsCarryInMsg
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ST TD[0].0 R4
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ST TD[0].1 R5
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; Pack Src[1][0,1] with a Mac and extract Carry/Msg in Dst[0][2,3]
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LD R10 TS[1].0
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LD R11 TS[1].1
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MAC R13 R11 R10 4
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PBS R14 R13 PbsMsgOnly
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PBS R15 R13 PbsCarryInMsg
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ST TD[0].2 R14
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ST TD[0].3 R15
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@@ -1,19 +0,0 @@
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; CUST_19
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; Simple IOp to check PbsMl2
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; Correct result:
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; * Dst[0][0] <- Src[0][0]
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; * Dst[0][1] <- 0
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; * Dst[0][2] <- Src[0][0] +1
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; * Dst[0][3] <- 0
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; i.e Cust_19(0x2) => 0x32
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; Construct a 0 for destination padding
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SUB R16 R16 R16
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; Apply PbsMl2 on Src[0] result goes in dest[0][0-3] (0-padded)
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LD R0 TS[0].0
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PBS_ML2_F R0 R0 PbsTestMany2
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ST TD[0].0 R0
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ST TD[0].1 R16
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ST TD[0].2 R1
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ST TD[0].3 R16
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@@ -1,11 +0,0 @@
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# CUST_2
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# Simple IOp to check the xfer between Hpu/Cpu
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# Dest <- Src_b
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LD R0 TS[1].0
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LD R1 TS[1].1
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LD R2 TS[1].2
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LD R3 TS[1].3
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ST TD[0].0 R0
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ST TD[0].1 R1
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ST TD[0].2 R2
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ST TD[0].3 R3
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@@ -1,22 +0,0 @@
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; CUST_20
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; Simple IOp to check PbsMl4
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; Correct result:
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; * Dst[0][0] <- Src[0][0]
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; * Dst[0][1] <- Src[0][0] +1
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; * Dst[0][2] <- Src[0][0] +2
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; * Dst[0][3] <- Src[0][0] +3
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; i.e Cust_20(0x0) => 0xe4
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SUB R16 R16 R16
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ST TD[0].0 R0
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ST TD[0].1 R0
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ST TD[0].2 R0
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ST TD[0].3 R0
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; Apply PbsMl4 on Src[0] result goes in dest[0][0-3]
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LD R0 TS[0].0
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PBS_ML4_F R0 R0 PbsTestMany4
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ST TD[0].0 R0
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ST TD[0].1 R1
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ST TD[0].2 R2
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ST TD[0].3 R3
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@@ -1,24 +0,0 @@
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; CUST_21
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; Simple IOp to check PbsMl8
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; WARN: This operation required 16b ct width
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; Correct result:
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; * Dst[0][0] <- Src[0][0]
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; * Dst[0][1] <- Src[0][0] +1
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; * Dst[0][2] <- Src[0][0] +2
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; * Dst[0][3] <- Src[0][0] +3
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; * Dst[0][4] <- Src[0][0] +4
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; * Dst[0][5] <- Src[0][0] +5
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; * Dst[0][6] <- Src[0][0] +6
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; * Dst[0][7] <- Src[0][0] +7
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; Apply PbsMl8 on Src[0] result goes in dest[0][0-7]
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LD R0 TS[0].0
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PBS_ML8_F R0 R0 PbsTestMany8
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ST TD[0].0 R0
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ST TD[0].1 R1
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ST TD[0].2 R2
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ST TD[0].3 R3
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ST TD[0].4 R4
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ST TD[0].5 R5
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ST TD[0].6 R6
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ST TD[0].7 R7
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@@ -1,16 +0,0 @@
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# CUST_3
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# Simple IOp to check isc behavior
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# Generate obvious deps and check that isc correctly issued the dop
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# Correct result must bu Dest <- Src[0]
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LD R0 TS[0].0
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LD R1 TS[0].1
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LD R2 TS[0].2
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LD R3 TS[0].3
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PBS R4 R0 PbsNone
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ST TD[0].0 R4
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PBS R4 R1 PbsNone
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ST TD[0].1 R4
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PBS R4 R2 PbsNone
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ST TD[0].2 R4
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PBS_F R4 R3 PbsNone
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ST TD[0].3 R4
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@@ -1,19 +0,0 @@
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; CUST_8
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; Simple IOp to check the ALU operation
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; Dst[0].0 <- Src[0].0 + Src[1].0
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LD R1 TS[0].0
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LD R2 TS[1].0
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ADD R0 R1 R2
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ST TD[0].0 R0
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; Dst[0].1 <- Src[0].1 - Src[1].1
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LD R5 TS[0].1
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LD R6 TS[1].1
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SUB R4 R5 R6
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ST TD[0].1 R4
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; Dst[0].2 <- Src[0].2 + (Src[1].2 *4)
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LD R9 TS[0].2
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LD R10 TS[1].2
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MAC R8 R9 R10 4
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ST TD[0].2 R8
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@@ -1,21 +0,0 @@
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; CUST_9
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; Simple IOp to check the ALU Scalar operation
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; Dst[0].0 <- Src[0].0 + Imm[0].0
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LD R1 TS[0].0
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ADDS R0 R1 TI[0].0
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ST TD[0].0 R0
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; Dst[0].1 <- Src[0].1 - Imm[0].1
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LD R5 TS[0].1
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SUBS R4 R5 TI[0].1
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ST TD[0].1 R4
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; Dst[0].2 <- Imm[0].2 - Src[0].2
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LD R9 TS[0].2
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SSUB R8 R9 TI[0].2
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ST TD[0].2 R8
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; Dst[0].3 <- Src[0].3 * Imm[0].3
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LD R13 TS[0].3
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MULS R12 R13 TI[0].3
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ST TD[0].3 R12
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@@ -1,98 +0,0 @@
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[fpga]
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regmap=["${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core.toml"]
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polling_us=10
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[fpga.ffi.Xrt]
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id= 0
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kernel= "hpu_msplit_3parts_1in3"
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xclbin="${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_msplit_3parts.xclbin"
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[rtl]
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bpip_use = true
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bpip_use_opportunism = true
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bpip_timeout = 100_000
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[board]
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ct_mem = 4096
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ct_pc = [
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{Hbm= {pc=10}},
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{Hbm= {pc=11}},
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]
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heap_size = 3584
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lut_mem = 256
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lut_pc = {Hbm={pc=12}}
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fw_size= 65536
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fw_pc = {Hbm={pc=1}}
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bsk_pc = [
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{Hbm={pc=2}},
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{Hbm={pc=3}},
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{Hbm={pc=4}},
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{Hbm={pc=5}},
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{Hbm={pc=6}},
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{Hbm={pc=7}},
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{Hbm={pc=8}},
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{Hbm={pc=9}}
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]
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ksk_pc = [
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{Hbm={pc=24}},
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{Hbm={pc=25}},
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{Hbm={pc=26}},
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{Hbm={pc=27}},
|
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{Hbm={pc=28}},
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{Hbm={pc=29}},
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{Hbm={pc=30}},
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{Hbm={pc=31}}
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]
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trace_pc = {Hbm={pc=0}}
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trace_depth = 4 # In MB
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|
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[firmware]
|
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implementation = "Llt"
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integer_w=[4,6,8,10,12,14,16,32,64,128]
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min_batch_size = 6
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kogge_cfg = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/kogge_cfg.toml"
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|
||||||
custom_iop.'IOP[0]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_0.asm"
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||||||
custom_iop.'IOP[1]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_1.asm"
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||||||
custom_iop.'IOP[2]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_2.asm"
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||||||
custom_iop.'IOP[3]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_3.asm"
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||||||
custom_iop.'IOP[8]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_8.asm"
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||||||
custom_iop.'IOP[9]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_9.asm"
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||||||
custom_iop.'IOP[16]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_16.asm"
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||||||
custom_iop.'IOP[17]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_17.asm"
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||||||
custom_iop.'IOP[18]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_18.asm"
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custom_iop.'IOP[19]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_19.asm"
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custom_iop.'IOP[20]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_20.asm"
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||||||
custom_iop.'IOP[21]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_21.asm"
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||||||
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[firmware.op_cfg.default]
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|
||||||
fill_batch_fifo = true
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||||||
min_batch_size = false
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|
||||||
use_tiers = false
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|
||||||
flush_behaviour = "Patient"
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|
||||||
flush = true
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|
||||||
|
|
||||||
[firmware.op_cfg.by_op.MUL]
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|
||||||
fill_batch_fifo = false
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|
||||||
min_batch_size = false
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|
||||||
use_tiers = false
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|
||||||
flush_behaviour = "Patient"
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|
||||||
flush = true
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|
||||||
|
|
||||||
[firmware.op_cfg.by_op.MULS]
|
|
||||||
fill_batch_fifo = false
|
|
||||||
min_batch_size = false
|
|
||||||
use_tiers = false
|
|
||||||
flush_behaviour = "Patient"
|
|
||||||
flush = true
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|
||||||
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|
||||||
[firmware.op_cfg.by_op.ERC_20]
|
|
||||||
fill_batch_fifo = false
|
|
||||||
min_batch_size = true
|
|
||||||
use_tiers = true
|
|
||||||
flush_behaviour = "Patient"
|
|
||||||
flush = true
|
|
||||||
@@ -1,3 +0,0 @@
|
|||||||
version https://git-lfs.github.com/spec/v1
|
|
||||||
oid sha256:35ad67cf9760e37256a6c92cf29ea67334690b724fd3b7b859919ee9b0bde6d3
|
|
||||||
size 78194785
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -1,622 +0,0 @@
|
|||||||
# This is a sample example of register-map definition
|
|
||||||
|
|
||||||
module_name="hpu_regif_core"
|
|
||||||
description="Hpu top-level register interface. Used by the host to retrieved RTL information, configure it and issue commands."
|
|
||||||
word_size_b = 32
|
|
||||||
offset = 0x00
|
|
||||||
range = 0x10000
|
|
||||||
ext_pkg = ["axi_if_common_param_pkg", "axi_if_shell_axil_pkg"]
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.Xrt]
|
|
||||||
description="Vitis Required registers"
|
|
||||||
offset= 0x0
|
|
||||||
|
|
||||||
# Currently not in used -> Placeholder only
|
|
||||||
[section.Xrt.register.reserved]
|
|
||||||
description="Xrt reserved"
|
|
||||||
default={Cst=0x00}
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.info]
|
|
||||||
description="Contain all the RTL parameters used that have impact on associated SW"
|
|
||||||
offset= 0x10
|
|
||||||
|
|
||||||
[section.info.register.version]
|
|
||||||
description="RTL version"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="VERSION"}
|
|
||||||
|
|
||||||
[section.info.register.ntt_architecture]
|
|
||||||
description="NTT architecture"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="NTT_CORE_ARCH"}
|
|
||||||
|
|
||||||
[section.info.register.ntt_structure]
|
|
||||||
description="NTT structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.radix = { size_b=8, offset_b=0 , default={Param="R"}, description="NTT radix"}
|
|
||||||
field.psi = { size_b=8, offset_b=8 , default={Param="PSI"}, description="NTT psi"}
|
|
||||||
field.div = { size_b=8, offset_b=16, default={Param="BWD_PSI_DIV"}, description="NTT backward div"}
|
|
||||||
field.delta = { size_b=8, offset_b=24, default={Param="DELTA"}, description="NTT network delta (for wmm arch)"}
|
|
||||||
|
|
||||||
[section.info.register.ntt_rdx_cut]
|
|
||||||
description="NTT radix cuts, in log2 unit (for gf64 arch)"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.radix_cut0 = { size_b=4, offset_b=0 , default={Param="NTT_RDX_CUT_S_0"}, description="NTT radix cut #0"}
|
|
||||||
field.radix_cut1 = { size_b=4, offset_b=4 , default={Param="NTT_RDX_CUT_S_1"}, description="NTT radix cut #1"}
|
|
||||||
field.radix_cut2 = { size_b=4, offset_b=8 , default={Param="NTT_RDX_CUT_S_2"}, description="NTT radix cut #2"}
|
|
||||||
field.radix_cut3 = { size_b=4, offset_b=12, default={Param="NTT_RDX_CUT_S_3"}, description="NTT radix cut #3"}
|
|
||||||
field.radix_cut4 = { size_b=4, offset_b=16, default={Param="NTT_RDX_CUT_S_4"}, description="NTT radix cut #4"}
|
|
||||||
field.radix_cut5 = { size_b=4, offset_b=20, default={Param="NTT_RDX_CUT_S_5"}, description="NTT radix cut #5"}
|
|
||||||
field.radix_cut6 = { size_b=4, offset_b=24, default={Param="NTT_RDX_CUT_S_6"}, description="NTT radix cut #6"}
|
|
||||||
field.radix_cut7 = { size_b=4, offset_b=28, default={Param="NTT_RDX_CUT_S_7"}, description="NTT radix cut #7"}
|
|
||||||
|
|
||||||
[section.info.register.ntt_pbs]
|
|
||||||
description="Maximum number of PBS in the NTT pipeline"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.batch_pbs_nb = { size_b=8, offset_b=0 , default={Param="BATCH_PBS_NB"}, description="Maximum number of PBS in the NTT pipe"}
|
|
||||||
field.total_pbs_nb = { size_b=8, offset_b=8 , default={Param="TOTAL_PBS_NB"}, description="Maximum number of PBS stored in PEP buffer"}
|
|
||||||
|
|
||||||
[section.info.register.ntt_modulo]
|
|
||||||
description="Code associated to the NTT prime"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="MOD_NTT_NAME"}
|
|
||||||
|
|
||||||
[section.info.register.application]
|
|
||||||
description="Code associated with the application"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="APPLICATION_NAME"}
|
|
||||||
|
|
||||||
[section.info.register.ks_structure]
|
|
||||||
description="Key-switch structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.x = { size_b=8, offset_b=0 , default={Param="LBX"}, description="Number of coefficients on X dimension"}
|
|
||||||
field.y = { size_b=8, offset_b=8 , default={Param="LBY"}, description="Number of coefficients on Y dimension"}
|
|
||||||
field.z = { size_b=8, offset_b=16, default={Param="LBZ"}, description="Number of coefficients on Z dimension"}
|
|
||||||
|
|
||||||
[section.info.register.ks_crypto_param]
|
|
||||||
description="Key-switch crypto parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.mod_ksk_w = { size_b=8, offset_b=0 , default={Param="MOD_KSK_W"}, description="Width of KSK modulo"}
|
|
||||||
field.ks_l = { size_b=8, offset_b=8 , default={Param="KS_L"}, description="Number of KS decomposition level"}
|
|
||||||
field.ks_b = { size_b=8, offset_b=16, default={Param="KS_B_W"}, description="Width of KS decomposition base"}
|
|
||||||
|
|
||||||
[section.info.register.regf_structure]
|
|
||||||
description="Register file structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.reg_nb = { size_b=8, offset_b=0 , default={Param="REGF_REG_NB"}, description="Number of registers in regfile"}
|
|
||||||
field.coef_nb = { size_b=8, offset_b=8 , default={Param="REGF_COEF_NB"}, description="Number of coefficients at regfile interface"}
|
|
||||||
|
|
||||||
[section.info.register.isc_structure]
|
|
||||||
description="Instruction scheduler structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.depth = { size_b=8, offset_b=0 , default={Param="ISC_DEPTH"}, description="Number of slots in ISC lookahead buffer."}
|
|
||||||
field.min_iop_size = { size_b=8, offset_b=8 , default={Param="MIN_IOP_SIZE"}, description="Minimum number of DOp per IOp to prevent sync_id overflow."}
|
|
||||||
|
|
||||||
[section.info.register.pe_properties]
|
|
||||||
description="Processing elements parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.alu_nb = { size_b=8, offset_b=24 , default={Param="PEA_ALU_NB"}, description="Number of coefficients processed in parallel in pe_alu"}
|
|
||||||
field.pep_regf_period = { size_b=8, offset_b=16 , default={Param="PEP_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEP and regfile"}
|
|
||||||
field.pem_regf_period = { size_b=8, offset_b=8 , default={Param="PEM_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEM and regfile"}
|
|
||||||
field.pea_regf_period = { size_b=8, offset_b=0 , default={Param="PEA_REGF_PERIOD"}, description="Number of cycles between 2 consecutive data transfer between PEA and regfile"}
|
|
||||||
|
|
||||||
[section.info.register.bsk_structure]
|
|
||||||
description="BSK manager structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.bsk_cut_nb = { size_b=8, offset_b=8 , default={Param="BSK_CUT_NB"}, description="BSK cut nb"}
|
|
||||||
|
|
||||||
[section.info.register.ksk_structure]
|
|
||||||
description="KSK manager structure parameters"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.ksk_cut_nb = { size_b=8, offset_b=8 , default={Param="KSK_CUT_NB"}, description="KSK cut nb"}
|
|
||||||
|
|
||||||
[section.info.register.hbm_axi4_nb]
|
|
||||||
description="Number of AXI4 connections to HBM"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.bsk_pc = { size_b=8, offset_b=0 , default={Param="BSK_PC"}, description="Number of HBM connections for BSK"}
|
|
||||||
field.ksk_pc = { size_b=8, offset_b=8, default={Param="KSK_PC"}, description="Number of HBM connections for KSK"}
|
|
||||||
field.pem_pc = { size_b=8, offset_b=16, default={Param="PEM_PC"}, description="Number of HBM connections for ciphertexts (PEM)"}
|
|
||||||
field.glwe_pc = { size_b=8, offset_b=24, default={Param="GLWE_PC"}, description="Number of HBM connections for GLWE"}
|
|
||||||
|
|
||||||
[section.info.register.hbm_axi4_dataw_pem]
|
|
||||||
description="Ciphertext HBM AXI4 connection data width"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="AXI4_PEM_DATA_W"}
|
|
||||||
|
|
||||||
[section.info.register.hbm_axi4_dataw_glwe]
|
|
||||||
description="GLWE HBM AXI4 connection data width"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="AXI4_GLWE_DATA_W"}
|
|
||||||
|
|
||||||
[section.info.register.hbm_axi4_dataw_bsk]
|
|
||||||
description="BSK HBM AXI4 connection data width"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="AXI4_BSK_DATA_W"}
|
|
||||||
|
|
||||||
[section.info.register.hbm_axi4_dataw_ksk]
|
|
||||||
description="KSK HBM AXI4 connection data width"
|
|
||||||
owner="Parameter"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
default={Param="AXI4_KSK_DATA_W"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.bpip]
|
|
||||||
offset= 0x200
|
|
||||||
description="BPIP configuration"
|
|
||||||
|
|
||||||
[section.bpip.register.use]
|
|
||||||
description="(1) Use BPIP mode, (0) use IPIP mode (default)"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
field.use_bpip = { size_b=1, offset_b=0 , default={Cst=1}, description="use"}
|
|
||||||
field.use_opportunism = { size_b=1, offset_b=1 , default={Cst=0}, description="use opportunistic PBS flush"}
|
|
||||||
|
|
||||||
[section.bpip.register.timeout]
|
|
||||||
description="Timeout for BPIP mode"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
default={Cst=0xffffffff}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.hbm_axi4_addr_1in3]
|
|
||||||
offset= 0x400
|
|
||||||
description="HBM AXI4 connection address offset"
|
|
||||||
|
|
||||||
[section.hbm_axi4_addr_1in3.register.ct]
|
|
||||||
description="Address offset for each ciphertext HBM AXI4 connection"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
duplicate=["_pc0_lsb", "_pc0_msb","_pc1_lsb", "_pc1_msb"]
|
|
||||||
|
|
||||||
[section.hbm_axi4_addr_1in3.register.glwe]
|
|
||||||
description="Address offset for each GLWE HBM AXI4 connection"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
duplicate=["_pc0_lsb", "_pc0_msb"]
|
|
||||||
|
|
||||||
|
|
||||||
[section.hbm_axi4_addr_1in3.register.ksk]
|
|
||||||
description="Address offset for each KSK HBM AXI4 connection"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
duplicate=["_pc0_lsb", "_pc0_msb", "_pc1_lsb", "_pc1_msb", "_pc2_lsb", "_pc2_msb", "_pc3_lsb", "_pc3_msb", "_pc4_lsb", "_pc4_msb", "_pc5_lsb", "_pc5_msb", "_pc6_lsb", "_pc6_msb", "_pc7_lsb", "_pc7_msb"]
|
|
||||||
|
|
||||||
[section.hbm_axi4_addr_1in3.register.trc]
|
|
||||||
description="Address offset for each trace HBM AXI4 connection"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
duplicate=["_pc0_lsb", "_pc0_msb"]
|
|
||||||
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.hbm_axi4_addr_3in3]
|
|
||||||
description="HBM AXI4 connection address offset"
|
|
||||||
|
|
||||||
[section.hbm_axi4_addr_3in3.register.bsk]
|
|
||||||
description="Address offset for each BSK HBM AXI4 connection"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
duplicate=["_pc0_lsb", "_pc0_msb", "_pc1_lsb", "_pc1_msb", "_pc2_lsb", "_pc2_msb", "_pc3_lsb", "_pc3_msb", "_pc4_lsb", "_pc4_msb", "_pc5_lsb", "_pc5_msb", "_pc6_lsb", "_pc6_msb", "_pc7_lsb", "_pc7_msb"]
|
|
||||||
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.status_1in3]
|
|
||||||
description="HPU status of part 1in3"
|
|
||||||
offset= 0x800
|
|
||||||
|
|
||||||
[section.status_1in3.register.error]
|
|
||||||
description="Error register (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
field.pbs = { size_b=32, offset_b=0 , default={Cst=0}, description="HPU error part 1in3"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.status_3in3]
|
|
||||||
description="HPU status of parts 2in3 and 3in3"
|
|
||||||
|
|
||||||
[section.status_3in3.register.error]
|
|
||||||
description="Error register (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
field.pbs = { size_b=32, offset_b=0 , default={Cst=0}, description="HPU error part 3in3"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.ksk_avail]
|
|
||||||
description="KSK availability configuration"
|
|
||||||
offset= 0x1000
|
|
||||||
|
|
||||||
[section.ksk_avail.register.avail]
|
|
||||||
description="KSK available bit"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
field.avail = { size_b=1, offset_b=0 , default={Cst=0}, description="avail"}
|
|
||||||
|
|
||||||
[section.ksk_avail.register.reset]
|
|
||||||
description="KSK reset sequence"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
field.request = { size_b=1, offset_b=0 , default={Cst=0}, description="request"}
|
|
||||||
field.done = { size_b=1, offset_b=31 , default={Cst=0}, description="done"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.bsk_avail]
|
|
||||||
description="BSK availability configuration"
|
|
||||||
|
|
||||||
[section.bsk_avail.register.avail]
|
|
||||||
description="BSK available bit"
|
|
||||||
owner="User"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="Write"
|
|
||||||
field.avail = { size_b=1, offset_b=0 , default={Cst=0}, description="avail"}
|
|
||||||
|
|
||||||
[section.bsk_avail.register.reset]
|
|
||||||
description="BSK reset sequence"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
field.request = { size_b=1, offset_b=0 , default={Cst=0}, description="request"}
|
|
||||||
field.done = { size_b=1, offset_b=31 , default={Cst=0}, description="done"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.runtime_1in3]
|
|
||||||
description="Runtime information"
|
|
||||||
offset= 0x2000
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_cmux_loop]
|
|
||||||
description="PEP: CMUX iteration loop number"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.br_loop = { size_b=15, offset_b=0 , default={Cst=0}, description="PBS current BR-loop"}
|
|
||||||
field.br_loop_c = { size_b=1, offset_b=15 , default={Cst=0}, description="PBS current BR-loop parity"}
|
|
||||||
field.ks_loop = { size_b=15, offset_b=16 , default={Cst=0}, description="KS current KS-loop"}
|
|
||||||
field.ks_loop_c = { size_b=1, offset_b=31 , default={Cst=0}, description="KS current KS-loop parity"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_pointer_0]
|
|
||||||
description="PEP: pointers (part 1)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.pool_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP pool_rp"}
|
|
||||||
field.pool_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP pool_wp"}
|
|
||||||
field.ldg_pt = { size_b=8, offset_b=16 , default={Cst=0}, description="PEP ldg_pt"}
|
|
||||||
field.ldb_pt = { size_b=8, offset_b=24 , default={Cst=0}, description="PEP ldb_pt"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_pointer_1]
|
|
||||||
description="PEP: pointers (part 2)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.ks_in_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP ks_in_rp"}
|
|
||||||
field.ks_in_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP ks_in_wp"}
|
|
||||||
field.ks_out_rp = { size_b=8, offset_b=16 , default={Cst=0}, description="PEP ks_out_rp"}
|
|
||||||
field.ks_out_wp = { size_b=8, offset_b=24 , default={Cst=0}, description="PEP ks_out_wp"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_pointer_2]
|
|
||||||
description="PEP: pointers (part 3)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.pbs_in_rp = { size_b=8, offset_b=0 , default={Cst=0}, description="PEP pbs_in_rp"}
|
|
||||||
field.pbs_in_wp = { size_b=8, offset_b=8 , default={Cst=0}, description="PEP pbs_in_wp"}
|
|
||||||
field.ipip_flush_last_pbs_in_loop = { size_b=16, offset_b=16 , default={Cst=0}, description="PEP IPIP flush last pbs_in_loop"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.isc_latest_instruction]
|
|
||||||
description="ISC: 4 latest instructions received ([0] is the most recent)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
duplicate=["_0","_1","_2","_3"]
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_bpip_batch_cnt]
|
|
||||||
description="PEP: BPIP batch counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_bpip_batch_flush_cnt]
|
|
||||||
description="PEP: BPIP batch triggered by a flush counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_bpip_batch_timeout_cnt]
|
|
||||||
description="PEP: BPIP batch triggered by a timeout counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_bpip_waiting_batch_cnt]
|
|
||||||
description="PEP: BPIP batch that waits the trigger counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_bpip_batch_filling_cnt]
|
|
||||||
description="PEP: Count batch with filled with a given number of CT (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
duplicate=["_1","_2","_3","_4","_5","_6","_7","_8","_9","_10","_11","_12","_13","_14","_15","_16"]
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_ld_ack_cnt]
|
|
||||||
description="PEP: load BLWE ack counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_cmux_not_full_batch_cnt]
|
|
||||||
description="PEP: not full batch CMUX counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_seq_ipip_flush_cnt]
|
|
||||||
description="PEP: IPIP flush CMUX counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_ldb_rcp_dur]
|
|
||||||
description="PEP: load BLWE reception max duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_ldg_req_dur]
|
|
||||||
description="PEP: load GLWE request max duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_ldg_rcp_dur]
|
|
||||||
description="PEP: load GLWE reception max duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_load_ksk_rcp_dur]
|
|
||||||
description="PEP: load KSK slice reception max duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
duplicate=["_pc0","_pc1","_pc2","_pc3","_pc4","_pc5","_pc6","_pc7","_pc8","_pc9","_pc10","_pc11","_pc12","_pc13","_pc14","_pc15"]
|
|
||||||
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_mmacc_sxt_rcp_dur]
|
|
||||||
description="PEP: MMACC SXT reception duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_mmacc_sxt_req_dur]
|
|
||||||
description="PEP: MMACC SXT request duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_mmacc_sxt_cmd_wait_b_dur]
|
|
||||||
description="PEP: MMACC SXT command wait for b duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_inst_cnt]
|
|
||||||
description="PEP: input instruction counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pep_ack_cnt]
|
|
||||||
description="PEP: instruction acknowledge counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_load_inst_cnt]
|
|
||||||
description="PEM: load input instruction counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_load_ack_cnt]
|
|
||||||
description="PEM: load instruction acknowledge counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_inst_cnt]
|
|
||||||
description="PEM: store input instruction counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_ack_cnt]
|
|
||||||
description="PEM: store instruction acknowledge counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pea_inst_cnt]
|
|
||||||
description="PEA: input instruction counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pea_ack_cnt]
|
|
||||||
description="PEA: instruction acknowledge counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.isc_inst_cnt]
|
|
||||||
description="ISC: input instruction counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.isc_ack_cnt]
|
|
||||||
description="ISC: instruction acknowledge counter (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_load_info_0]
|
|
||||||
description="PEM: load first data)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
duplicate=["_pc0_0","_pc0_1","_pc0_2","_pc0_3","_pc1_0","_pc1_1","_pc1_2","_pc1_3"]
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_load_info_1]
|
|
||||||
description="PEM: load first address"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
duplicate=["_pc0_lsb","_pc0_msb","_pc1_lsb","_pc1_msb"]
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_info_0]
|
|
||||||
description="PEM: store info 0)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.cmd_vld = { size_b=1, offset_b=0 , default={Cst=0}, description="PEM_ST cmd vld"}
|
|
||||||
field.cmd_rdy = { size_b=1, offset_b=1 , default={Cst=0}, description="PEM_ST cmd rdy"}
|
|
||||||
field.pem_regf_rd_req_vld = { size_b=1, offset_b=2 , default={Cst=0}, description="PEM_ST pem_regf_rd_req_vld"}
|
|
||||||
field.pem_regf_rd_req_rdy = { size_b=1, offset_b=3 , default={Cst=0}, description="PEM_ST pem_regf_rd_req_rdy"}
|
|
||||||
field.brsp_fifo_in_vld = { size_b=4, offset_b=4 , default={Cst=0}, description="PEM_ST brsp_fifo_in_vld"}
|
|
||||||
field.brsp_fifo_in_rdy = { size_b=4, offset_b=8 , default={Cst=0}, description="PEM_ST brsp_fifo_in_rdy"}
|
|
||||||
field.rcp_fifo_in_vld = { size_b=4, offset_b=12 , default={Cst=0}, description="PEM_ST rcp_fifo_in_vld"}
|
|
||||||
field.rcp_fifo_in_rdy = { size_b=4, offset_b=16 , default={Cst=0}, description="PEM_ST rcp_fifo_in_rdy"}
|
|
||||||
field.r2_axi_vld = { size_b=4, offset_b=20 , default={Cst=0}, description="PEM_ST r2_axi_vld"}
|
|
||||||
field.r2_axi_rdy = { size_b=4, offset_b=24 , default={Cst=0}, description="PEM_ST r2_axi_rdy"}
|
|
||||||
field.c0_enough_location = { size_b=4, offset_b=28 , default={Cst=0}, description="PEM_ST c0_enough_location"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_info_1]
|
|
||||||
description="PEM: store info 1"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.s0_cmd_vld = { size_b=4, offset_b=0 , default={Cst=0}, description="PEM_ST s0_cmd_vld"}
|
|
||||||
field.s0_cmd_rdy = { size_b=4, offset_b=4 , default={Cst=0}, description="PEM_ST s0_cmd_rdy"}
|
|
||||||
field.m_axi_bvalid = { size_b=4, offset_b=8 , default={Cst=0}, description="PEM_ST m_axi_bvalid"}
|
|
||||||
field.m_axi_bready = { size_b=4, offset_b=12 , default={Cst=0}, description="PEM_ST m_axi_bready"}
|
|
||||||
field.m_axi_wvalid = { size_b=4, offset_b=16 , default={Cst=0}, description="PEM_ST m_axi_wvalid"}
|
|
||||||
field.m_axi_wready = { size_b=4, offset_b=20 , default={Cst=0}, description="PEM_ST m_axi_wready"}
|
|
||||||
field.m_axi_awvalid = { size_b=4, offset_b=24 , default={Cst=0}, description="PEM_ST m_axi_awvalid"}
|
|
||||||
field.m_axi_awready = { size_b=4, offset_b=28 , default={Cst=0}, description="PEM_ST m_axi_awready"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_info_2]
|
|
||||||
description="PEM: store info 2"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.c0_free_loc_cnt = { size_b=16, offset_b=0 , default={Cst=0}, description="PEM_ST c0_free_loc_cnt"}
|
|
||||||
field.brsp_bresp_cnt = { size_b=16, offset_b=16 , default={Cst=0}, description="PEM_ST brsp_bresp_cnt"}
|
|
||||||
|
|
||||||
[section.runtime_1in3.register.pem_store_info_3]
|
|
||||||
description="PEM: store info 3"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.brsp_ack_seen = { size_b=16, offset_b=0 , default={Cst=0}, description="PEM_ST brsp_ack_seen"}
|
|
||||||
field.c0_cmd_cnt = { size_b=8, offset_b=16 , default={Cst=0}, description="PEM_ST c0_cmd_cnt"}
|
|
||||||
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.runtime_3in3]
|
|
||||||
description="Runtime information"
|
|
||||||
|
|
||||||
[section.runtime_3in3.register.pep_load_bsk_rcp_dur]
|
|
||||||
description="PEP: load BSK slice reception max duration (Could be reset by user)"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
duplicate=["_pc0","_pc1","_pc2","_pc3","_pc4","_pc5","_pc6","_pc7","_pc8","_pc9","_pc10","_pc11","_pc12","_pc13","_pc14","_pc15"]
|
|
||||||
|
|
||||||
[section.runtime_3in3.register.pep_bskif_req_info_0]
|
|
||||||
description="PEP: BSK_IF: requester info 0"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.req_br_loop_rp = { size_b=16, offset_b=0 , default={Cst=0}, description="PEP BSK_IF requester BSK read pointer"}
|
|
||||||
field.req_br_loop_wp = { size_b=16, offset_b=16 , default={Cst=0}, description="PEP BSK_IF requester BSK write pointer"}
|
|
||||||
|
|
||||||
[section.runtime_3in3.register.pep_bskif_req_info_1]
|
|
||||||
description="PEP: BSK_IF: requester info 0"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="None"
|
|
||||||
field.req_prf_br_loop = { size_b=16, offset_b=0 , default={Cst=0}, description="PEP BSK_IF requester BSK prefetch pointer"}
|
|
||||||
field.req_parity = { size_b=1, offset_b=16 , default={Cst=0}, description="PEP BSK_IF requester BSK pointer parity"}
|
|
||||||
field.req_assigned = { size_b=1, offset_b=31 , default={Cst=0}, description="PEP BSK_IF requester assignment"}
|
|
||||||
|
|
||||||
# =====================================================================================================================
|
|
||||||
[section.WorkAck]
|
|
||||||
description="Purpose of this section"
|
|
||||||
offset= 0x8000
|
|
||||||
|
|
||||||
[section.WorkAck.register.workq]
|
|
||||||
description="Insert work in workq and read status"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="Read"
|
|
||||||
write_access="WriteNotify"
|
|
||||||
|
|
||||||
[section.WorkAck.register.ackq]
|
|
||||||
description="Pop ack from in ackq"
|
|
||||||
owner="Kernel"
|
|
||||||
read_access="ReadNotify"
|
|
||||||
write_access="None"
|
|
||||||
@@ -2,7 +2,7 @@
|
|||||||
//! The aim is to completely hide underlying specificities and enable compile-time
|
//! The aim is to completely hide underlying specificities and enable compile-time
|
||||||
//! swapping.
|
//! swapping.
|
||||||
//!
|
//!
|
||||||
//! Mainly replacing Xrt(u55c)/V80 by a simulation interface to ease CI
|
//! Mainly replacing V80 by a simulation interface to ease CI
|
||||||
|
|
||||||
use crate::interface::FFIMode;
|
use crate::interface::FFIMode;
|
||||||
|
|
||||||
|
|||||||
12
setup_hpu.sh
12
setup_hpu.sh
@@ -8,7 +8,6 @@ HPU_MOCKUP_DIR=$CUR_SCRIPT_DIR/mockups/tfhe-hpu-mockup
|
|||||||
# Default default bitstream
|
# Default default bitstream
|
||||||
# Available options are:
|
# Available options are:
|
||||||
# * sim: use with the mockup (i.e simulation)
|
# * sim: use with the mockup (i.e simulation)
|
||||||
# * u55c: use with u55c (latest bitstream with gf64 config)
|
|
||||||
# * v80: use with v80 (i.e should specify pcie-dev flag [zamav80: 01, srvzama: 21]
|
# * v80: use with v80 (i.e should specify pcie-dev flag [zamav80: 01, srvzama: 21]
|
||||||
HPU_CONFIG="sim"
|
HPU_CONFIG="sim"
|
||||||
|
|
||||||
@@ -35,7 +34,7 @@ do
|
|||||||
case "$1" in
|
case "$1" in
|
||||||
-h|--help)
|
-h|--help)
|
||||||
echo "Available options are:"
|
echo "Available options are:"
|
||||||
echo " * --config: target configuration [sim, u55c_gf64, v80]"
|
echo " * --config: target configuration [sim, v80]"
|
||||||
echo " * --rust-log: Specify rust verbosity [Cf. tracing]"
|
echo " * --rust-log: Specify rust verbosity [Cf. tracing]"
|
||||||
echo " * --pcie-dev: target pcie device [Warn: v80 only]"
|
echo " * --pcie-dev: target pcie device [Warn: v80 only]"
|
||||||
return 0
|
return 0
|
||||||
@@ -111,15 +110,6 @@ if [[ "$HPU_CONFIG" == sim* ]]; then
|
|||||||
export HPU_MOCKUP_DIR
|
export HPU_MOCKUP_DIR
|
||||||
fi
|
fi
|
||||||
|
|
||||||
# U55c specific init ###########################################################
|
|
||||||
if [[ "$HPU_CONFIG" == u55c* ]]; then
|
|
||||||
# Setup Xrt for low-level xfer with u55c
|
|
||||||
XRT_SETUP=/opt/xilinx/xrt/setup.sh
|
|
||||||
if [[ -f $XRT_SETUP ]]; then
|
|
||||||
source $XRT_SETUP
|
|
||||||
fi
|
|
||||||
fi
|
|
||||||
|
|
||||||
# V80 specific init ###########################################################
|
# V80 specific init ###########################################################
|
||||||
if [[ "$HPU_CONFIG" == v80* ]]; then
|
if [[ "$HPU_CONFIG" == v80* ]]; then
|
||||||
export V80_PCIE_DEV
|
export V80_PCIE_DEV
|
||||||
|
|||||||
@@ -88,9 +88,6 @@ mod hpu_test {
|
|||||||
(std::sync::Mutex::new(hpu_device), cks, key_seed)
|
(std::sync::Mutex::new(hpu_device), cks, key_seed)
|
||||||
}
|
}
|
||||||
|
|
||||||
// NB: Currently u55c didn't check for workq overflow.
|
|
||||||
// -> Use default value < queue depth to circumvent this limitation
|
|
||||||
// NB': This is only for u55c, on V80 user could set HPU_TEST_ITER to whatever value he want
|
|
||||||
const DEFAULT_TEST_ITER: usize = 32;
|
const DEFAULT_TEST_ITER: usize = 32;
|
||||||
|
|
||||||
macro_rules! hpu_testbundle {
|
macro_rules! hpu_testbundle {
|
||||||
|
|||||||
Reference in New Issue
Block a user