This backend abstract communication with Hpu Fpga hardware.
It define it's proper entities to prevent circular dependencies with
tfhe-rs.
Object lifetime is handle through Arc<Mutex<T>> wrapper, and enforce
that all objects currently alive in Hpu Hw are also kept valid on the
host side.
It contains the second version of HPU instruction set (HIS_V2.0):
* DOp have following properties:
+ Template as first class citizen
+ Support of Immediate template
+ Direct parser and conversion between Asm/Hex
+ Replace deku (and it's associated endianess limitation) by
+ bitfield_struct and manual parsing
* IOp have following properties:
+ Support various number of Destination
+ Support various number of Sources
+ Support various number of Immediat values
+ Support of multiple bitwidth (Not implemented yet in the Fpga
firmware)
Details could be view in `backends/tfhe-hpu-backend/Readme.md`
Add integer and hlapi function to perform
`clear - ciphertext`
As subtraction is not commutative having a specialized version
is better.
As can be seen from the code, the real benefit is for the default
version where the cost of `clear - ciphertext` is the same as
`clear + ciphertex` which is better that transforming the clear into
a trivial ciphertext to perform the subtract algorithm
This is done to load benchmarks machine in smarter way. This makes
sure to saturate compute load of the benchmark machine while
keeping execution time reasonable.
iter_batched() criterion method is used instead of iter() so that
benchmarks are compatible with other flavors of operations
(unchecked_* or smart_*).
BREAKING_CHANGE:
- The x86_64, x86_64-unix, aarch64, aarch64-unix have been removed, the target
architecture and os family are now automatically detected. A `software_prng`
feature has been added to force the use of a software implementation on older
CPUs
