mirror of
https://github.com/zama-ai/tfhe-rs.git
synced 2026-01-09 14:47:56 -05:00
25362b2db2
Including the pfail 2e-128 parameter set. Note: The HPU mockup still does not support mean compensation.
479 lines
17 KiB
Rust
479 lines
17 KiB
Rust
//!
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//! Extract architecture properties from RTL registers
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//! Read Rtl parameters from registers.
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//! NB: Some registers contains encoded value that must be converted to concrete one (i.e.
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//! apps/ntt_moduls)
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use parameters::HpuNttPrime;
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use super::*;
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use crate::entities::*;
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// Set of constant defined in RTL and associated rust definition
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// -> Cf. fpga/hw/common_lib/common_package/rtl/common_definition_pkg.sv
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pub const NTT_CORE_ARCH_OFS: u32 = 5 << 8;
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pub const MOD_NTT_NAME_OFS: u32 = 6 << 8;
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pub const APPLICATION_NAME_OFS: u32 = 7 << 8;
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pub const SIMULATION_CODE: u32 = 1;
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impl FromRtl for HpuParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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let pbs_params = HpuPBSParameters::from_rtl(ffi_hw, regmap);
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let ntt_params = HpuNttParameters::from_rtl(ffi_hw, regmap);
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let ks_params = HpuKeyswitchParameters::from_rtl(ffi_hw, regmap);
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let pc_params = HpuPcParameters::from_rtl(ffi_hw, regmap);
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let regf_params = HpuRegfileParameters::from_rtl(ffi_hw, regmap);
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let isc_params = HpuIscParameters::from_rtl(ffi_hw, regmap);
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Self {
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pbs_params,
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ntt_params,
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ks_params,
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pc_params,
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regf_params,
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isc_params,
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}
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}
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}
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impl FromRtl for HpuKeyswitchParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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let ks_shape = regmap
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.register()
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.get("info::ks_structure")
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.expect("Unknown register, check regmap definition");
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let shape_val = ffi_hw.read_reg(*ks_shape.offset() as u64);
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let shape_fields = ks_shape.as_field(shape_val);
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let ks_info = regmap
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.register()
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.get("info::ks_crypto_param")
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.expect("Unknown register, check regmap definition");
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let info_val = ffi_hw.read_reg(*ks_info.offset() as u64);
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let info_fields = ks_info.as_field(info_val);
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Self {
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width: *info_fields.get("mod_ksk_w").expect("Unknown field") as usize,
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lbx: *shape_fields.get("x").expect("Unknown field") as usize,
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lby: *shape_fields.get("y").expect("Unknown field") as usize,
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lbz: *shape_fields.get("z").expect("Unknown field") as usize,
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}
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}
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}
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impl FromRtl for HpuNttParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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let core_arch = HpuNttCoreArch::from_rtl(ffi_hw, regmap);
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// Values extracted from NttInternal register
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let ntt_internal = regmap
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.register()
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.get("info::ntt_structure")
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.expect("Unknown register, check regmap definition");
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let internal_val = ffi_hw.read_reg(*ntt_internal.offset() as u64);
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let internal_fields = ntt_internal.as_field(internal_val);
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let radix = *internal_fields.get("radix").expect("Unknown field") as usize;
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let psi = *internal_fields.get("psi").expect("Unknown field") as usize;
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let delta = *internal_fields.get("delta").expect("Unknown field") as usize;
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// Values extracted from NttInternal register
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let ntt_pbs_nb = regmap
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.register()
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.get("info::ntt_pbs")
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.expect("Unknown register, check regmap definition");
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let pbs_nb_val = ffi_hw.read_reg(*ntt_pbs_nb.offset() as u64);
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let pbs_nb_fields = ntt_pbs_nb.as_field(pbs_nb_val);
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let batch_pbs_nb = *pbs_nb_fields.get("batch_pbs_nb").expect("Unknown field") as usize;
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let total_pbs_nb = *pbs_nb_fields.get("total_pbs_nb").expect("Unknown field") as usize;
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// Values extracted from NttModulo register
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// Modulus isn't directly expressed, instead used custom encoding
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let ntt_modulo = regmap
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.register()
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.get("info::ntt_modulo")
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.expect("Unknown register, check regmap definition");
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let ntt_modulo_val = ffi_hw.read_reg(*ntt_modulo.offset() as u64);
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let prime_modulus = {
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// Check register encoding
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let field_code = ntt_modulo_val & (!0xFF_u32);
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assert_eq!(
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field_code, MOD_NTT_NAME_OFS,
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"Invalid register encoding. Check register map definition"
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);
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match (ntt_modulo_val & 0xFF) as u8 {
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enum_id if enum_id == HpuNttPrime::GF64 as u8 => HpuNttPrime::GF64,
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enum_id if enum_id == HpuNttPrime::Solinas3_32_17_13 as u8 => {
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HpuNttPrime::Solinas3_32_17_13
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}
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enum_id if enum_id == HpuNttPrime::Solinas2_44_14 as u8 => {
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HpuNttPrime::Solinas2_44_14
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}
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_ => panic!("Unknown NttModName encoding"),
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}
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};
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// Values extracted from Application
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// Not the cleanest way but some required ntt information are only available in the
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// parameters set Thus parse extract HpuPBSParameters inside HpuNttParameters
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let pbs_params = HpuPBSParameters::from_rtl(ffi_hw, regmap);
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let stg_nb = pbs_params.polynomial_size.ilog(radix) as usize;
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Self {
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core_arch,
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min_pbs_nb: None, // TODO: Get this from a register
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batch_pbs_nb,
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total_pbs_nb,
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ct_width: pbs_params.ciphertext_width as u32,
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radix,
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stg_nb,
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prime_modulus,
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psi,
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delta,
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}
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}
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}
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impl FromRtl for HpuNttCoreArch {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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// Values extracted from NttModulo register
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// Modulus isn't directly expressed, instead used custom encoding
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let ntt_core_arch = regmap
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.register()
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.get("info::ntt_architecture")
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.expect("Unknown register, check regmap definition");
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let ntt_core_arch_val = ffi_hw.read_reg(*ntt_core_arch.offset() as u64);
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// Check register encoding
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let field_code = ntt_core_arch_val & (!0xFF_u32);
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assert_eq!(
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field_code, NTT_CORE_ARCH_OFS,
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"Invalid register encoding. Check register map definition"
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);
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match ntt_core_arch_val & 0xFF {
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// NB: Previous arch aren't supported anymore
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3 => Self::WmmCompactPcg,
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4 => Self::WmmUnfoldPcg,
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5 => {
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// Extract associated radix split
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let radix_cut = regmap
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.register()
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.get("info::ntt_rdx_cut")
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.expect("Unknown register, check regmap definition");
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let radix_cut_val = ffi_hw.read_reg(*radix_cut.offset() as u64);
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let cut_l = (0..(u32::BITS / 4))
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.map(|ofst| ((radix_cut_val >> (ofst * 4)) & 0xf) as u8)
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.filter(|x| *x != 0)
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.collect::<Vec<u8>>();
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Self::GF64(cut_l)
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}
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_ => panic!("Unknown NttCoreArch encoding"),
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}
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}
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}
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impl FromRtl for HpuPcParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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// Extract number of Pc for each channel
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let hbm_pc = regmap
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.register()
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.get("info::hbm_axi4_nb")
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.expect("Unknown register, check regmap definition");
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let hbm_pc_val = ffi_hw.read_reg(*hbm_pc.offset() as u64);
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let hbm_pc_fields = hbm_pc.as_field(hbm_pc_val);
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let ksk_pc = *hbm_pc_fields.get("ksk_pc").expect("Unknown field") as usize;
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let bsk_pc = *hbm_pc_fields.get("bsk_pc").expect("Unknown field") as usize;
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let pem_pc = *hbm_pc_fields.get("pem_pc").expect("Unknown field") as usize;
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// Extract bus width for each channel
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let ksk_bytes_w = {
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let ksk_axi4_data_w = regmap
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.register()
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.get("info::hbm_axi4_dataw_ksk")
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.expect("Unknown register, check regmap definition");
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let ksk_axi4_data_w_val = ffi_hw.read_reg(*ksk_axi4_data_w.offset() as u64);
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// Value is in bit in rtl and SW expect bytes
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ksk_axi4_data_w_val.div_ceil(u8::BITS) as usize
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};
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let bsk_bytes_w = {
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let bsk_axi4_data_w = regmap
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.register()
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.get("info::hbm_axi4_dataw_bsk")
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.expect("Unknown register, check regmap definition");
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let bsk_axi4_data_w_val = ffi_hw.read_reg(*bsk_axi4_data_w.offset() as u64);
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// Value is in bit in rtl and SW expect bytes
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bsk_axi4_data_w_val.div_ceil(u8::BITS) as usize
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};
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let pem_bytes_w = {
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let pem_axi4_data_w = regmap
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.register()
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.get("info::hbm_axi4_dataw_pem")
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.expect("Unknown register, check regmap definition");
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let pem_axi4_data_w_val = ffi_hw.read_reg(*pem_axi4_data_w.offset() as u64);
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// Value is in bit in rtl and SW expect bytes
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pem_axi4_data_w_val.div_ceil(u8::BITS) as usize
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};
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let glwe_bytes_w = {
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let glwe_axi4_data_w = regmap
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.register()
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.get("info::hbm_axi4_dataw_glwe")
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.expect("Unknown register, check regmap definition");
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let glwe_axi4_data_w_val = ffi_hw.read_reg(*glwe_axi4_data_w.offset() as u64);
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// Value is in bit in rtl and SW expect bytes
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glwe_axi4_data_w_val.div_ceil(u8::BITS) as usize
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};
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Self {
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ksk_pc,
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bsk_pc,
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pem_pc,
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ksk_bytes_w,
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bsk_bytes_w,
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pem_bytes_w,
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glwe_bytes_w,
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}
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}
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}
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impl FromRtl for HpuRegfileParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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let regf = regmap
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.register()
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.get("info::regf_structure")
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.expect("Unknown register, check regmap definition");
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let regf_val = ffi_hw.read_reg(*regf.offset() as u64);
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let regf_fields = regf.as_field(regf_val);
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Self {
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reg_nb: *regf_fields.get("reg_nb").expect("Unknown field") as usize,
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coef_nb: *regf_fields.get("coef_nb").expect("Unknown field") as usize,
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}
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}
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}
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impl FromRtl for HpuIscParameters {
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fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
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let isc = regmap
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.register()
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.get("info::isc_structure")
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.expect("Unknown register, check regmap definition");
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let isc_val = ffi_hw.read_reg(*isc.offset() as u64);
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let isc_fields = isc.as_field(isc_val);
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Self {
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min_iop_size: *isc_fields.get("min_iop_size").expect("Unknown field") as usize,
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depth: *isc_fields.get("depth").expect("Unknown field") as usize,
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}
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}
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}
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// Define parameters set as constants
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// Used to easily derived IoMeasure version without duplication
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pub const CONCRETE_BOOLEAN: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 586,
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glwe_dimension: 2,
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polynomial_size: 512,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(0.00000000007069849454709433),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(
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0.0000000000000000000029403601535432533,
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),
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pbs_base_log: 8,
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pbs_level: 2,
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ks_base_log: 5,
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ks_level: 4,
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message_width: 1,
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carry_width: 0,
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ciphertext_width: 32,
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};
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pub const MSG2_CARRY2: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 742,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(9.039_924_320_497_611e-6_f64),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(3.1529314934984704e-16_f64),
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pbs_base_log: 19,
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pbs_level: 1,
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ks_base_log: 3,
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ks_level: 5,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: u64::BITS as usize,
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};
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pub const MSG2_CARRY2_64B: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 710,
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glwe_dimension: 2,
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polynomial_size: 1024,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(1.630_783_646_854_603e-5_f64),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(3.1529314934984704e-16_f64),
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pbs_base_log: 25,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 7,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: u64::BITS as usize,
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};
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pub const MSG2_CARRY2_44B: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 724,
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glwe_dimension: 2,
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polynomial_size: 1024,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(
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1.259_780_968_897_627_7e-5_f64,
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),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(2.2737367544323206e-13_f64),
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pbs_base_log: 20,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 7,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 44,
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};
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pub const MSG2_CARRY2_64B_FAKE: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 724,
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glwe_dimension: 2,
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polynomial_size: 1024,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(
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1.259_780_968_897_627_7e-5_f64,
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),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(2.2737367544323206e-13_f64),
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pbs_base_log: 20,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 7,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 64,
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};
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pub const MSG2_CARRY2_GAUSSIAN: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 834,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(
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3.553_990_235_944_282_5e-6_f64,
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),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(2.845267479601915e-15_f64),
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pbs_base_log: 23,
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pbs_level: 1,
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ks_base_log: 3,
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ks_level: 5,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 64,
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};
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pub const MSG2_CARRY2_TUNIFORM: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 887,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(
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3.553_990_235_944_282_5e-6_f64,
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),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(2.845267479601915e-15_f64),
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pbs_base_log: 22,
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pbs_level: 1,
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ks_base_log: 3,
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ks_level: 5,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 64,
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};
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pub const MSG2_CARRY2_PFAIL64_132B_GAUSSIAN_1F72DBA: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 804,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(5.963_599_673_924_788e-6_f64),
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glwe_noise_distribution: HpuNoiseDistributionInput::GaussianStdDev(2.8452674713391114e-15_f64),
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pbs_base_log: 23,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 8,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 64,
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};
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pub const MSG2_CARRY2_PFAIL64_132B_TUNIFORM_7E47D8C: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 839,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::TUniformBound(4),
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glwe_noise_distribution: HpuNoiseDistributionInput::TUniformBound(17),
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pbs_base_log: 23,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 7,
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message_width: 2,
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carry_width: 2,
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ciphertext_width: 64,
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};
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pub const MSG2_CARRY2_PFAIL128_132B_TUNIFORM_144A47: HpuPBSParameters = HpuPBSParameters {
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lwe_dimension: 879,
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glwe_dimension: 1,
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polynomial_size: 2048,
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lwe_noise_distribution: HpuNoiseDistributionInput::TUniformBound(3),
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glwe_noise_distribution: HpuNoiseDistributionInput::TUniformBound(17),
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pbs_base_log: 23,
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pbs_level: 1,
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ks_base_log: 2,
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ks_level: 8,
|
|
message_width: 2,
|
|
carry_width: 2,
|
|
ciphertext_width: 64,
|
|
};
|
|
|
|
impl FromRtl for HpuPBSParameters {
|
|
fn from_rtl(ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) -> Self {
|
|
let pbs_app = regmap
|
|
.register()
|
|
.get("info::application")
|
|
.expect("Unknown register, check regmap definition");
|
|
let pbs_app_val = ffi_hw.read_reg(*pbs_app.offset() as u64);
|
|
|
|
// Check register encoding
|
|
let field_code = pbs_app_val & (!0xFF_u32);
|
|
#[cfg(not(any(feature = "hw-xrt", feature = "hw-v80")))]
|
|
{
|
|
if (field_code == 0) && (pbs_app_val == SIMULATION_CODE) {
|
|
tracing::warn!("Run an simulation backend with custom SIMU parameters set");
|
|
return ffi_hw.get_pbs_parameters();
|
|
}
|
|
}
|
|
#[cfg(any(feature = "hw-xrt", feature = "hw-v80"))]
|
|
{
|
|
assert_eq!(
|
|
field_code, APPLICATION_NAME_OFS,
|
|
"Invalid register encoding. Check register map definition"
|
|
);
|
|
}
|
|
|
|
match pbs_app_val & 0xFF {
|
|
0 => CONCRETE_BOOLEAN,
|
|
1 => MSG2_CARRY2,
|
|
2 => {
|
|
let mut params = MSG2_CARRY2;
|
|
params.lwe_dimension = 2;
|
|
params
|
|
}
|
|
3 => MSG2_CARRY2_64B,
|
|
4 => MSG2_CARRY2_44B,
|
|
9 => MSG2_CARRY2_64B_FAKE,
|
|
10 => MSG2_CARRY2_GAUSSIAN,
|
|
11 => MSG2_CARRY2_TUNIFORM,
|
|
12 => MSG2_CARRY2_PFAIL64_132B_GAUSSIAN_1F72DBA,
|
|
13 => MSG2_CARRY2_PFAIL64_132B_TUNIFORM_7E47D8C,
|
|
14 => MSG2_CARRY2_PFAIL128_132B_TUNIFORM_144A47,
|
|
_ => panic!("Unknown TfheAppName encoding"),
|
|
}
|
|
}
|
|
}
|