mirror of
https://github.com/zama-ai/tfhe-rs.git
synced 2026-01-06 21:34:05 -05:00
9ee8259002
This backend abstract communication with Hpu Fpga hardware.
It define it's proper entities to prevent circular dependencies with
tfhe-rs.
Object lifetime is handle through Arc<Mutex<T>> wrapper, and enforce
that all objects currently alive in Hpu Hw are also kept valid on the
host side.
It contains the second version of HPU instruction set (HIS_V2.0):
* DOp have following properties:
+ Template as first class citizen
+ Support of Immediate template
+ Direct parser and conversion between Asm/Hex
+ Replace deku (and it's associated endianess limitation) by
+ bitfield_struct and manual parsing
* IOp have following properties:
+ Support various number of Destination
+ Support various number of Sources
+ Support various number of Immediat values
+ Support of multiple bitwidth (Not implemented yet in the Fpga
firmware)
Details could be view in `backends/tfhe-hpu-backend/Readme.md`
109 lines
3.2 KiB
TOML
109 lines
3.2 KiB
TOML
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[fpga]
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regmap=["${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core_cfg_1in3.toml",
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"${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core_cfg_3in3.toml",
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"${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core_prc_1in3.toml",
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"${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/hpu_regif_core_prc_3in3.toml",
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"${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/tb_hpu_regif_dummy.toml"]
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polling_us=100000
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[fpga.ffi.Sim]
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ipc_name="/tmp/${USER}/hpu_mockup_ipc"
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[rtl]
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bpip_use = true
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bpip_use_opportunism = true
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bpip_timeout = 100_000
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[board]
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ct_mem = 32768
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ct_pc = [
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{Hbm= {pc=32}},
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{Hbm= {pc=33}},
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]
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heap_size = 16384
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lut_mem = 256
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lut_pc = {Hbm={pc=34}}
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fw_size= 16777215 # i.e. 16 MiB
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fw_pc = {Ddr= {offset= 0x3900_0000}} # NB: Allocation must take place in the Discret DDR
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bsk_pc = [
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{Hbm={pc=8}},
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{Hbm={pc=12}},
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{Hbm={pc=24}},
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{Hbm={pc=28}},
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{Hbm={pc=40}},
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{Hbm={pc=44}},
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{Hbm={pc=56}},
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{Hbm={pc=60}}
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]
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ksk_pc = [
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{Hbm={pc=0}},
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{Hbm={pc=1}},
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{Hbm={pc=2}},
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{Hbm={pc=3}},
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{Hbm={pc=4}},
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{Hbm={pc=5}},
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{Hbm={pc=6}},
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{Hbm={pc=7}},
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{Hbm={pc=16}},
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{Hbm={pc=17}},
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{Hbm={pc=18}},
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{Hbm={pc=19}},
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{Hbm={pc=20}},
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{Hbm={pc=21}},
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{Hbm={pc=22}},
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{Hbm={pc=23}}
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]
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trace_pc = {Hbm={pc=35}}
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trace_depth = 32 # In MB
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[firmware]
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implementation = "Llt"
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integer_w=[2,4,6,8,10,12,14,16,32,64,128]
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min_batch_size = 11
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kogge_cfg = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/kogge_cfg.toml"
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custom_iop.'IOP[0]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_0.asm"
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custom_iop.'IOP[1]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_1.asm"
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custom_iop.'IOP[2]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_2.asm"
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custom_iop.'IOP[3]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_3.asm"
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custom_iop.'IOP[8]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_8.asm"
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custom_iop.'IOP[9]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_9.asm"
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custom_iop.'IOP[16]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_16.asm"
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custom_iop.'IOP[17]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_17.asm"
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custom_iop.'IOP[18]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_18.asm"
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custom_iop.'IOP[19]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_19.asm"
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custom_iop.'IOP[20]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_20.asm"
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custom_iop.'IOP[21]' = "${HPU_BACKEND_DIR}/config_store/${HPU_CONFIG}/custom_iop/cust_21.asm"
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[firmware.op_cfg.default]
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fill_batch_fifo = true
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min_batch_size = false
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use_tiers = false
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flush_behaviour = "Patient"
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flush = true
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[firmware.op_cfg.by_op.MUL]
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fill_batch_fifo = false
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min_batch_size = false
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use_tiers = false
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flush_behaviour = "Patient"
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flush = true
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[firmware.op_cfg.by_op.MULS]
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fill_batch_fifo = false
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min_batch_size = false
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use_tiers = false
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flush_behaviour = "Patient"
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flush = true
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[firmware.op_cfg.by_op.ERC_20]
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fill_batch_fifo = true
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min_batch_size = false
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use_tiers = true
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flush_behaviour = "Patient"
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flush = true
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