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9ee8259002
This backend abstract communication with Hpu Fpga hardware.
It define it's proper entities to prevent circular dependencies with
tfhe-rs.
Object lifetime is handle through Arc<Mutex<T>> wrapper, and enforce
that all objects currently alive in Hpu Hw are also kept valid on the
host side.
It contains the second version of HPU instruction set (HIS_V2.0):
* DOp have following properties:
+ Template as first class citizen
+ Support of Immediate template
+ Direct parser and conversion between Asm/Hex
+ Replace deku (and it's associated endianess limitation) by
+ bitfield_struct and manual parsing
* IOp have following properties:
+ Support various number of Destination
+ Support various number of Sources
+ Support various number of Immediat values
+ Support of multiple bitwidth (Not implemented yet in the Fpga
firmware)
Details could be view in `backends/tfhe-hpu-backend/Readme.md`
29 lines
685 B
Python
Executable File
29 lines
685 B
Python
Executable File
#!/usr/bin/env python3
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from pandas import DataFrame
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from isctrace.analysis import Refilled, Retired, Trace
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freq_mhz = 300
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iops = Trace.from_hw("data/trace.json")
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def analyze_iop(iop):
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retired = Retired(iop)
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# Print the retired instructions as a table
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print(retired.to_df().to_string())
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# Print a batch latency table
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latency_table = retired.pbs_latency_table(freq_mhz=freq_mhz).drop(columns='data')
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print(latency_table)
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# And the runtime
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runtime = retired.runtime_us(freq_mhz=freq_mhz)
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print(f"batches: {latency_table['count'].sum()}")
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print(f"Runtime: {runtime}us")
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if __name__ == "__main__":
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analyze_iop(iops[0])
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# vim: fdm=marker
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