mirror of
https://github.com/zama-ai/tfhe-rs.git
synced 2026-01-06 21:34:05 -05:00
9ee8259002
This backend abstract communication with Hpu Fpga hardware.
It define it's proper entities to prevent circular dependencies with
tfhe-rs.
Object lifetime is handle through Arc<Mutex<T>> wrapper, and enforce
that all objects currently alive in Hpu Hw are also kept valid on the
host side.
It contains the second version of HPU instruction set (HIS_V2.0):
* DOp have following properties:
+ Template as first class citizen
+ Support of Immediate template
+ Direct parser and conversion between Asm/Hex
+ Replace deku (and it's associated endianess limitation) by
+ bitfield_struct and manual parsing
* IOp have following properties:
+ Support various number of Destination
+ Support various number of Sources
+ Support various number of Immediat values
+ Support of multiple bitwidth (Not implemented yet in the Fpga
firmware)
Details could be view in `backends/tfhe-hpu-backend/Readme.md`
111 lines
2.6 KiB
Python
111 lines
2.6 KiB
Python
from . import analysis
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class BaseInstruction:
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def __init__(self, data):
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self.data = data
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def args(self):
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return str(self.data)
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def __str__(self):
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return f'{self.__class__.__name__} {self.args()}'
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class NamedInstruction:
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def __init__(self, name, args):
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self.name = name
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self._args = args
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def args(self):
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return self._args
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def __str__(self):
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return f'{self.name} {self.args()}'
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class PBS(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src_rid} @{self.gid}'
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class LD(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.rid} @{hex(self.slot["Addr"])}'
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class ST(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'@{hex(self.slot["Addr"])} R{self.rid}'
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class MAC(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src0_rid} ' +\
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f'R{self.src1_rid} X{self.mul_factor} '
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class ADD(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src0_rid} R{self.src1_rid}'
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class ADDS(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src_rid} {self.msg_cst["Cst"]}'
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class SUB(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src0_rid} R{self.src1_rid}'
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class SSUB(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} {self.msg_cst["Cst"]} R{self.src_rid}'
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class SUBS(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f'R{self.dst_rid} R{self.src_rid} {self.msg_cst["Cst"]}'
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class SYNC(BaseInstruction):
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def __init__(self, d):
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self.__dict__ = d
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def args(self):
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return f"{self.sid}"
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PBS_ML2 = PBS
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PBS_ML4 = PBS
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PBS_ML8 = PBS
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PBS_F = PBS
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PBS_ML2_F = PBS
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PBS_ML4_F = PBS
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PBS_ML8_F = PBS
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MULS = ADDS
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SUBS = ADDS
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class Insn:
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def __init__(self, insn):
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self.opcode, data = next(iter(insn.items()))
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self.data = globals()[self.opcode](data) if self.opcode in globals() \
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else NamedInstruction(self.opcode, data)
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def to_analysis(self):
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return analysis.Instruction(self.opcode, self.data.args())
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