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https://github.com/zama-ai/tfhe-rs.git
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9ee8259002
This backend abstract communication with Hpu Fpga hardware.
It define it's proper entities to prevent circular dependencies with
tfhe-rs.
Object lifetime is handle through Arc<Mutex<T>> wrapper, and enforce
that all objects currently alive in Hpu Hw are also kept valid on the
host side.
It contains the second version of HPU instruction set (HIS_V2.0):
* DOp have following properties:
+ Template as first class citizen
+ Support of Immediate template
+ Direct parser and conversion between Asm/Hex
+ Replace deku (and it's associated endianess limitation) by
+ bitfield_struct and manual parsing
* IOp have following properties:
+ Support various number of Destination
+ Support various number of Sources
+ Support various number of Immediat values
+ Support of multiple bitwidth (Not implemented yet in the Fpga
firmware)
Details could be view in `backends/tfhe-hpu-backend/Readme.md`
45 lines
805 B
TOML
45 lines
805 B
TOML
[pbs_params]
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lwe_dimension=20
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glwe_dimension=2
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polynomial_size=1024
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lwe_noise_distribution={GaussianStdDev=0.0}
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glwe_noise_distribution={GaussianStdDev=0.0}
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pbs_base_log=20
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pbs_level=1
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ks_base_log=2
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ks_level=7
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message_width=2
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carry_width=2
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ciphertext_width=44
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[ntt_params]
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core_arch="WmmCompactPcg"
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min_pbs_nb= 10
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batch_pbs_nb= 16
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total_pbs_nb= 32
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ct_width= 44
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radix= 2
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stg_nb= 10
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prime_modulus="Solinas2_44_14"
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psi= 32
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delta= 5
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[ks_params]
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width= 21
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lbx= 2
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lby= 32
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lbz= 3
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[pc_params]
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ksk_pc= 4
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ksk_bytes_w= 64
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bsk_pc= 4
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bsk_bytes_w= 64
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pem_pc= 2
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pem_bytes_w= 64
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glwe_bytes_w= 64
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[regf_params]
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reg_nb= 64
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coef_nb= 32
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[isc_params]
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min_iop_size= 4
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depth= 64
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