# mypy: ignore-errors
import ctypes
from tinygrad.helpers import unwrap
from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR
class _anonunion0(ctypes.Union): pass
NvUPtr = ctypes.c_uint64
_anonunion0._fields_ = [
  ('v', NvUPtr),
  ('p', ctypes.c_void_p),
]
class _anonunion1(ctypes.Union): pass
_anonunion1._fields_ = [
  ('v', NvUPtr),
  ('p', ctypes.c_void_p),
]
class struct_NV0000_ALLOC_PARAMETERS(Struct): pass
NvHandle = ctypes.c_uint32
NvU32 = ctypes.c_uint32
NvP64 = ctypes.c_void_p
struct_NV0000_ALLOC_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('processID', NvU32),
  ('processName', (ctypes.c_char * 100)),
  ('pOsPidInfo', NvP64),
]
NV0000_ALLOC_PARAMETERS = struct_NV0000_ALLOC_PARAMETERS
class struct_NV0080_ALLOC_PARAMETERS(Struct): pass
NvV32 = ctypes.c_uint32
NvU64 = ctypes.c_uint64
struct_NV0080_ALLOC_PARAMETERS._fields_ = [
  ('deviceId', NvU32),
  ('hClientShare', NvHandle),
  ('hTargetClient', NvHandle),
  ('hTargetDevice', NvHandle),
  ('flags', NvV32),
  ('vaSpaceSize', NvU64),
  ('vaStartInternal', NvU64),
  ('vaLimitInternal', NvU64),
  ('vaMode', NvV32),
]
NV0080_ALLOC_PARAMETERS = struct_NV0080_ALLOC_PARAMETERS
class struct_NV2080_ALLOC_PARAMETERS(Struct): pass
struct_NV2080_ALLOC_PARAMETERS._fields_ = [
  ('subDeviceId', NvU32),
]
NV2080_ALLOC_PARAMETERS = struct_NV2080_ALLOC_PARAMETERS
class struct__cl2080_tag0(Struct): pass
struct__cl2080_tag0._fields_ = [
  ('Reserved00', (NvV32 * 1984)),
]
class volatile_struct__cl2080_tag0(Struct): pass
Nv2080Typedef = volatile_struct__cl2080_tag0
volatile_struct__cl2080_tag0._fields_ = [
  ('Reserved00', (NvV32 * 1984)),
]
Nv20Subdevice0 = volatile_struct__cl2080_tag0
class struct_Nv2080HdcpStatusChangeNotificationRec(Struct): pass
struct_Nv2080HdcpStatusChangeNotificationRec._fields_ = [
  ('displayId', NvU32),
  ('hdcpStatusChangeNotif', NvU32),
]
Nv2080HdcpStatusChangeNotification = struct_Nv2080HdcpStatusChangeNotificationRec
class struct_Nv2080PStateChangeNotificationRec(Struct): pass
class struct_Nv2080PStateChangeNotificationRec_timeStamp(Struct): pass
struct_Nv2080PStateChangeNotificationRec_timeStamp._fields_ = [
  ('nanoseconds', (NvU32 * 2)),
]
struct_Nv2080PStateChangeNotificationRec._fields_ = [
  ('timeStamp', struct_Nv2080PStateChangeNotificationRec_timeStamp),
  ('NewPstate', NvU32),
]
Nv2080PStateChangeNotification = struct_Nv2080PStateChangeNotificationRec
class struct_Nv2080ClocksChangeNotificationRec(Struct): pass
class struct_Nv2080ClocksChangeNotificationRec_timeStamp(Struct): pass
struct_Nv2080ClocksChangeNotificationRec_timeStamp._fields_ = [
  ('nanoseconds', (NvU32 * 2)),
]
struct_Nv2080ClocksChangeNotificationRec._fields_ = [
  ('timeStamp', struct_Nv2080ClocksChangeNotificationRec_timeStamp),
]
Nv2080ClocksChangeNotification = struct_Nv2080ClocksChangeNotificationRec
class struct_Nv2080WorkloadModulationChangeNotificationRec(Struct): pass
class struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp(Struct): pass
struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp._fields_ = [
  ('nanoseconds', (NvU32 * 2)),
]
NvBool = ctypes.c_ubyte
struct_Nv2080WorkloadModulationChangeNotificationRec._fields_ = [
  ('timeStamp', struct_Nv2080WorkloadModulationChangeNotificationRec_timeStamp),
  ('WorkloadModulationEnabled', NvBool),
]
Nv2080WorkloadModulationChangeNotification = struct_Nv2080WorkloadModulationChangeNotificationRec
class Nv2080HotplugNotification(Struct): pass
Nv2080HotplugNotification._fields_ = [
  ('plugDisplayMask', NvU32),
  ('unplugDisplayMask', NvU32),
]
class Nv2080PowerEventNotification(Struct): pass
Nv2080PowerEventNotification._fields_ = [
  ('bSwitchToAC', NvBool),
  ('bGPUCapabilityChanged', NvBool),
  ('displayMaskAffected', NvU32),
]
class struct_Nv2080DpIrqNotificationRec(Struct): pass
struct_Nv2080DpIrqNotificationRec._fields_ = [
  ('displayId', NvU32),
]
Nv2080DpIrqNotification = struct_Nv2080DpIrqNotificationRec
class struct_Nv2080DstateXusbPpcNotificationRec(Struct): pass
struct_Nv2080DstateXusbPpcNotificationRec._fields_ = [
  ('dstateXusb', NvU32),
  ('dstatePpc', NvU32),
]
Nv2080DstateXusbPpcNotification = struct_Nv2080DstateXusbPpcNotificationRec
class struct_Nv2080XusbPpcConnectStateNotificationRec(Struct): pass
struct_Nv2080XusbPpcConnectStateNotificationRec._fields_ = [
  ('bConnected', NvBool),
]
Nv2080XusbPpcConnectStateNotification = struct_Nv2080XusbPpcConnectStateNotificationRec
class struct_Nv2080ACPIEvent(Struct): pass
struct_Nv2080ACPIEvent._fields_ = [
  ('event', NvU32),
]
Nv2080ACPIEvent = struct_Nv2080ACPIEvent
class struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC(Struct): pass
struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC._fields_ = [
  ('currentZone', NvU32),
]
NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC
class struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC(Struct): pass
struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC._fields_ = [
  ('currentZone', NvU32),
]
NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC = struct__NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC
class struct_Nv2080AudioHdcpRequestRec(Struct): pass
struct_Nv2080AudioHdcpRequestRec._fields_ = [
  ('displayId', NvU32),
  ('requestedState', NvU32),
]
Nv2080AudioHdcpRequest = struct_Nv2080AudioHdcpRequestRec
class struct_Nv2080GC5GpuReadyParams(Struct): pass
struct_Nv2080GC5GpuReadyParams._fields_ = [
  ('event', NvU32),
  ('sciIntr0', NvU32),
  ('sciIntr1', NvU32),
]
Nv2080GC5GpuReadyParams = struct_Nv2080GC5GpuReadyParams
class Nv2080PrivRegAccessFaultNotification(Struct): pass
Nv2080PrivRegAccessFaultNotification._fields_ = [
  ('errAddr', NvU32),
]
class struct_Nv2080DstateHdaCodecNotificationRec(Struct): pass
struct_Nv2080DstateHdaCodecNotificationRec._fields_ = [
  ('dstateHdaCodec', NvU32),
]
Nv2080DstateHdaCodecNotification = struct_Nv2080DstateHdaCodecNotificationRec
class struct_Nv2080HdmiFrlRequestNotificationRec(Struct): pass
struct_Nv2080HdmiFrlRequestNotificationRec._fields_ = [
  ('displayId', NvU32),
]
Nv2080HdmiFrlRequestNotification = struct_Nv2080HdmiFrlRequestNotificationRec
class struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS(Struct): pass
NvU8 = ctypes.c_ubyte
struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS._fields_ = [
  ('platformPowerModeIndex', NvU8),
  ('platformPowerModeMask', NvU8),
  ('eventReason', NvU8),
]
NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS = struct__NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS
class struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE(Struct): pass
struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE._fields_ = [
  ('workloadType', NvU8),
]
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE = struct__NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE
class Nv2080QosIntrNotification(Struct): pass
Nv2080QosIntrNotification._fields_ = [
  ('engineType', NvU32),
]
class Nv2080EccDbeNotification(Struct): pass
Nv2080EccDbeNotification._fields_ = [
  ('physAddress', NvU64),
]
class Nv2080LpwrDifrPrefetchNotification(Struct): pass
Nv2080LpwrDifrPrefetchNotification._fields_ = [
  ('l2CacheSize', NvU32),
]
class Nv2080NvlinkLnkChangeNotification(Struct): pass
Nv2080NvlinkLnkChangeNotification._fields_ = [
  ('GpuId', NvU32),
  ('linkId', NvU32),
]
class Nv2080VrrSetTimeoutNotification(Struct): pass
Nv2080VrrSetTimeoutNotification._fields_ = [
  ('head', NvU32),
]
class struct_Nvc56fControl_struct(Struct): pass
struct_Nvc56fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 16)),
  ('Put', NvU32),
  ('Get', NvU32),
  ('Reference', NvU32),
  ('PutHi', NvU32),
  ('Ignored01', (NvU32 * 2)),
  ('TopLevelGet', NvU32),
  ('TopLevelGetHi', NvU32),
  ('GetHi', NvU32),
  ('Ignored02', (NvU32 * 7)),
  ('Ignored03', NvU32),
  ('Ignored04', (NvU32 * 1)),
  ('GPGet', NvU32),
  ('GPPut', NvU32),
  ('Ignored05', (NvU32 * 92)),
]
class volatile_struct_Nvc56fControl_struct(Struct): pass
Nvc56fControl = volatile_struct_Nvc56fControl_struct
volatile_struct_Nvc56fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 16)),
  ('Put', NvU32),
  ('Get', NvU32),
  ('Reference', NvU32),
  ('PutHi', NvU32),
  ('Ignored01', (NvU32 * 2)),
  ('TopLevelGet', NvU32),
  ('TopLevelGetHi', NvU32),
  ('GetHi', NvU32),
  ('Ignored02', (NvU32 * 7)),
  ('Ignored03', NvU32),
  ('Ignored04', (NvU32 * 1)),
  ('GPGet', NvU32),
  ('GPPut', NvU32),
  ('Ignored05', (NvU32 * 92)),
]
AmpereAControlGPFifo = volatile_struct_Nvc56fControl_struct
class struct_Nvc86fControl_struct(Struct): pass
struct_Nvc86fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 16)),
  ('Put', NvU32),
  ('Get', NvU32),
  ('Reference', NvU32),
  ('PutHi', NvU32),
  ('Ignored01', (NvU32 * 2)),
  ('TopLevelGet', NvU32),
  ('TopLevelGetHi', NvU32),
  ('GetHi', NvU32),
  ('Ignored02', (NvU32 * 7)),
  ('Ignored03', NvU32),
  ('Ignored04', (NvU32 * 1)),
  ('GPGet', NvU32),
  ('GPPut', NvU32),
  ('Ignored05', (NvU32 * 92)),
]
class volatile_struct_Nvc86fControl_struct(Struct): pass
Nvc86fControl = volatile_struct_Nvc86fControl_struct
volatile_struct_Nvc86fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 16)),
  ('Put', NvU32),
  ('Get', NvU32),
  ('Reference', NvU32),
  ('PutHi', NvU32),
  ('Ignored01', (NvU32 * 2)),
  ('TopLevelGet', NvU32),
  ('TopLevelGetHi', NvU32),
  ('GetHi', NvU32),
  ('Ignored02', (NvU32 * 7)),
  ('Ignored03', NvU32),
  ('Ignored04', (NvU32 * 1)),
  ('GPGet', NvU32),
  ('GPPut', NvU32),
  ('Ignored05', (NvU32 * 92)),
]
HopperAControlGPFifo = volatile_struct_Nvc86fControl_struct
class struct_Nvc96fControl_struct(Struct): pass
struct_Nvc96fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 35)),
  ('GPPut', NvU32),
  ('Ignored01', (NvU32 * 92)),
]
class volatile_struct_Nvc96fControl_struct(Struct): pass
Nvc96fControl = volatile_struct_Nvc96fControl_struct
volatile_struct_Nvc96fControl_struct._fields_ = [
  ('Ignored00', (NvU32 * 35)),
  ('GPPut', NvU32),
  ('Ignored01', (NvU32 * 92)),
]
BlackwellAControlGPFifo = volatile_struct_Nvc96fControl_struct
class struct_NV83DE_ALLOC_PARAMETERS(Struct): pass
struct_NV83DE_ALLOC_PARAMETERS._fields_ = [
  ('hDebuggerClient_Obsolete', NvHandle),
  ('hAppClient', NvHandle),
  ('hClass3dObject', NvHandle),
]
NV83DE_ALLOC_PARAMETERS = struct_NV83DE_ALLOC_PARAMETERS
class struct__clc9b5_tag0(Struct): pass
struct__clc9b5_tag0._fields_ = [
  ('Reserved00', (NvV32 * 64)),
  ('Nop', NvV32),
  ('Reserved01', (NvV32 * 15)),
  ('PmTrigger', NvV32),
  ('Reserved02', (NvV32 * 54)),
  ('SetMonitoredFenceType', NvV32),
  ('SetMonitoredFenceSignalAddrBaseUpper', NvV32),
  ('SetMonitoredFenceSignalAddrBaseLower', NvV32),
  ('Reserved03', (NvV32 * 6)),
  ('SetSemaphoreA', NvV32),
  ('SetSemaphoreB', NvV32),
  ('SetSemaphorePayload', NvV32),
  ('SetSemaphorePayloadUpper', NvV32),
  ('Reserved04', (NvV32 * 1)),
  ('SetRenderEnableA', NvV32),
  ('SetRenderEnableB', NvV32),
  ('SetRenderEnableC', NvV32),
  ('SetSrcPhysMode', NvV32),
  ('SetDstPhysMode', NvV32),
  ('Reserved05', (NvV32 * 38)),
  ('LaunchDma', NvV32),
  ('Reserved06', (NvV32 * 63)),
  ('OffsetInUpper', NvV32),
  ('OffsetInLower', NvV32),
  ('OffsetOutUpper', NvV32),
  ('OffsetOutLower', NvV32),
  ('PitchIn', NvV32),
  ('PitchOut', NvV32),
  ('LineLengthIn', NvV32),
  ('LineCount', NvV32),
  ('Reserved07', (NvV32 * 56)),
  ('SetSecureCopyMode', NvV32),
  ('SetDecryptIv0', NvV32),
  ('SetDecryptIv1', NvV32),
  ('SetDecryptIv2', NvV32),
  ('Reserved_SetAESCounter', NvV32),
  ('SetDecryptAuthTagCompareAddrUpper', NvV32),
  ('SetDecryptAuthTagCompareAddrLower', NvV32),
  ('Reserved08', (NvV32 * 5)),
  ('SetEncryptAuthTagAddrUpper', NvV32),
  ('SetEncryptAuthTagAddrLower', NvV32),
  ('SetEncryptIvAddrUpper', NvV32),
  ('SetEncryptIvAddrLower', NvV32),
  ('Reserved09', (NvV32 * 16)),
  ('SetCompressionParameters', NvV32),
  ('SetDecompressOutLength', NvV32),
  ('SetDecompressOutLengthAddrUpper', NvV32),
  ('SetDecompressOutLengthAddrLower', NvV32),
  ('SetDecompressChecksum', NvV32),
  ('Reserved10', (NvV32 * 90)),
  ('SetMemoryScrubParameters', NvV32),
  ('SetRemapConstA', NvV32),
  ('SetRemapConstB', NvV32),
  ('SetRemapComponents', NvV32),
  ('SetDstBlockSize', NvV32),
  ('SetDstWidth', NvV32),
  ('SetDstHeight', NvV32),
  ('SetDstDepth', NvV32),
  ('SetDstLayer', NvV32),
  ('SetDstOrigin', NvV32),
  ('Reserved11', (NvV32 * 1)),
  ('SetSrcBlockSize', NvV32),
  ('SetSrcWidth', NvV32),
  ('SetSrcHeight', NvV32),
  ('SetSrcDepth', NvV32),
  ('SetSrcLayer', NvV32),
  ('SetSrcOrigin', NvV32),
  ('Reserved12', (NvV32 * 1)),
  ('SrcOriginX', NvV32),
  ('SrcOriginY', NvV32),
  ('DstOriginX', NvV32),
  ('DstOriginY', NvV32),
  ('Reserved13', (NvV32 * 624)),
  ('PmTriggerEnd', NvV32),
  ('Reserved14', (NvV32 * 954)),
]
class volatile_struct__clc9b5_tag0(Struct): pass
blackwell_dma_copy_aControlPio = volatile_struct__clc9b5_tag0
volatile_struct__clc9b5_tag0._fields_ = [
  ('Reserved00', (NvV32 * 64)),
  ('Nop', NvV32),
  ('Reserved01', (NvV32 * 15)),
  ('PmTrigger', NvV32),
  ('Reserved02', (NvV32 * 54)),
  ('SetMonitoredFenceType', NvV32),
  ('SetMonitoredFenceSignalAddrBaseUpper', NvV32),
  ('SetMonitoredFenceSignalAddrBaseLower', NvV32),
  ('Reserved03', (NvV32 * 6)),
  ('SetSemaphoreA', NvV32),
  ('SetSemaphoreB', NvV32),
  ('SetSemaphorePayload', NvV32),
  ('SetSemaphorePayloadUpper', NvV32),
  ('Reserved04', (NvV32 * 1)),
  ('SetRenderEnableA', NvV32),
  ('SetRenderEnableB', NvV32),
  ('SetRenderEnableC', NvV32),
  ('SetSrcPhysMode', NvV32),
  ('SetDstPhysMode', NvV32),
  ('Reserved05', (NvV32 * 38)),
  ('LaunchDma', NvV32),
  ('Reserved06', (NvV32 * 63)),
  ('OffsetInUpper', NvV32),
  ('OffsetInLower', NvV32),
  ('OffsetOutUpper', NvV32),
  ('OffsetOutLower', NvV32),
  ('PitchIn', NvV32),
  ('PitchOut', NvV32),
  ('LineLengthIn', NvV32),
  ('LineCount', NvV32),
  ('Reserved07', (NvV32 * 56)),
  ('SetSecureCopyMode', NvV32),
  ('SetDecryptIv0', NvV32),
  ('SetDecryptIv1', NvV32),
  ('SetDecryptIv2', NvV32),
  ('Reserved_SetAESCounter', NvV32),
  ('SetDecryptAuthTagCompareAddrUpper', NvV32),
  ('SetDecryptAuthTagCompareAddrLower', NvV32),
  ('Reserved08', (NvV32 * 5)),
  ('SetEncryptAuthTagAddrUpper', NvV32),
  ('SetEncryptAuthTagAddrLower', NvV32),
  ('SetEncryptIvAddrUpper', NvV32),
  ('SetEncryptIvAddrLower', NvV32),
  ('Reserved09', (NvV32 * 16)),
  ('SetCompressionParameters', NvV32),
  ('SetDecompressOutLength', NvV32),
  ('SetDecompressOutLengthAddrUpper', NvV32),
  ('SetDecompressOutLengthAddrLower', NvV32),
  ('SetDecompressChecksum', NvV32),
  ('Reserved10', (NvV32 * 90)),
  ('SetMemoryScrubParameters', NvV32),
  ('SetRemapConstA', NvV32),
  ('SetRemapConstB', NvV32),
  ('SetRemapComponents', NvV32),
  ('SetDstBlockSize', NvV32),
  ('SetDstWidth', NvV32),
  ('SetDstHeight', NvV32),
  ('SetDstDepth', NvV32),
  ('SetDstLayer', NvV32),
  ('SetDstOrigin', NvV32),
  ('Reserved11', (NvV32 * 1)),
  ('SetSrcBlockSize', NvV32),
  ('SetSrcWidth', NvV32),
  ('SetSrcHeight', NvV32),
  ('SetSrcDepth', NvV32),
  ('SetSrcLayer', NvV32),
  ('SetSrcOrigin', NvV32),
  ('Reserved12', (NvV32 * 1)),
  ('SrcOriginX', NvV32),
  ('SrcOriginY', NvV32),
  ('DstOriginX', NvV32),
  ('DstOriginY', NvV32),
  ('Reserved13', (NvV32 * 624)),
  ('PmTriggerEnd', NvV32),
  ('Reserved14', (NvV32 * 954)),
]
class UVM_RESERVE_VA_PARAMS(Struct): pass
NV_STATUS = ctypes.c_uint32
UVM_RESERVE_VA_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_RELEASE_VA_PARAMS(Struct): pass
UVM_RELEASE_VA_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_REGION_COMMIT_PARAMS(Struct): pass
UvmStream = ctypes.c_uint64
class struct_nv_uuid(Struct): pass
NvProcessorUuid = struct_nv_uuid
struct_nv_uuid._fields_ = [
  ('uuid', (NvU8 * 16)),
]
UVM_REGION_COMMIT_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('streamId', UvmStream),
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_REGION_DECOMMIT_PARAMS(Struct): pass
UVM_REGION_DECOMMIT_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_REGION_SET_STREAM_PARAMS(Struct): pass
UVM_REGION_SET_STREAM_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('newStreamId', UvmStream),
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_SET_STREAM_RUNNING_PARAMS(Struct): pass
UVM_SET_STREAM_RUNNING_PARAMS._fields_ = [
  ('streamId', UvmStream),
  ('rmStatus', NV_STATUS),
]
class UVM_SET_STREAM_STOPPED_PARAMS(Struct): pass
UVM_SET_STREAM_STOPPED_PARAMS._fields_ = [
  ('streamIdArray', (UvmStream * 32)),
  ('nStreams', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_RUN_TEST_PARAMS(Struct): pass
class UVM_RUN_TEST_PARAMS_multiGpu(Struct): pass
UVM_RUN_TEST_PARAMS_multiGpu._fields_ = [
  ('peerGpuUuid', NvProcessorUuid),
  ('peerId', NvU32),
]
UVM_RUN_TEST_PARAMS._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('test', NvU32),
  ('multiGpu', UVM_RUN_TEST_PARAMS_multiGpu),
  ('rmStatus', NV_STATUS),
]
class UVM_ADD_SESSION_PARAMS(Struct): pass
NvS32 = ctypes.c_int32
UVM_ADD_SESSION_PARAMS._fields_ = [
  ('pidTarget', NvU32),
  ('countersBaseAddress', NvP64),
  ('sessionIndex', NvS32),
  ('rmStatus', NV_STATUS),
]
class UVM_REMOVE_SESSION_PARAMS(Struct): pass
UVM_REMOVE_SESSION_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('rmStatus', NV_STATUS),
]
class UVM_ENABLE_COUNTERS_PARAMS(Struct): pass
class UvmCounterConfig(Struct): pass
UvmCounterConfig._fields_ = [
  ('scope', NvU32),
  ('name', NvU32),
  ('gpuid', NvProcessorUuid),
  ('state', NvU32),
]
UVM_ENABLE_COUNTERS_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('config', (UvmCounterConfig * 32)),
  ('count', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_MAP_COUNTER_PARAMS(Struct): pass
UVM_MAP_COUNTER_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('scope', NvU32),
  ('counterName', NvU32),
  ('gpuUuid', NvProcessorUuid),
  ('addr', NvP64),
  ('rmStatus', NV_STATUS),
]
class UVM_CREATE_EVENT_QUEUE_PARAMS(Struct): pass
UVM_CREATE_EVENT_QUEUE_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('eventQueueIndex', NvU32),
  ('queueSize', NvU64),
  ('notificationCount', NvU64),
  ('timeStampType', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_REMOVE_EVENT_QUEUE_PARAMS(Struct): pass
UVM_REMOVE_EVENT_QUEUE_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('eventQueueIndex', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_MAP_EVENT_QUEUE_PARAMS(Struct): pass
UVM_MAP_EVENT_QUEUE_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('eventQueueIndex', NvU32),
  ('userRODataAddr', NvP64),
  ('userRWDataAddr', NvP64),
  ('readIndexAddr', NvP64),
  ('writeIndexAddr', NvP64),
  ('queueBufferAddr', NvP64),
  ('rmStatus', NV_STATUS),
]
class UVM_EVENT_CTRL_PARAMS(Struct): pass
UVM_EVENT_CTRL_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('eventQueueIndex', NvU32),
  ('eventType', NvS32),
  ('enable', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_REGISTER_MPS_SERVER_PARAMS(Struct): pass
UVM_REGISTER_MPS_SERVER_PARAMS._fields_ = [
  ('gpuUuidArray', (NvProcessorUuid * 32)),
  ('numGpus', NvU32),
  ('serverId', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_REGISTER_MPS_CLIENT_PARAMS(Struct): pass
UVM_REGISTER_MPS_CLIENT_PARAMS._fields_ = [
  ('serverId', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_GET_GPU_UUID_TABLE_PARAMS(Struct): pass
UVM_GET_GPU_UUID_TABLE_PARAMS._fields_ = [
  ('gpuUuidArray', (NvProcessorUuid * 32)),
  ('validCount', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_CREATE_RANGE_GROUP_PARAMS(Struct): pass
UVM_CREATE_RANGE_GROUP_PARAMS._fields_ = [
  ('rangeGroupId', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_DESTROY_RANGE_GROUP_PARAMS(Struct): pass
UVM_DESTROY_RANGE_GROUP_PARAMS._fields_ = [
  ('rangeGroupId', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_REGISTER_GPU_VASPACE_PARAMS(Struct): pass
UVM_REGISTER_GPU_VASPACE_PARAMS._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('rmCtrlFd', NvS32),
  ('hClient', NvHandle),
  ('hVaSpace', NvHandle),
  ('rmStatus', NV_STATUS),
]
class UVM_UNREGISTER_GPU_VASPACE_PARAMS(Struct): pass
UVM_UNREGISTER_GPU_VASPACE_PARAMS._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_REGISTER_CHANNEL_PARAMS(Struct): pass
UVM_REGISTER_CHANNEL_PARAMS._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('rmCtrlFd', NvS32),
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('base', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_UNREGISTER_CHANNEL_PARAMS(Struct): pass
UVM_UNREGISTER_CHANNEL_PARAMS._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('rmStatus', NV_STATUS),
]
class UVM_ENABLE_PEER_ACCESS_PARAMS(Struct): pass
UVM_ENABLE_PEER_ACCESS_PARAMS._fields_ = [
  ('gpuUuidA', NvProcessorUuid),
  ('gpuUuidB', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_DISABLE_PEER_ACCESS_PARAMS(Struct): pass
UVM_DISABLE_PEER_ACCESS_PARAMS._fields_ = [
  ('gpuUuidA', NvProcessorUuid),
  ('gpuUuidB', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_SET_RANGE_GROUP_PARAMS(Struct): pass
UVM_SET_RANGE_GROUP_PARAMS._fields_ = [
  ('rangeGroupId', NvU64),
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_MAP_EXTERNAL_ALLOCATION_PARAMS(Struct): pass
class UvmGpuMappingAttributes(Struct): pass
UvmGpuMappingAttributes._fields_ = [
  ('gpuUuid', NvProcessorUuid),
  ('gpuMappingType', NvU32),
  ('gpuCachingType', NvU32),
  ('gpuFormatType', NvU32),
  ('gpuElementBits', NvU32),
  ('gpuCompressionType', NvU32),
]
UVM_MAP_EXTERNAL_ALLOCATION_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('offset', NvU64),
  ('perGpuAttributes', (UvmGpuMappingAttributes * 256)),
  ('gpuAttributesCount', NvU64),
  ('rmCtrlFd', NvS32),
  ('hClient', NvU32),
  ('hMemory', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_FREE_PARAMS(Struct): pass
UVM_FREE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_MEM_MAP_PARAMS(Struct): pass
UVM_MEM_MAP_PARAMS._fields_ = [
  ('regionBase', NvP64),
  ('regionLength', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_DEBUG_ACCESS_MEMORY_PARAMS(Struct): pass
UVM_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [
  ('sessionIndex', NvS32),
  ('baseAddress', NvU64),
  ('sizeInBytes', NvU64),
  ('accessType', NvU32),
  ('buffer', NvU64),
  ('isBitmaskSet', NvBool),
  ('bitmask', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_REGISTER_GPU_PARAMS(Struct): pass
UVM_REGISTER_GPU_PARAMS._fields_ = [
  ('gpu_uuid', NvProcessorUuid),
  ('numaEnabled', NvBool),
  ('numaNodeId', NvS32),
  ('rmCtrlFd', NvS32),
  ('hClient', NvHandle),
  ('hSmcPartRef', NvHandle),
  ('rmStatus', NV_STATUS),
]
class UVM_UNREGISTER_GPU_PARAMS(Struct): pass
UVM_UNREGISTER_GPU_PARAMS._fields_ = [
  ('gpu_uuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_PAGEABLE_MEM_ACCESS_PARAMS(Struct): pass
UVM_PAGEABLE_MEM_ACCESS_PARAMS._fields_ = [
  ('pageableMemAccess', NvBool),
  ('rmStatus', NV_STATUS),
]
class UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS(Struct): pass
UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [
  ('rangeGroupIds', (NvU64 * 32)),
  ('numGroupIds', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS(Struct): pass
UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS._fields_ = [
  ('rangeGroupIds', (NvU64 * 32)),
  ('numGroupIds', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_SET_PREFERRED_LOCATION_PARAMS(Struct): pass
UVM_SET_PREFERRED_LOCATION_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('preferredLocation', NvProcessorUuid),
  ('preferredCpuNumaNode', NvS32),
  ('rmStatus', NV_STATUS),
]
class UVM_UNSET_PREFERRED_LOCATION_PARAMS(Struct): pass
UVM_UNSET_PREFERRED_LOCATION_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_ENABLE_READ_DUPLICATION_PARAMS(Struct): pass
UVM_ENABLE_READ_DUPLICATION_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_DISABLE_READ_DUPLICATION_PARAMS(Struct): pass
UVM_DISABLE_READ_DUPLICATION_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_SET_ACCESSED_BY_PARAMS(Struct): pass
UVM_SET_ACCESSED_BY_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('accessedByUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_UNSET_ACCESSED_BY_PARAMS(Struct): pass
UVM_UNSET_ACCESSED_BY_PARAMS._fields_ = [
  ('requestedBase', NvU64),
  ('length', NvU64),
  ('accessedByUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_MIGRATE_PARAMS(Struct): pass
UVM_MIGRATE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('destinationUuid', NvProcessorUuid),
  ('flags', NvU32),
  ('semaphoreAddress', NvU64),
  ('semaphorePayload', NvU32),
  ('cpuNumaNode', NvS32),
  ('userSpaceStart', NvU64),
  ('userSpaceLength', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_MIGRATE_RANGE_GROUP_PARAMS(Struct): pass
UVM_MIGRATE_RANGE_GROUP_PARAMS._fields_ = [
  ('rangeGroupId', NvU64),
  ('destinationUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Struct): pass
UVM_ENABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [
  ('gpu_uuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS(Struct): pass
UVM_DISABLE_SYSTEM_WIDE_ATOMICS_PARAMS._fields_ = [
  ('gpu_uuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS(Struct): pass
UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS._fields_ = [
  ('queueBuffer', NvU64),
  ('queueBufferSize', NvU64),
  ('controlBuffer', NvU64),
  ('processor', NvProcessorUuid),
  ('allProcessors', NvU32),
  ('uvmFd', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS(Struct): pass
UVM_TOOLS_SET_NOTIFICATION_THRESHOLD_PARAMS._fields_ = [
  ('notificationThreshold', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS(Struct): pass
UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS_PARAMS._fields_ = [
  ('eventTypeFlags', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS(Struct): pass
UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS_PARAMS._fields_ = [
  ('eventTypeFlags', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_ENABLE_COUNTERS_PARAMS(Struct): pass
UVM_TOOLS_ENABLE_COUNTERS_PARAMS._fields_ = [
  ('counterTypeFlags', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_DISABLE_COUNTERS_PARAMS(Struct): pass
UVM_TOOLS_DISABLE_COUNTERS_PARAMS._fields_ = [
  ('counterTypeFlags', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS(Struct): pass
UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS._fields_ = [
  ('buffer', NvU64),
  ('size', NvU64),
  ('targetVa', NvU64),
  ('bytesRead', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS(Struct): pass
UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS._fields_ = [
  ('buffer', NvU64),
  ('size', NvU64),
  ('targetVa', NvU64),
  ('bytesWritten', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS(Struct): pass
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS._fields_ = [
  ('tablePtr', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS(Struct): pass
UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_UNMAP_EXTERNAL_PARAMS(Struct): pass
UVM_UNMAP_EXTERNAL_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_TOOLS_FLUSH_EVENTS_PARAMS(Struct): pass
UVM_TOOLS_FLUSH_EVENTS_PARAMS._fields_ = [
  ('rmStatus', NV_STATUS),
]
class UVM_ALLOC_SEMAPHORE_POOL_PARAMS(Struct): pass
UVM_ALLOC_SEMAPHORE_POOL_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('perGpuAttributes', (UvmGpuMappingAttributes * 256)),
  ('gpuAttributesCount', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS(Struct): pass
UVM_CLEAN_UP_ZOMBIE_RESOURCES_PARAMS._fields_ = [
  ('rmStatus', NV_STATUS),
]
class UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS(Struct): pass
UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS._fields_ = [
  ('gpu_uuid', NvProcessorUuid),
  ('pageableMemAccess', NvBool),
  ('rmStatus', NV_STATUS),
]
class UVM_POPULATE_PAGEABLE_PARAMS(Struct): pass
UVM_POPULATE_PAGEABLE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('flags', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_VALIDATE_VA_RANGE_PARAMS(Struct): pass
UVM_VALIDATE_VA_RANGE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_CREATE_EXTERNAL_RANGE_PARAMS(Struct): pass
UVM_CREATE_EXTERNAL_RANGE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('rmStatus', NV_STATUS),
]
class UVM_MAP_EXTERNAL_SPARSE_PARAMS(Struct): pass
UVM_MAP_EXTERNAL_SPARSE_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('gpuUuid', NvProcessorUuid),
  ('rmStatus', NV_STATUS),
]
class UVM_MM_INITIALIZE_PARAMS(Struct): pass
UVM_MM_INITIALIZE_PARAMS._fields_ = [
  ('uvmFd', NvS32),
  ('rmStatus', NV_STATUS),
]
UVM_TOOLS_INIT_EVENT_TRACKER_V2_PARAMS = UVM_TOOLS_INIT_EVENT_TRACKER_PARAMS
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2_PARAMS = UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_PARAMS
class UVM_ALLOC_DEVICE_P2P_PARAMS(Struct): pass
UVM_ALLOC_DEVICE_P2P_PARAMS._fields_ = [
  ('base', NvU64),
  ('length', NvU64),
  ('offset', NvU64),
  ('gpuUuid', NvProcessorUuid),
  ('rmCtrlFd', NvS32),
  ('hClient', NvU32),
  ('hMemory', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS(Struct): pass
UVM_CLEAR_ALL_ACCESS_COUNTERS_PARAMS._fields_ = [
  ('rmStatus', NV_STATUS),
]
class UVM_IS_8_SUPPORTED_PARAMS(Struct): pass
UVM_IS_8_SUPPORTED_PARAMS._fields_ = [
  ('is8Supported', NvU32),
  ('rmStatus', NV_STATUS),
]
class UVM_INITIALIZE_PARAMS(Struct): pass
UVM_INITIALIZE_PARAMS._fields_ = [
  ('flags', NvU64),
  ('rmStatus', NV_STATUS),
]
class nv_pci_info_t(Struct): pass
NvU16 = ctypes.c_uint16
nv_pci_info_t._fields_ = [
  ('domain', NvU32),
  ('bus', NvU8),
  ('slot', NvU8),
  ('function', NvU8),
  ('vendor_id', NvU16),
  ('device_id', NvU16),
]
class struct_nv_ioctl_xfer(Struct): pass
struct_nv_ioctl_xfer._fields_ = [
  ('cmd', NvU32),
  ('size', NvU32),
  ('ptr', NvP64),
]
nv_ioctl_xfer_t = struct_nv_ioctl_xfer
class struct_nv_ioctl_card_info(Struct): pass
struct_nv_ioctl_card_info._fields_ = [
  ('valid', NvBool),
  ('pci_info', nv_pci_info_t),
  ('gpu_id', NvU32),
  ('interrupt_line', NvU16),
  ('reg_address', NvU64),
  ('reg_size', NvU64),
  ('fb_address', NvU64),
  ('fb_size', NvU64),
  ('minor_number', NvU32),
  ('dev_name', (NvU8 * 10)),
]
nv_ioctl_card_info_t = struct_nv_ioctl_card_info
class struct_nv_ioctl_alloc_os_event(Struct): pass
struct_nv_ioctl_alloc_os_event._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('fd', NvU32),
  ('Status', NvU32),
]
nv_ioctl_alloc_os_event_t = struct_nv_ioctl_alloc_os_event
class struct_nv_ioctl_free_os_event(Struct): pass
struct_nv_ioctl_free_os_event._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('fd', NvU32),
  ('Status', NvU32),
]
nv_ioctl_free_os_event_t = struct_nv_ioctl_free_os_event
class struct_nv_ioctl_status_code(Struct): pass
struct_nv_ioctl_status_code._fields_ = [
  ('domain', NvU32),
  ('bus', NvU8),
  ('slot', NvU8),
  ('status', NvU32),
]
nv_ioctl_status_code_t = struct_nv_ioctl_status_code
class struct_nv_ioctl_rm_api_version(Struct): pass
struct_nv_ioctl_rm_api_version._fields_ = [
  ('cmd', NvU32),
  ('reply', NvU32),
  ('versionString', (ctypes.c_char * 64)),
]
nv_ioctl_rm_api_version_t = struct_nv_ioctl_rm_api_version
class struct_nv_ioctl_query_device_intr(Struct): pass
struct_nv_ioctl_query_device_intr._fields_ = [
  ('intrStatus', NvU32),
  ('status', NvU32),
]
nv_ioctl_query_device_intr = struct_nv_ioctl_query_device_intr
class struct_nv_ioctl_sys_params(Struct): pass
struct_nv_ioctl_sys_params._fields_ = [
  ('memblock_size', NvU64),
]
nv_ioctl_sys_params_t = struct_nv_ioctl_sys_params
class struct_nv_ioctl_register_fd(Struct): pass
struct_nv_ioctl_register_fd._fields_ = [
  ('ctl_fd', ctypes.c_int32),
]
nv_ioctl_register_fd_t = struct_nv_ioctl_register_fd
class struct_nv_ioctl_export_to_dma_buf_fd(Struct): pass
struct_nv_ioctl_export_to_dma_buf_fd._fields_ = [
  ('fd', ctypes.c_int32),
  ('hClient', NvHandle),
  ('totalObjects', NvU32),
  ('numObjects', NvU32),
  ('index', NvU32),
  ('totalSize', NvU64),
  ('mappingType', NvU8),
  ('handles', (NvHandle * 128)),
  ('offsets', (NvU64 * 128)),
  ('sizes', (NvU64 * 128)),
  ('status', NvU32),
]
nv_ioctl_export_to_dma_buf_fd_t = struct_nv_ioctl_export_to_dma_buf_fd
class struct_nv_ioctl_wait_open_complete(Struct): pass
struct_nv_ioctl_wait_open_complete._fields_ = [
  ('rc', ctypes.c_int32),
  ('adapterStatus', NvU32),
]
nv_ioctl_wait_open_complete_t = struct_nv_ioctl_wait_open_complete
class struct_offline_addresses(Struct): pass
uint64_t = ctypes.c_uint64
uint32_t = ctypes.c_uint32
struct_offline_addresses._fields_ = [
  ('addresses', (uint64_t * 64)),
  ('numEntries', uint32_t),
]
nv_offline_addresses_t = struct_offline_addresses
class struct_nv_ioctl_numa_info(Struct): pass
int32_t = ctypes.c_int32
uint8_t = ctypes.c_ubyte
struct_nv_ioctl_numa_info._fields_ = [
  ('nid', int32_t),
  ('status', int32_t),
  ('memblock_size', uint64_t),
  ('numa_mem_addr', uint64_t),
  ('numa_mem_size', uint64_t),
  ('use_auto_online', uint8_t),
  ('offline_addresses', nv_offline_addresses_t),
]
nv_ioctl_numa_info_t = struct_nv_ioctl_numa_info
class struct_nv_ioctl_set_numa_status(Struct): pass
struct_nv_ioctl_set_numa_status._fields_ = [
  ('status', int32_t),
]
nv_ioctl_set_numa_status_t = struct_nv_ioctl_set_numa_status
class nv_ioctl_nvos02_parameters_with_fd(Struct): pass
class NVOS02_PARAMETERS(Struct): pass
NVOS02_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('flags', NvV32),
  ('pMemory', NvP64),
  ('limit', NvU64),
  ('status', NvV32),
]
nv_ioctl_nvos02_parameters_with_fd._fields_ = [
  ('params', NVOS02_PARAMETERS),
  ('fd', ctypes.c_int32),
]
class nv_ioctl_nvos33_parameters_with_fd(Struct): pass
class NVOS33_PARAMETERS(Struct): pass
NVOS33_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hMemory', NvHandle),
  ('offset', NvU64),
  ('length', NvU64),
  ('pLinearAddress', NvP64),
  ('status', NvU32),
  ('flags', NvU32),
]
nv_ioctl_nvos33_parameters_with_fd._fields_ = [
  ('params', NVOS33_PARAMETERS),
  ('fd', ctypes.c_int32),
]
class struct_NV_MEMORY_DESC_PARAMS(Struct): pass
struct_NV_MEMORY_DESC_PARAMS._fields_ = [
  ('base', NvU64),
  ('size', NvU64),
  ('addressSpace', NvU32),
  ('cacheAttrib', NvU32),
]
NV_MEMORY_DESC_PARAMS = struct_NV_MEMORY_DESC_PARAMS
class struct_NV_CHANNEL_ALLOC_PARAMS(Struct): pass
struct_NV_CHANNEL_ALLOC_PARAMS._fields_ = [
  ('hObjectError', NvHandle),
  ('hObjectBuffer', NvHandle),
  ('gpFifoOffset', NvU64),
  ('gpFifoEntries', NvU32),
  ('flags', NvU32),
  ('hContextShare', NvHandle),
  ('hVASpace', NvHandle),
  ('hUserdMemory', (NvHandle * 8)),
  ('userdOffset', (NvU64 * 8)),
  ('engineType', NvU32),
  ('cid', NvU32),
  ('subDeviceId', NvU32),
  ('hObjectEccError', NvHandle),
  ('instanceMem', NV_MEMORY_DESC_PARAMS),
  ('userdMem', NV_MEMORY_DESC_PARAMS),
  ('ramfcMem', NV_MEMORY_DESC_PARAMS),
  ('mthdbufMem', NV_MEMORY_DESC_PARAMS),
  ('hPhysChannelGroup', NvHandle),
  ('internalFlags', NvU32),
  ('errorNotifierMem', NV_MEMORY_DESC_PARAMS),
  ('eccErrorNotifierMem', NV_MEMORY_DESC_PARAMS),
  ('ProcessID', NvU32),
  ('SubProcessID', NvU32),
  ('encryptIv', (NvU32 * 3)),
  ('decryptIv', (NvU32 * 3)),
  ('hmacNonce', (NvU32 * 8)),
  ('tpcConfigID', NvU32),
]
NV_CHANNEL_ALLOC_PARAMS = struct_NV_CHANNEL_ALLOC_PARAMS
NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS = struct_NV_CHANNEL_ALLOC_PARAMS
class NVOS00_PARAMETERS(Struct): pass
NVOS00_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectOld', NvHandle),
  ('status', NvV32),
]
class NVOS05_PARAMETERS(Struct): pass
NVOS05_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('status', NvV32),
]
Callback1ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.c_void_p)
Callback5ArgVoidReturn = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32)
class NVOS10_EVENT_KERNEL_CALLBACK(Struct): pass
NVOS10_EVENT_KERNEL_CALLBACK._fields_ = [
  ('func', Callback1ArgVoidReturn),
  ('arg', ctypes.c_void_p),
]
class NVOS10_EVENT_KERNEL_CALLBACK_EX(Struct): pass
NVOS10_EVENT_KERNEL_CALLBACK_EX._fields_ = [
  ('func', Callback5ArgVoidReturn),
  ('arg', ctypes.c_void_p),
]
class NVOS_I2C_ACCESS_PARAMS(Struct): pass
NVOS_I2C_ACCESS_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('paramSize', NvU32),
  ('paramStructPtr', NvP64),
  ('status', NvV32),
]
class NVOS21_PARAMETERS(Struct): pass
NVOS21_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('pAllocParms', NvP64),
  ('paramsSize', NvU32),
  ('status', NvV32),
]
class NVOS64_PARAMETERS(Struct): pass
NVOS64_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('pAllocParms', NvP64),
  ('pRightsRequested', NvP64),
  ('paramsSize', NvU32),
  ('flags', NvU32),
  ('status', NvV32),
]
class NVOS62_PARAMETERS(Struct): pass
NVOS62_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('paramSize', NvU32),
  ('status', NvV32),
]
class NVOS65_PARAMETERS(Struct): pass
NVOS65_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('paramSize', NvU32),
  ('versionMagic', NvU32),
  ('maskSize', NvU32),
  ('status', NvV32),
]
class NVOS30_PARAMETERS(Struct): pass
NVOS30_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hChannel', NvHandle),
  ('numChannels', NvV32),
  ('phClients', NvP64),
  ('phDevices', NvP64),
  ('phChannels', NvP64),
  ('flags', NvV32),
  ('timeout', NvV32),
  ('status', NvV32),
]
BindResultFunc = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32)
class NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS(Struct): pass
NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS._fields_ = [
  ('sgt', NvP64),
  ('gem', NvP64),
]
class NVOS32_BLOCKINFO(Struct): pass
NVOS32_BLOCKINFO._fields_ = [
  ('startOffset', NvU64),
  ('size', NvU64),
  ('flags', NvU32),
]
class NVOS32_PARAMETERS(Struct): pass
NvS16 = ctypes.c_int16
class NVOS32_PARAMETERS_data(ctypes.Union): pass
class NVOS32_PARAMETERS_data_AllocSize(Struct): pass
NVOS32_PARAMETERS_data_AllocSize._fields_ = [
  ('owner', NvU32),
  ('hMemory', NvHandle),
  ('type', NvU32),
  ('flags', NvU32),
  ('attr', NvU32),
  ('format', NvU32),
  ('comprCovg', NvU32),
  ('zcullCovg', NvU32),
  ('partitionStride', NvU32),
  ('width', NvU32),
  ('height', NvU32),
  ('size', NvU64),
  ('alignment', NvU64),
  ('offset', NvU64),
  ('limit', NvU64),
  ('address', NvP64),
  ('rangeBegin', NvU64),
  ('rangeEnd', NvU64),
  ('attr2', NvU32),
  ('ctagOffset', NvU32),
  ('numaNode', NvS32),
]
class NVOS32_PARAMETERS_data_AllocTiledPitchHeight(Struct): pass
NVOS32_PARAMETERS_data_AllocTiledPitchHeight._fields_ = [
  ('owner', NvU32),
  ('hMemory', NvHandle),
  ('type', NvU32),
  ('flags', NvU32),
  ('height', NvU32),
  ('pitch', NvS32),
  ('attr', NvU32),
  ('width', NvU32),
  ('format', NvU32),
  ('comprCovg', NvU32),
  ('zcullCovg', NvU32),
  ('partitionStride', NvU32),
  ('size', NvU64),
  ('alignment', NvU64),
  ('offset', NvU64),
  ('limit', NvU64),
  ('address', NvP64),
  ('rangeBegin', NvU64),
  ('rangeEnd', NvU64),
  ('attr2', NvU32),
  ('ctagOffset', NvU32),
  ('numaNode', NvS32),
]
class NVOS32_PARAMETERS_data_Free(Struct): pass
NVOS32_PARAMETERS_data_Free._fields_ = [
  ('owner', NvU32),
  ('hMemory', NvHandle),
  ('flags', NvU32),
]
class NVOS32_PARAMETERS_data_ReleaseCompr(Struct): pass
NVOS32_PARAMETERS_data_ReleaseCompr._fields_ = [
  ('owner', NvU32),
  ('flags', NvU32),
  ('hMemory', NvHandle),
]
class NVOS32_PARAMETERS_data_ReacquireCompr(Struct): pass
NVOS32_PARAMETERS_data_ReacquireCompr._fields_ = [
  ('owner', NvU32),
  ('flags', NvU32),
  ('hMemory', NvHandle),
]
class NVOS32_PARAMETERS_data_Info(Struct): pass
NVOS32_PARAMETERS_data_Info._fields_ = [
  ('attr', NvU32),
  ('offset', NvU64),
  ('size', NvU64),
  ('base', NvU64),
]
class NVOS32_PARAMETERS_data_Dump(Struct): pass
NVOS32_PARAMETERS_data_Dump._fields_ = [
  ('flags', NvU32),
  ('pBuffer', NvP64),
  ('numBlocks', NvU32),
]
class NVOS32_PARAMETERS_data_AllocSizeRange(Struct): pass
NVOS32_PARAMETERS_data_AllocSizeRange._fields_ = [
  ('owner', NvU32),
  ('hMemory', NvHandle),
  ('type', NvU32),
  ('flags', NvU32),
  ('attr', NvU32),
  ('format', NvU32),
  ('comprCovg', NvU32),
  ('zcullCovg', NvU32),
  ('partitionStride', NvU32),
  ('size', NvU64),
  ('alignment', NvU64),
  ('offset', NvU64),
  ('limit', NvU64),
  ('rangeBegin', NvU64),
  ('rangeEnd', NvU64),
  ('address', NvP64),
  ('attr2', NvU32),
  ('ctagOffset', NvU32),
  ('numaNode', NvS32),
]
class NVOS32_PARAMETERS_data_AllocHintAlignment(Struct): pass
NVOS32_PARAMETERS_data_AllocHintAlignment._fields_ = [
  ('alignType', NvU32),
  ('alignAttr', NvU32),
  ('alignInputFlags', NvU32),
  ('alignSize', NvU64),
  ('alignHeight', NvU32),
  ('alignWidth', NvU32),
  ('alignPitch', NvU32),
  ('alignPad', NvU32),
  ('alignMask', NvU32),
  ('alignOutputFlags', (NvU32 * 4)),
  ('alignBank', (NvU32 * 4)),
  ('alignKind', NvU32),
  ('alignAdjust', NvU32),
  ('alignAttr2', NvU32),
]
class NVOS32_PARAMETERS_data_HwAlloc(Struct): pass
class NVOS32_PARAMETERS_data_HwAlloc_comprInfo(Struct): pass
NVOS32_PARAMETERS_data_HwAlloc_comprInfo._fields_ = [
  ('compPageShift', NvU32),
  ('compressedKind', NvU32),
  ('compTagLineMin', NvU32),
  ('compPageIndexLo', NvU32),
  ('compPageIndexHi', NvU32),
  ('compTagLineMultiplier', NvU32),
]
NVOS32_PARAMETERS_data_HwAlloc._fields_ = [
  ('allocOwner', NvU32),
  ('allochMemory', NvHandle),
  ('flags', NvU32),
  ('allocType', NvU32),
  ('allocAttr', NvU32),
  ('allocInputFlags', NvU32),
  ('allocSize', NvU64),
  ('allocHeight', NvU32),
  ('allocWidth', NvU32),
  ('allocPitch', NvU32),
  ('allocMask', NvU32),
  ('allocComprCovg', NvU32),
  ('allocZcullCovg', NvU32),
  ('bindResultFunc', NvP64),
  ('pHandle', NvP64),
  ('hResourceHandle', NvHandle),
  ('retAttr', NvU32),
  ('kind', NvU32),
  ('osDeviceHandle', NvU64),
  ('allocAttr2', NvU32),
  ('retAttr2', NvU32),
  ('allocAddr', NvU64),
  ('comprInfo', NVOS32_PARAMETERS_data_HwAlloc_comprInfo),
  ('uncompressedKind', NvU32),
]
class NVOS32_PARAMETERS_data_HwFree(Struct): pass
NVOS32_PARAMETERS_data_HwFree._fields_ = [
  ('hResourceHandle', NvHandle),
  ('flags', NvU32),
]
class NVOS32_PARAMETERS_data_AllocOsDesc(Struct): pass
NVOS32_PARAMETERS_data_AllocOsDesc._fields_ = [
  ('hMemory', NvHandle),
  ('type', NvU32),
  ('flags', NvU32),
  ('attr', NvU32),
  ('attr2', NvU32),
  ('descriptor', NvP64),
  ('limit', NvU64),
  ('descriptorType', NvU32),
]
NVOS32_PARAMETERS_data._fields_ = [
  ('AllocSize', NVOS32_PARAMETERS_data_AllocSize),
  ('AllocTiledPitchHeight', NVOS32_PARAMETERS_data_AllocTiledPitchHeight),
  ('Free', NVOS32_PARAMETERS_data_Free),
  ('ReleaseCompr', NVOS32_PARAMETERS_data_ReleaseCompr),
  ('ReacquireCompr', NVOS32_PARAMETERS_data_ReacquireCompr),
  ('Info', NVOS32_PARAMETERS_data_Info),
  ('Dump', NVOS32_PARAMETERS_data_Dump),
  ('AllocSizeRange', NVOS32_PARAMETERS_data_AllocSizeRange),
  ('AllocHintAlignment', NVOS32_PARAMETERS_data_AllocHintAlignment),
  ('HwAlloc', NVOS32_PARAMETERS_data_HwAlloc),
  ('HwFree', NVOS32_PARAMETERS_data_HwFree),
  ('AllocOsDesc', NVOS32_PARAMETERS_data_AllocOsDesc),
]
NVOS32_PARAMETERS._fields_ = [
  ('hRoot', NvHandle),
  ('hObjectParent', NvHandle),
  ('function', NvU32),
  ('hVASpace', NvHandle),
  ('ivcHeapNumber', NvS16),
  ('status', NvV32),
  ('total', NvU64),
  ('free', NvU64),
  ('data', NVOS32_PARAMETERS_data),
]
class NVOS32_HEAP_DUMP_BLOCK(Struct): pass
NVOS32_HEAP_DUMP_BLOCK._fields_ = [
  ('owner', NvU32),
  ('format', NvU32),
  ('begin', NvU64),
  ('align', NvU64),
  ('end', NvU64),
]
class NV_CONTEXT_DMA_ALLOCATION_PARAMS(Struct): pass
NV_CONTEXT_DMA_ALLOCATION_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('flags', NvV32),
  ('hMemory', NvHandle),
  ('offset', NvU64),
  ('limit', NvU64),
]
class NV_MEMORY_ALLOCATION_PARAMS(Struct): pass
NV_MEMORY_ALLOCATION_PARAMS._fields_ = [
  ('owner', NvU32),
  ('type', NvU32),
  ('flags', NvU32),
  ('width', NvU32),
  ('height', NvU32),
  ('pitch', NvS32),
  ('attr', NvU32),
  ('attr2', NvU32),
  ('format', NvU32),
  ('comprCovg', NvU32),
  ('zcullCovg', NvU32),
  ('rangeLo', NvU64),
  ('rangeHi', NvU64),
  ('size', NvU64),
  ('alignment', NvU64),
  ('offset', NvU64),
  ('limit', NvU64),
  ('address', NvP64),
  ('ctagOffset', NvU32),
  ('hVASpace', NvHandle),
  ('internalflags', NvU32),
  ('tag', NvU32),
  ('numaNode', NvS32),
]
class NV_OS_DESC_MEMORY_ALLOCATION_PARAMS(Struct): pass
NV_OS_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [
  ('type', NvU32),
  ('flags', NvU32),
  ('attr', NvU32),
  ('attr2', NvU32),
  ('descriptor', NvP64),
  ('limit', NvU64),
  ('descriptorType', NvU32),
  ('tag', NvU32),
]
class NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS(Struct): pass
NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS._fields_ = [
  ('flags', NvU32),
  ('physAddr', NvU64),
  ('size', NvU64),
  ('tag', NvU32),
  ('bGuestAllocated', NvBool),
]
class NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS(Struct): pass
NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS._fields_ = [
  ('owner', NvU32),
  ('flags', NvU32),
  ('type', NvU32),
  ('attr', NvU32),
  ('attr2', NvU32),
  ('height', NvU32),
  ('width', NvU32),
  ('pitch', NvU32),
  ('alignment', NvU32),
  ('comprCovg', NvU32),
  ('zcullCovg', NvU32),
  ('kind', NvU32),
  ('bindResultFunc', NvP64),
  ('pHandle', NvP64),
  ('osDeviceHandle', NvU64),
  ('size', NvU64),
  ('allocAddr', NvU64),
  ('compPageShift', NvU32),
  ('compressedKind', NvU32),
  ('compTagLineMin', NvU32),
  ('compPageIndexLo', NvU32),
  ('compPageIndexHi', NvU32),
  ('compTagLineMultiplier', NvU32),
  ('uncompressedKind', NvU32),
  ('tag', NvU32),
]
class NVOS34_PARAMETERS(Struct): pass
NVOS34_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hMemory', NvHandle),
  ('pLinearAddress', NvP64),
  ('status', NvU32),
  ('flags', NvU32),
]
class NVOS38_PARAMETERS(Struct): pass
NVOS38_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hObject', NvHandle),
  ('AccessType', NvV32),
  ('DevNodeLength', NvV32),
  ('pDevNode', NvP64),
  ('ParmStrLength', NvV32),
  ('pParmStr', NvP64),
  ('BinaryDataLength', NvV32),
  ('pBinaryData', NvP64),
  ('Data', NvV32),
  ('Entry', NvV32),
  ('status', NvV32),
]
class NVOS39_PARAMETERS(Struct): pass
NVOS39_PARAMETERS._fields_ = [
  ('hObjectParent', NvHandle),
  ('hSubDevice', NvHandle),
  ('hObjectNew', NvHandle),
  ('hClass', NvV32),
  ('flags', NvV32),
  ('selector', NvU32),
  ('hMemory', NvHandle),
  ('offset', NvU64),
  ('limit', NvU64),
  ('status', NvV32),
]
class NvUnixEvent(Struct): pass
NvUnixEvent._fields_ = [
  ('hObject', NvHandle),
  ('NotifyIndex', NvV32),
  ('info32', NvV32),
  ('info16', NvU16),
]
class NVOS41_PARAMETERS(Struct): pass
NVOS41_PARAMETERS._fields_ = [
  ('pEvent', NvP64),
  ('MoreEvents', NvV32),
  ('status', NvV32),
]
class NVOS2C_PARAMETERS(Struct): pass
NVOS2C_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('offset', NvU32),
  ('bar', NvU32),
  ('bytes', NvU32),
  ('write', NvU32),
  ('data', NvU32),
  ('status', NvU32),
]
class NVOS46_PARAMETERS(Struct): pass
NVOS46_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hDma', NvHandle),
  ('hMemory', NvHandle),
  ('offset', NvU64),
  ('length', NvU64),
  ('flags', NvV32),
  ('dmaOffset', NvU64),
  ('status', NvV32),
]
class NVOS47_PARAMETERS(Struct): pass
NVOS47_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hDma', NvHandle),
  ('hMemory', NvHandle),
  ('flags', NvV32),
  ('dmaOffset', NvU64),
  ('size', NvU64),
  ('status', NvV32),
]
class NVOS49_PARAMETERS(Struct): pass
NVOS49_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('hCtxDma', NvHandle),
  ('status', NvV32),
]
class NVOS54_PARAMETERS(Struct): pass
NVOS54_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hObject', NvHandle),
  ('cmd', NvV32),
  ('flags', NvU32),
  ('params', NvP64),
  ('paramsSize', NvU32),
  ('status', NvV32),
]
class NVOS63_PARAMETERS(Struct): pass
NVOS63_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hObject', NvHandle),
  ('cmd', NvV32),
  ('paramsSize', NvU32),
  ('status', NvV32),
]
class NVOS55_PARAMETERS(Struct): pass
NVOS55_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hParent', NvHandle),
  ('hObject', NvHandle),
  ('hClientSrc', NvHandle),
  ('hObjectSrc', NvHandle),
  ('flags', NvU32),
  ('status', NvU32),
]
class NVOS56_PARAMETERS(Struct): pass
NVOS56_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hMemory', NvHandle),
  ('pOldCpuAddress', NvP64),
  ('pNewCpuAddress', NvP64),
  ('status', NvV32),
]
class NVOS57_PARAMETERS(Struct): pass
class struct_RS_SHARE_POLICY(Struct): pass
RS_SHARE_POLICY = struct_RS_SHARE_POLICY
class struct_RS_ACCESS_MASK(Struct): pass
RS_ACCESS_MASK = struct_RS_ACCESS_MASK
RsAccessLimb = ctypes.c_uint32
struct_RS_ACCESS_MASK._fields_ = [
  ('limbs', (RsAccessLimb * 1)),
]
struct_RS_SHARE_POLICY._fields_ = [
  ('target', NvU32),
  ('accessMask', RS_ACCESS_MASK),
  ('type', NvU16),
  ('action', NvU8),
]
NVOS57_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hObject', NvHandle),
  ('sharePolicy', RS_SHARE_POLICY),
  ('status', NvU32),
]
class NVPOWERSTATE_PARAMETERS(Struct): pass
NVPOWERSTATE_PARAMETERS._fields_ = [
  ('deviceReference', NvU32),
  ('head', NvU32),
  ('state', NvU32),
  ('forceMonitorState', NvU8),
  ('bForcePerfBiosLevel', NvU8),
  ('bIsD3HotTransition', NvU8),
  ('bForcePowerStateFail', NvU8),
  ('errorStatus', NvU32),
  ('fastBootPowerState', NvU32),
  ('bGC8Transition', NvU8),
  ('bGC8InputRailCutOff', NvU8),
]
PNVPOWERSTATE_PARAMETERS = ctypes.POINTER(NVPOWERSTATE_PARAMETERS)
class NV_GR_ALLOCATION_PARAMETERS(Struct): pass
NV_GR_ALLOCATION_PARAMETERS._fields_ = [
  ('version', NvU32),
  ('flags', NvU32),
  ('size', NvU32),
  ('caps', NvU32),
]
ChannelPBSize = CEnum(ctypes.c_uint32)
PB_SIZE_4KB = ChannelPBSize.define('PB_SIZE_4KB', 0)
PB_SIZE_8KB = ChannelPBSize.define('PB_SIZE_8KB', 1)
PB_SIZE_16KB = ChannelPBSize.define('PB_SIZE_16KB', 2)
PB_SIZE_32KB = ChannelPBSize.define('PB_SIZE_32KB', 3)
PB_SIZE_64KB = ChannelPBSize.define('PB_SIZE_64KB', 4)

class NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS(Struct): pass
NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS._fields_ = [
  ('channelInstance', NvV32),
  ('hObjectBuffer', NvHandle),
  ('hObjectNotify', NvHandle),
  ('offset', NvU32),
  ('pControl', NvP64),
  ('flags', NvU32),
  ('channelPBSize', ChannelPBSize),
  ('subDeviceId', NvU32),
]
class NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS(Struct): pass
NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS._fields_ = [
  ('channelInstance', NvV32),
  ('hObjectNotify', NvHandle),
  ('pControl', NvP64),
]
class NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS(Struct): pass
NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS._fields_ = [
  ('hObjectError', NvHandle),
  ('hObjectEccError', NvHandle),
  ('hVASpace', NvHandle),
  ('engineType', NvU32),
  ('bIsCallingContextVgpuPlugin', NvBool),
]
class NV_SWRUNLIST_ALLOCATION_PARAMS(Struct): pass
NV_SWRUNLIST_ALLOCATION_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('maxTSGs', NvU32),
  ('qosIntrEnableMask', NvU32),
]
class NV_ME_ALLOCATION_PARAMETERS(Struct): pass
NV_ME_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('caps', NvU32),
]
class NV_BSP_ALLOCATION_PARAMETERS(Struct): pass
NV_BSP_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
  ('engineInstance', NvU32),
]
class NV_VP_ALLOCATION_PARAMETERS(Struct): pass
NV_VP_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('caps', NvU32),
  ('flags', NvU32),
  ('altUcode', NvU32),
  ('rawUcode', NvP64),
  ('rawUcodeSize', NvU32),
  ('numSubClasses', NvU32),
  ('numSubSets', NvU32),
  ('subClasses', NvP64),
  ('prohibitMultipleInstances', NvU32),
  ('pControl', NvP64),
  ('hMemoryCmdBuffer', NvHandle),
  ('offset', NvU64),
]
class NV_PPP_ALLOCATION_PARAMETERS(Struct): pass
NV_PPP_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
]
class NV_MSENC_ALLOCATION_PARAMETERS(Struct): pass
NV_MSENC_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
  ('engineInstance', NvU32),
]
class NV_SEC2_ALLOCATION_PARAMETERS(Struct): pass
NV_SEC2_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
]
class NV_NVJPG_ALLOCATION_PARAMETERS(Struct): pass
NV_NVJPG_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
  ('engineInstance', NvU32),
]
class NV_OFA_ALLOCATION_PARAMETERS(Struct): pass
NV_OFA_ALLOCATION_PARAMETERS._fields_ = [
  ('size', NvU32),
  ('prohibitMultipleInstances', NvU32),
  ('engineInstance', NvU32),
]
class NVOS61_PARAMETERS(Struct): pass
OSVBLANKCALLBACKPROC = ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_void_p)
NVOS61_PARAMETERS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hVblank', NvHandle),
  ('pProc', OSVBLANKCALLBACKPROC),
  ('LogicalHead', NvV32),
  ('pParm1', ctypes.c_void_p),
  ('pParm2', ctypes.c_void_p),
  ('bAdd', NvU32),
  ('status', NvV32),
]
class NV_VASPACE_ALLOCATION_PARAMETERS(Struct): pass
NV_VASPACE_ALLOCATION_PARAMETERS._fields_ = [
  ('index', NvU32),
  ('flags', NvV32),
  ('vaSize', NvU64),
  ('vaStartInternal', NvU64),
  ('vaLimitInternal', NvU64),
  ('bigPageSize', NvU32),
  ('vaBase', NvU64),
]
class NV_CTXSHARE_ALLOCATION_PARAMETERS(Struct): pass
NV_CTXSHARE_ALLOCATION_PARAMETERS._fields_ = [
  ('hVASpace', NvHandle),
  ('flags', NvU32),
  ('subctxId', NvU32),
]
class NV_TIMEOUT_CONTROL_PARAMETERS(Struct): pass
NV_TIMEOUT_CONTROL_PARAMETERS._fields_ = [
  ('cmd', NvU32),
  ('timeoutInMs', NvU32),
  ('deviceInstance', NvU32),
]
NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE = CEnum(ctypes.c_uint32)
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT', 0)
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH', 1)
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_NCOH', 2)
NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID = NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE.define('NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_VID', 3)

class NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS(Struct): pass
NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS._fields_ = [
  ('bDirtyTracking', NvBool),
  ('granularity', NvU32),
  ('accessBitMask', (NvU64 * 64)),
  ('noOfEntries', NvU32),
  ('addrSpace', NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS_ADDR_SPACE),
]
class NV_HOPPER_USERMODE_A_PARAMS(Struct): pass
NV_HOPPER_USERMODE_A_PARAMS._fields_ = [
  ('bBar1Mapping', NvBool),
  ('bPriv', NvBool),
]
class struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS(Struct): pass
struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS._fields_ = [
  ('workSubmitToken', NvU32),
]
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
class struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS(Struct): pass
struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS._fields_ = [
  ('bar2Addr', (NvU64 * 2)),
]
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS = struct_NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS
class struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS(Struct): pass
struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS._fields_ = [
  ('index', NvU32),
]
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS = struct_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS = struct_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS._fields_ = [
  ('cpuCapability', NvU8),
  ('gpusCapability', NvU8),
  ('environment', NvU8),
  ('ccFeature', NvU8),
  ('devToolsMode', NvU8),
  ('multiGpuMode', NvU8),
]
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS._fields_ = [
  ('bAcceptClientRequest', NvBool),
]
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS._fields_ = [
  ('bAcceptClientRequest', NvBool),
]
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('protectedMemSizeInKb', NvU64),
  ('unprotectedMemSizeInKb', NvU64),
]
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('protectedMemSizeInKb', NvU64),
  ('unprotectedMemSizeInKb', NvU64),
]
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('numSupportedSec2CCSecureChannels', NvU32),
  ('numSupportedCeCCSecureChannels', NvU32),
]
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('certChain', (NvU8 * 4096)),
  ('certChainSize', NvU32),
  ('attestationCertChain', (NvU8 * 5120)),
  ('attestationCertChainSize', NvU32),
]
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('nonce', (NvU8 * 32)),
  ('attestationReport', (NvU8 * 8192)),
  ('attestationReportSize', NvU32),
  ('isCecAttestationReportPresent', NvBool),
  ('cecAttestationReport', (NvU8 * 4096)),
  ('cecAttestationReportSize', NvU32),
]
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('maxSec2Channels', NvU32),
  ('maxCeChannels', NvU32),
]
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS
class struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS(Struct): pass
struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('keyRotationState', NvU32),
]
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS = struct_NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS
class struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS(Struct): pass
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS._fields_ = [
  ('bEnable', NvBool),
  ('bSkipSubmit', NvBool),
]
class struct_NVA06F_CTRL_BIND_PARAMS(Struct): pass
NVA06C_CTRL_BIND_PARAMS = struct_NVA06F_CTRL_BIND_PARAMS
struct_NVA06F_CTRL_BIND_PARAMS._fields_ = [
  ('engineType', NvU32),
]
class struct_NVA06C_CTRL_TIMESLICE_PARAMS(Struct): pass
struct_NVA06C_CTRL_TIMESLICE_PARAMS._fields_ = [
  ('timesliceUs', NvU64),
]
NVA06C_CTRL_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS
NVA06C_CTRL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS
NVA06C_CTRL_GET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS
class struct_NVA06C_CTRL_PREEMPT_PARAMS(Struct): pass
struct_NVA06C_CTRL_PREEMPT_PARAMS._fields_ = [
  ('bWait', NvBool),
  ('bManualTimeout', NvBool),
  ('timeoutUs', NvU32),
]
NVA06C_CTRL_PREEMPT_PARAMS = struct_NVA06C_CTRL_PREEMPT_PARAMS
class struct_NVA06C_CTRL_GET_INFO_PARAMS(Struct): pass
struct_NVA06C_CTRL_GET_INFO_PARAMS._fields_ = [
  ('tsgID', NvU32),
]
NVA06C_CTRL_GET_INFO_PARAMS = struct_NVA06C_CTRL_GET_INFO_PARAMS
class struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS(Struct): pass
struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS._fields_ = [
  ('tsgInterleaveLevel', NvU32),
]
NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS = struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS
enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = CEnum(ctypes.c_uint32)
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_NONE', 0)
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_64B', 1)
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE.define('NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE_128B', 2)

NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE = enum_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD(Struct): pass
struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD._fields_ = [
  ('size', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_SIZE),
]
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD
class struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS(Struct): pass
struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS._fields_ = [
  ('l1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD),
  ('t1', NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_FIELD),
]
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS = struct_NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS
class struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS(Struct): pass
class struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO(Struct): pass
NV2080_CTRL_INTERNAL_MEMDESC_INFO = struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO
struct_NV2080_CTRL_INTERNAL_MEMDESC_INFO._fields_ = [
  ('base', NvU64),
  ('size', NvU64),
  ('alignment', NvU64),
  ('addressSpace', NvU32),
  ('cpuCacheAttrib', NvU32),
]
struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS._fields_ = [
  ('methodBufferMemdesc', (NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2)),
  ('bar2Addr', (NvU64 * 2)),
  ('numValidEntries', NvU32),
]
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS = struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS
class struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS(Struct): pass
struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS._fields_ = [
  ('bRealtime', NvBool),
]
NVA06C_CTRL_MAKE_REALTIME_PARAMS = struct_NVA06C_CTRL_MAKE_REALTIME_PARAMS
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS = struct_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS = struct_NVA06C_CTRL_TIMESLICE_PARAMS
class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('pFmt', NvP64),
]
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS
class struct_NV_CTRL_VASPACE_PAGE_LEVEL(Struct): pass
class struct_MMU_FMT_LEVEL(Struct): pass
struct_MMU_FMT_LEVEL._fields_ = [
  ('virtAddrBitLo', NvU8),
  ('virtAddrBitHi', NvU8),
  ('entrySize', NvU8),
  ('bPageTable', NvBool),
  ('numSubLevels', NvU8),
  ('pageLevelIdTag', NvU32),
  ('subLevels', ctypes.POINTER(struct_MMU_FMT_LEVEL)),
]
MMU_FMT_LEVEL = struct_MMU_FMT_LEVEL
struct_NV_CTRL_VASPACE_PAGE_LEVEL._fields_ = [
  ('pFmt', ctypes.POINTER(struct_MMU_FMT_LEVEL)),
  ('levelFmt', MMU_FMT_LEVEL),
  ('sublevelFmt', (MMU_FMT_LEVEL * 2)),
  ('physAddress', NvU64),
  ('aperture', NvU32),
  ('size', NvU64),
  ('entryIndex', NvU32),
]
NV_CTRL_VASPACE_PAGE_LEVEL = struct_NV_CTRL_VASPACE_PAGE_LEVEL
class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('virtAddress', NvU64),
  ('pageSize', NvU64),
  ('flags', NvU64),
  ('numLevels', NvU32),
  ('levels', (NV_CTRL_VASPACE_PAGE_LEVEL * 6)),
]
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('pageSize', NvU64),
  ('virtAddrLo', NvU64),
  ('virtAddrHi', NvU64),
]
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS
class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('pageSize', NvU64),
  ('virtAddrLo', NvU64),
  ('virtAddrHi', NvU64),
]
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Struct): pass
class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level(Struct): pass
struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level._fields_ = [
  ('physAddress', NvU64),
  ('size', NvU64),
  ('aperture', NvU32),
  ('pageShift', NvU8),
]
struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('pageSize', NvU64),
  ('virtAddrLo', NvU64),
  ('virtAddrHi', NvU64),
  ('numLevelsToCopy', NvU32),
  ('levels', (struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_level * 6)),
]
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS
class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('requiredVaRange', NvU64),
]
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS
class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(Struct): pass
struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._fields_ = [
  ('hSubDevice', NvHandle),
  ('subDeviceId', NvU32),
  ('bytesFree', NvU64),
  ('bytesTotal', NvU64),
  ('largestFreeOffset', NvU64),
  ('largestFreeSize', NvU64),
  ('usableBytesFree', NvU64),
  ('numFreeBlocks', NvU32),
]
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS
class struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS._fields_ = [
  ('hObject', NvHandle),
  ('mapFlags', NvU32),
  ('addrSpaceType', NvU32),
]
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS(Struct): pass
class struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data(ctypes.Union): pass
struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data._fields_ = [
  ('hResult', NvHandle),
  ('iResult', NvU64),
]
struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS._fields_ = [
  ('hObject', NvHandle),
  ('index', NvU32),
  ('data', struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_data),
]
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS = struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS
class struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS._fields_ = [
  ('hObject', NvHandle),
  ('hClient', NvHandle),
  ('maskResult', RS_ACCESS_MASK),
]
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS = struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS
class struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS._fields_ = [
  ('sharePolicy', RS_SHARE_POLICY),
]
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS = struct_NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS
class struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS(Struct): pass
struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS._fields_ = [
  ('hParent', NvHandle),
  ('classId', NvU32),
  ('hObject', NvHandle),
]
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS = struct_NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS
class struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS._fields_ = [
  ('hObject', NvHandle),
  ('sharePolicy', RS_SHARE_POLICY),
]
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS = struct_NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS
class struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS._fields_ = [
  ('hObject1', NvHandle),
  ('hObject2', NvHandle),
  ('bDuplicates', NvBool),
]
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS = struct_NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS
class struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS(Struct): pass
struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS._fields_ = [
  ('devDescriptor', NvU64),
  ('channel', NvU32),
]
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS = struct_NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS._fields_ = [
  ('state', NvU32),
  ('count', NvU32),
  ('missedCount', NvU32),
  ('bCircularBuffer', NvBool),
]
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS
class struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS._fields_ = [
  ('state', NvU32),
  ('bCircularBuffer', NvBool),
]
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS = struct_NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS
class struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY(Struct): pass
struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY._fields_ = [
  ('counter', NvU64),
  ('line', NvU32),
  ('filename', (NvU8 * 12)),
  ('tag', NvU16),
  ('cpuNum', NvU8),
  ('irql', NvU8),
  ('threadId', NvU64),
  ('data0', NvU32),
  ('data1', NvU32),
  ('data2', NvU32),
]
NV0000_CTRL_DIAG_LOCK_METER_ENTRY = struct_NV0000_CTRL_DIAG_LOCK_METER_ENTRY
class struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS(Struct): pass
struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS._fields_ = [
  ('entryCount', NvU32),
  ('entries', (NV0000_CTRL_DIAG_LOCK_METER_ENTRY * 64)),
]
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS = struct_NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS
class struct_RPC_METER_ENTRY(Struct): pass
struct_RPC_METER_ENTRY._fields_ = [
  ('startTimeInNs', NvU64),
  ('endTimeInNs', NvU64),
  ('rpcDataTag', NvU64),
  ('rpcExtraData', NvU64),
]
RPC_METER_ENTRY = struct_RPC_METER_ENTRY
class struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS(Struct): pass
struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS._fields_ = [
  ('rpcProfileCmd', NvU32),
]
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS = struct_NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS
class struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS(Struct): pass
struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS._fields_ = [
  ('firstEntryOffset', NvU32),
  ('outputEntryCount', NvU32),
  ('remainingEntryCount', NvU32),
  ('elapsedTimeInNs', NvU64),
  ('rpcProfilerBuffer', (RPC_METER_ENTRY * 100)),
]
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS = struct_NV0000_CTRL_DIAG_DUMP_RPC_PARAMS
class struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Struct): pass
struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [
  ('event', NvU32),
  ('action', NvU32),
]
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS
class struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS._fields_ = [
  ('event', NvU32),
  ('status', NvU32),
]
NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS = struct_NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS
class struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
]
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS
class struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('gpuFlags', NvU32),
  ('deviceInstance', NvU32),
  ('subDeviceInstance', NvU32),
  ('szName', NvP64),
  ('sliStatus', NvU32),
  ('boardId', NvU32),
  ('gpuInstance', NvU32),
  ('numaId', NvS32),
]
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_PARAMS
class struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('gpuFlags', NvU32),
  ('deviceInstance', NvU32),
  ('subDeviceInstance', NvU32),
  ('sliStatus', NvU32),
  ('boardId', NvU32),
  ('gpuInstance', NvU32),
  ('numaId', NvS32),
]
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS = struct_NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS
class struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('status', NvU32),
]
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS = struct_NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS
class struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS._fields_ = [
  ('deviceIds', NvU32),
]
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS
class struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
  ('excludedGpuIds', (NvU32 * 32)),
]
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS
class struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('domain', NvU32),
  ('bus', NvU16),
  ('slot', NvU16),
]
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS
class struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
  ('failedId', NvU32),
]
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_ATTACH_IDS_PARAMS
class struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
]
NV0000_CTRL_GPU_DETACH_IDS_PARAMS = struct_NV0000_CTRL_GPU_DETACH_IDS_PARAMS
class struct_NV0000_CTRL_GPU_VIDEO_LINKS(Struct): pass
struct_NV0000_CTRL_GPU_VIDEO_LINKS._fields_ = [
  ('gpuId', NvU32),
  ('connectedGpuIds', (NvU32 * 8)),
]
NV0000_CTRL_GPU_VIDEO_LINKS = struct_NV0000_CTRL_GPU_VIDEO_LINKS
class struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS._fields_ = [
  ('links', (NV0000_CTRL_GPU_VIDEO_LINKS * 32)),
]
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS = struct_NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS
class struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('svmSize', NvU32),
]
NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS = struct_NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS
class struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS._fields_ = [
  ('gpuUuid', (NvU8 * 256)),
  ('flags', NvU32),
  ('gpuId', NvU32),
  ('deviceInstance', NvU32),
  ('subdeviceInstance', NvU32),
]
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS
class struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('flags', NvU32),
  ('gpuUuid', (NvU8 * 256)),
  ('uuidStrLen', NvU32),
]
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS = struct_NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS
class struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('newState', NvU32),
  ('flags', NvU32),
]
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS
class struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('drainState', NvU32),
  ('flags', NvU32),
]
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS = struct_NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS
class struct_NV0000_CTRL_GPU_DISCOVER_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_DISCOVER_PARAMS._fields_ = [
  ('domain', NvU32),
  ('bus', NvU8),
  ('slot', NvU8),
  ('function', NvU8),
]
NV0000_CTRL_GPU_DISCOVER_PARAMS = struct_NV0000_CTRL_GPU_DISCOVER_PARAMS
class struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS._fields_ = [
  ('enableMask', NvU32),
]
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS = struct_NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS
class struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('mask', NvU32),
  ('bSkipHwNvlinkDisable', NvBool),
]
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS = struct_NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS(Struct): pass
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data(ctypes.Union): pass
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet(Struct): pass
struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet._fields_ = [
  ('newValue', NvU32),
  ('oldValue', NvU32),
]
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx(Struct): pass
struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx._fields_ = [
  ('paramData', (NvU8 * 373)),
  ('paramSize', NvU32),
]
class struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty(Struct): pass
struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty._fields_ = [
  ('propertyId', NvU32),
  ('propertyIn', (NvU32 * 6)),
  ('propertyOut', (NvU32 * 5)),
]
struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data._fields_ = [
  ('configSet', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configSet),
  ('configEx', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_configEx),
  ('reservedProperty', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data_reservedProperty),
]
struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS._fields_ = [
  ('hContext', NvHandle),
  ('opType', NvU32),
  ('index', NvV32),
  ('dataType', NvU32),
  ('data', struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_data),
]
NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS = struct_NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS
class struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS._fields_ = [
  ('hDevice', NvHandle),
  ('hChannel', NvHandle),
  ('numChannels', NvV32),
  ('phClients', NvP64),
  ('phDevices', NvP64),
  ('phChannels', NvP64),
  ('flags', NvV32),
  ('timeout', NvV32),
]
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS = struct_NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS
class struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS._fields_ = [
  ('image', NvU8),
  ('totalSize', NvU64),
  ('pData', NvP64),
]
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS = struct_NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS
class struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS._fields_ = [
  ('mode', NvU8),
]
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS
class struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS._fields_ = [
  ('mode', NvU8),
  ('bwModeScope', NvU8),
]
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS = struct_NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS
class struct_NV0000_CTRL_GPU_ACTIVE_DEVICE(Struct): pass
struct_NV0000_CTRL_GPU_ACTIVE_DEVICE._fields_ = [
  ('gpuId', NvU32),
  ('gpuInstanceId', NvU32),
  ('computeInstanceId', NvU32),
]
NV0000_CTRL_GPU_ACTIVE_DEVICE = struct_NV0000_CTRL_GPU_ACTIVE_DEVICE
class struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS._fields_ = [
  ('numDevices', NvU32),
  ('devices', (NV0000_CTRL_GPU_ACTIVE_DEVICE * 256)),
]
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS = struct_NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS
class struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS._fields_ = [
  ('gpuId', NvU32),
]
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS
class struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS._fields_ = [
  ('gpuId', NvU32),
]
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS = struct_NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS
class struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('pid', NvU32),
  ('newState', NvU32),
]
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('pid', NvU32),
  ('state', NvU32),
]
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS
class struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('pid', NvU32),
  ('subPid', NvU32),
  ('gpuUtil', NvU32),
  ('fbUtil', NvU32),
  ('maxFbUsage', NvU64),
  ('startTime', NvU64),
  ('endTime', NvU64),
]
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS
class struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('pid', NvU32),
  ('pidTbl', (NvU32 * 4000)),
  ('pidCount', NvU32),
]
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS = struct_NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS
class struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS(Struct): pass
struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('pid', NvU32),
]
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS = struct_NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS
class struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS(Struct): pass
struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS._fields_ = [
  ('gsyncIds', (NvU32 * 4)),
]
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS
class struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS._fields_ = [
  ('gsyncId', NvU32),
  ('gsyncFlags', NvU32),
  ('gsyncInstance', NvU32),
]
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS = struct_NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS
class struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [
  ('component', NvU32),
  ('size', NvU32),
]
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS
class struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [
  ('pBuffer', NvP64),
  ('component', NvU32),
  ('size', NvU32),
]
NV0000_CTRL_NVD_GET_DUMP_PARAMS = struct_NV0000_CTRL_NVD_GET_DUMP_PARAMS
class struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS._fields_ = [
  ('timestamp', NvU64),
  ('cpuClkId', NvU8),
]
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS = struct_NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS
class struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS._fields_ = [
  ('component', NvU32),
  ('version', NvU32),
  ('runtimeSizes', (NvU8 * 16)),
  ('printFlags', NvU32),
  ('signature', (NvU32 * 4)),
  ('bufferTags', (NvU32 * 3840)),
]
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS
class struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS._fields_ = [
  ('component', NvU32),
  ('buffer', NvU32),
  ('tag', NvU32),
  ('size', NvU32),
  ('flags', NvU32),
  ('pos', NvU32),
  ('overflow', NvU32),
]
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS
class struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS._fields_ = [
  ('component', NvU32),
  ('buffer', NvU32),
  ('blockNum', NvU32),
  ('size', NvU32),
  ('data', (NvU8 * 4000)),
]
NV0000_CTRL_NVD_GET_NVLOG_PARAMS = struct_NV0000_CTRL_NVD_GET_NVLOG_PARAMS
class struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY(Struct): pass
struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY._fields_ = [
  ('tag', NvU32),
  ('value', NvU32),
  ('attribute', NvU32),
]
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY = struct_NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY
class struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS(Struct): pass
struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS._fields_ = [
  ('reqIdx', NvU16),
  ('rptIdx', NvU16),
  ('GPUTag', NvU32),
  ('rptTime', NvU32),
  ('startIdx', NvU16),
  ('endIdx', NvU16),
  ('rptType', NvU16),
  ('flags', NvU32),
  ('rptCount', NvU16),
  ('owner', NvU32),
  ('processId', NvU32),
  ('report', (NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_ENTRY * 200)),
]
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS = struct_NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS
class struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS(Struct): pass
struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS._fields_ = [
  ('tsBufferSize', NvU32),
  ('pTSBuffer', NvP64),
]
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS = struct_NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS
class struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS(Struct): pass
struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS._fields_ = [
  ('subProcessID', NvU32),
  ('subProcessName', (ctypes.c_char * 100)),
]
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS = struct_NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS
class struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS(Struct): pass
struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS._fields_ = [
  ('bIsSubProcessDisabled', NvBool),
]
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS = struct_NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS
class struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS(Struct): pass
struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS._fields_ = [
  ('bEnabled', NvBool),
]
NV0000_SYNC_GPU_BOOST_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_INFO_PARAMS
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG(Struct): pass
struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG._fields_ = [
  ('gpuCount', NvU32),
  ('gpuIds', (NvU32 * 32)),
  ('boostGroupId', NvU32),
  ('bBridgeless', NvBool),
]
NV0000_SYNC_GPU_BOOST_GROUP_CONFIG = struct_NV0000_SYNC_GPU_BOOST_GROUP_CONFIG
class struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS(Struct): pass
struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS._fields_ = [
  ('boostConfig', NV0000_SYNC_GPU_BOOST_GROUP_CONFIG),
]
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS
class struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS(Struct): pass
struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS._fields_ = [
  ('boostGroupId', NvU32),
]
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS
class struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS(Struct): pass
struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS._fields_ = [
  ('groupCount', NvU32),
  ('pBoostGroups', (NV0000_SYNC_GPU_BOOST_GROUP_CONFIG * 16)),
]
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS = struct_NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS._fields_ = [
  ('featuresMask', NvU32),
]
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS._fields_ = [
  ('sizeOfStrings', NvU32),
  ('pDriverVersionBuffer', NvP64),
  ('pVersionBuffer', NvP64),
  ('pTitleBuffer', NvP64),
  ('changelistNumber', NvU32),
  ('officialChangelistNumber', NvU32),
]
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS
enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE = CEnum(ctypes.c_uint32)
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NA', 0)
NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE.define('NV0000_CTRL_SYSTEM_SH_SOC_TYPE_NV_GRACE', 1)

NV0000_CTRL_SYSTEM_SH_SOC_TYPE = enum_NV0000_CTRL_SYSTEM_SH_SOC_TYPE
class struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS._fields_ = [
  ('type', NvU32),
  ('capabilities', NvU32),
  ('clock', NvU32),
  ('L1DataCacheSize', NvU32),
  ('L2DataCacheSize', NvU32),
  ('dataCacheLineSize', NvU32),
  ('numLogicalCpus', NvU32),
  ('numPhysicalCpus', NvU32),
  ('name', (NvU8 * 52)),
  ('family', NvU32),
  ('model', NvU32),
  ('stepping', NvU8),
  ('coresOnDie', NvU32),
  ('bCCEnabled', NvBool),
  ('selfHostedSocType', NV0000_CTRL_SYSTEM_SH_SOC_TYPE),
]
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS._fields_ = [
  ('vendorId', NvU16),
  ('deviceId', NvU16),
  ('subSysVendorId', NvU16),
  ('subSysDeviceId', NvU16),
  ('HBvendorId', NvU16),
  ('HBdeviceId', NvU16),
  ('HBsubSysVendorId', NvU16),
  ('HBsubSysDeviceId', NvU16),
  ('sliBondId', NvU32),
  ('vendorNameString', (NvU8 * 32)),
  ('subSysVendorNameString', (NvU8 * 32)),
  ('chipsetNameString', (NvU8 * 32)),
  ('sliBondNameString', (NvU8 * 32)),
  ('flags', NvU32),
]
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS._fields_ = [
  ('bIsPresent', NvBool),
]
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS._fields_ = [
  ('waitApiLock', NvU64),
  ('holdRoApiLock', NvU64),
  ('holdRwApiLock', NvU64),
  ('waitGpuLock', NvU64),
  ('holdGpuLock', NvU64),
]
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS._fields_ = [
  ('numClasses', NvU32),
  ('classes', (NvU32 * 32)),
]
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS
class struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS._fields_ = [
  ('eventType', NvU32),
  ('eventData', NvU32),
  ('bEventDataForced', NvBool),
]
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS = struct_NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS
class struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS(Struct): pass
struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS._fields_ = [
  ('systemType', NvU32),
]
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS
class struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('count', NvU32),
  ('data', (NvU8 * 512)),
]
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS
class struct_NV0000_CTRL_SYSTEM_HWBC_INFO(Struct): pass
struct_NV0000_CTRL_SYSTEM_HWBC_INFO._fields_ = [
  ('hwbcId', NvU32),
  ('firmwareVersion', NvU32),
  ('subordinateBus', NvU32),
  ('secondaryBus', NvU32),
]
NV0000_CTRL_SYSTEM_HWBC_INFO = struct_NV0000_CTRL_SYSTEM_HWBC_INFO
class struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS._fields_ = [
  ('hwbcInfo', (NV0000_CTRL_SYSTEM_HWBC_INFO * 128)),
]
NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS._fields_ = [
  ('command', NvU16),
  ('locale', NvU16),
  ('data', NvU32),
]
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS(Struct): pass
class struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData._fields_ = [
  ('command', NvU16),
  ('locale', NvU16),
  ('data', NvU32),
]
struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS._fields_ = [
  ('cmdCount', NvU32),
  ('succeeded', NvU32),
  ('cmdData', (struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_cmdData * 16)),
]
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
  ('gpuCount', NvU32),
  ('p2pCaps', NvU32),
  ('p2pOptimalReadCEs', NvU32),
  ('p2pOptimalWriteCEs', NvU32),
  ('p2pCapsStatus', (NvU8 * 9)),
  ('busPeerIds', NvP64),
  ('busEgmPeerIds', NvP64),
]
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS._fields_ = [
  ('gpuIds', (NvU32 * 32)),
  ('gpuCount', NvU32),
  ('p2pCaps', NvU32),
  ('p2pOptimalReadCEs', NvU32),
  ('p2pOptimalWriteCEs', NvU32),
  ('p2pCapsStatus', (NvU8 * 9)),
  ('busPeerIds', (NvU32 * 1024)),
  ('busEgmPeerIds', (NvU32 * 1024)),
]
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS
NV0000_CTRL_P2P_CAPS_MATRIX_ROW = (ctypes.c_uint32 * 8)
class struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS._fields_ = [
  ('grpACount', NvU32),
  ('grpBCount', NvU32),
  ('gpuIdGrpA', (NvU32 * 8)),
  ('gpuIdGrpB', (NvU32 * 8)),
  ('p2pCaps', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)),
  ('a2bOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)),
  ('a2bOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)),
  ('b2aOptimalReadCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)),
  ('b2aOptimalWriteCes', (NV0000_CTRL_P2P_CAPS_MATRIX_ROW * 8)),
]
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('input', (NvS32 * 2)),
  ('result', (NvS32 * 4)),
]
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [
  ('objHndl', NvU32),
  ('blockId', NvU32),
  ('nextExpectedSampleTimems', NvU32),
  ('countersReq', NvU32),
  ('countersReturned', NvU32),
  ('counterBlock', (NvU32 * 32)),
]
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('input', NvU32),
  ('resultSz', NvU32),
  ('result', (NvU32 * 288)),
]
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS
class struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS._fields_ = [
  ('method', NvU32),
  ('inData', NvP64),
  ('inDataSize', NvU16),
  ('outStatus', NvU32),
  ('outData', NvP64),
  ('outDataSize', NvU16),
]
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS = struct_NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS
class struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS._fields_ = [
  ('moduleMask', NvU32),
]
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS = struct_NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE._fields_ = [
  ('frameTime', NvU16),
  ('renderTime', NvU16),
  ('targetTime', NvU16),
  ('sleepTime', NvU8),
  ('sampleNumber', NvU8),
]
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE
class struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS._fields_ = [
  ('samples', (NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE * 64)),
  ('nextSampleNumber', NvU8),
]
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS
class struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS._fields_ = [
  ('sampleData', NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE),
]
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS._fields_ = [
  ('szHostDriverVersionBuffer', (ctypes.c_char * 256)),
  ('szHostVersionBuffer', (ctypes.c_char * 256)),
  ('szHostTitleBuffer', (ctypes.c_char * 256)),
  ('szPluginTitleBuffer', (ctypes.c_char * 256)),
  ('szHostUnameBuffer', (ctypes.c_char * 256)),
  ('iHostChangelistNumber', NvU32),
  ('iPluginChangelistNumber', NvU32),
]
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS._fields_ = [
  ('gpuCount', NvU8),
  ('gpuBus', (NvU8 * 32)),
  ('gpuExternalPowerStatus', (NvU8 * 32)),
]
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS._fields_ = [
  ('privStatusFlags', NvU8),
]
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS
enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = CEnum(ctypes.c_uint32)
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP', 1)
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED', 2)
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS', 3)
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS.define('NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED', 4)

NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS = enum_NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS
class struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS._fields_ = [
  ('fabricStatus', NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS),
]
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS
class struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS._fields_ = [
  ('host_min_supported_version', NvU32),
  ('host_max_supported_version', NvU32),
  ('user_min_supported_version', NvU32),
  ('user_max_supported_version', NvU32),
]
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS
class struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS._fields_ = [
  ('min_version', NvU32),
  ('max_version', NvU32),
]
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS = struct_NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS._fields_ = [
  ('rm_instance_id', NvU64),
]
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS
class struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT(Struct): pass
struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT._fields_ = [
  ('batteryStateOfChargePercent', NvU8),
  ('batteryCurrentLimitmA', NvU32),
  ('restOfSytemReservedPowermW', NvU32),
  ('minCpuTdpmW', NvU32),
  ('maxCpuTdpmW', NvU32),
  ('shortTimescaleBatteryCurrentLimitmA', NvU32),
]
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT = struct_NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT
class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS(Struct): pass
class struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam(ctypes.Union): pass
struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam._fields_ = [
  ('weight', NvU8),
  ('windowSize', NvU8),
]
struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('tpp', NvU32),
  ('ratedTgp', NvU32),
  ('subFunc', NvU32),
  ('ctgpOffsetmW', NvS32),
  ('targetTppOffsetmW', NvS32),
  ('maxOutputOffsetmW', NvS32),
  ('minOutputOffsetmW', NvS32),
  ('ctgpBattOffsetmW', NvS32),
  ('targetTppBattOffsetmW', NvS32),
  ('dcRosReserveOverridemW', NvU32),
  ('dcTspLongTimescaleLimitmA', NvU32),
  ('dcTspShortTimescaleLimitmA', NvU32),
  ('bRequireDcSysPowerLimitsTable', NvBool),
  ('bAllowDcRestOfSystemReserveOverride', NvBool),
  ('bSupportDcTsp', NvBool),
  ('bEnableForAC', NvBool),
  ('bEnableForDC', NvBool),
  ('version', NvU8),
  ('samplingPeriodmS', NvU16),
  ('samplingMulti', NvU16),
  ('filterType', NvU8),
  ('filterParam', struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_filterParam),
  ('filterReserved', NvU16),
  ('bIsBoostController', NvBool),
  ('incRatio', NvU16),
  ('decRatio', NvU16),
  ('bSupportBatt', NvBool),
  ('cpuType', NvU8),
  ('gpuType', NvU8),
  ('sysPwrIndex', NvU32),
  ('sysPwrGetInfo', (NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT * 32)),
  ('bIsTspSupported', NvBool),
  ('sysPwrLimitsTableVersion', NvU8),
  ('type', NvU32),
  ('cpuTdpmw', NvU32),
]
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS
NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS
class struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS(Struct): pass
struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS._fields_ = [
  ('bExternalFabricMgmt', NvBool),
]
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS = struct_NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS._fields_ = [
  ('clientCount', NvU32),
  ('resourceCount', NvU64),
]
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS
class struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS._fields_ = [
  ('driverVersionBuffer', (ctypes.c_char * 256)),
  ('versionBuffer', (ctypes.c_char * 256)),
  ('driverBranch', (ctypes.c_char * 256)),
  ('titleBuffer', (ctypes.c_char * 256)),
  ('changelistNumber', NvU32),
  ('officialChangelistNumber', NvU32),
]
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS = struct_NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS
class struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('mode', NvU32),
]
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS._fields_ = [
  ('command', NvU16),
  ('locale', NvU16),
  ('data', NvU32),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS(Struct): pass
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData._fields_ = [
  ('command', NvU16),
  ('locale', NvU16),
  ('data', NvU32),
]
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS._fields_ = [
  ('cmdCount', NvU32),
  ('succeeded', NvU32),
  ('cmdData', (struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_cmdData * 16)),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('input', (NvS32 * 2)),
  ('result', (NvS32 * 4)),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS._fields_ = [
  ('objHndl', NvU32),
  ('blockId', NvU32),
  ('nextExpectedSampleTimems', NvU32),
  ('countersReq', NvU32),
  ('countersReturned', NvU32),
  ('counterBlock', (NvU32 * 32)),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('input', NvU32),
  ('resultSz', NvU32),
  ('result', (NvU32 * 288)),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE._fields_ = [
  ('frameTime', NvU16),
  ('renderTime', NvU16),
  ('targetTime', NvU16),
  ('sleepTime', NvU8),
  ('sampleNumber', NvU8),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS._fields_ = [
  ('samples', (NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE * 64)),
  ('nextSampleNumber', NvU8),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS
class struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS(Struct): pass
struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS._fields_ = [
  ('sampleData', NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE),
]
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS = struct_NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS
class struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS._fields_ = [
  ('offset', NvU64),
  ('length', NvU64),
  ('cacheOps', NvU32),
  ('hDevice', NvHandle),
  ('hObject', NvHandle),
  ('internalOnly', NvU64),
]
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS = struct_NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS
class struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS._fields_ = [
  ('fd', NvS32),
]
NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS
enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = CEnum(ctypes.c_uint32)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE', 0)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE.define('NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM', 1)

NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE = enum_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT(Struct): pass
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data(ctypes.Union): pass
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject(Struct): pass
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject._fields_ = [
  ('hDevice', NvHandle),
  ('hParent', NvHandle),
  ('hObject', NvHandle),
]
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data._fields_ = [
  ('rmObject', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data_rmObject),
]
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT._fields_ = [
  ('type', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE),
  ('data', struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_data),
]
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS._fields_ = [
  ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT),
  ('fd', NvS32),
  ('flags', NvU32),
]
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS._fields_ = [
  ('fd', NvS32),
  ('object', NV0000_CTRL_OS_UNIX_EXPORT_OBJECT),
]
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS
class struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('minorNum', NvU32),
]
NV0000_CTRL_OS_GET_GPU_INFO_PARAMS = struct_NV0000_CTRL_OS_GET_GPU_INFO_PARAMS
class struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS._fields_ = [
  ('fd', NvS32),
  ('deviceInstance', NvU32),
  ('gpuInstanceId', NvU32),
  ('maxObjects', NvU16),
  ('metadata', (NvU8 * 64)),
]
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS = struct_NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS
class struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS._fields_ = [
  ('hDevice', NvHandle),
  ('maxObjects', NvU16),
  ('metadata', (NvU8 * 64)),
  ('fd', NvS32),
]
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS
class struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS._fields_ = [
  ('fd', NvS32),
  ('hDevice', NvHandle),
  ('maxObjects', NvU16),
  ('metadata', (NvU8 * 64)),
  ('objects', (NvHandle * 512)),
  ('numObjects', NvU16),
  ('index', NvU16),
]
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS
class struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS(Struct): pass
struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS._fields_ = [
  ('fd', NvS32),
  ('hParent', NvHandle),
  ('objects', (NvHandle * 128)),
  ('objectTypes', (NvU8 * 128)),
  ('numObjects', NvU16),
  ('index', NvU16),
]
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS = struct_NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS
class struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS._fields_ = [
  ('vgpuName', (NvU8 * 16)),
  ('gpuPciId', NvU32),
  ('gpuPciBdf', NvU32),
  ('vgpuTypeId', NvU32),
  ('vgpuId', NvU16),
  ('gpuInstanceId', NvU32),
  ('placementId', NvU32),
]
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS
class struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS._fields_ = [
  ('gpuPciId', NvU32),
  ('gpuPciBdf', NvU32),
  ('numVgpuTypes', NvU32),
  ('vgpuTypeIds', (NvU32 * 64)),
  ('availableInstances', (NvU32 * 64)),
]
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS = struct_NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS
class struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS._fields_ = [
  ('vgpuName', (NvU8 * 16)),
  ('vgpuId', NvU16),
]
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS = struct_NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS
class struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS(Struct): pass
struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS._fields_ = [
  ('returnStatus', NvU32),
  ('gpuId', NvU32),
]
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS = struct_NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS
class struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS(Struct): pass
struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS._fields_ = [
  ('vgpuName', (NvU8 * 16)),
  ('mode', NvU32),
  ('sysfs_val', NvU32),
]
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS = struct_NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS
class struct_NV0080_CTRL_BIF_RESET_PARAMS(Struct): pass
struct_NV0080_CTRL_BIF_RESET_PARAMS._fields_ = [
  ('flags', NvU32),
]
NV0080_CTRL_BIF_RESET_PARAMS = struct_NV0080_CTRL_BIF_RESET_PARAMS
class struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS(Struct): pass
struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS._fields_ = [
  ('aspmFeatureSupported', NvU32),
]
NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS = struct_NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS
class struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS(Struct): pass
struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS._fields_ = [
  ('bL0sEnable', NvBool),
  ('bL1Enable', NvBool),
]
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS = struct_NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS
class struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS(Struct): pass
struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS._fields_ = [
  ('pciePowerControlMask', NvU32),
  ('pciePowerControlIdentifiedKeyOrder', NvU32),
  ('pciePowerControlIdentifiedKeyLocation', NvU32),
]
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS = struct_NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS
class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
  ('instanceId', NvU32),
]
NV0080_CTRL_BSP_GET_CAPS_PARAMS = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS
class struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2(Struct): pass
struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2._fields_ = [
  ('capsTbl', (NvU8 * 8)),
  ('instanceId', NvU32),
]
NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 = struct_NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2
class struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK(Struct): pass
struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK._fields_ = [
  ('pageSize', NvU64),
  ('pteEntrySize', NvU64),
  ('comptagLine', NvU32),
  ('kind', NvU32),
  ('pteFlags', NvU32),
]
NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK
class struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS._fields_ = [
  ('gpuAddr', NvU64),
  ('subDeviceId', NvU32),
  ('skipVASpaceInit', NvU8),
  ('pteBlocks', (NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5)),
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS
class struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS._fields_ = [
  ('gpuAddr', NvU64),
  ('subDeviceId', NvU32),
  ('pteBlocks', (NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK * 5)),
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS = struct_NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS(Struct): pass
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource(Struct): pass
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('hMemory', NvHandle),
  ('subDeviceId', NvU32),
]
class struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo(Struct): pass
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo._fields_ = [
  ('fbKind', NvU32),
  ('sysKind', NvU32),
  ('compTagStartOffset', NvU32),
]
struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS._fields_ = [
  ('pageCount', NvU32),
  ('hwResource', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_hwResource),
  ('comprInfo', struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_comprInfo),
  ('offset', NvU64),
  ('gpuAddr', NvU64),
  ('pageArray', NvP64),
  ('pteMem', NvP64),
  ('pteMemPfn', NvU32),
  ('pageSize', NvU32),
  ('startPageIndex', NvU32),
  ('flags', NvU32),
  ('hSrcVASpace', NvHandle),
  ('hTgtVASpace', NvHandle),
  ('peerId', NvU32),
]
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS = struct_NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS
class struct_NV0080_CTRL_DMA_FLUSH_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_FLUSH_PARAMS._fields_ = [
  ('targetUnit', NvU32),
]
NV0080_CTRL_DMA_FLUSH_PARAMS = struct_NV0080_CTRL_DMA_FLUSH_PARAMS
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT(Struct): pass
struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT._fields_ = [
  ('pageTableSize', NvU32),
  ('pageTableCoverage', NvU32),
]
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT
class struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS._fields_ = [
  ('vaBitCount', NvU32),
  ('pdeCoverageBitCount', NvU32),
  ('num4KPageTableFormats', NvU32),
  ('bigPageSize', NvU32),
  ('compressionPageSize', NvU32),
  ('dualPageTableSupported', NvU32),
  ('idealVRAMPageSize', NvU32),
  ('pageTableBigFormat', NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT),
  ('pageTable4KFormat', (NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT * 16)),
  ('hVASpace', NvHandle),
  ('vaRangeLo', NvU64),
  ('vaSpaceId', NvU32),
  ('supportedPageSizeMask', NvU64),
]
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS = struct_NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS
class struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK(Struct): pass
struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK._fields_ = [
  ('ptePhysAddr', NvU64),
  ('pteCacheAttrib', NvU32),
  ('pteEntrySize', NvU32),
  ('pageSize', NvU32),
  ('pteAddrSpace', NvU32),
  ('pdeVASpaceSize', NvU32),
  ('pdeFlags', NvU32),
]
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK = struct_NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK
class struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS._fields_ = [
  ('gpuAddr', NvU64),
  ('pdeVirtAddr', NvU64),
  ('pdeEntrySize', NvU32),
  ('pdeAddrSpace', NvU32),
  ('pdeSize', NvU32),
  ('subDeviceId', NvU32),
  ('pteBlocks', (NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK * 5)),
  ('pdbAddr', NvU64),
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS = struct_NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS
class struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [
  ('hVASpace', NvHandle),
  ('flags', NvU32),
]
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS
class struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', (NvU8 * 8)),
]
NV0080_CTRL_DMA_GET_CAPS_PARAMS = struct_NV0080_CTRL_DMA_GET_CAPS_PARAMS
class struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS._fields_ = [
  ('vaSpaceSize', NvU64),
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS = struct_NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS._fields_ = [
  ('physAddr', NvU64),
  ('numEntries', NvU32),
  ('aperture', NvU32),
]
NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS
class struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS._fields_ = [
  ('pdeIndex', NvU32),
  ('flags', NvU32),
  ('ptParams', (NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS * 2)),
  ('hVASpace', NvHandle),
  ('pPdeBuffer', NvP64),
  ('subDeviceId', NvU32),
]
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS = struct_NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS
class struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS._fields_ = [
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS = struct_NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS
class struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS._fields_ = [
  ('hVASpace', NvHandle),
]
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS = struct_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS
class struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS._fields_ = [
  ('physAddress', NvU64),
  ('numEntries', NvU32),
  ('flags', NvU32),
  ('hVASpace', NvHandle),
  ('chId', NvU32),
  ('subDeviceId', NvU32),
  ('pasid', NvU32),
]
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS
class struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS(Struct): pass
struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS._fields_ = [
  ('hVASpace', NvHandle),
  ('subDeviceId', NvU32),
]
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS = struct_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS
class struct_NV0080_CTRL_FB_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_FB_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV0080_CTRL_FB_GET_CAPS_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_PARAMS
class struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS._fields_ = [
  ('Size', NvU64),
  ('Address', NvU64),
  ('AddressSpace', NvU32),
  ('MaxCompbitLine', NvU32),
  ('comptagsPerCacheLine', NvU32),
  ('cacheLineSize', NvU32),
  ('cacheLineSizePerSlice', NvU32),
  ('cacheLineFetchAlignment', NvU32),
  ('backingStoreBase', NvU64),
  ('gobsPerComptagPerSlice', NvU32),
  ('backingStoreCbcBase', NvU32),
  ('comptaglineAllocationPolicy', NvU32),
  ('privRegionStartOffset', NvU64),
  ('cbcCoveragePerSlice', NvU32),
]
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS = struct_NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS
class struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 3)),
]
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FB_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS(Struct): pass
struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS._fields_ = [
  ('value', NvU32),
]
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS = struct_NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS
enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = CEnum(ctypes.c_uint32)
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT', 0)
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS', 1)
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS', 2)
NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY.define('NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS', 3)

NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY = enum_NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY
class struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV0080_CTRL_FIFO_GET_CAPS_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_PARAMS
class struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('alignment', NvU32),
  ('size', NvU32),
]
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
class struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM(Struct): pass
struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM._fields_ = [
  ('hChannel1', NvHandle),
  ('hChannel2', NvHandle),
]
NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_GROUP_CHANNELS_PARAM
class struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM(Struct): pass
struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM._fields_ = [
  ('hChannel', NvHandle),
  ('tsDivisor', NvU32),
]
NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM = struct_NV0080_CTRL_FIFO_RUNLIST_DIVIDE_TIMESLICE_PARAM
class struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS._fields_ = [
  ('hRunlist', NvHandle),
  ('engineID', NvU32),
]
NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_PREEMPT_RUNLIST_PARAMS
class struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS._fields_ = [
  ('numChannels', NvU32),
  ('pChannelHandleList', NvP64),
  ('pChannelList', NvP64),
]
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS = struct_NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS
class struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS._fields_ = [
  ('engineID', NvU32),
  ('gpEntries', NvU32),
  ('pbEntries', NvU32),
]
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS = struct_NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS
class struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('property', NvU32),
  ('value', NvU64),
]
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS = struct_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS
class struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS._fields_ = [
  ('engineID', NvU32),
]
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS
class struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS._fields_ = [
  ('engineID', NvU32),
]
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS = struct_NV0080_CTRL_FIFO_START_RUNLIST_PARAMS
class struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 2)),
]
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS(Struct): pass
struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS._fields_ = [
  ('numChannels', NvU32),
  ('hChannels', (NvHandle * 4096)),
  ('flags', NvU32),
  ('timeout', NvU32),
]
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS = struct_NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS._fields_ = [
  ('numClasses', NvU32),
  ('classList', NvP64),
]
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS
class struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS._fields_ = [
  ('numSubDevices', NvU32),
]
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS = struct_NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS
class struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS._fields_ = [
  ('ConnectionCount', NvU32),
  ('Order', (NvU32 * 8)),
]
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS = struct_NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS
class struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS._fields_ = [
  ('subDeviceInstance', NvU32),
]
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS
class struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS._fields_ = [
  ('subDeviceInstance', NvU32),
]
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS = struct_NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS
class struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS._fields_ = [
  ('enable', NvU32),
]
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS = struct_NV0080_CTRL_GPU_SET_VIDLINK_PARAMS
class struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [
  ('newState', NvU32),
]
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS
class struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS._fields_ = [
  ('swStatePersistence', NvU32),
]
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS = struct_NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS
class struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS._fields_ = [
  ('virtualizationMode', NvU32),
  ('isGridBuild', NvBool),
]
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS
class struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [
  ('defaultSetting', NvU32),
  ('currentSetting', NvU32),
  ('pendingSetting', NvU32),
]
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
class struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS._fields_ = [
  ('setting', NvU32),
]
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS
class struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS._fields_ = [
  ('isVgx', NvBool),
]
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS
class struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS._fields_ = [
  ('totalVFs', NvU32),
  ('firstVfOffset', NvU32),
  ('vfFeatureMask', NvU32),
  ('FirstVFBar0Address', NvU64),
  ('FirstVFBar1Address', NvU64),
  ('FirstVFBar2Address', NvU64),
  ('bar0Size', NvU64),
  ('bar1Size', NvU64),
  ('bar2Size', NvU64),
  ('b64bitBar0', NvBool),
  ('b64bitBar1', NvBool),
  ('b64bitBar2', NvBool),
  ('bSriovEnabled', NvBool),
  ('bSriovHeavyEnabled', NvBool),
  ('bEmulateVFBar0TlbInvalidationRegister', NvBool),
  ('bClientRmAllocatedCtxBuffer', NvBool),
  ('bNonPowerOf2ChannelCountSupported', NvBool),
  ('bVfResizableBAR1Supported', NvBool),
]
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS
class struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS._fields_ = [
  ('numClasses', NvU32),
  ('classList', (NvU32 * 100)),
]
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS = struct_NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS
class struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM(Struct): pass
struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM._fields_ = [
  ('subDeviceInst', NvU32),
  ('hSubDevice', NvHandle),
]
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM = struct_NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM
class struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS._fields_ = [
  ('brands', NvU32),
]
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS = struct_NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS
class struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS._fields_ = [
  ('vfBar1SizeMB', NvU32),
  ('numVfs', NvU32),
]
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS
class struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [
  ('bHeterogeneousMode', NvBool),
]
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
class struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [
  ('bHeterogeneousMode', NvBool),
]
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS
class struct_NV0080_CTRL_GR_ROUTE_INFO(Struct): pass
struct_NV0080_CTRL_GR_ROUTE_INFO._fields_ = [
  ('flags', NvU32),
  ('route', NvU64),
]
NV0080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO
class struct_NV0080_CTRL_GR_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_GR_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV0080_CTRL_GR_GET_CAPS_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_PARAMS
class struct_NVXXXX_CTRL_XXX_INFO(Struct): pass
NV0080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO
struct_NVXXXX_CTRL_XXX_INFO._fields_ = [
  ('index', NvU32),
  ('data', NvU32),
]
class struct_NV0080_CTRL_GR_GET_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_GR_GET_INFO_PARAMS._fields_ = [
  ('grInfoListSize', NvU32),
  ('grInfoList', NvP64),
]
NV0080_CTRL_GR_GET_INFO_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_PARAMS
enum_NV0080_CTRL_GR_TPC_PARTITION_MODE = CEnum(ctypes.c_uint32)
NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_NONE', 0)
NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_STATIC', 1)
NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE.define('NV0080_CTRL_GR_TPC_PARTITION_MODE_DYNAMIC', 2)

NV0080_CTRL_GR_TPC_PARTITION_MODE = enum_NV0080_CTRL_GR_TPC_PARTITION_MODE
class struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS(Struct): pass
struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS._fields_ = [
  ('hChannelGroup', NvHandle),
  ('mode', NV0080_CTRL_GR_TPC_PARTITION_MODE),
  ('bEnableAllTpcs', NvBool),
  ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO),
]
NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
class struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 23)),
  ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO),
  ('bCapsPopulated', NvBool),
]
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS._fields_ = [
  ('grInfoListSize', NvU32),
  ('grInfoList', (NV0080_CTRL_GR_INFO * 58)),
  ('grRouteInfo', NV0080_CTRL_GR_ROUTE_INFO),
]
NV0080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
class struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV0080_CTRL_HOST_GET_CAPS_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_PARAMS
class struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 3)),
]
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS(Struct): pass
struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS._fields_ = [
  ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS),
]
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS
class struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS(Struct): pass
struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS._fields_ = [
  ('params', NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS),
]
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS = struct_NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS
class struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS(Struct): pass
struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS._fields_ = [
  ('numClients', NvU32),
  ('clientHandles', (NvHandle * 200)),
]
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS = struct_NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS
class struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS(Struct): pass
struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS._fields_ = [
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV0080_CTRL_MSENC_GET_CAPS_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_PARAMS
class struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 4)),
  ('instanceId', NvU32),
]
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS._fields_ = [
  ('capsTbl', (NvU8 * 9)),
  ('instanceId', NvU32),
]
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS
class struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS(Struct): pass
struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [
  ('bActivate', NvBool),
]
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS
class struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS(Struct): pass
struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS._fields_ = [
  ('bCudaLimit', NvBool),
]
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS = struct_NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS
class struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS(Struct): pass
struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS._fields_ = [
  ('cmd', NvU32),
]
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS
class struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS(Struct): pass
struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS._fields_ = [
  ('subDeviceInstance', NvU32),
  ('width', NvU16),
  ('height', NvU16),
  ('depth', NvU16),
  ('pitch', NvU16),
  ('baseAddress', NvU64),
  ('size', NvU64),
]
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS = struct_NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS
NV2080_CTRL_BIOS_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS._fields_ = [
  ('biosInfoListSize', NvU32),
  ('biosInfoList', NvP64),
]
NV2080_CTRL_BIOS_GET_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_PARAMS
class struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS._fields_ = [
  ('biosInfoListSize', NvU32),
  ('biosInfoList', (NV2080_CTRL_BIOS_INFO * 15)),
]
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING(Struct): pass
class struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value(ctypes.Union): pass
struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value._fields_ = [
  ('ascii', (NvU8 * 256)),
  ('unicode', (NvU16 * 256)),
  ('hash', NvU16),
]
struct_NV2080_CTRL_BIOS_NBSI_REG_STRING._fields_ = [
  ('size', NvU32),
  ('type', NvU32),
  ('value', struct_NV2080_CTRL_BIOS_NBSI_REG_STRING_value),
]
NV2080_CTRL_BIOS_NBSI_REG_STRING = struct_NV2080_CTRL_BIOS_NBSI_REG_STRING
class struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS._fields_ = [
  ('module', NvU32),
  ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING),
  ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING),
  ('retBuf', NvP64),
  ('retSize', NvU32),
  ('errorCode', NvU32),
]
NV2080_CTRL_BIOS_GET_NBSI_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_PARAMS
class struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS._fields_ = [
  ('module', NvU32),
  ('path', NV2080_CTRL_BIOS_NBSI_REG_STRING),
  ('valueName', NV2080_CTRL_BIOS_NBSI_REG_STRING),
  ('retBuf', (NvU8 * 256)),
  ('retSize', NvU32),
  ('errorCode', NvU32),
]
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS
class struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS._fields_ = [
  ('globType', NvU16),
  ('globIndex', NvU8),
  ('globSource', NvU16),
  ('retBufOffset', NvU32),
  ('retBuf', NvP64),
  ('retSize', NvU32),
  ('totalObjSize', NvU32),
  ('errorCode', NvU32),
]
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS = struct_NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS
class struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS._fields_ = [
  ('BoardID', NvU32),
  ('chipSKU', (ctypes.c_char * 9)),
  ('chipSKUMod', (ctypes.c_char * 5)),
  ('skuConfigVersion', NvU32),
  ('project', (ctypes.c_char * 5)),
  ('projectSKU', (ctypes.c_char * 5)),
  ('CDP', (ctypes.c_char * 6)),
  ('projectSKUMod', (ctypes.c_char * 2)),
  ('businessCycle', NvU32),
]
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = struct_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
class struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS._fields_ = [
  ('vbiosPostTime', NvU64),
]
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS = struct_NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS
class struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS(Struct): pass
struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS._fields_ = [
  ('version', NvU32),
  ('flags', NvU32),
]
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS = struct_NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS
class struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS._fields_ = [
  ('pciDeviceId', NvU32),
  ('pciSubSystemId', NvU32),
  ('pciRevisionId', NvU32),
  ('pciExtDeviceId', NvU32),
]
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS
NV2080_CTRL_BUS_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_BUS_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_INFO_PARAMS._fields_ = [
  ('busInfoListSize', NvU32),
  ('busInfoList', NvP64),
]
NV2080_CTRL_BUS_GET_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_PARAMS
class struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS._fields_ = [
  ('busInfoListSize', NvU32),
  ('busInfoList', (NV2080_CTRL_BUS_INFO * 52)),
]
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_BUS_PCI_BAR_INFO(Struct): pass
struct_NV2080_CTRL_BUS_PCI_BAR_INFO._fields_ = [
  ('flags', NvU32),
  ('barSize', NvU32),
  ('barSizeBytes', NvU64),
  ('barOffset', NvU64),
]
NV2080_CTRL_BUS_PCI_BAR_INFO = struct_NV2080_CTRL_BUS_PCI_BAR_INFO
class struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS._fields_ = [
  ('pciBarCount', NvU32),
  ('pciBarInfo', (NV2080_CTRL_BUS_PCI_BAR_INFO * 8)),
]
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS = struct_NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS
class struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS._fields_ = [
  ('pcieLinkWidth', NvU32),
  ('failingReason', NvU32),
]
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS
class struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS._fields_ = [
  ('busSpeed', NvU32),
]
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS = struct_NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS
class struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS._fields_ = [
  ('hMemory', NvHandle),
]
NV2080_CTRL_BUS_MAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_MAP_BAR2_PARAMS
class struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS._fields_ = [
  ('hMemory', NvHandle),
]
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS = struct_NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS
class struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS._fields_ = [
  ('hMemory', NvHandle),
  ('offset', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS = struct_NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS
class struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS._fields_ = [
  ('command', NvU8),
  ('deviceState', NvU32),
]
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS = struct_NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS
class struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS._fields_ = [
  ('pexCounterMask', NvU32),
  ('pexTotalCorrectableErrors', NvU32),
  ('pexCorrectableErrors', NvU16),
  ('pexTotalNonFatalErrors', NvU8),
  ('pexTotalFatalErrors', NvU8),
  ('pexTotalUnsupportedReqs', NvU8),
  ('pexCounters', (NvU16 * 31)),
]
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS
class struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS._fields_ = [
  ('pexCounterMask', NvU32),
]
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS
class struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS._fields_ = [
  ('pexCounterMask', NvU32),
  ('bFreezeRmCounter', NvBool),
]
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS._fields_ = [
  ('pexLaneErrorStatus', NvU16),
  ('pexLaneCounter', (NvU8 * 16)),
]
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS._fields_ = [
  ('bPexLtrRegkeyOverride', NvBool),
  ('bPexRootPortLtrSupported', NvBool),
  ('bPexGpuLtrSupported', NvBool),
  ('pexLtrSnoopLatencyValue', NvU16),
  ('pexLtrSnoopLatencyScale', NvU8),
  ('pexLtrNoSnoopLatencyValue', NvU16),
  ('pexLtrNoSnoopLatencyScale', NvU8),
]
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS
class struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS._fields_ = [
  ('pexLtrSnoopLatencyValue', NvU16),
  ('pexLtrSnoopLatencyScale', NvU8),
  ('pexLtrNoSnoopLatencyValue', NvU16),
  ('pexLtrNoSnoopLatencyScale', NvU8),
]
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS
class struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS._fields_ = [
  ('pexCounterMask', NvU32),
  ('pexCounters', (NvU32 * 7)),
]
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS
class struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS._fields_ = [
  ('pexCounterMask', NvU32),
]
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS = struct_NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS
class struct_NV2080_CTRL_BUS_GET_BFD_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_BFD_PARAMS._fields_ = [
  ('valid', NvBool),
  ('deviceID', NvU16),
  ('vendorID', NvU16),
  ('domain', NvU32),
  ('bus', NvU16),
  ('device', NvU16),
  ('function', NvU8),
]
NV2080_CTRL_BUS_GET_BFD_PARAMS = struct_NV2080_CTRL_BUS_GET_BFD_PARAMS
class struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR(Struct): pass
struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR._fields_ = [
  ('params', (NV2080_CTRL_BUS_GET_BFD_PARAMS * 32)),
]
NV2080_CTRL_BUS_GET_BFD_PARAMSARR = struct_NV2080_CTRL_BUS_GET_BFD_PARAMSARR
class struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS._fields_ = [
  ('aspmDisableFlags', (NvBool * 9)),
]
NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS = struct_NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS._fields_ = [
  ('bEnable', NvBool),
]
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS = struct_NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS
class struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS._fields_ = [
  ('nvlinkPeerIdMask', (NvU32 * 32)),
]
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS = struct_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS
class struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS._fields_ = [
  ('eomMode', NvU8),
  ('eomNblks', NvU8),
  ('eomNerrs', NvU8),
]
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS = struct_NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS._fields_ = [
  ('regAddress', NvU32),
  ('laneSelectMask', NvU32),
  ('regValue', NvU16),
]
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS
class struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS._fields_ = [
  ('eomMode', NvU8),
  ('eomNblks', NvU8),
  ('eomNerrs', NvU8),
  ('eomBerEyeSel', NvU8),
  ('eomPamEyeSel', NvU8),
  ('laneMask', NvU32),
  ('eomStatus', (NvU16 * 32)),
]
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS = struct_NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS._fields_ = [
  ('capType', NvU32),
  ('dbdf', NvU32),
  ('atomicsCaps', NvU32),
]
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
class struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO(Struct): pass
struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO._fields_ = [
  ('bSupported', NvBool),
  ('attributes', NvU32),
]
NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO = struct_NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS._fields_ = [
  ('capType', NvU32),
  ('dbdf', NvU32),
  ('atomicOp', (NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO * 13)),
]
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS._fields_ = [
  ('bIsLinkUp', NvBool),
  ('nrLinks', NvU32),
  ('maxNrLinks', NvU32),
  ('linkMask', NvU32),
  ('perLinkBwMBps', NvU32),
  ('perLinkLaneWidth', NvU32),
  ('remoteType', NvU32),
]
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
class struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS._fields_ = [
  ('bDisable', NvBool),
]
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS = struct_NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS
class struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS._fields_ = [
  ('connectionType', NvU32),
  ('peerId', NvU32),
  ('bEgmPeer', NvBool),
  ('bSpaAccessOnly', NvBool),
  ('bUseUuid', NvBool),
  ('remoteGpuId', NvU32),
  ('remoteGpuUuid', (NvU8 * 16)),
]
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS
class struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS._fields_ = [
  ('connectionType', NvU32),
  ('peerId', NvU32),
  ('bUseUuid', NvBool),
  ('remoteGpuId', NvU32),
  ('remoteGpuUuid', (NvU8 * 16)),
]
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS = struct_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS
class struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS._fields_ = [
  ('atomicsCaps', NvU32),
]
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS = struct_NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS
class struct_NV2080_CTRL_CE_GET_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_CAPS_PARAMS._fields_ = [
  ('ceEngineType', NvU32),
  ('capsTblSize', NvU32),
  ('capsTbl', NvP64),
]
NV2080_CTRL_CE_GET_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_PARAMS
class struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS._fields_ = [
  ('ceEngineType', NvU32),
  ('capsTbl', (NvU8 * 2)),
]
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
class struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS._fields_ = [
  ('ceEngineType', NvU32),
  ('pceMask', NvU32),
]
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS
class struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS._fields_ = [
  ('ceEngineType', NvU32),
  ('pceLceMap', (NvU32 * 32)),
  ('grceSharedLceMap', (NvU32 * 4)),
]
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS = struct_NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS._fields_ = [
  ('pceLceMap', (NvU32 * 32)),
  ('grceConfig', (NvU32 * 4)),
  ('exposeCeMask', NvU32),
  ('bUpdateNvlinkPceLce', NvBool),
]
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS
class struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS._fields_ = [
  ('stubbedCeMask', NvU32),
]
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS = struct_NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_CAPS_V2_PARAMS
class struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS._fields_ = [
  ('size', NvU32),
]
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS._fields_ = [
  ('hshubPceMasks', (NvU32 * 32)),
  ('fbhubPceMask', NvU32),
]
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS
class struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS._fields_ = [
  ('capsTbl', ((NvU8 * 2) * 64)),
  ('present', NvU64),
]
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS = struct_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
class struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS._fields_ = [
  ('ceEngineType', NvU32),
  ('shimInstance', NvU32),
  ('shimLocalLceIdx', NvU32),
]
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS = struct_NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS
class struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS._fields_ = [
  ('pceLceMap', (NvU32 * 32)),
  ('grceConfig', (NvU32 * 4)),
  ('exposeCeMask', NvU32),
  ('bUpdateNvlinkPceLce', NvBool),
  ('shimInstance', NvU32),
]
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS = struct_NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS
class struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS._fields_ = [
  ('connectingHubPceMasks', (NvU32 * 32)),
  ('fbhubPceMask', NvU32),
  ('shimInstance', NvU32),
]
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS = struct_NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS
enum_NV2080_CTRL_CE_LCE_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CE_LCE_TYPE_PCIE = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE', 1)
NV2080_CTRL_CE_LCE_TYPE_DECOMP = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_DECOMP', 2)
NV2080_CTRL_CE_LCE_TYPE_SCRUB = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_SCRUB', 3)
NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER', 4)
NV2080_CTRL_CE_LCE_TYPE_C2C = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C', 5)
NV2080_CTRL_CE_LCE_TYPE_PCIE_RD = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_RD', 6)
NV2080_CTRL_CE_LCE_TYPE_PCIE_WR = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_PCIE_WR', 7)
NV2080_CTRL_CE_LCE_TYPE_C2C_H2D = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_H2D', 8)
NV2080_CTRL_CE_LCE_TYPE_C2C_D2H = enum_NV2080_CTRL_CE_LCE_TYPE.define('NV2080_CTRL_CE_LCE_TYPE_C2C_D2H', 9)

NV2080_CTRL_CE_LCE_TYPE = enum_NV2080_CTRL_CE_LCE_TYPE
class struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS._fields_ = [
  ('lceType', NV2080_CTRL_CE_LCE_TYPE),
  ('numPces', NvU32),
  ('numLces', NvU32),
  ('supportedPceMask', NvU32),
  ('supportedLceMask', NvU32),
  ('pcePerHshub', NvU32),
]
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS = struct_NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS
class struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS._fields_ = [
  ('decompLceMask', NvU64),
  ('shimInstance', NvU32),
]
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS = struct_NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS
class struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS(Struct): pass
struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS._fields_ = [
  ('lceIndex', NvU32),
  ('bDecompEnabled', NvBool),
]
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS = struct_NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS
class struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS(Struct): pass
struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hDevice', NvHandle),
  ('engine', NvU32),
  ('hVASpace', NvHandle),
]
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS = struct_NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS
NV2080_CTRL_DMA_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_DMA_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_DMA_GET_INFO_PARAMS._fields_ = [
  ('dmaInfoTblSize', NvU32),
  ('dmaInfoTbl', (NV2080_CTRL_DMA_INFO * 256)),
]
NV2080_CTRL_DMA_GET_INFO_PARAMS = struct_NV2080_CTRL_DMA_GET_INFO_PARAMS
class struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO(Struct): pass
struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO._fields_ = [
  ('srcAddr', NvU32),
  ('dstAddr', NvU32),
  ('relComptagIndex', NvU16),
]
NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO = struct_NV2080_CTRL_DMA_UPDATE_COMPTAG_INFO_TILE_INFO
class struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO(Struct): pass
struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO._fields_ = [
  ('hMemory', NvHandle),
  ('offset', NvU64),
  ('size', NvU64),
]
NV2080_CTRL_DMABUF_MEM_HANDLE_INFO = struct_NV2080_CTRL_DMABUF_MEM_HANDLE_INFO
class struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS(Struct): pass
struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS._fields_ = [
  ('fd', NvS32),
  ('totalObjects', NvU32),
  ('numObjects', NvU32),
  ('index', NvU32),
  ('totalSize', NvU64),
  ('mappingType', NvU8),
  ('handles', (NV2080_CTRL_DMABUF_MEM_HANDLE_INFO * 128)),
]
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS = struct_NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS
class struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS._fields_ = [
  ('sramParityUncorrectedUnique', NvU64),
  ('sramSecDedUncorrectedUnique', NvU64),
  ('sramCorrectedUnique', NvU64),
  ('dramUncorrectedTotal', NvU64),
  ('dramCorrectedTotal', NvU64),
  ('lastClearedTimestamp', NvU32),
  ('sramBucketL2', NvU64),
  ('sramBucketSM', NvU64),
  ('sramBucketPcie', NvU64),
  ('sramBucketFirmware', NvU64),
  ('sramBucketOther', NvU64),
  ('sramErrorThresholdExceeded', NvBool),
]
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS = struct_NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS
class struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS(Struct): pass
struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS._fields_ = [
  ('sramCorUni', NvU64),
  ('sramUncParityUni', NvU64),
  ('sramUncSecDedUni', NvU64),
  ('dramCorTot', NvU64),
  ('dramUncTot', NvU64),
]
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS = struct_NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS
class struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS._fields_ = [
  ('event', NvU32),
  ('action', NvU32),
  ('bNotifyState', NvBool),
  ('info32', NvU32),
  ('info16', NvU16),
]
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS
enum_NV2080_EVENT_HDACODEC_DSTATE = CEnum(ctypes.c_uint32)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D0', 0)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D1', 1)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2 = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D2', 2)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_HOT', 3)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_D3_COLD', 4)
NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX = enum_NV2080_EVENT_HDACODEC_DSTATE.define('NV2080_EVENT_HDACODEC_DEVICE_DSTATE_DSTATE_MAX', 5)

NV2080_EVENT_HDACODEC_DSTATE = enum_NV2080_EVENT_HDACODEC_DSTATE
class struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS._fields_ = [
  ('hMemory', NvHandle),
]
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS = struct_NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS
class struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS._fields_ = [
  ('hSemMemory', NvHandle),
  ('semOffset', NvU32),
]
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS
class struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS._fields_ = [
  ('guestMSIAddr', NvU64),
  ('guestMSIData', NvU32),
  ('hSemMemory', NvHandle),
  ('isReset', NvBool),
  ('vgpuUuid', (NvU8 * 16)),
  ('domainId', NvU64),
]
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS = struct_NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS
class struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS._fields_ = [
  ('hSemMemory', NvHandle),
  ('isSemaMemValidationEnabled', NvBool),
]
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS = struct_NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS
class struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS._fields_ = [
  ('hEvent', NvHandle),
]
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS = struct_NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS
enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = CEnum(ctypes.c_uint32)
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_FULL', 0)
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_SIMPLE', 1)
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD.define('NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD_CUSTOM', 2)

NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD = enum_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD
class struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS._fields_ = [
  ('hEventBuffer', NvHandle),
  ('recordSize', NvU32),
  ('levelOfDetail', NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_LOD),
  ('eventFilter', NvU32),
  ('bAllUsers', NvBool),
]
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS
class struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS(Struct): pass
struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS._fields_ = [
  ('hEventBuffer', NvHandle),
  ('tracepointMask', NvU64),
  ('gspLoggingBufferSize', NvU32),
  ('gspLoggingBufferWatermark', NvU32),
]
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS = struct_NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS
NV2080_CTRL_FB_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_FB_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_INFO_PARAMS._fields_ = [
  ('fbInfoListSize', NvU32),
  ('fbInfoList', NvP64),
]
NV2080_CTRL_FB_GET_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_PARAMS
class struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS._fields_ = [
  ('fbInfoListSize', NvU32),
  ('fbInfoList', (NV2080_CTRL_FB_INFO * 57)),
]
NV2080_CTRL_FB_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_FB_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS._fields_ = [
  ('cpuVirtAddress', NvP64),
  ('gpuVirtAddress', NvU64),
]
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS = struct_NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS
class struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS._fields_ = [
  ('flags', NvU32),
  ('driveStrengthRiseCount', NvU32),
  ('driveStrengthFallCount', NvU32),
  ('driveStrengthTermCount', NvU32),
  ('slewStrengthRiseCount', NvU32),
  ('slewStrengthFallCount', NvU32),
]
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS = struct_NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS
class struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS._fields_ = [
  ('flags', NvU32),
]
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS = struct_NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS
class struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS._fields_ = [
  ('addressArray', (NvU64 * 500)),
  ('addressArraySize', NvU32),
  ('addressAlign', NvU32),
  ('memBlockSizeBytes', NvU64),
  ('flags', NvU32),
]
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS = struct_NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS
class struct_NV2080_CTRL_FB_IS_KIND_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_IS_KIND_PARAMS._fields_ = [
  ('operation', NvU32),
  ('kind', NvU32),
  ('result', NvBool),
]
NV2080_CTRL_FB_IS_KIND_PARAMS = struct_NV2080_CTRL_FB_IS_KIND_PARAMS
class struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS._fields_ = [
  ('powerState', NvU32),
  ('writeMode', NvU32),
  ('bypassMode', NvU32),
  ('rcmState', NvU32),
]
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS
NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG = (ctypes.c_ubyte * 17)
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO._fields_ = [
  ('base', NvU64),
  ('limit', NvU64),
  ('reserved', NvU64),
  ('performance', NvU32),
  ('supportCompressed', NvBool),
  ('supportISO', NvBool),
  ('bProtected', NvBool),
  ('blackList', NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG),
]
NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO
class struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS._fields_ = [
  ('numFBRegions', NvU32),
  ('fbRegion', (NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO * 16)),
]
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
class struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO(Struct): pass
struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO._fields_ = [
  ('pageAddressWithEccOn', NvU64),
  ('pageAddressWithEccOff', NvU64),
  ('rbcAddress', NvU32),
  ('source', NvU32),
  ('status', NvU32),
  ('timestamp', NvU32),
]
NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO
class struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS._fields_ = [
  ('offlined', (NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64)),
  ('pageSize', NvU32),
  ('validEntries', NvU32),
  ('numPagesAdded', NvU32),
]
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS = struct_NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS
class struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS._fields_ = [
  ('offlined', (NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO * 64)),
  ('validEntries', NvU32),
  ('bRetirementPending', NvBool),
  ('retirementPending', NvU8),
]
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS
enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS', 0)
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_REGION_PROPERTY', 1)
NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_GET_FALCON_STATUS', 2)

NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE
enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_NONE', 0)
NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE.define('NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_INVALID_CLIENT_REQUEST', 1)

NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE = enum_NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE
class struct_ACR_REQUEST_PARAMS(Struct): pass
struct_ACR_REQUEST_PARAMS._fields_ = [
  ('clientId', NvU32),
  ('reqReadMask', NvU32),
  ('reqWriteMask', NvU32),
  ('regionSize', NvU32),
]
ACR_REQUEST_PARAMS = struct_ACR_REQUEST_PARAMS
class struct_ACR_REGION_ID_PROP(Struct): pass
struct_ACR_REGION_ID_PROP._fields_ = [
  ('regionId', NvU32),
  ('readMask', NvU32),
  ('writeMask', NvU32),
  ('regionSize', NvU32),
  ('clientMask', NvU32),
  ('physicalAddress', NvU64),
]
ACR_REGION_ID_PROP = struct_ACR_REGION_ID_PROP
class struct_ACR_STATUS_PARAMS(Struct): pass
struct_ACR_STATUS_PARAMS._fields_ = [
  ('allocStatus', NvU32),
  ('regionId', NvU32),
  ('physicalAddress', NvU64),
]
ACR_STATUS_PARAMS = struct_ACR_STATUS_PARAMS
class struct_ACR_REGION_HANDLE(Struct): pass
struct_ACR_REGION_HANDLE._fields_ = [
  ('hClient', NvHandle),
  ('hParent', NvHandle),
  ('hMemory', NvHandle),
  ('hClass', NvU32),
  ('hDevice', NvHandle),
]
ACR_REGION_HANDLE = struct_ACR_REGION_HANDLE
class struct_ACR_FALCON_LS_STATUS(Struct): pass
struct_ACR_FALCON_LS_STATUS._fields_ = [
  ('falconId', NvU16),
  ('bIsInLs', NvBool),
]
ACR_FALCON_LS_STATUS = struct_ACR_FALCON_LS_STATUS
class struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS._fields_ = [
  ('queryType', NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE),
  ('errorCode', NV2080_CTRL_CMD_FB_ACR_QUERY_ERROR_CODE),
  ('acrRegionIdProp', ACR_REGION_ID_PROP),
  ('clientReq', ACR_REQUEST_PARAMS),
  ('clientReqStatus', ACR_STATUS_PARAMS),
  ('handle', ACR_REGION_HANDLE),
  ('falconStatus', ACR_FALCON_LS_STATUS),
]
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS
class struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS._fields_ = [
  ('sourceMask', NvU32),
]
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS._fields_ = [
  ('pCompBitCopyObj', NvP64),
  ('pSwizzleParams', NvP64),
]
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS
class struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS._fields_ = [
  ('fbpIndex', NvU8),
  ('ltcMask', NvU32),
  ('ltcCount', NvU32),
  ('ltsMask', NvU32),
  ('ltsCount', NvU32),
]
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = struct_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS._fields_ = [
  ('CBCBaseAddress', NvU32),
  ('backingStorePA', NvU64),
  ('backingStoreVA', ctypes.POINTER(NvU8)),
  ('backingStoreChunkPA', NvU64),
  ('backingStoreChunkVA', ctypes.POINTER(NvU8)),
  ('backingStoreChunkSize', NvU32),
  ('cacheWriteBitMap', ctypes.POINTER(NvU8)),
  ('backingStoreChunkOverfetch', NvBool),
  ('PageSizeSrc', NvU32),
  ('PageSizeDest', NvU32),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS._fields_ = [
  ('fcbits', ctypes.POINTER(NvU32)),
  ('compbits', ctypes.POINTER(NvU32)),
  ('dataPhysicalStart', NvU64),
  ('surfaceOffset', NvU64),
  ('comptagLine', NvU32),
  ('upper64KBCompbitSel', NvBool),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS._fields_ = [
  ('fcbits', NvU32),
  ('compbits', NvU32),
  ('writeFc', NvBool),
  ('dataPhysicalStart', NvU64),
  ('surfaceOffset', NvU64),
  ('comptagLine', NvU32),
  ('upper64KBCompbitSel', NvBool),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS._fields_ = [
  ('SrcDataPhysicalStart', NvU64),
  ('SrcComptagLine', NvU32),
  ('page64KB', NvU32),
  ('compbitBuffer', ctypes.POINTER(NvU32)),
  ('upper64KBCompbitSel', NvBool),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS._fields_ = [
  ('DstDataPhysicalStart', NvU64),
  ('DstComptagLine', NvU32),
  ('page64KB', NvU32),
  ('compbitBuffer', ctypes.POINTER(NvU32)),
  ('upper64KBCompbitSel', NvBool),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS
class struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS._fields_ = [
  ('bForceBar1', NvBool),
]
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS = struct_NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS
class struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS._fields_ = [
  ('pAmapConfParams', NvP64),
  ('pCbcSwizzleParams', NvP64),
]
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS
enum_CTRL_CMD_FB_CBC_OP = CEnum(ctypes.c_uint32)
CTRL_CMD_FB_CBC_OP_CLEAN = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_CLEAN', 0)
CTRL_CMD_FB_CBC_OP_INVALIDATE = enum_CTRL_CMD_FB_CBC_OP.define('CTRL_CMD_FB_CBC_OP_INVALIDATE', 1)

CTRL_CMD_FB_CBC_OP = enum_CTRL_CMD_FB_CBC_OP
class struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS._fields_ = [
  ('fbCBCOp', CTRL_CMD_FB_CBC_OP),
]
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS = struct_NV2080_CTRL_CMD_FB_CBC_OP_PARAMS
class struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS._fields_ = [
  ('pCompTags', (NvU32 * 127)),
  ('numCompTags', NvU32),
]
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS = struct_NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS
class struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS._fields_ = [
  ('attr', NvU32),
  ('attr2', NvU32),
  ('size', NvU32),
  ('ctagOffset', NvU32),
  ('hwResId', NvU32),
  ('retCompTagLineMin', NvU32),
  ('retCompTagLineMax', NvU32),
]
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS = struct_NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS
class struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS._fields_ = [
  ('hwResId', NvU32),
]
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS = struct_NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS
enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_FB_SET_VPR = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE.define('NV2080_CTRL_CMD_FB_SET_VPR', 0)

NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE = enum_NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE
enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_GENERIC', 0)
NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE.define('NV2080_CTRL_CMD_FB_VPR_ERROR_INVALID_CLIENT_REQUEST', 1)

NV2080_CTRL_CMD_FB_VPR_ERROR_CODE = enum_NV2080_CTRL_CMD_FB_VPR_ERROR_CODE
class struct_VPR_REQUEST_PARAMS(Struct): pass
struct_VPR_REQUEST_PARAMS._fields_ = [
  ('startAddr', NvU32),
  ('size', NvU32),
]
VPR_REQUEST_PARAMS = struct_VPR_REQUEST_PARAMS
class struct_VPR_STATUS_PARAMS(Struct): pass
struct_VPR_STATUS_PARAMS._fields_ = [
  ('status', NvU32),
]
VPR_STATUS_PARAMS = struct_VPR_STATUS_PARAMS
class struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS._fields_ = [
  ('requestType', NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE),
  ('requestParams', VPR_REQUEST_PARAMS),
  ('statusParams', VPR_STATUS_PARAMS),
]
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS
PNV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS)
class struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS._fields_ = [
  ('offlinedPages', (NvU32 * 64)),
  ('pageSize', NvU32),
  ('validEntries', NvU32),
]
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS
class struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS._fields_ = [
  ('defaultPageSize', NvU32),
  ('comptagsPerCacheLine', NvU32),
  ('unpackedComptagLinesPerCacheLine', NvU32),
  ('compCacheLineSizePerLTC', NvU32),
  ('unpackedCompCacheLineSizePerLTC', NvU32),
  ('slicesPerLTC', NvU32),
  ('numActiveLTCs', NvU32),
  ('familyName', NvU32),
  ('chipName', NvU32),
  ('bitsPerRAMEntry', NvU32),
  ('ramBankWidth', NvU32),
  ('bitsPerComptagLine', NvU32),
  ('ramEntriesPerCompCacheLine', NvU32),
  ('comptagLineSize', NvU32),
]
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS
class struct_NV2080_CTRL_FB_SET_RRD_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_SET_RRD_PARAMS._fields_ = [
  ('rrd', NvU32),
]
NV2080_CTRL_FB_SET_RRD_PARAMS = struct_NV2080_CTRL_FB_SET_RRD_PARAMS
class struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS._fields_ = [
  ('limit', NvU8),
]
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS = struct_NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS
class struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS._fields_ = [
  ('bEnable', NvBool),
]
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS = struct_NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS
class struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS._fields_ = [
  ('alignType', NvU32),
  ('alignAttr', NvU32),
  ('alignInputFlags', NvU32),
  ('alignHead', NvU32),
  ('alignSize', NvU64),
  ('alignHeight', NvU32),
  ('alignWidth', NvU32),
  ('alignPitch', NvU32),
  ('alignPad', NvU32),
  ('alignMask', NvU32),
  ('alignOutputFlags', (NvU32 * 4)),
  ('alignBank', (NvU32 * 4)),
  ('alignKind', NvU32),
  ('alignAdjust', NvU32),
  ('alignAttr2', NvU32),
]
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS = struct_NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS
class struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS._fields_ = [
  ('cbcBaseAddress', NvU32),
  ('compCacheLineSize', NvU32),
  ('backingStoreStartPA', NvU64),
  ('backingStoreAllocPA', NvU64),
  ('backingStoreChunkOverfetch', NvU32),
]
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS
class struct_NV2080_CTRL_FB_REMAP_ENTRY(Struct): pass
struct_NV2080_CTRL_FB_REMAP_ENTRY._fields_ = [
  ('remapRegVal', NvU32),
  ('timestamp', NvU32),
  ('fbpa', NvU8),
  ('sublocation', NvU8),
  ('source', NvU8),
  ('flags', NvU8),
]
NV2080_CTRL_FB_REMAP_ENTRY = struct_NV2080_CTRL_FB_REMAP_ENTRY
class struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS._fields_ = [
  ('entryCount', NvU32),
  ('flags', NvU8),
  ('entries', (NV2080_CTRL_FB_REMAP_ENTRY * 512)),
]
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS = struct_NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS._fields_ = [
  ('data', (NvU8 * 24)),
]
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('fbpEnMask', NvU64),
]
NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('ltcEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('ltsEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('fbpaEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('fbpaSubpEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('fbpLogicalIndex', NvU32),
]
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('ropEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('ltcEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('ltsEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('fbpaEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('ropEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('fbpaSubpEnMask', NvU64),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS._fields_ = [
  ('sysIdx', NvU32),
  ('sysl2LtcEnMask', NvU32),
]
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS
class struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS._fields_ = [
  ('sysIdx', NvU32),
  ('sysl2LtsEnMask', NvU64),
]
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS = struct_NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('pacEnMask', NvU32),
]
NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('logicalLtcEnMask', NvU64),
]
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS._fields_ = [
  ('fbpIndex', NvU32),
  ('swizzId', NvU32),
  ('logicalLtcEnMask', NvU64),
]
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS = struct_NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS
class struct_NV2080_CTRL_FB_FS_INFO_QUERY(Struct): pass
class struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams(ctypes.Union): pass
struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams._fields_ = [
  ('inv', NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS),
  ('fbp', NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS),
  ('ltc', NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS),
  ('lts', NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS),
  ('fbpa', NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS),
  ('rop', NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS),
  ('dmLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS),
  ('dmLts', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS),
  ('dmFbpa', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS),
  ('dmRop', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS),
  ('dmFbpaSubp', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS),
  ('fbpaSubp', NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS),
  ('fbpLogicalMap', NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS),
  ('sysl2Ltc', NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS),
  ('pac', NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS),
  ('logicalLtc', NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS),
  ('dmLogicalLtc', NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS),
  ('sysl2Lts', NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS),
]
struct_NV2080_CTRL_FB_FS_INFO_QUERY._fields_ = [
  ('queryType', NvU16),
  ('reserved', (NvU8 * 2)),
  ('status', NvU32),
  ('queryParams', struct_NV2080_CTRL_FB_FS_INFO_QUERY_queryParams),
]
NV2080_CTRL_FB_FS_INFO_QUERY = struct_NV2080_CTRL_FB_FS_INFO_QUERY
class struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS._fields_ = [
  ('numQueries', NvU16),
  ('reserved', (NvU8 * 6)),
  ('queries', (NV2080_CTRL_FB_FS_INFO_QUERY * 120)),
]
NV2080_CTRL_FB_GET_FS_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_FS_INFO_PARAMS
class struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS._fields_ = [
  ('histogram', (NvU32 * 5)),
]
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS = struct_NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS
class struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO(Struct): pass
struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO._fields_ = [
  ('pageNumber', NvU64),
  ('source', NvU8),
]
NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO = struct_NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO
class struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS._fields_ = [
  ('offlined', (NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO * 64)),
  ('validEntries', NvU32),
  ('baseIndex', NvU32),
  ('bMore', NvBool),
]
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS = struct_NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS
class struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO(Struct): pass
struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO._fields_ = [
  ('client', NvU32),
  ('flags', NvU32),
  ('beginAddr', NvU64),
  ('size', NvU64),
]
NV2080_CTRL_CMD_FB_ALLOCATION_INFO = struct_NV2080_CTRL_CMD_FB_ALLOCATION_INFO
class struct_NV2080_CTRL_CMD_FB_CLIENT_INFO(Struct): pass
struct_NV2080_CTRL_CMD_FB_CLIENT_INFO._fields_ = [
  ('handle', NvHandle),
  ('pid', NvU32),
  ('subProcessID', NvU32),
  ('subProcessName', (ctypes.c_char * 100)),
]
NV2080_CTRL_CMD_FB_CLIENT_INFO = struct_NV2080_CTRL_CMD_FB_CLIENT_INFO
class struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS._fields_ = [
  ('allocCount', NvU64),
  ('pAllocInfo', NvP64),
  ('clientCount', NvU64),
  ('pClientInfo', NvP64),
]
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS = struct_NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS
class struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS._fields_ = [
  ('bOnline', NvBool),
]
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS = struct_NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS
class struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS._fields_ = [
  ('numaNodeId', NvS32),
  ('numaMemAddr', NvU64),
  ('numaMemSize', NvU64),
  ('numaOfflineAddressesCount', NvU32),
  ('numaOfflineAddresses', (NvU64 * 64)),
]
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS
class struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS._fields_ = [
  ('maxSubmittedSemaphoreValueOffset', NvU64),
  ('monitoredFenceThresholdOffset', NvU64),
  ('size', NvU64),
  ('caps', NvU32),
]
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS = struct_NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS
class struct_NV2080_CTRL_CMD_FB_STATS_ENTRY(Struct): pass
struct_NV2080_CTRL_CMD_FB_STATS_ENTRY._fields_ = [
  ('totalSize', NvU64),
  ('rsvdSize', NvU64),
  ('osSize', NvU64),
  ('r1Size', NvU64),
  ('r2Size', NvU64),
  ('freeSize', NvU64),
]
NV2080_CTRL_CMD_FB_STATS_ENTRY = struct_NV2080_CTRL_CMD_FB_STATS_ENTRY
class struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS(Struct): pass
struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('invalidateAll', NvBool),
]
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS = struct_NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS
class struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO(Struct): pass
struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO._fields_ = [
  ('allocSize', NvU64),
  ('numBlocks', NvU32),
  ('rsvdSize', NvU64),
]
NV2080_CTRL_CMD_FB_STATS_OWNER_INFO = struct_NV2080_CTRL_CMD_FB_STATS_OWNER_INFO
class struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS._fields_ = [
  ('version', NvU64),
  ('fbSizeInfo', NV2080_CTRL_CMD_FB_STATS_ENTRY),
  ('fbBlockInfo', (NV2080_CTRL_CMD_FB_STATS_OWNER_INFO * 200)),
]
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS = struct_NV2080_CTRL_CMD_FB_STATS_GET_PARAMS
class struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS._fields_ = [
  ('bStaticBar1Enabled', NvBool),
  ('staticBar1StartOffset', NvU64),
  ('staticBar1Size', NvU64),
]
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS = struct_NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS._fields_ = [
  ('currentConfiguration', NvU32),
]
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS
class struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS._fields_ = [
  ('newConfiguration', NvU32),
]
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS = struct_NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS
class struct_NV2080_CTRL_FB_GET_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_GET_STATUS_PARAMS._fields_ = [
  ('fbStatus', NvU32),
]
NV2080_CTRL_FB_GET_STATUS_PARAMS = struct_NV2080_CTRL_FB_GET_STATUS_PARAMS
class struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS._fields_ = [
  ('isSupported', NvU32),
]
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS = struct_NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS
class struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS._fields_ = [
  ('currentStatus', NvU32),
]
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS = struct_NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS
class struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('base', NvU64),
  ('numEntries', NvU32),
]
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS = struct_NV2080_CTRL_CMD_SET_GPFIFO_PARAMS
class struct_NV2080_CTRL_FIFO_BIND_CHANNEL(Struct): pass
struct_NV2080_CTRL_FIFO_BIND_CHANNEL._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
]
NV2080_CTRL_FIFO_BIND_CHANNEL = struct_NV2080_CTRL_FIFO_BIND_CHANNEL
class struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS._fields_ = [
  ('bindChannelCount', NvU32),
  ('bindChannels', (NV2080_CTRL_FIFO_BIND_CHANNEL * 16)),
]
NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS = struct_NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS
class struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS._fields_ = [
  ('flags', NvU32),
]
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS = struct_NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS
class struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS._fields_ = [
  ('physChannelCount', NvU32),
  ('physChannelCountInUse', NvU32),
]
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS = struct_NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS
NV2080_CTRL_FIFO_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS._fields_ = [
  ('fifoInfoTblSize', NvU32),
  ('fifoInfoTbl', (NV2080_CTRL_FIFO_INFO * 256)),
  ('engineType', NvU32),
]
NV2080_CTRL_FIFO_GET_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_INFO_PARAMS
class struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS._fields_ = [
  ('hChannel', NvHandle),
]
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS = struct_NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS._fields_ = [
  ('bDisable', NvBool),
  ('numChannels', NvU32),
  ('bOnlyDisableScheduling', NvBool),
  ('bRewindGpPut', NvBool),
  ('pRunlistPreemptEvent', NvP64),
  ('hClientList', (NvHandle * 64)),
  ('hChannelList', (NvHandle * 64)),
]
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS
class struct_NV2080_CTRL_FIFO_MEM_INFO(Struct): pass
struct_NV2080_CTRL_FIFO_MEM_INFO._fields_ = [
  ('aperture', NvU32),
  ('base', NvU64),
  ('size', NvU64),
]
NV2080_CTRL_FIFO_MEM_INFO = struct_NV2080_CTRL_FIFO_MEM_INFO
class struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO(Struct): pass
struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO._fields_ = [
  ('inst', NV2080_CTRL_FIFO_MEM_INFO),
  ('ramfc', NV2080_CTRL_FIFO_MEM_INFO),
  ('methodBuf', (NV2080_CTRL_FIFO_MEM_INFO * 2)),
  ('methodBufCount', NvU32),
]
NV2080_CTRL_FIFO_CHANNEL_MEM_INFO = struct_NV2080_CTRL_FIFO_CHANNEL_MEM_INFO
class struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('chMemInfo', NV2080_CTRL_FIFO_CHANNEL_MEM_INFO),
]
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS
class struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS._fields_ = [
  ('aperture', NvU32),
  ('attribute', NvU32),
]
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS = struct_NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS(Struct): pass
class struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry(Struct): pass
NvS64 = ctypes.c_int64
struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry._fields_ = [
  ('timestampNs', NvU64),
  ('timeRunTotalNs', NvS64),
  ('timeRunNs', NvU32),
  ('swrlId', NvU32),
  ('targetTimeSlice', NvU32),
  ('cumulativePreemptionTime', NvU64),
  ('counters', (NvU64 * 8)),
]
struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('count', NvU32),
  ('entry', (struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_entry * 200)),
  ('schedPolicy', NvU32),
  ('arrEnabled', NvU32),
  ('arrAvgFactor', NvU32),
  ('targetTimesliceNs', NvU32),
]
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS
class struct_NV2080_CTRL_FIFO_DEVICE_ENTRY(Struct): pass
struct_NV2080_CTRL_FIFO_DEVICE_ENTRY._fields_ = [
  ('engineData', (NvU32 * 16)),
  ('pbdmaIds', (NvU32 * 2)),
  ('pbdmaFaultIds', (NvU32 * 2)),
  ('numPbdmas', NvU32),
  ('engineName', (ctypes.c_char * 16)),
]
NV2080_CTRL_FIFO_DEVICE_ENTRY = struct_NV2080_CTRL_FIFO_DEVICE_ENTRY
class struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [
  ('baseIndex', NvU32),
  ('numEntries', NvU32),
  ('bMore', NvBool),
  ('entries', (NV2080_CTRL_FIFO_DEVICE_ENTRY * 32)),
]
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS
class struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('vChid', NvU32),
  ('faultType', NvU32),
]
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS = struct_NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS
class struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS._fields_ = [
  ('flags', NvU32),
  ('schedPolicy', NvU32),
]
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS = struct_NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS
class struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('hUserdMemory', NvHandle),
  ('gpFifoEntries', NvU32),
  ('gpFifoOffset', NvU64),
  ('userdOffset', NvU64),
]
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS = struct_NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS
class struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS._fields_ = [
  ('bDisable', NvBool),
]
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS
class struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS._fields_ = [
  ('base', NvU64),
  ('size', NvU64),
  ('addressSpace', NvU32),
  ('cacheAttrib', NvU32),
]
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS = struct_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS
class struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS._fields_ = [
  ('runlistId', NvU32),
  ('bitMask', (NvU32 * 128)),
]
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS = struct_NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [
  ('numChannels', NvU32),
  ('hClientList', (NvHandle * 64)),
  ('hChannelList', (NvHandle * 64)),
  ('bEnableAfterKeyRotation', NvBool),
]
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS
class struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS._fields_ = [
  ('numChannels', NvU32),
  ('hChannelList', (NvHandle * 64)),
  ('bEnableAfterKeyRotation', NvBool),
]
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS = struct_NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('schedPolicy', NvU32),
  ('arrEnabled', NvU32),
  ('targetTimesliceNs', NvU32),
  ('arrAvgFactor', NvU32),
]
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS
class struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('schedPolicy', NvU32),
  ('enableArr', NvU32),
  ('timesliceTargetNs', NvU32),
  ('frequencyForARR', NvU32),
  ('avgFactorForARR', NvU32),
]
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS
class struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('supportedSchedulers', (NvU32 * 3)),
  ('bIsArrModeSupported', NvBool),
  ('maxTimesliceNs', NvU32),
  ('minTimesliceNs', NvU32),
  ('maxFrequencyForARR', NvU32),
  ('minFrequencyForARR', NvU32),
  ('maxAvgFactorForARR', NvU32),
  ('minAvgFactorForARR', NvU32),
]
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS = struct_NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS
class struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hChannelOrTsg', NvHandle),
  ('tsgId', NvU32),
  ('numChannels', NvU32),
  ('channelUniqueID', (NvU32 * 128)),
  ('vasUniqueID', (NvU32 * 128)),
  ('veid', (NvU32 * 128)),
]
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS = struct_NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS
class struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS._fields_ = [
  ('hClients', (NvHandle * 128)),
  ('hChannels', (NvHandle * 128)),
  ('numChannels', NvU32),
  ('channelUniqueIDs', (NvU32 * 128)),
]
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS = struct_NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS
class struct_NV2080_CTRL_FLA_RANGE_PARAMS(Struct): pass
struct_NV2080_CTRL_FLA_RANGE_PARAMS._fields_ = [
  ('base', NvU64),
  ('size', NvU64),
  ('mode', NvU32),
  ('hVASpace', NvHandle),
]
NV2080_CTRL_FLA_RANGE_PARAMS = struct_NV2080_CTRL_FLA_RANGE_PARAMS
enum_NV2080_CTRL_FLA_ADDRSPACE = CEnum(ctypes.c_uint32)
NV2080_CTRL_FLA_ADDRSPACE_SYSMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_SYSMEM', 0)
NV2080_CTRL_FLA_ADDRSPACE_FBMEM = enum_NV2080_CTRL_FLA_ADDRSPACE.define('NV2080_CTRL_FLA_ADDRSPACE_FBMEM', 1)

NV2080_CTRL_FLA_ADDRSPACE = enum_NV2080_CTRL_FLA_ADDRSPACE
enum_NV2080_CTRL_FLA_ACTION = CEnum(ctypes.c_uint32)
NV2080_CTRL_FLA_ACTION_BIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_BIND', 0)
NV2080_CTRL_FLA_ACTION_UNBIND = enum_NV2080_CTRL_FLA_ACTION.define('NV2080_CTRL_FLA_ACTION_UNBIND', 1)

NV2080_CTRL_FLA_ACTION = enum_NV2080_CTRL_FLA_ACTION
class struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS(Struct): pass
struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS._fields_ = [
  ('imbPhysAddr', NvU64),
  ('addrSpace', NV2080_CTRL_FLA_ADDRSPACE),
  ('flaAction', NV2080_CTRL_FLA_ACTION),
]
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS = struct_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS
class struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS(Struct): pass
struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS._fields_ = [
  ('base', NvU64),
  ('size', NvU64),
]
NV2080_CTRL_FLA_GET_RANGE_PARAMS = struct_NV2080_CTRL_FLA_GET_RANGE_PARAMS
class struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS._fields_ = [
  ('totalSize', NvU64),
  ('freeSize', NvU64),
]
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS = struct_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS
class struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS._fields_ = [
  ('flcnID', NvU32),
  ('heapSize', NvU32),
  ('heapFree', NvU32),
]
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS = struct_NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS
class struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS._fields_ = [
  ('engine', NvU32),
  ('engineArch', NvU32),
]
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS = struct_NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS
class struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER(Struct): pass
struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER._fields_ = [
  ('mask', (NvU8 * 36)),
]
NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER = struct_NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER
class struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS._fields_ = [
  ('engine', NvU32),
  ('pageSize', NvU32),
  ('offset', NvUPtr),
  ('size', NvU32),
  ('queueFeatureId', NvU8),
]
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS
class struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS._fields_ = [
  ('engine', NvU32),
  ('eventFilter', NV2080_CTRL_FLCN_USTREAMER_EVENT_FILTER),
  ('queueId', NvU8),
]
NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS = struct_NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [
  ('hUserClient', NvHandle),
  ('hChannel', NvHandle),
  ('alignment', NvU64),
  ('size', NvU64),
  ('bufferHandle', NvP64),
  ('pageCount', NvU64),
  ('physAddr', NvU64),
  ('aperture', NvU32),
  ('kind', NvU32),
  ('pageSize', NvU32),
  ('bIsContigous', NvBool),
  ('bDeviceDescendant', NvBool),
  ('uuid', (NvU8 * 16)),
]
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS
class struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('totalBufferSize', NvU64),
]
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS._fields_ = [
  ('gpioPin', NvU32),
  ('bInput', NvBool),
]
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS._fields_ = [
  ('gpioPin', NvU32),
  ('value', NvU32),
]
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS._fields_ = [
  ('gpioPin', NvU32),
  ('value', NvU32),
]
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS._fields_ = [
  ('function', NvU32),
  ('pin', NvU32),
]
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS = struct_NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS
NV2080_CTRL_GPU_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_GPU_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_INFO_PARAMS._fields_ = [
  ('gpuInfoListSize', NvU32),
  ('gpuInfoList', NvP64),
]
NV2080_CTRL_GPU_GET_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS._fields_ = [
  ('gpuInfoListSize', NvU32),
  ('gpuInfoList', (NV2080_CTRL_GPU_INFO * 65)),
]
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS(Struct): pass
class struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString(ctypes.Union): pass
struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString._fields_ = [
  ('ascii', (NvU8 * 64)),
  ('unicode', (NvU16 * 64)),
]
struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS._fields_ = [
  ('gpuNameStringFlags', NvU32),
  ('gpuNameString', struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_gpuNameString),
]
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS
class struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS._fields_ = [
  ('gpuShortNameString', (NvU8 * 64)),
]
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS = struct_NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS
class struct_NV2080_CTRL_GPU_SET_POWER_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_POWER_PARAMS._fields_ = [
  ('target', NvU32),
  ('newLevel', NvU32),
  ('oldLevel', NvU32),
]
NV2080_CTRL_GPU_SET_POWER_PARAMS = struct_NV2080_CTRL_GPU_SET_POWER_PARAMS
class struct_NV2080_CTRL_GPU_GET_SDM_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_SDM_PARAMS._fields_ = [
  ('subdeviceMask', NvU32),
]
NV2080_CTRL_GPU_GET_SDM_PARAMS = struct_NV2080_CTRL_GPU_GET_SDM_PARAMS
class struct_NV2080_CTRL_GPU_SET_SDM_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_SDM_PARAMS._fields_ = [
  ('subdeviceMask', NvU32),
]
NV2080_CTRL_GPU_SET_SDM_PARAMS = struct_NV2080_CTRL_GPU_SET_SDM_PARAMS
class struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS._fields_ = [
  ('type', NvU32),
]
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS
class struct_NV2080_CTRL_GPU_REG_OP(Struct): pass
struct_NV2080_CTRL_GPU_REG_OP._fields_ = [
  ('regOp', NvU8),
  ('regType', NvU8),
  ('regStatus', NvU8),
  ('regQuad', NvU8),
  ('regGroupMask', NvU32),
  ('regSubGroupMask', NvU32),
  ('regOffset', NvU32),
  ('regValueHi', NvU32),
  ('regValueLo', NvU32),
  ('regAndNMaskHi', NvU32),
  ('regAndNMaskLo', NvU32),
]
NV2080_CTRL_GPU_REG_OP = struct_NV2080_CTRL_GPU_REG_OP
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS(Struct): pass
NV2080_CTRL_GR_ROUTE_INFO = struct_NV0080_CTRL_GR_ROUTE_INFO
struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS._fields_ = [
  ('hClientTarget', NvHandle),
  ('hChannelTarget', NvHandle),
  ('bNonTransactional', NvU32),
  ('reserved00', (NvU32 * 2)),
  ('regOpCount', NvU32),
  ('regOps', NvP64),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS._fields_ = [
  ('engineCount', NvU32),
  ('engineList', NvP64),
]
NV2080_CTRL_GPU_GET_ENGINES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS._fields_ = [
  ('engineCount', NvU32),
  ('engineList', (NvU32 * 84)),
]
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('numClasses', NvU32),
  ('classList', NvP64),
]
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('mmuFaultId', NvU32),
  ('bSubcontextSupported', NvBool),
]
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS
class struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS._fields_ = [
  ('mode', NvU32),
]
NV2080_CTRL_GPU_QUERY_MODE_PARAMS = struct_NV2080_CTRL_GPU_QUERY_MODE_PARAMS
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(Struct): pass
struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY._fields_ = [
  ('gpuPhysAddr', NvU64),
  ('gpuVirtAddr', NvU64),
  ('size', NvU64),
  ('physAttr', NvU32),
  ('bufferId', NvU16),
  ('bInitialize', NvU8),
  ('bNonmapped', NvU8),
]
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY = struct_NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY
class struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('hClient', NvHandle),
  ('ChID', NvU32),
  ('hChanClient', NvHandle),
  ('hObject', NvHandle),
  ('hVirtMemory', NvHandle),
  ('virtAddress', NvU64),
  ('size', NvU64),
  ('entryCount', NvU32),
  ('promoteEntry', (NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY * 16)),
]
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS
PNV2080_CTRL_GPU_PROMOTE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS)
class struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('hClient', NvHandle),
  ('ChID', NvU32),
  ('hChanClient', NvHandle),
  ('hObject', NvHandle),
]
NV2080_CTRL_GPU_EVICT_CTX_PARAMS = struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS
PNV2080_CTRL_GPU_EVICT_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_EVICT_CTX_PARAMS)
class struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('hClient', NvHandle),
  ('ChID', NvU32),
  ('hChanClient', NvHandle),
  ('hObject', NvHandle),
  ('hVirtMemory', NvHandle),
  ('physAddress', NvU64),
  ('physAttr', NvU32),
  ('hDmaHandle', NvHandle),
  ('index', NvU32),
  ('size', NvU64),
]
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS
PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS)
class struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS._fields_ = [
  ('eccIntrStatus', NvU32),
]
NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS
class struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS._fields_ = [
  ('count', NvU64),
]
NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS
class struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS._fields_ = [
  ('enabled', NvBool),
  ('scrubComplete', NvBool),
  ('supported', NvBool),
  ('dbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS),
  ('dbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS),
  ('sbe', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS),
  ('sbeNonResettable', NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS),
]
NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS = struct_NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS
class struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS._fields_ = [
  ('units', (NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS * 36)),
  ('bFatalPoisonError', NvBool),
  ('uncorrectableError', NvU8),
  ('flags', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS._fields_ = [
  ('rules', NvU32),
  ('flags', NvU32),
]
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS
class struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS._fields_ = [
  ('rules', NvU32),
]
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS = struct_NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS
class struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS._fields_ = [
  ('currentConfiguration', NvU32),
  ('defaultConfiguration', NvU32),
]
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS
class struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS._fields_ = [
  ('newConfiguration', NvU32),
]
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS = struct_NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS
class struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS._fields_ = [
  ('statuses', NvU32),
  ('flags', NvU8),
]
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS = struct_NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS._fields_ = [
  ('gpcMask', NvU32),
]
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('tpcMask', NvU32),
]
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('zcullMask', NvU32),
]
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS._fields_ = [
  ('buildDate', NvU32),
  ('marketingName', (NvU8 * 24)),
  ('serialNumber', (NvU8 * 16)),
  ('memoryManufacturer', NvU8),
  ('memoryPartID', (NvU8 * 20)),
  ('memoryDateCode', (NvU8 * 6)),
  ('productPartNumber', (NvU8 * 20)),
  ('boardRevision', (NvU8 * 3)),
  ('boardType', NvU8),
  ('board699PartNumber', (NvU8 * 20)),
  ('board965PartNumber', (NvU8 * 20)),
]
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ID_PARAMS._fields_ = [
  ('gpuId', NvU32),
]
NV2080_CTRL_GPU_GET_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_PARAMS
class struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS._fields_ = [
  ('mode', NvU32),
]
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS
class struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS._fields_ = [
  ('currentMode', NvU32),
]
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS = struct_NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS._fields_ = [
  ('engineType', NvU32),
  ('partnershipClassId', NvU32),
  ('runqueue', NvU32),
  ('numPartners', NvU32),
  ('partnerList', (NvU32 * 32)),
]
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS
class struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS._fields_ = [
  ('index', NvU32),
  ('flags', NvU32),
  ('length', NvU32),
  ('data', (NvU8 * 256)),
]
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS._fields_ = [
  ('objectType', (ctypes.c_char * 3)),
  ('version', NvU8),
  ('subversion', NvU8),
]
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS
class struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS._fields_ = [
  ('isOptimusEnabled', NvBool),
]
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS = struct_NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS._fields_ = [
  ('targetEngine', NvU32),
  ('ipVersion', NvU32),
]
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS
class struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS._fields_ = [
  ('attribute', NvU32),
  ('bSupported', NvBool),
]
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS
class struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS._fields_ = [
  ('attribute', NvU32),
  ('value', NvU32),
]
NV2080_CTRL_CMD_GPU_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
NV2080_CTRL_GPU_GET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
NV2080_CTRL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_CMD_GPU_ILLUM_PARAMS
class struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS._fields_ = [
  ('version', (NvU8 * 16)),
]
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS
class struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS._fields_ = [
  ('fwVersion', NvU32),
  ('oemVersion', NvU8),
  ('siliconRevision', NvU8),
  ('hwbcResourceType', NvU8),
]
NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS
class struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS._fields_ = [
  ('bridgeCount', NvU8),
  ('hPhysicalBridges', (NvHandle * 100)),
  ('bridgeList', (NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS * 100)),
]
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS
class struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS._fields_ = [
  ('bus', NvU8),
  ('device', NvU8),
  ('func', NvU8),
  ('oemVersion', NvU8),
  ('siliconRevision', NvU8),
  ('hwbcResourceType', NvU8),
  ('domain', NvU32),
  ('fwVersion', NvU32),
]
NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS = struct_NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS
class struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS._fields_ = [
  ('bridgeCount', NvU8),
  ('physicalBridgeIds', (NvU32 * 100)),
  ('bridgeList', (NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS * 100)),
]
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS = struct_NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS
class struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS._fields_ = [
  ('scrubberStatus', NvU32),
  ('remainingTimeMs', NvU32),
  ('scrubStartAddr', NvU64),
  ('scrubEndAddr', NvU64),
]
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS = struct_NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS._fields_ = [
  ('minStartAddr', NvU64),
  ('maxEndAddr', NvU64),
]
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS
class struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('numPesInGpc', NvU32),
  ('activePesMask', NvU32),
  ('maxTpcPerGpcCount', NvU32),
  ('tpcToPesMap', (NvU32 * 10)),
]
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PES_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS._fields_ = [
  ('oemInfo', (NvU8 * 504)),
]
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS
enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_VPR_CAPS', 0)
NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_VPR_INFO_QUERY_CUR_VPR_RANGE', 1)

NV2080_CTRL_VPR_INFO_QUERY_TYPE = enum_NV2080_CTRL_VPR_INFO_QUERY_TYPE
class struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS._fields_ = [
  ('queryType', NV2080_CTRL_VPR_INFO_QUERY_TYPE),
  ('bIsVprEnabled', NvBool),
  ('vprStartAddressInBytes', NvU64),
  ('vprEndAddressInBytes', NvU64),
]
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS
enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264', 0)
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC', 1)
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE.define('NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1', 2)

NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE = enum_NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE
class struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS._fields_ = [
  ('queryType', NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE),
  ('encoderCapacity', NvU32),
]
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS._fields_ = [
  ('encoderSessionCount', NvU32),
  ('averageEncodeFps', NvU32),
  ('averageEncodeLatency', NvU32),
]
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS
class struct_NV2080_CTRL_NVENC_SW_SESSION_INFO(Struct): pass
struct_NV2080_CTRL_NVENC_SW_SESSION_INFO._fields_ = [
  ('processId', NvU32),
  ('subProcessId', NvU32),
  ('sessionId', NvU32),
  ('codecType', NvU32),
  ('hResolution', NvU32),
  ('vResolution', NvU32),
  ('averageEncodeFps', NvU32),
  ('averageEncodeLatency', NvU32),
]
NV2080_CTRL_NVENC_SW_SESSION_INFO = struct_NV2080_CTRL_NVENC_SW_SESSION_INFO
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS._fields_ = [
  ('sessionInfoTblEntry', NvU32),
  ('sessionInfoTbl', NvP64),
]
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS
class struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS._fields_ = [
  ('fabricBaseAddr', NvU64),
]
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS
class struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS._fields_ = [
  ('handle', NvU32),
]
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS = struct_NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS
class struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS._fields_ = [
  ('statusMask', NvU32),
  ('xusbData', NvU32),
  ('ppcData', NvU32),
]
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS = struct_NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_PARTITION_SPAN(Struct): pass
struct_NV2080_CTRL_GPU_PARTITION_SPAN._fields_ = [
  ('lo', NvU64),
  ('hi', NvU64),
]
NV2080_CTRL_GPU_PARTITION_SPAN = struct_NV2080_CTRL_GPU_PARTITION_SPAN
class struct_NV2080_CTRL_EXEC_PARTITION_SPAN(Struct): pass
struct_NV2080_CTRL_EXEC_PARTITION_SPAN._fields_ = [
  ('lo', NvU64),
  ('hi', NvU64),
]
NV2080_CTRL_EXEC_PARTITION_SPAN = struct_NV2080_CTRL_EXEC_PARTITION_SPAN
class struct_NV2080_CTRL_GPU_SET_PARTITION_INFO(Struct): pass
struct_NV2080_CTRL_GPU_SET_PARTITION_INFO._fields_ = [
  ('swizzId', NvU32),
  ('uuid', (NvU8 * 16)),
  ('partitionFlag', NvU32),
  ('bValid', NvBool),
  ('placement', NV2080_CTRL_GPU_PARTITION_SPAN),
]
NV2080_CTRL_GPU_SET_PARTITION_INFO = struct_NV2080_CTRL_GPU_SET_PARTITION_INFO
class struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS._fields_ = [
  ('partitionCount', NvU32),
  ('partitionInfo', (NV2080_CTRL_GPU_SET_PARTITION_INFO * 8)),
]
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
class struct_NV2080_CTRL_GPU_GET_PARTITION_INFO(Struct): pass
struct_NV2080_CTRL_GPU_GET_PARTITION_INFO._fields_ = [
  ('swizzId', NvU32),
  ('partitionFlag', NvU32),
  ('grEngCount', NvU32),
  ('veidCount', NvU32),
  ('smCount', NvU32),
  ('ceCount', NvU32),
  ('nvEncCount', NvU32),
  ('nvDecCount', NvU32),
  ('nvJpgCount', NvU32),
  ('nvOfaCount', NvU32),
  ('gpcCount', NvU32),
  ('virtualGpcCount', NvU32),
  ('gfxGpcCount', NvU32),
  ('gpcsPerGr', (NvU32 * 8)),
  ('virtualGpcsPerGr', (NvU32 * 8)),
  ('gfxGpcPerGr', (NvU32 * 8)),
  ('veidsPerGr', (NvU32 * 8)),
  ('memSize', NvU64),
  ('span', NV2080_CTRL_GPU_PARTITION_SPAN),
  ('bValid', NvBool),
  ('bPartitionError', NvBool),
  ('validCTSIdMask', NvU64),
  ('validGfxCTSIdMask', NvU64),
]
NV2080_CTRL_GPU_GET_PARTITION_INFO = struct_NV2080_CTRL_GPU_GET_PARTITION_INFO
class struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS._fields_ = [
  ('queryPartitionInfo', (NV2080_CTRL_GPU_GET_PARTITION_INFO * 8)),
  ('validPartitionCount', NvU32),
  ('bGetAllPartitionInfo', NvBool),
]
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
class struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('gpcCountPerSmcEng', (NvU32 * 8)),
  ('updateSmcEngMask', NvU32),
  ('bUseAllGPCs', NvBool),
]
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
class struct_NV2080_CTRL_GPU_FAULT_PACKET(Struct): pass
struct_NV2080_CTRL_GPU_FAULT_PACKET._fields_ = [
  ('data', (NvU8 * 32)),
]
NV2080_CTRL_GPU_FAULT_PACKET = struct_NV2080_CTRL_GPU_FAULT_PACKET
class struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS._fields_ = [
  ('faultPacket', NV2080_CTRL_GPU_FAULT_PACKET),
]
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS = struct_NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS._fields_ = [
  ('engineList', (NvU32 * 84)),
  ('runlistPriBase', (NvU32 * 84)),
  ('runlistId', (NvU32 * 84)),
]
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS
class struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS._fields_ = [
  ('engineList', (NvU32 * 84)),
  ('hwEngineID', (NvU32 * 84)),
]
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS = struct_NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS._fields_ = [
  ('sessionCount', NvU32),
  ('averageFPS', NvU32),
  ('averageLatency', NvU32),
]
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS
class struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO(Struct): pass
struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO._fields_ = [
  ('processId', NvU32),
  ('subProcessId', NvU32),
  ('vgpuInstanceId', NvU32),
  ('sessionId', NvU32),
  ('sessionType', NvU32),
  ('displayOrdinal', NvU32),
  ('sessionFlags', NvU32),
  ('hMaxResolution', NvU32),
  ('vMaxResolution', NvU32),
  ('hResolution', NvU32),
  ('vResolution', NvU32),
  ('averageFPS', NvU32),
  ('averageLatency', NvU32),
]
NV2080_CTRL_NVFBC_SW_SESSION_INFO = struct_NV2080_CTRL_NVFBC_SW_SESSION_INFO
class struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS._fields_ = [
  ('sessionInfoCount', NvU32),
  ('sessionInfoTbl', (NV2080_CTRL_NVFBC_SW_SESSION_INFO * 256)),
]
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS._fields_ = [
  ('firstAsyncCEIdx', NvU32),
]
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS = struct_NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS
class struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS._fields_ = [
  ('vmmuSegmentSize', NvU64),
]
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS
class struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS._fields_ = [
  ('partitionFlag', NvU32),
  ('partitionCount', NvU32),
  ('availableSpans', (NV2080_CTRL_GPU_PARTITION_SPAN * 8)),
  ('availableSpansCount', NvU32),
  ('totalPartitionCount', NvU32),
  ('totalSpans', (NV2080_CTRL_GPU_PARTITION_SPAN * 8)),
  ('totalSpansCount', NvU32),
  ('bStaticInfo', NvBool),
]
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS._fields_ = [
  ('partitioningMode', NvU32),
]
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO(Struct): pass
struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO._fields_ = [
  ('partitionFlag', NvU32),
  ('grCount', NvU32),
  ('gfxGrCount', NvU32),
  ('gpcCount', NvU32),
  ('virtualGpcCount', NvU32),
  ('gfxGpcCount', NvU32),
  ('veidCount', NvU32),
  ('smCount', NvU32),
  ('ceCount', NvU32),
  ('nvEncCount', NvU32),
  ('nvDecCount', NvU32),
  ('nvJpgCount', NvU32),
  ('nvOfaCount', NvU32),
  ('memorySize', NvU64),
]
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO
class struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS._fields_ = [
  ('descCount', NvU32),
  ('partitionDescs', (NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO * 40)),
]
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS = struct_NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS
class struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS._fields_ = [
  ('maxSupportedPageSize', NvU64),
]
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS = struct_NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS
class struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('count', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS = struct_NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS
class struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS._fields_ = [
  ('swizzId', (NvU32 * 9)),
  ('partitionCount', NvU32),
]
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS = struct_NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS
class struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS._fields_ = [
  ('idType', NvU32),
  ('id', NvU32),
  ('pidTblCount', NvU32),
  ('pidTbl', (NvU32 * 950)),
]
NV2080_CTRL_GPU_GET_PIDS_PARAMS = struct_NV2080_CTRL_GPU_GET_PIDS_PARAMS
class struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO(Struct): pass
struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO._fields_ = [
  ('computeInstanceId', NvU32),
  ('gpuInstanceId', NvU32),
]
NV2080_CTRL_SMC_SUBSCRIPTION_INFO = struct_NV2080_CTRL_SMC_SUBSCRIPTION_INFO
class struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA(Struct): pass
struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA._fields_ = [
  ('memPrivate', NvU64),
  ('memSharedOwned', NvU64),
  ('memSharedDuped', NvU64),
  ('protectedMemPrivate', NvU64),
  ('protectedMemSharedOwned', NvU64),
  ('protectedMemSharedDuped', NvU64),
]
NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA = struct_NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA
class union_NV2080_CTRL_GPU_PID_INFO_DATA(ctypes.Union): pass
union_NV2080_CTRL_GPU_PID_INFO_DATA._fields_ = [
  ('vidMemUsage', NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA),
]
NV2080_CTRL_GPU_PID_INFO_DATA = union_NV2080_CTRL_GPU_PID_INFO_DATA
class struct_NV2080_CTRL_GPU_PID_INFO(Struct): pass
struct_NV2080_CTRL_GPU_PID_INFO._fields_ = [
  ('pid', NvU32),
  ('index', NvU32),
  ('result', NvU32),
  ('data', NV2080_CTRL_GPU_PID_INFO_DATA),
  ('smcSubscription', NV2080_CTRL_SMC_SUBSCRIPTION_INFO),
]
NV2080_CTRL_GPU_PID_INFO = struct_NV2080_CTRL_GPU_PID_INFO
class struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS._fields_ = [
  ('pidInfoListCount', NvU32),
  ('pidInfoList', (NV2080_CTRL_GPU_PID_INFO * 200)),
]
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_PID_INFO_PARAMS
class struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS._fields_ = [
  ('faultType', NvU32),
]
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS = struct_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS
enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_DEFAULT', 0)
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_SHORT', 1)
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MEDIUM', 2)
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_LONG', 3)
NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE.define('NV2080_CTRL_CMD_GPU_COMPUTE_TIMESLICE_MAX', 4)

NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE = enum_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG(Struct): pass
class struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data(ctypes.Union): pass
struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data._fields_ = [
  ('timeslice', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE),
]
struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG._fields_ = [
  ('type', NvU32),
  ('data', struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_data),
]
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG = struct_NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG
class struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS._fields_ = [
  ('config', NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG),
]
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS
class struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS._fields_ = [
  ('numConfigs', NvU32),
  ('configList', (NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG * 32)),
]
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS
class struct_NV2080_CTRL_GPU_GET_GFID_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_GFID_PARAMS._fields_ = [
  ('domain', NvU32),
  ('bus', NvU8),
  ('device', NvU8),
  ('func', NvU8),
  ('gfid', NvU32),
  ('gfidMask', NvU32),
]
NV2080_CTRL_GPU_GET_GFID_PARAMS = struct_NV2080_CTRL_GPU_GET_GFID_PARAMS
class struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('bEnable', NvBool),
  ('fabricPartitionId', NvU32),
]
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS = struct_NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS
class struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS._fields_ = [
  ('addressStart', NvU64),
  ('addressLength', NvU64),
  ('protection', NvU32),
]
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS = struct_NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS
class struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS._fields_ = [
  ('egmGpaFabricBaseAddr', NvU64),
]
NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS = struct_NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS
class struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS._fields_ = [
  ('engineCount', NvU32),
  ('engineList', (NvU32 * 200)),
  ('engineStateLoadTime', (NvU64 * 200)),
  ('engineIsInit', (NvBool * 200)),
]
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS = struct_NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS
class struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS._fields_ = [
  ('engineCount', NvU32),
  ('engineID', (NvU32 * 200)),
  ('engineName', ((ctypes.c_char * 100) * 200)),
]
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS = struct_NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS
class struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS._fields_ = [
  ('hClientTarget', NvHandle),
  ('hChannelTarget', NvHandle),
  ('bNonTransactional', NvU32),
  ('reserved00', (NvU32 * 2)),
  ('regOpCount', NvU32),
  ('regOps', (NV2080_CTRL_GPU_REG_OP * 100)),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS = struct_NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS
class struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO(Struct): pass
struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO._fields_ = [
  ('gpuId', NvU32),
  ('gpuUuid', (NvU8 * 16)),
  ('p2pCaps', NvU32),
  ('p2pOptimalReadCEs', NvU32),
  ('p2pOptimalWriteCEs', NvU32),
  ('p2pCapsStatus', (NvU8 * 9)),
  ('busPeerId', NvU32),
  ('busEgmPeerId', NvU32),
]
NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO = struct_NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO
class struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS._fields_ = [
  ('bAllCaps', NvBool),
  ('bUseUuid', NvBool),
  ('peerGpuCount', NvU32),
  ('peerGpuCaps', (NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO * 32)),
]
NV2080_CTRL_GET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_GET_P2P_CAPS_PARAMS
class struct_NV2080_CTRL_GPU_COMPUTE_PROFILE(Struct): pass
struct_NV2080_CTRL_GPU_COMPUTE_PROFILE._fields_ = [
  ('computeSize', NvU8),
  ('gfxGpcCount', NvU32),
  ('gpcCount', NvU32),
  ('veidCount', NvU32),
  ('smCount', NvU32),
]
NV2080_CTRL_GPU_COMPUTE_PROFILE = struct_NV2080_CTRL_GPU_COMPUTE_PROFILE
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS._fields_ = [
  ('partitionFlag', NvU32),
  ('profileCount', NvU32),
  ('profiles', (NV2080_CTRL_GPU_COMPUTE_PROFILE * 8)),
]
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
class struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [
  ('state', NvU8),
  ('status', NV_STATUS),
  ('clusterUuid', (NvU8 * 16)),
  ('fabricPartitionId', NvU16),
  ('fabricCaps', NvU64),
  ('fabricCliqueId', NvU32),
  ('fabricHealthMask', NvU32),
]
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
class struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS._fields_ = [
  ('pciDevId', NvU32),
  ('chipSku', (NvU8 * 4)),
  ('chipMajor', NvU32),
  ('chipMinor', NvU32),
]
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS = struct_NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
class struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS._fields_ = [
  ('swizzId', NvU32),
]
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS = struct_NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS
class struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS._fields_ = [
  ('hClientTarget', NvHandle),
  ('hChannelTarget', NvHandle),
  ('bNonTransactional', NvU32),
  ('regOpCount', NvU32),
  ('smIds', (NvU32 * 50)),
  ('regOps', (NV2080_CTRL_GPU_REG_OP * 50)),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS = struct_NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS
class struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS._fields_ = [
  ('bResetRequired', NvBool),
]
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS._fields_ = [
  ('bDrainRecommended', NvBool),
]
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS
class struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS._fields_ = [
  ('sessionInfoTblEntry', NvU32),
  ('sessionInfoTbl', (NV2080_CTRL_NVENC_SW_SESSION_INFO * 512)),
]
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS = struct_NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS
class struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO(Struct): pass
struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO._fields_ = [
  ('engDesc', NvU32),
  ('ctxAttr', NvU32),
  ('ctxBufferSize', NvU32),
  ('addrSpaceList', NvU32),
  ('registerBase', NvU32),
]
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO = struct_NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO
class struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS._fields_ = [
  ('numConstructedFalcons', NvU32),
  ('constructedFalconsTable', (NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO * 64)),
]
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS = struct_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
class struct_NV2080_VF_MSIX_CAPS(Struct): pass
struct_NV2080_VF_MSIX_CAPS._fields_ = [
  ('msix_header', NvU32),
  ('msix_table', NvU32),
  ('msix_pba', NvU32),
]
NV2080_VF_MSIX_CAPS = struct_NV2080_VF_MSIX_CAPS
class struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('vfMsixCap', NV2080_VF_MSIX_CAPS),
]
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS = struct_NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS
enum_NV2080_CTRL_GPU_RECOVERY_ACTION = CEnum(ctypes.c_uint32)
NV2080_CTRL_GPU_RECOVERY_ACTION_NONE = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NONE', 0)
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET', 1)
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT', 2)
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P', 3)
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = enum_NV2080_CTRL_GPU_RECOVERY_ACTION.define('NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET', 4)

NV2080_CTRL_GPU_RECOVERY_ACTION = enum_NV2080_CTRL_GPU_RECOVERY_ACTION
class struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS._fields_ = [
  ('action', NV2080_CTRL_GPU_RECOVERY_ACTION),
]
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS = struct_NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS
class struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS._fields_ = [
  ('bFipsEnabled', NvBool),
]
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS = struct_NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS
enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = CEnum(ctypes.c_uint32)
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID', 0)
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC', 1)
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE.define('NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC', 2)

NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE = enum_NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE
class struct_NV2080_RAFTS_FLOORSWEEP_INFO(Struct): pass
struct_NV2080_RAFTS_FLOORSWEEP_INFO._fields_ = [
  ('unitType', NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE),
  ('parentId', NvU32),
  ('mask', NvU32),
]
NV2080_RAFTS_FLOORSWEEP_INFO = struct_NV2080_RAFTS_FLOORSWEEP_INFO
class struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS._fields_ = [
  ('tpcCountMatrix', ((NvU8 * 12) * 2)),
  ('bValid', NvBool),
  ('floorSweepConfig', (NV2080_RAFTS_FLOORSWEEP_INFO * 26)),
  ('gfxGpcCount', NvU8),
  ('gfxTpcPerGpcCount', NvU8),
  ('maxUgpuTpcDiff', NvU8),
]
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS
class struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS._fields_ = [
  ('partitionFlag', NvU32),
  ('computeSize', NvU32),
  ('totalProfileCount', NvU32),
  ('totalSpans', (NV2080_CTRL_EXEC_PARTITION_SPAN * 8)),
  ('totalSpansCount', NvU32),
]
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS = struct_NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
class struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [
  ('gpc', NvU32),
  ('tpcReconfigMask', NvU32),
]
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS
class struct_NV2080_CTRL_GPUMON_SAMPLE(Struct): pass
struct_NV2080_CTRL_GPUMON_SAMPLE._fields_ = [
  ('timeStamp', NvU64),
]
NV2080_CTRL_GPUMON_SAMPLE = struct_NV2080_CTRL_GPUMON_SAMPLE
class struct_NV2080_CTRL_GPUMON_SAMPLES(Struct): pass
struct_NV2080_CTRL_GPUMON_SAMPLES._fields_ = [
  ('type', NvU8),
  ('bufSize', NvU32),
  ('count', NvU32),
  ('tracker', NvU32),
  ('pSamples', NvP64),
]
NV2080_CTRL_GPUMON_SAMPLES = struct_NV2080_CTRL_GPUMON_SAMPLES
NV2080_CTRL_GR_INFO = struct_NVXXXX_CTRL_XXX_INFO
class struct_NV2080_CTRL_GR_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_INFO_PARAMS._fields_ = [
  ('grInfoListSize', NvU32),
  ('grInfoList', NvP64),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_INFO_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('hShareClient', NvHandle),
  ('hShareChannel', NvHandle),
  ('zcullMode', NvU32),
]
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS
class struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS._fields_ = [
  ('widthAlignPixels', NvU32),
  ('heightAlignPixels', NvU32),
  ('pixelSquaresByAliquots', NvU32),
  ('aliquotTotal', NvU32),
  ('zcullRegionByteMultiplier', NvU32),
  ('zcullRegionHeaderSize', NvU32),
  ('zcullSubregionHeaderSize', NvU32),
  ('subregionCount', NvU32),
  ('subregionWidthAlignPixels', NvU32),
  ('subregionHeightAlignPixels', NvU32),
]
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('pmMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('vMemPtr', NvU64),
  ('zcullMode', NvU32),
]
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('vMemPtr', NvU64),
  ('pmMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('vMemPtr', NvU64),
]
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
class struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS._fields_ = [
  ('mapValueCount', NvU32),
  ('mapValues', (NvU8 * 128)),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
class struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('smpcMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS(Struct): pass
class struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId(Struct): pass
struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId._fields_ = [
  ('gpcId', NvU32),
  ('tpcId', NvU32),
]
struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS._fields_ = [
  ('smId', (struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_smId * 240)),
  ('smCount', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS = struct_NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS
class struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS._fields_ = [
  ('flags', NvU32),
  ('hChannel', NvHandle),
  ('gfxpPreemptMode', NvU32),
  ('cilpPreemptMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS = struct_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS
enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN', 0)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL', 1)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL', 2)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB', 3)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV', 4)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL', 5)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL', 6)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU', 7)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SETUP', 8)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS.define('NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END', 9)

NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS = enum_NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS
class struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS._fields_ = [
  ('flags', NvU32),
  ('hClient', NvHandle),
  ('hChannel', NvHandle),
  ('vMemPtrs', (NvU64 * 9)),
  ('gfxpPreemptMode', NvU32),
  ('cilpPreemptMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS
class struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('samplingMode', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS = struct_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS
class struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS._fields_ = [
  ('ropUnitCount', NvU32),
  ('ropOperationsFactor', NvU32),
  ('ropOperationsCount', NvU32),
]
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_ROP_INFO_PARAMS
class struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('flags', NvU32),
  ('saveCnt', NvU32),
  ('restoreCnt', NvU32),
  ('wfiSaveCnt', NvU32),
  ('ctaSaveCnt', NvU32),
  ('cilpSaveCnt', NvU32),
  ('gfxpSaveCnt', NvU32),
]
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('totalBufferSize', NvU64),
]
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS
class struct_NV2080_CTRL_GR_CTX_BUFFER_INFO(Struct): pass
struct_NV2080_CTRL_GR_CTX_BUFFER_INFO._fields_ = [
  ('alignment', NvU64),
  ('size', NvU64),
  ('bufferHandle', NvP64),
  ('pageCount', NvU64),
  ('physAddr', NvU64),
  ('bufferType', NvU32),
  ('aperture', NvU32),
  ('kind', NvU32),
  ('pageSize', NvU32),
  ('bIsContigous', NvBool),
  ('bGlobalBuffer', NvBool),
  ('bLocalBuffer', NvBool),
  ('bDeviceDescendant', NvBool),
  ('uuid', (NvU8 * 16)),
]
NV2080_CTRL_GR_CTX_BUFFER_INFO = struct_NV2080_CTRL_GR_CTX_BUFFER_INFO
PNV2080_CTRL_GR_CTX_BUFFER_INFO = ctypes.POINTER(struct_NV2080_CTRL_GR_CTX_BUFFER_INFO)
class struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS._fields_ = [
  ('hUserClient', NvHandle),
  ('hChannel', NvHandle),
  ('bufferCount', NvU32),
  ('ctxBufferInfo', (NV2080_CTRL_GR_CTX_BUFFER_INFO * 64)),
]
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS(Struct): pass
class struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId(Struct): pass
struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId._fields_ = [
  ('gpcId', NvU16),
  ('localTpcId', NvU16),
  ('localSmId', NvU16),
  ('globalTpcId', NvU16),
  ('virtualGpcId', NvU16),
  ('migratableTpcId', NvU16),
]
struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [
  ('globalSmId', (struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_globalSmId * 512)),
  ('numSm', NvU16),
  ('numTpc', NvU16),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS
class struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS._fields_ = [
  ('chID', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS = struct_NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC(Struct): pass
struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC._fields_ = [
  ('errorCounter', NvU64),
  ('errorTimestamp', NvU64),
  ('warningCounter', NvU64),
  ('warningTimestamp', NvU64),
]
NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC(Struct): pass
struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC._fields_ = [
  ('tpc', (NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC * 10)),
]
NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC = struct_NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC
class struct_NV2080_CTRL_GR_VAT_ALARM_DATA(Struct): pass
struct_NV2080_CTRL_GR_VAT_ALARM_DATA._fields_ = [
  ('gpc', (NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC * 10)),
]
NV2080_CTRL_GR_VAT_ALARM_DATA = struct_NV2080_CTRL_GR_VAT_ALARM_DATA
class struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS._fields_ = [
  ('smVatAlarm', NV2080_CTRL_GR_VAT_ALARM_DATA),
  ('maxGpcCount', NvU32),
  ('maxTpcPerGpcCount', NvU32),
]
NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS
PNV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS = ctypes.POINTER(struct_NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS)
class struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS._fields_ = [
  ('attribBufferSize', NvU32),
]
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS = struct_NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS
class struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS._fields_ = [
  ('maxSlots', NvU32),
  ('slotStride', NvU32),
  ('ctrlStructSize', NvU64),
  ('ctrlStructAlign', NvU64),
  ('poolSize', NvU64),
  ('poolAlign', NvU64),
]
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS
class struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS._fields_ = [
  ('maxSlots', NvU32),
  ('hMemory', NvHandle),
  ('offset', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
class struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS._fields_ = [
  ('numSlots', NvU32),
  ('slots', (NvU32 * 64)),
  ('hMemory', NvHandle),
  ('offset', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
class struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS._fields_ = [
  ('numSlots', NvU32),
  ('slots', (NvU32 * 64)),
  ('bRemoveSpecificSlots', NvBool),
  ('hMemory', NvHandle),
  ('offset', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS = struct_NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS = struct_NV0080_CTRL_GR_GET_CAPS_V2_PARAMS
NV2080_CTRL_GR_GET_INFO_V2_PARAMS = struct_NV0080_CTRL_GR_GET_INFO_V2_PARAMS
class struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('gpcMask', NvU32),
]
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_GPC_MASK_PARAMS
class struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('gpcId', NvU32),
  ('tpcMask', NvU32),
]
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_MASK_PARAMS
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS = struct_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS
class struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('engineId', NvU32),
  ('alignment', NvU32),
  ('size', NvU32),
  ('bInfoPopulated', NvBool),
]
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS = struct_NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS
class struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('imla0', NvU8),
  ('fmla16', NvU8),
  ('dp', NvU8),
  ('fmla32', NvU8),
  ('ffma', NvU8),
  ('imla1', NvU8),
  ('imla2', NvU8),
  ('imla3', NvU8),
  ('imla4', NvU8),
]
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = CEnum(ctypes.c_uint32)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_FULL', 0)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_SIMPLE', 1)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_COMPAT', 2)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD.define('NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD_CUSTOM', 3)

NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS._fields_ = [
  ('hEventBuffer', NvHandle),
  ('recordSize', NvU32),
  ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD),
  ('eventFilter', NvU32),
  ('bAllUsers', NvBool),
]
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS
class struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS._fields_ = [
  ('physSyspipeId', NvU32),
  ('gpcMask', NvU32),
]
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS
class struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('gpcId', NvU32),
  ('ppcMask', NvU32),
]
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_PPC_MASK_PARAMS
class struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('numTpcs', NvU32),
]
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS = struct_NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS
class struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('zcullMode', NvU32),
  ('pmMode', NvU32),
  ('smpcMode', NvU32),
  ('cilpPreemptMode', NvU32),
  ('gfxpPreemptMode', NvU32),
]
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS = struct_NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS
class struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('zcullMask', NvU32),
]
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS
enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = CEnum(ctypes.c_uint32)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE', 0)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_GPU_TOO_OLD', 1)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED_GPU', 2)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED', 3)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN', 4)
NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE.define('NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY', 5)

NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE = enum_NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE
class struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS._fields_ = [
  ('hEventBuffer', NvHandle),
  ('recordSize', NvU32),
  ('levelOfDetail', NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD),
  ('eventFilter', NvU32),
  ('bAllUsers', NvBool),
  ('reasonCode', NvU32),
]
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS = struct_NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS
class struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('physGfxGpcMask', NvU32),
  ('numGfxTpc', NvU32),
]
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS = struct_NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS
class struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS._fields_ = [
  ('gpc', NvU32),
  ('tpcReconfigMask', NvU32),
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
]
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS = struct_NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS._fields_ = [
  ('gpcCount', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('chipletGpcMap', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('tpcMask', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('ppcMask', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('gpcId', NvU32),
  ('chipletGpcMap', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS._fields_ = [
  ('gpcId', NvU32),
  ('ropMask', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS._fields_ = [
  ('chipletSyspipeMask', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS._fields_ = [
  ('swizzId', NvU16),
  ('physSyspipeIdCount', NvU16),
  ('physSyspipeId', (NvU8 * 8)),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('grIdx', NvU32),
  ('gpcEnMask', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS._fields_ = [
  ('syspipeId', NvU32),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS(Struct): pass
class struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData(ctypes.Union): pass
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData._fields_ = [
  ('gpcCountData', NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS),
  ('chipletGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS),
  ('tpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS),
  ('ppcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS),
  ('partitionGpcMapData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS),
  ('syspipeMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS),
  ('partitionChipletSyspipeData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS),
  ('dmGpcMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS),
  ('partitionSyspipeIdData', NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS),
  ('ropMaskData', NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS),
]
struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS._fields_ = [
  ('queryType', NvU16),
  ('reserved', (NvU8 * 2)),
  ('status', NvU32),
  ('queryData', struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_queryData),
]
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS = struct_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS
class struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS._fields_ = [
  ('numQueries', NvU16),
  ('reserved', (NvU8 * 6)),
  ('queries', (NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS * 96)),
]
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS = struct_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS
class struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS(Struct): pass
struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS._fields_ = [
  ('gspFeatures', NvU32),
  ('bValid', NvBool),
  ('bDefaultGspRmGpu', NvBool),
  ('firmwareVersion', (NvU8 * 64)),
]
NV2080_CTRL_GSP_GET_FEATURES_PARAMS = struct_NV2080_CTRL_GSP_GET_FEATURES_PARAMS
class struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT(Struct): pass
struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT._fields_ = [
  ('allocatedSize', NvU64),
  ('usableSize', NvU64),
  ('memTrackOverhead', NvU64),
  ('allocationCount', NvU32),
]
NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT = struct_NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
class struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('managedSize', NvU64),
  ('largestFreeChunkSize', NvU64),
  ('current', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT),
  ('peak', NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT),
]
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS = struct_NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS
class struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS._fields_ = [
  ('allocatedSize', NvU64),
  ('peakAllocatedSize', NvU64),
  ('managedSize', NvU64),
  ('allocationCount', NvU32),
  ('peakAllocationCount', NvU32),
  ('largestFreeChunkSize', NvU64),
]
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS
class struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS(Struct): pass
struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS._fields_ = [
  ('allocations', NvU32),
  ('peakAllocations', NvU32),
  ('objectSize', NvU64),
]
NV2080_CTRL_GSP_LIBOS_POOL_STATS = struct_NV2080_CTRL_GSP_LIBOS_POOL_STATS
class struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS._fields_ = [
  ('poolStats', (NV2080_CTRL_GSP_LIBOS_POOL_STATS * 64)),
  ('totalHeapSize', NvU64),
  ('poolCount', NvU8),
]
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS = struct_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS
class struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS._fields_ = [
  ('hshubNcisocMask', NvU32),
  ('hshubNvlMask', NvU32),
]
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS
class struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS._fields_ = [
  ('ecMode', NvU32),
  ('status', NvU32),
]
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS = struct_NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS
class struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS._fields_ = [
  ('version', NvU32),
  ('port', NvU32),
  ('flags', NvU32),
  ('inputCount', NvU32),
  ('inputBuffer', (NvU8 * 256)),
  ('outputCount', NvU32),
  ('outputBuffer', (NvU8 * 256)),
]
NV2080_CTRL_I2C_READ_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_READ_BUFFER_PARAMS
class struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS._fields_ = [
  ('version', NvU32),
  ('port', NvU32),
  ('flags', NvU32),
  ('inputCount', NvU32),
  ('inputBuffer', (NvU8 * 256)),
  ('encrClientID', NvU32),
]
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS = struct_NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS
class struct_NV2080_CTRL_I2C_RW_REG_PARAMS(Struct): pass
struct_NV2080_CTRL_I2C_RW_REG_PARAMS._fields_ = [
  ('version', NvU32),
  ('port', NvU32),
  ('flags', NvU32),
  ('addr', NvU32),
  ('reg', NvU8),
  ('bufsize', NvU8),
  ('buffer', (NvU8 * 255)),
]
NV2080_CTRL_I2C_RW_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
NV2080_CTRL_I2C_READ_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
NV2080_CTRL_I2C_WRITE_REG_PARAMS = struct_NV2080_CTRL_I2C_RW_REG_PARAMS
class struct_NV2080_CTRL_I2C_ACCESS_PARAMS(Struct): pass
struct_NV2080_CTRL_I2C_ACCESS_PARAMS._fields_ = [
  ('token', NvU32),
  ('cmd', NvU32),
  ('port', NvU32),
  ('flags', NvU32),
  ('data', NvP64),
  ('status', NvU32),
  ('dataBuffSize', NvU32),
  ('speed', NvU32),
  ('encrClientID', NvU32),
]
NV2080_CTRL_I2C_ACCESS_PARAMS = struct_NV2080_CTRL_I2C_ACCESS_PARAMS
class struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._fields_ = [
  ('head', NvU32),
  ('authType', NvU32),
  ('status', NvU32),
]
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS._fields_ = [
  ('feHwSysCap', NvU32),
  ('windowPresentMask', NvU32),
  ('bFbRemapperEnabled', NvBool),
  ('numHeads', NvU32),
  ('i2cPort', NvU32),
  ('internalDispActiveMask', NvU32),
  ('embeddedDisplayPortMask', NvU32),
  ('bExternalMuxSupported', NvBool),
  ('bInternalMuxSupported', NvBool),
  ('numDispChannels', NvU32),
]
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS._fields_ = [
  ('bOneToOneComptagLineAllocation', NvBool),
  ('bUseOneToFourComptagLineAllocation', NvBool),
  ('bUseRawModeComptaglineAllocation', NvBool),
  ('bDisableCompbitBacking', NvBool),
  ('bDisablePostL2Compression', NvBool),
  ('bEnabledEccFBPA', NvBool),
  ('bL2PreFill', NvBool),
  ('l2CacheSize', NvU64),
  ('bFbpaPresent', NvBool),
  ('comprPageSize', NvU32),
  ('comprPageShift', NvU32),
  ('ramType', NvU32),
  ('ltcCount', NvU32),
  ('ltsPerLtcCount', NvU32),
]
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [
  ('accessCounterIndex', NvU32),
  ('bufferSize', NvU32),
  ('bufferPteArray', (NvU64 * 64)),
]
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS._fields_ = [
  ('accessCounterIndex', NvU32),
]
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS._fields_ = [
  ('capsTbl', (NvU8 * 23)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_CAPS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CAPS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS._fields_ = [
  ('engineCaps', (NV2080_CTRL_INTERNAL_STATIC_GR_CAPS * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER(Struct): pass
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId._fields_ = [
  ('gpcId', NvU16),
  ('localTpcId', NvU16),
  ('localSmId', NvU16),
  ('globalTpcId', NvU16),
  ('virtualGpcId', NvU16),
  ('migratableTpcId', NvU16),
]
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER._fields_ = [
  ('globalSmId', (struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_globalSmId * 240)),
  ('numSm', NvU16),
  ('numTpc', NvU16),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS._fields_ = [
  ('globalSmOrder', (NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
class struct_NV2080_CTRL_INTERNAL_BSP_CAPS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BSP_CAPS._fields_ = [
  ('capsTbl', (NvU8 * 8)),
]
NV2080_CTRL_INTERNAL_BSP_CAPS = struct_NV2080_CTRL_INTERNAL_BSP_CAPS
class struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS._fields_ = [
  ('caps', (NV2080_CTRL_INTERNAL_BSP_CAPS * 8)),
  ('valid', (NvBool * 8)),
]
NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_MSENC_CAPS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MSENC_CAPS._fields_ = [
  ('capsTbl', (NvU8 * 4)),
]
NV2080_CTRL_INTERNAL_MSENC_CAPS = struct_NV2080_CTRL_INTERNAL_MSENC_CAPS
class struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS._fields_ = [
  ('caps', (NV2080_CTRL_INTERNAL_MSENC_CAPS * 8)),
  ('valid', (NvBool * 8)),
]
NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS._fields_ = [
  ('gpcMask', NvU32),
  ('tpcMask', (NvU32 * 12)),
  ('tpcCount', (NvU32 * 12)),
  ('physGpcMask', NvU32),
  ('mmuPerGpc', (NvU32 * 12)),
  ('tpcToPesMap', (NvU32 * 10)),
  ('numPesPerGpc', (NvU32 * 12)),
  ('zcullMask', (NvU32 * 12)),
  ('physGfxGpcMask', NvU32),
  ('numGfxTpc', NvU32),
]
NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS._fields_ = [
  ('floorsweepingMasks', (NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
class struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS(Struct): pass
struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS._fields_ = [
  ('hUserClient', NvHandle),
  ('hChannel', NvHandle),
  ('bufferType', NvU32),
  ('firstPage', NvU32),
  ('numPages', NvU32),
  ('physAddrs', (NvU64 * 128)),
  ('bNoMorePages', NvBool),
]
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS = struct_NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS
class struct_NV2080_CTRL_INTERNAL_GR_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_GR_INFO._fields_ = [
  ('index', NvU32),
  ('data', NvU32),
]
NV2080_CTRL_INTERNAL_GR_INFO = struct_NV2080_CTRL_INTERNAL_GR_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO._fields_ = [
  ('infoList', (NV2080_CTRL_INTERNAL_GR_INFO * 58)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS._fields_ = [
  ('engineInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_INFO * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO._fields_ = [
  ('widthAlignPixels', NvU32),
  ('heightAlignPixels', NvU32),
  ('pixelSquaresByAliquots', NvU32),
  ('aliquotTotal', NvU32),
  ('zcullRegionByteMultiplier', NvU32),
  ('zcullRegionHeaderSize', NvU32),
  ('zcullSubregionHeaderSize', NvU32),
  ('subregionCount', NvU32),
  ('subregionWidthAlignPixels', NvU32),
  ('subregionHeightAlignPixels', NvU32),
]
NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS._fields_ = [
  ('engineZcullInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO._fields_ = [
  ('ropUnitCount', NvU32),
  ('ropOperationsFactor', NvU32),
  ('ropOperationsCount', NvU32),
]
NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS._fields_ = [
  ('engineRopInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS._fields_ = [
  ('mask', (NvU32 * 12)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS._fields_ = [
  ('enginePpcMasks', (NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
class struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO._fields_ = [
  ('size', NvU32),
  ('alignment', NvU32),
]
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO = struct_NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO._fields_ = [
  ('engine', (NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO * 26)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO = struct_NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS._fields_ = [
  ('engineContextBuffersInfo', (NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER._fields_ = [
  ('imla0', NvU8),
  ('fmla16', NvU8),
  ('dp', NvU8),
  ('fmla32', NvU8),
  ('ffma', NvU8),
  ('imla1', NvU8),
  ('imla2', NvU8),
  ('imla3', NvU8),
  ('imla4', NvU8),
]
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER = struct_NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS._fields_ = [
  ('smIssueRateModifier', (NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS._fields_ = [
  ('chipSubRev', NvU8),
  ('emulationRev1', NvU32),
  ('isCmpSku', NvBool),
  ('pciDeviceId', NvU32),
  ('pciSubDeviceId', NvU32),
  ('pciRevisionId', NvU32),
  ('regBases', (NvU32 * 16)),
]
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('bEnable', NvBool),
]
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS._fields_ = [
  ('grRouteInfo', NV2080_CTRL_GR_ROUTE_INFO),
  ('offset', NvU32),
]
NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE._fields_ = [
  ('fecsRecordSize', NvU32),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS._fields_ = [
  ('fecsRecordSize', (NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES._fields_ = [
  ('fecsRecordSize', NvU32),
  ('timestampHiTagMask', NvU32),
  ('timestampHiTagShift', NvU8),
  ('timestampVMask', NvU64),
  ('numLowerBitsZeroShift', NvU8),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS._fields_ = [
  ('fecsTraceDefines', (NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
class struct_NV2080_CTRL_INTERNAL_DEVICE_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_DEVICE_INFO._fields_ = [
  ('faultId', NvU32),
  ('instanceId', NvU32),
  ('typeEnum', NvU32),
  ('resetId', NvU32),
  ('devicePriBase', NvU32),
  ('isEngine', NvU32),
  ('rlEngId', NvU32),
  ('runlistPriBase', NvU32),
  ('groupId', NvU32),
  ('ginTargetId', NvU32),
  ('deviceBroadcastPriBase', NvU32),
  ('groupLocalInstanceId', NvU32),
]
NV2080_CTRL_INTERNAL_DEVICE_INFO = struct_NV2080_CTRL_INTERNAL_DEVICE_INFO
class struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS._fields_ = [
  ('numEntries', NvU32),
  ('deviceInfoTable', (NV2080_CTRL_INTERNAL_DEVICE_INFO * 512)),
]
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS._fields_ = [
  ('userRegisterAccessMapSize', NvU32),
  ('compressedSize', NvU32),
  ('compressedData', (NvU8 * 4096)),
  ('profilingRangesSize', NvU32),
  ('profilingRanges', (NvU8 * 4096)),
]
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS
class struct_NV2080_CTRL_INTERNAL_NV_RANGE(Struct): pass
struct_NV2080_CTRL_INTERNAL_NV_RANGE._fields_ = [
  ('lo', NvU64),
  ('hi', NvU64),
]
NV2080_CTRL_INTERNAL_NV_RANGE = struct_NV2080_CTRL_INTERNAL_NV_RANGE
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('memAddrRange', NV2080_CTRL_INTERNAL_NV_RANGE),
]
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS._fields_ = [
  ('bTeardown', NvBool),
]
NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES._fields_ = [
  ('bPerSubCtxheaderSupported', NvBool),
]
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES = struct_NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES
class struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS._fields_ = [
  ('pdbTable', (NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS._fields_ = [
  ('instMemPhysAddr', NvU64),
  ('instMemSize', NvU64),
  ('instMemAddrSpace', NvU32),
  ('instMemCpuCacheAttr', NvU32),
]
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS._fields_ = [
  ('ipVersion', NvU32),
]
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS._fields_ = [
  ('smcMode', NvU32),
]
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS._fields_ = [
  ('head', NvU32),
  ('rgLineNum', NvU32),
  ('intrLine', NvU32),
  ('bEnable', NvBool),
]
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS
class struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO._fields_ = [
  ('partitionFlag', NvU32),
  ('grCount', NvU32),
  ('gfxGrCount', NvU32),
  ('gpcCount', NvU32),
  ('virtualGpcCount', NvU32),
  ('gfxGpcCount', NvU32),
  ('veidCount', NvU32),
  ('smCount', NvU32),
  ('ceCount', NvU32),
  ('nvEncCount', NvU32),
  ('nvDecCount', NvU32),
  ('nvJpgCount', NvU32),
  ('nvOfaCount', NvU32),
  ('validCTSIdMask', NvU64),
  ('validGfxCTSIdMask', NvU64),
]
NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO = struct_NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS._fields_ = [
  ('count', NvU32),
  ('table', (NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO * 60)),
]
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS._fields_ = [
  ('partitionableMemSize', NvU64),
  ('bottomRsvdSize', NvU64),
  ('topRsvdSize', NvU64),
  ('partitionableStartAddr', NvU64),
  ('partitionableEndAddr', NvU64),
]
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS._fields_ = [
  ('engineMask', (NvU64 * 4)),
]
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
class struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS._fields_ = [
  ('rlBuffers', ((NV2080_CTRL_INTERNAL_MEMDESC_INFO * 2) * 64)),
  ('runlistIdMask', NvU64),
  ('swizzId', NvU32),
]
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS(Struct): pass
class struct_TEGRA_IMP_IMPORT_DATA(Struct): pass
TEGRA_IMP_IMPORT_DATA = struct_TEGRA_IMP_IMPORT_DATA
class struct_DRAM_CLK_INSTANCE(Struct): pass
DRAM_CLK_INSTANCE = struct_DRAM_CLK_INSTANCE
struct_DRAM_CLK_INSTANCE._fields_ = [
  ('dram_clk_freq_khz', NvU32),
  ('mchub_clk_khz', NvU32),
  ('mc_clk_khz', NvU32),
  ('max_iso_bw_kbps', NvU32),
  ('switch_latency_ns', NvU32),
]
struct_TEGRA_IMP_IMPORT_DATA._fields_ = [
  ('max_iso_bw_kbps', NvU32),
  ('num_dram_channels', NvU32),
  ('num_dram_clk_entries', NvU32),
  ('dram_clk_instance', (DRAM_CLK_INSTANCE * 24)),
]
struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS._fields_ = [
  ('tegraImpImportData', TEGRA_IMP_IMPORT_DATA),
]
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS._fields_ = [
  ('pciDeviceId', NvU16),
  ('pciSubDeviceId', NvU16),
  ('iseGPUBridge', NvBool),
  ('approvedBusType', NvU8),
]
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS._fields_ = [
  ('local2Remote', NvU32),
  ('remote2Local', NvU32),
  ('localP2PDomainRemoteAddr', NvU64),
  ('remoteP2PDomainLocalAddr', NvU64),
  ('remoteWMBoxLocalAddr', NvU64),
  ('p2pWmbTag', NvU64),
  ('bNeedWarBug999673', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS._fields_ = [
  ('local2Remote', NvU32),
  ('remote2Local', NvU32),
  ('localP2PDomainRemoteAddr', NvU64),
  ('remoteP2PDomainLocalAddr', NvU64),
  ('remoteWMBoxAddrU64', NvU64),
  ('p2pWmbTag', NvU64),
]
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS
class struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS._fields_ = [
  ('peerIdx', NvU32),
  ('bNeedWarBug999673', NvBool),
]
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS
class struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS._fields_ = [
  ('peerId', NvU32),
]
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS
class struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS._fields_ = [
  ('peerId', NvU32),
]
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS
class struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('numEntries', NvU32),
  ('gpaEntries', (NvU64 * 128)),
  ('spaEntries', (NvU64 * 128)),
]
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS = struct_NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS._fields_ = [
  ('addressSpace', NvU32),
  ('physicalAddr', NvU64),
  ('limit', NvU64),
  ('cacheSnoop', NvU32),
  ('hclass', NvU32),
  ('channelInstance', NvU32),
  ('valid', NvBool),
  ('pbTargetAperture', NvU32),
  ('channelPBSize', NvU32),
  ('subDeviceId', NvU32),
]
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS._fields_ = [
  ('replayableFaultBufferSize', NvU32),
  ('replayableShadowFaultBufferMetadataSize', NvU32),
  ('nonReplayableFaultBufferSize', NvU32),
  ('nonReplayableShadowFaultBufferMetadataSize', NvU32),
]
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS = struct_NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS
class struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS._fields_ = [
  ('moduleIndex', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS
enum_NV2080_INTR_CATEGORY = CEnum(ctypes.c_uint32)
NV2080_INTR_CATEGORY_DEFAULT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_DEFAULT', 0)
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE', 1)
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION', 2)
NV2080_INTR_CATEGORY_RUNLIST = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST', 3)
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION', 4)
NV2080_INTR_CATEGORY_UVM_OWNED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_OWNED', 5)
NV2080_INTR_CATEGORY_UVM_SHARED = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_UVM_SHARED', 6)
NV2080_INTR_CATEGORY_ENUM_COUNT = enum_NV2080_INTR_CATEGORY.define('NV2080_INTR_CATEGORY_ENUM_COUNT', 7)

NV2080_INTR_CATEGORY = enum_NV2080_INTR_CATEGORY
class struct_NV2080_INTR_CATEGORY_SUBTREE_MAP(Struct): pass
struct_NV2080_INTR_CATEGORY_SUBTREE_MAP._fields_ = [
  ('subtreeStart', NvU8),
  ('subtreeEnd', NvU8),
]
NV2080_INTR_CATEGORY_SUBTREE_MAP = struct_NV2080_INTR_CATEGORY_SUBTREE_MAP
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY(Struct): pass
struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY._fields_ = [
  ('engineIdx', NvU16),
  ('pmcIntrMask', NvU32),
  ('vectorStall', NvU32),
  ('vectorNonStall', NvU32),
]
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY
class struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS._fields_ = [
  ('tableLen', NvU32),
  ('table', (NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY * 128)),
  ('subtreeMap', (NV2080_INTR_CATEGORY_SUBTREE_MAP * 7)),
]
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS._fields_ = [
  ('bReservation', NvBool),
]
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS._fields_ = [
  ('bReservation', NvBool),
  ('bClientHandlesGrGating', NvBool),
  ('bRmHandlesIdleSlow', NvBool),
]
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS._fields_ = [
  ('displayMask', NvU32),
  ('numHeads', NvU32),
]
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS = struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS._fields_ = [
  ('fbMemPageRanges', (NV2080_CTRL_INTERNAL_NV_RANGE * 15)),
]
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS._fields_ = [
  ('runlistId', NvU32),
  ('numChannels', NvU32),
]
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS._fields_ = [
  ('memBoundaryCfgA', NvU64),
  ('memBoundaryCfgB', NvU64),
  ('memBoundaryCfgC', NvU32),
  ('memBoundaryCfg', NvU32),
  ('memBoundaryCfgValInit', NvU32),
]
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS._fields_ = [
  ('data', (NvU32 * 8)),
]
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS._fields_ = [
  ('powerState', NvU32),
]
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X._fields_ = [
  ('flags', NvBool),
  ('duration', NvU32),
]
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS._fields_ = [
  ('bActivate', NvBool),
]
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS._fields_ = [
  ('flags', NvU32),
  ('bBridgeless', NvBool),
  ('currLimits', (NvU32 * 2)),
]
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS._fields_ = [
  ('hysteresisus', NvU64),
  ('bHystersisEnable', NvBool),
  ('bSliGpuBoostSyncEnable', NvBool),
]
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hObject', NvHandle),
  ('faultBufferSize', NvU32),
  ('faultBufferPteArray', (NvU64 * 256)),
]
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [
  ('shadowFaultBufferQueuePhysAddr', NvU64),
  ('shadowFaultBufferSize', NvU32),
  ('shadowFaultBufferMetadataSize', NvU32),
  ('shadowFaultBufferPteArray', (NvU64 * 3000)),
  ('shadowFaultBufferType', NvU32),
  ('faultBufferSharedMemoryPhysAddr', NvU64),
]
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._fields_ = [
  ('shadowFaultBufferType', NvU32),
]
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS
class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._fields_ = [
  ('PdeCopyParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS),
]
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X._fields_ = [
  ('flags', NvU32),
  ('boostDuration', NvU32),
  ('gfId', NvU32),
  ('bOverrideInfinite', NvBool),
]
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X
class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X._fields_ = [
  ('bIsCudaClient', NvBool),
  ('gfId', NvU32),
]
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X = struct_NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X
class struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO._fields_ = [
  ('skylineVgpcSize', (NvU8 * 12)),
  ('singletonVgpcMask', NvU32),
  ('maxInstances', NvU32),
  ('computeSizeFlag', NvU32),
  ('numNonSingletonVgpcs', NvU32),
]
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO = struct_NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
class struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS._fields_ = [
  ('skylineTable', (NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO * 8)),
  ('validEntries', NvU32),
]
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS = struct_NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS._fields_ = [
  ('bZbcSurfacesExist', NvBool),
]
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO._fields_ = [
  ('enginesMask', (NvU64 * 4)),
  ('partitionFlags', NvU32),
  ('gpcMask', NvU32),
  ('virtualGpcCount', NvU32),
  ('veidOffset', NvU32),
  ('veidCount', NvU32),
]
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO = struct_NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO
class struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS._fields_ = [
  ('swizzId', NvU32),
  ('uuid', (NvU8 * 16)),
  ('info', NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO),
]
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS = struct_NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS._fields_ = [
  ('flags', NvU32),
]
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS
class struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS._fields_ = [
  ('bPcieGen4Capable', NvBool),
  ('bIsC2CLinkUp', NvBool),
  ('bIsDeviceMultiFunction', NvBool),
  ('bGcxPmuCfgSpaceRestore', NvBool),
]
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS._fields_ = [
  ('programPeerMask', NvU32),
  ('invalidatePeerMask', NvU32),
  ('programPciePeerMask', NvU32),
]
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('hshubIds', (NvU8 * 32)),
]
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS._fields_ = [
  ('numHshubs', NvU32),
]
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS._fields_ = [
  ('hshubId', NvU8),
]
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS._fields_ = [
  ('egmPeerId', NvU32),
]
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS._fields_ = [
  ('bGet', NvBool),
  ('addr', NvU64),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS
class struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS._fields_ = [
  ('bCyaMaskL1', NvBool),
  ('bEnableAspmDtL1', NvBool),
]
NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS
class struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS._fields_ = [
  ('maxActiveVGpuVMCount', NvU8),
]
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS = struct_NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS._fields_ = [
  ('bRawMode', NvBool),
]
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS._fields_ = [
  ('ccuSampleSize', NvU32),
]
NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO._fields_ = [
  ('phyAddr', NvU64),
  ('shrBufSize', NvU32),
  ('cntBlkSize', NvU32),
]
NV2080_CTRL_INTERNAL_CCU_MAP_INFO = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO
class struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS._fields_ = [
  ('mapInfo', (NV2080_CTRL_INTERNAL_CCU_MAP_INFO * 9)),
]
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS._fields_ = [
  ('bDevShrBuf', NvBool),
  ('bMigShrBuf', NvBool),
]
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO._fields_ = [
  ('gpuId', NvU32),
  ('gpuInstance', NvU32),
  ('p2pCaps', NvU32),
  ('p2pOptimalReadCEs', NvU32),
  ('p2pOptimalWriteCEs', NvU32),
  ('p2pCapsStatus', (NvU8 * 9)),
  ('busPeerId', NvU32),
  ('busEgmPeerId', NvU32),
]
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO
class struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS._fields_ = [
  ('peerGpuCount', NvU32),
  ('peerGpuInfos', (NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO * 32)),
]
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS._fields_ = [
  ('peerGpuIdCount', NvU32),
  ('peerGpuIds', (NvU32 * 32)),
]
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS._fields_ = [
  ('bCommonPciSwitchFound', NvBool),
  ('p2pReadCapsStatus', NvU8),
  ('p2pWriteCapsStatus', NvU8),
]
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS = struct_NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS._fields_ = [
  ('enableRo', NvBool),
]
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS._fields_ = [
  ('bSave', NvBool),
  ('bUseVbios', NvBool),
  ('bReturnEarly', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS._fields_ = [
  ('bSave', NvBool),
  ('bUseVbios', NvBool),
  ('bVbiosCallSuccessful', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS
class struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE(Struct): pass
struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE._fields_ = [
  ('computeSize', NvU8),
  ('gfxGpcCount', NvU32),
  ('gpcCount', NvU32),
  ('veidCount', NvU32),
  ('smCount', NvU32),
  ('physicalSlots', NvU32),
]
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE = struct_NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
class struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS._fields_ = [
  ('profileCount', NvU32),
  ('profiles', (NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE * 8)),
]
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS = struct_NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS
class struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS._fields_ = [
  ('bStreamState', NvBool),
]
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS._fields_ = [
  ('bExtDevFound', NvBool),
]
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS(Struct): pass
class struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS(Struct): pass
NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS = struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS
struct_NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS._fields_ = [
  ('gpuId', NvU32),
  ('output', NvU32),
  ('protocol', NvU32),
  ('structure', NvU32),
  ('adjust', NvU32),
  ('hDeltaStep', NvU32),
  ('hDeltaMax', NvU32),
  ('vDeltaStep', NvU32),
  ('vDeltaMax', NvU32),
  ('hSyncEnd', NvU32),
  ('hBlankEnd', NvU32),
  ('hBlankStart', NvU32),
  ('hTotal', NvU32),
  ('vSyncEnd', NvU32),
  ('vBlankEnd', NvU32),
  ('vBlankStart', NvU32),
  ('vInterlacedBlankEnd', NvU32),
  ('vInterlacedBlankStart', NvU32),
  ('vTotal', NvU32),
  ('refreshX10K', NvU32),
  ('pixelClockHz', NvU64),
  ('bOptimized', NvBool),
]
struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS._fields_ = [
  ('timingParameters', NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS),
]
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS._fields_ = [
  ('displayIds', (NvU32 * 4)),
]
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS._fields_ = [
  ('slave', (NvU32 * 4)),
  ('localSlave', (NvU32 * 4)),
  ('master', (NvU32 * 4)),
  ('regStatus', NvU32),
]
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS._fields_ = [
  ('headIdx', NvU32),
  ('vActiveLines', NvU32),
]
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS._fields_ = [
  ('displays', NvU32),
  ('displayId', NvU32),
]
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS._fields_ = [
  ('bEnableMaster', NvBool),
  ('bRasterSyncGpioSaved', NvBool),
  ('bRasterSyncGpioDirection', NvU32),
]
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS
class struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS._fields_ = [
  ('hClient', NvHandle),
  ('hSysMem', NvHandle),
  ('bEnteringGcoffState', NvBool),
  ('sysmemAddrOfSuspendResumeData', NvU64),
]
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS = struct_NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS._fields_ = [
  ('bDisableActiveChannels', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS._fields_ = [
  ('hostReservedFb', NvU64),
  ('vgpuTypeId', NvU32),
]
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS
class struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS._fields_ = [
  ('status', NvU32),
  ('backLightDataSize', NvU16),
  ('backLightData', (NvU8 * 4096)),
]
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS._fields_ = [
  ('numActiveLinksPerIoctrl', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS._fields_ = [
  ('numLinksPerIoctrl', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
class struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS._fields_ = [
  ('bIsSysCtrlSupported', NvBool),
  ('bIsPlatformLegacy', NvBool),
]
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS = struct_NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI(Struct): pass
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI._fields_ = [
  ('sensorId', NvU32),
  ('limit', NvU32),
]
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA(Struct): pass
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data(ctypes.Union): pass
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data._fields_ = [
  ('smbpbi', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI),
]
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA._fields_ = [
  ('type', NvU8),
  ('data', struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_data),
]
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA
class struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS._fields_ = [
  ('flags', NvU8),
  ('syncData', NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA),
]
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS = struct_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS._fields_ = [
  ('flag', NvU8),
  ('bStatus', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS._fields_ = [
  ('bEnable', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS._fields_ = [
  ('bEnable', NvBool),
  ('clientLimit', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS._fields_ = [
  ('targetTemp', NvS32),
]
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS._fields_ = [
  ('bEnable', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS._fields_ = [
  ('ctgpOffsetmW', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS._fields_ = [
  ('bVpsPs20Supported', NvBool),
  ('vPstateIdxHighest', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS._fields_ = [
  ('pStateIdx', NvU32),
  ('vPstateIdxMapping', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS._fields_ = [
  ('vPstateIdx', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS._fields_ = [
  ('bIsGC6Satisfied', NvBool),
  ('bIsGCOFFSatisfied', NvBool),
]
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS = struct_NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS._fields_ = [
  ('maxSec2SecureChannels', NvU32),
  ('maxCeSecureChannels', NvU32),
]
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS
class struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS._fields_ = [
  ('bDisable', NvBool),
]
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS = struct_NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS._fields_ = [
  ('pinSetIn', NvU32),
  ('pinSetOut', NvU32),
  ('bMasterScanLock', NvBool),
  ('masterScanLockPin', NvU32),
  ('bSlaveScanLock', NvBool),
  ('slaveScanLockPin', NvU32),
]
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS
class struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS._fields_ = [
  ('pinSet', NvU32),
  ('gpioFunction', NvU32),
  ('gpioPin', NvU32),
  ('gpioDirection', NvBool),
]
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS = struct_NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS
class struct_NV2080_CTRL_INTERNAL_EDID_DATA(Struct): pass
struct_NV2080_CTRL_INTERNAL_EDID_DATA._fields_ = [
  ('status', NvU32),
  ('acpiId', NvU32),
  ('bufferSize', NvU32),
  ('edidBuffer', (NvU8 * 512)),
]
NV2080_CTRL_INTERNAL_EDID_DATA = struct_NV2080_CTRL_INTERNAL_EDID_DATA
class struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS._fields_ = [
  ('tableLen', NvU32),
  ('edidTable', (NV2080_CTRL_INTERNAL_EDID_DATA * 16)),
]
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [
  ('numProbes', NvU64),
]
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [
  ('bwMode', NvU8),
  ('bLocalEgmEnabled', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS._fields_ = [
  ('bwMode', NvU8),
]
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS._fields_ = [
  ('bIsBar1Trusted', NvBool),
  ('bIsPcieTrusted', NvBool),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK._fields_ = [
  ('ivMask', (NvU32 * 3)),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('ivMaskSet', (NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 3)),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS._fields_ = [
  ('engineId', NvU32),
  ('ivMaskSet', (NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK * 6)),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS._fields_ = [
  ('globalH2DKey', NvU32),
  ('updatedEncryptIVMask', (NvU32 * 3)),
  ('updatedDecryptIVMask', (NvU32 * 3)),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS
class struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS._fields_ = [
  ('exceptionType', NvU32),
  ('globalH2DKey', NvU32),
]
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS = struct_NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS._fields_ = [
  ('bAcceptClientRequest', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS._fields_ = [
  ('attackerAdvantage', NvU64),
]
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
class struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS._fields_ = [
  ('logicalUprocId', NvU8),
]
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS = struct_NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS
enum_NV2080_CTRL_MEMMGR_MEMORY_OP = CEnum(ctypes.c_uint32)
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY', 0)
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = enum_NV2080_CTRL_MEMMGR_MEMORY_OP.define('NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET', 1)

NV2080_CTRL_MEMMGR_MEMORY_OP = enum_NV2080_CTRL_MEMMGR_MEMORY_OP
class struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO._fields_ = [
  ('baseAddr', NvU64),
  ('size', NvU64),
  ('offset', NvU64),
  ('aperture', NvU32),
  ('cpuCacheAttrib', NvU32),
]
NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO = struct_NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO
class struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS._fields_ = [
  ('src', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO),
  ('authTag', (NvU8 * 16)),
  ('dst', NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO),
  ('transferSize', NvU64),
  ('value', NvU32),
  ('memop', NV2080_CTRL_MEMMGR_MEMORY_OP),
]
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS._fields_ = [
  ('addrSysPhys', NvU64),
  ('addrWidth', NvU32),
  ('mask', NvU32),
  ('maskWidth', NvU32),
]
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS._fields_ = [
  ('peerId', NvU32),
  ('addrSysPhys', NvU64),
  ('addrWidth', NvU32),
  ('mask', NvU32),
  ('maskWidth', NvU32),
]
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS._fields_ = [
  ('limitMin', NvU32),
  ('limitRated', NvU32),
  ('limitMax', NvU32),
  ('limitCurr', NvU32),
  ('limitBattRated', NvU32),
  ('limitBattMax', NvU32),
]
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS._fields_ = [
  ('physAddr', NvU64),
]
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS = struct_NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS
class struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS._fields_ = [
  ('polledDataMask', NvU64),
  ('pollFrequencyMs', NvU32),
]
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS = struct_NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS._fields_ = [
  ('tracepointMask', NvU64),
  ('bufferAddr', NvU64),
  ('bufferSize', NvU32),
  ('bufferWatermark', NvU32),
  ('flag', NvU8),
]
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS
class struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS._fields_ = [
  ('bMaxwellSec2Enabled', NvBool),
  ('bNv95A1TsecEnabled', NvBool),
  ('bHopperSec2WorkLaunchAEnabled', NvBool),
]
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS = struct_NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS = struct_NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS._fields_ = [
  ('bInPMTransition', NvBool),
  ('newPMLevel', NvU32),
]
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS._fields_ = [
  ('bSuccessful', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS._fields_ = [
  ('freeHeapSize', NvU64),
]
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS._fields_ = [
  ('attribute', NvU32),
  ('value', NvU32),
]
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS._fields_ = [
  ('bApplyStereoPinAlwaysHiWar', NvBool),
]
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS
class struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS._fields_ = [
  ('maxHshubs', NvU32),
]
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS = struct_NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS
class struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS._fields_ = [
  ('rasterSyncDecodeMode', NvU32),
]
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS._fields_ = [
  ('spaValue', NvU64),
]
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS = struct_NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS._fields_ = [
  ('peerMask', NvU32),
  ('bEnable', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS._fields_ = [
  ('mode', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS._fields_ = [
  ('seedData', (NvU32 * 7)),
]
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS._fields_ = [
  ('remoteDeviceType', NvU32),
  ('ipVerDlPl', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS._fields_ = [
  ('seedData', (NvU32 * 7)),
]
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO._fields_ = [
  ('remoteSid', NvU64),
  ('remoteDeviceType', NvU32),
  ('remoteLinkId', NvU32),
  ('localSid', NvU64),
]
NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS._fields_ = [
  ('bInitnegotiateConfigGood', NvBool),
  ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO),
]
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS._fields_ = [
  ('bPollDone', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS(Struct): pass
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams(ctypes.Union): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams._fields_ = [
  ('linkModeOffParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_OFF_PARAMS),
  ('linkModePreHsParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_PRE_HS_PARAMS),
  ('linkModeInitPhase1Params', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_INIT_PHASE1_PARAMS),
  ('linkModePostInitNegotiateParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITNEGOTIATE_PARAMS),
  ('linkModePostInitOptimizeParams', NV2080_CTRL_INTERNAL_NVLINK_SET_DL_LINK_MODE_POST_INITOPTIMIZE_PARAMS),
]
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS._fields_ = [
  ('mode', NvU64),
  ('bSync', NvBool),
  ('linkMode', NvU32),
  ('linkModeParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS_linkModeParams),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS._fields_ = [
  ('mode', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS._fields_ = [
  ('mode', NvU64),
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS._fields_ = [
  ('sublinkMode', NvU32),
  ('sublinkSubMode', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS._fields_ = [
  ('mode', NvU64),
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS._fields_ = [
  ('mode', NvU64),
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS._fields_ = [
  ('laneRxdetStatusMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS._fields_ = [
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS._fields_ = [
  ('ipVerDlPl', NvU32),
  ('token', NvU64),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS._fields_ = [
  ('bUnlocked', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE(Struct): pass
class struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams(ctypes.Union): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams._fields_ = [
  ('getDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_DL_LINK_MODE_PARAMS),
  ('setDlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_DL_LINK_MODE_PARAMS),
  ('getTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_TL_LINK_MODE_PARAMS),
  ('setTlLinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TL_LINK_MODE_PARAMS),
  ('getTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS),
  ('setTxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_TX_SUBLINK_MODE_PARAMS),
  ('getRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_SUBLINK_MODE_PARAMS),
  ('setRxSublinkMode', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_SUBLINK_MODE_PARAMS),
  ('getRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_RX_DETECT_PARAMS),
  ('setRxSublinkDetect', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_SET_RX_DETECT_PARAMS),
  ('writeDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS),
  ('readDiscoveryToken', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_RD_WR_DISCOVERY_TOKEN_PARAMS),
  ('getUphyLoad', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_GET_UPHY_LOAD_PARAMS),
]
struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE._fields_ = [
  ('type', NvU8),
  ('callbackParams', struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_callbackParams),
]
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE = struct_NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE
class struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('callbackType', NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE),
]
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('remoteLocalSidInfo', NV2080_CTRL_INTERNAL_NVLINK_REMOTE_LOCAL_SID_INFO),
]
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS._fields_ = [
  ('bEnableAli', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS._fields_ = [
  ('updateType', NvBool),
  ('bSysMem', NvBool),
  ('peerMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS._fields_ = [
  ('peerId', NvU32),
  ('peerLinkMask', NvU32),
  ('bEgmPeer', NvBool),
  ('bNvswitchConn', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS._fields_ = [
  ('peerMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS
class struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS._fields_ = [
  ('xid', NvU32),
  ('message', (NvU8 * 81)),
  ('len', NvU32),
]
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS = struct_NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS._fields_ = [
  ('mapTypeMask', NvU32),
  ('peerMask', NvU32),
  ('bL2Entry', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS._fields_ = [
  ('bSave', NvBool),
  ('linkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS._fields_ = [
  ('flags', NvU32),
  ('bSysmem', NvBool),
  ('peerLinkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS._fields_ = [
  ('bNvlinkSysmemEnabled', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS._fields_ = [
  ('gpuInst', NvU32),
  ('peerLinkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS._fields_ = [
  ('remoteDeviceType', NvU64),
  ('remoteChipSid', NvU64),
  ('linkId', NvU32),
  ('laneRxdetStatusMask', NvU32),
  ('remoteLinkNumber', NvU32),
  ('remotePciDeviceId', NvU32),
  ('remoteDomain', NvU32),
  ('remoteBus', NvU8),
  ('remoteDevice', NvU8),
  ('remoteFunction', NvU8),
  ('bConnected', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('initializedLinks', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS._fields_ = [
  ('postRxDetLinkMask', NvU64),
  ('laneRxdetStatusMask', (NvU32 * 64)),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('bSync', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES._fields_ = [
  ('bValid', NvBool),
  ('linkId', NvU8),
  ('ioctrlId', NvU32),
  ('pllMasterLinkId', NvU8),
  ('pllSlaveLinkId', NvU8),
  ('ipVerDlPl', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS._fields_ = [
  ('ioctrlMask', NvU32),
  ('ioctrlNumEntries', NvU8),
  ('ioctrlSize', NvU32),
  ('discoveredLinks', NvU64),
  ('ipVerNvlink', NvU32),
  ('linkInfo', (NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES * 64)),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES._fields_ = [
  ('ipVerIoctrl', NvU32),
  ('ipVerMinion', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS._fields_ = [
  ('ioctrlIdx', NvU32),
  ('PublicId', NvU32),
  ('localDiscoveredLinks', NvU32),
  ('localGlobalLinkOffset', NvU32),
  ('ioctrlDiscoverySize', NvU32),
  ('numDevices', NvU8),
  ('ipRevisions', NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS._fields_ = [
  ('bPlatformLinerateDefined', NvBool),
  ('platformLineRate', NvU32),
  ('nvlinkLinkSpeed', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('bActiveOnly', NvBool),
  ('bIsLinkActive', (NvBool * 64)),
]
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('flags', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS._fields_ = [
  ('linkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES._fields_ = [
  ('bLinkConnectedToSystem', NvBool),
  ('bLinkConnectedToPeer', NvBool),
  ('bLinkReset', NvBool),
  ('subLinkWidth', NvU8),
  ('linkState', NvU32),
  ('txSublinkState', NvU32),
  ('rxSublinkState', NvU32),
  ('bLaneReversal', NvBool),
  ('nvlinkLinkClockKHz', NvU32),
  ('nvlinkLineRateMbps', NvU32),
  ('nvlinkLinkClockMhz', NvU32),
  ('nvlinkLinkDataRateKiBps', NvU32),
  ('nvlinkRefClkType', NvU8),
  ('nvlinkReqLinkClockMhz', NvU32),
  ('nvlinkMinL1Threshold', NvU32),
  ('nvlinkMaxL1Threshold', NvU32),
  ('nvlinkL1ThresholdUnits', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES
class struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS._fields_ = [
  ('linkMask', NvU64),
  ('nvlinkRefClkSpeedKHz', NvU32),
  ('bSublinkStateInst', NvBool),
  ('linkInfo', (NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES * 64)),
]
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS._fields_ = [
  ('sysmemLinkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS._fields_ = [
  ('bLegacyForcedConfig', NvBool),
  ('bOverrideComputePeerMode', NvBool),
  ('phase', NvU32),
  ('linkConnection', (NvU32 * 64)),
]
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS._fields_ = [
  ('bLaneShutdownOnUnload', NvBool),
]
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS._fields_ = [
  ('notUsed', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS
class struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS._fields_ = [
  ('sysmemLinkMask', NvU32),
]
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS = struct_NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS
class struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS._fields_ = [
  ('ctrlParamVal', NvU32),
]
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS
class struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS._fields_ = [
  ('responseVal', NvU32),
]
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS = struct_NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS
class struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS._fields_ = [
  ('architecture', NvU32),
  ('implementation', NvU32),
  ('revision', NvU32),
  ('subRevision', NvU8),
]
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS = struct_NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS
class struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS._fields_ = [
  ('engines', NvU32),
]
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS = struct_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS
class struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS._fields_ = [
  ('manufacturer', NvU32),
]
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS = struct_NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS
class struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS._fields_ = [
  ('bOwnedByRm', NvBool),
]
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS = struct_NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS
class struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY(Struct): pass
struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY._fields_ = [
  ('nv2080EngineType', NvU32),
  ('notificationIntrVector', NvU32),
]
NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY = struct_NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY
class struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS._fields_ = [
  ('numEntries', NvU32),
  ('entries', (NV2080_CTRL_MC_ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY * 256)),
]
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS = struct_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
class struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY(Struct): pass
struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY._fields_ = [
  ('nv2080IntrType', NvU32),
  ('pmcIntrMask', NvU32),
  ('intrVectorStall', NvU32),
  ('intrVectorNonStall', NvU32),
]
NV2080_CTRL_MC_STATIC_INTR_ENTRY = struct_NV2080_CTRL_MC_STATIC_INTR_ENTRY
class struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(Struct): pass
struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS._fields_ = [
  ('numEntries', NvU32),
  ('entries', (NV2080_CTRL_MC_STATIC_INTR_ENTRY * 32)),
]
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS = struct_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
class struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS._fields_ = [
  ('component', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS
class struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS._fields_ = [
  ('pBuffer', NvP64),
  ('component', NvU32),
  ('size', NvU32),
]
NV2080_CTRL_NVD_GET_DUMP_PARAMS = struct_NV2080_CTRL_NVD_GET_DUMP_PARAMS
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS(Struct): pass
struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS._fields_ = [
  ('userMinOffset', NvS32),
  ('userMaxOffset', NvS32),
  ('factoryMinOffset', NvU32),
  ('factoryMaxOffset', NvU32),
  ('lastActiveClock', NvU32),
  ('lastActiveVolt', NvU32),
  ('lastActivePoint', NvU32),
  ('kappa', NvU32),
]
NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS
class struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG(Struct): pass
struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG._fields_ = [
  ('pstateVer', NvU32),
  ('gpcOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS),
  ('mclkOverclock', NV2080_NOCAT_JOURNAL_OVERCLOCK_DETAILS),
  ('bUserOverclocked', NvBool),
  ('bFactoryOverclocked', NvBool),
]
NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG = struct_NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG
class struct_NV2080_NOCAT_JOURNAL_GPU_STATE(Struct): pass
struct_NV2080_NOCAT_JOURNAL_GPU_STATE._fields_ = [
  ('bValid', NvBool),
  ('strap', NvU32),
  ('deviceId', NvU16),
  ('vendorId', NvU16),
  ('subsystemVendor', NvU16),
  ('subsystemId', NvU16),
  ('revision', NvU16),
  ('type', NvU16),
  ('vbiosVersion', NvU32),
  ('bOptimus', NvBool),
  ('bMsHybrid', NvBool),
  ('bFullPower', NvBool),
  ('vbiosOemVersion', NvU32),
  ('memoryType', NvU16),
  ('tag', (NvU8 * 65)),
  ('vbiosProject', (NvU8 * 65)),
  ('bInFullchipReset', NvBool),
  ('bInSecBusReset', NvBool),
  ('bInGc6Reset', NvBool),
  ('overclockCfg', NV2080_NOCAT_JOURNAL_OVERCLOCK_CFG),
]
NV2080_NOCAT_JOURNAL_GPU_STATE = struct_NV2080_NOCAT_JOURNAL_GPU_STATE
class struct_NV2080_NOCAT_JOURNAL_ENTRY(Struct): pass
struct_NV2080_NOCAT_JOURNAL_ENTRY._fields_ = [
  ('recType', NvU8),
  ('bugcheck', NvU32),
  ('tdrBucketId', NvU32),
  ('source', (NvU8 * 65)),
  ('subsystem', NvU32),
  ('errorCode', NvU64),
  ('diagBufferLen', NvU32),
  ('diagBuffer', (NvU8 * 1024)),
  ('faultingEngine', (NvU8 * 65)),
  ('mmuFaultType', NvU32),
  ('mmuErrorSrc', NvU32),
  ('tdrReason', (NvU8 * 65)),
]
NV2080_NOCAT_JOURNAL_ENTRY = struct_NV2080_NOCAT_JOURNAL_ENTRY
class struct_NV2080_NOCAT_JOURNAL_RECORD(Struct): pass
struct_NV2080_NOCAT_JOURNAL_RECORD._fields_ = [
  ('GPUTag', NvU32),
  ('loadAddress', NvU64),
  ('timeStamp', NvU64),
  ('stateMask', NvU64),
  ('nocatGpuState', NV2080_NOCAT_JOURNAL_GPU_STATE),
  ('nocatJournalEntry', NV2080_NOCAT_JOURNAL_ENTRY),
]
NV2080_NOCAT_JOURNAL_RECORD = struct_NV2080_NOCAT_JOURNAL_RECORD
class struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS(Struct): pass
struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS._fields_ = [
  ('flags', NvU32),
  ('nocatRecordCount', NvU32),
  ('nocatOutstandingRecordCount', NvU32),
  ('journalRecords', (NV2080_NOCAT_JOURNAL_RECORD * 10)),
  ('activityCounters', (NvU32 * 32)),
  ('reserved', (NvU8 * 65)),
]
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS = struct_NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS
class struct_NV2080CtrlNocatJournalDataTdrReason(Struct): pass
struct_NV2080CtrlNocatJournalDataTdrReason._fields_ = [
  ('flags', NvU32),
  ('source', (NvU8 * 65)),
  ('subsystem', NvU32),
  ('errorCode', NvU64),
  ('reasonCode', NvU32),
]
NV2080CtrlNocatJournalDataTdrReason = struct_NV2080CtrlNocatJournalDataTdrReason
class struct_NV2080CtrlNocatJournalSetTag(Struct): pass
struct_NV2080CtrlNocatJournalSetTag._fields_ = [
  ('flags', NvU32),
  ('tag', (NvU8 * 65)),
]
NV2080CtrlNocatJournalSetTag = struct_NV2080CtrlNocatJournalSetTag
class struct_NV2080CtrlNocatJournalRclog(Struct): pass
struct_NV2080CtrlNocatJournalRclog._fields_ = [
  ('flags', NvU32),
  ('rclogSize', NvU32),
  ('rmGpuId', NvU32),
  ('APIType', NvU32),
  ('contextType', NvU32),
  ('exceptType', NvU32),
  ('processImageName', (NvU8 * 65)),
]
NV2080CtrlNocatJournalRclog = struct_NV2080CtrlNocatJournalRclog
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS(Struct): pass
class struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData(ctypes.Union): pass
struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData._fields_ = [
  ('tdrReason', NV2080CtrlNocatJournalDataTdrReason),
  ('tagData', NV2080CtrlNocatJournalSetTag),
  ('rclog', NV2080CtrlNocatJournalRclog),
]
struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS._fields_ = [
  ('dataType', NvU32),
  ('targetRecordType', NvU32),
  ('nocatJournalData', struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_nocatJournalData),
]
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS = struct_NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS
class struct_NV2080CtrlNocatJournalInsertRecord(Struct): pass
struct_NV2080CtrlNocatJournalInsertRecord._fields_ = [
  ('flags', NvU32),
  ('timestamp', NvU64),
  ('recType', NvU8),
  ('bugcheck', NvU32),
  ('source', (ctypes.c_char * 65)),
  ('subsystem', NvU32),
  ('errorCode', NvU64),
  ('faultingEngine', (ctypes.c_char * 65)),
  ('tdrReason', NvU32),
  ('diagBufferLen', NvU32),
  ('diagBuffer', (NvU8 * 1024)),
]
NV2080CtrlNocatJournalInsertRecord = struct_NV2080CtrlNocatJournalInsertRecord
class struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS._fields_ = [
  ('nocatJournalRecord', NV2080CtrlNocatJournalInsertRecord),
]
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS = struct_NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS._fields_ = [
  ('capsTbl', NvU32),
  ('lowestNvlinkVersion', NvU8),
  ('highestNvlinkVersion', NvU8),
  ('lowestNciVersion', NvU8),
  ('highestNciVersion', NvU8),
  ('discoveredLinkMask', NvU32),
  ('enabledLinkMask', NvU32),
  ('discoveredLinks', NvU64),
  ('enabledLinks', NvU64),
]
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
class struct_NV2080_CTRL_NVLINK_DEVICE_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_DEVICE_INFO._fields_ = [
  ('deviceIdFlags', NvU32),
  ('domain', NvU32),
  ('bus', NvU16),
  ('device', NvU16),
  ('function', NvU16),
  ('pciDeviceId', NvU32),
  ('deviceType', NvU64),
  ('deviceUUID', (NvU8 * 16)),
  ('fabricRecoveryStatusMask', NvU32),
]
NV2080_CTRL_NVLINK_DEVICE_INFO = struct_NV2080_CTRL_NVLINK_DEVICE_INFO
class struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO._fields_ = [
  ('capsTbl', NvU32),
  ('phyType', NvU8),
  ('subLinkWidth', NvU8),
  ('linkState', NvU32),
  ('rxSublinkStatus', NvU8),
  ('txSublinkStatus', NvU8),
  ('bLaneReversal', NvBool),
  ('nvlinkVersion', NvU8),
  ('nciVersion', NvU8),
  ('phyVersion', NvU8),
  ('nvlinkLinkClockKHz', NvU32),
  ('nvlinkCommonClockSpeedKHz', NvU32),
  ('nvlinkRefClkSpeedKHz', NvU32),
  ('nvlinkCommonClockSpeedMhz', NvU32),
  ('nvlinkLineRateMbps', NvU32),
  ('nvlinkLinkClockMhz', NvU32),
  ('nvlinkRefClkType', NvU8),
  ('nvlinkLinkDataRateKiBps', NvU32),
  ('nvlinkRefClkSpeedMhz', NvU32),
  ('connected', NvBool),
  ('loopProperty', NvU8),
  ('remoteDeviceLinkNumber', NvU8),
  ('localDeviceLinkNumber', NvU8),
  ('remoteLinkSid', NvU64),
  ('localLinkSid', NvU64),
  ('laneRxdetStatusMask', NvU32),
  ('nvlinkMinL1Threshold', NvU32),
  ('nvlinkMaxL1Threshold', NvU32),
  ('nvlinkL1ThresholdUnits', NvU32),
  ('remoteDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO),
  ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO),
]
NV2080_CTRL_NVLINK_LINK_STATUS_INFO = struct_NV2080_CTRL_NVLINK_LINK_STATUS_INFO
enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = CEnum(ctypes.c_uint32)
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_100US', 0)
NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT.define('NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT_50US', 1)

NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT = enum_NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT
class struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS._fields_ = [
  ('enabledLinkMask', NvU32),
  ('bSublinkStateInst', NvBool),
  ('linkInfo', (NV2080_CTRL_NVLINK_LINK_STATUS_INFO * 64)),
]
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS
class struct_NV2080_CTRL_NVLINK_ERR_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_ERR_INFO._fields_ = [
  ('TLErrlog', NvU32),
  ('TLIntrEn', NvU32),
  ('TLCTxErrStatus0', NvU32),
  ('TLCTxErrStatus1', NvU32),
  ('TLCTxSysErrStatus0', NvU32),
  ('TLCRxErrStatus0', NvU32),
  ('TLCRxErrStatus1', NvU32),
  ('TLCRxSysErrStatus0', NvU32),
  ('TLCTxErrLogEn0', NvU32),
  ('TLCTxErrLogEn1', NvU32),
  ('TLCTxSysErrLogEn0', NvU32),
  ('TLCRxErrLogEn0', NvU32),
  ('TLCRxErrLogEn1', NvU32),
  ('TLCRxSysErrLogEn0', NvU32),
  ('MIFTxErrStatus0', NvU32),
  ('MIFRxErrStatus0', NvU32),
  ('NVLIPTLnkErrStatus0', NvU32),
  ('NVLIPTLnkErrLogEn0', NvU32),
  ('NVLIPTLnkCtrlLinkStateRequest', NvU32),
  ('DLSpeedStatusTx', NvU32),
  ('DLSpeedStatusRx', NvU32),
  ('NVLDLRxSlsmErrCntl', NvU32),
  ('NVLDLTopLinkState', NvU32),
  ('NVLDLTopIntr', NvU32),
  ('DLStatMN00', NvU32),
  ('DLStatUC01', NvU32),
  ('MinionNvlinkLinkIntr', NvU32),
  ('bExcessErrorDL', NvBool),
]
NV2080_CTRL_NVLINK_ERR_INFO = struct_NV2080_CTRL_NVLINK_ERR_INFO
class struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO._fields_ = [
  ('NVLIPTErrStatus0', NvU32),
  ('NVLIPTErrLogEn0', NvU32),
]
NV2080_CTRL_NVLINK_COMMON_ERR_INFO = struct_NV2080_CTRL_NVLINK_COMMON_ERR_INFO
class struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('linkErrInfo', (NV2080_CTRL_NVLINK_ERR_INFO * 64)),
  ('ioctrlMask', NvU32),
  ('commonErrInfo', (NV2080_CTRL_NVLINK_COMMON_ERR_INFO * 3)),
  ('ErrInfoFlags', NvU8),
]
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES._fields_ = [
  ('bTx0TlCounterOverflow', NvBool),
  ('bTx1TlCounterOverflow', NvBool),
  ('bRx0TlCounterOverflow', NvBool),
  ('bRx1TlCounterOverflow', NvBool),
  ('value', (NvU64 * 32)),
]
NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS._fields_ = [
  ('counterMask', NvU32),
  ('linkMask', NvU64),
  ('counters', (NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES * 64)),
]
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS._fields_ = [
  ('counterMask', NvU32),
  ('linkMask', NvU64),
]
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES(Struct): pass
struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES._fields_ = [
  ('overFlow', NvBool),
  ('value', NvU64),
]
NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES = struct_NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES
class struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS._fields_ = [
  ('linkMask', NvU64),
  ('counterMask', (NvU64 * 2)),
  ('counter', ((NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES * 28) * 64)),
]
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS
class struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS._fields_ = [
  ('linkMask', NvU64),
  ('counterMask', (NvU64 * 2)),
]
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS
class struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('bFatalError', NvBool),
]
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS
enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR', 1)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR', 2)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR', 3)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR', 4)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE.define('NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX', 5)

NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE = enum_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG(Struct): pass
struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG._fields_ = [
  ('errType', NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE),
  ('errSettings', NvU64),
]
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG
class struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS._fields_ = [
  ('linkMask', NvU64),
  ('errCfg', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG * 64)),
]
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS
class struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO._fields_ = [
  ('txErrInfo', NvU32),
  ('packetErrInfo', NvU32),
  ('authErrInfo', NvU32),
  ('linkStatus', NvU32),
  ('errInjectStatus', NvU32),
]
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO = struct_NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
class struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS._fields_ = [
  ('linkMask', NvU64),
  ('errInfo', (NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO * 64)),
]
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS = struct_NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS
class struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('numRecoveries', (NvU32 * 64)),
]
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('remoteType', NvU32),
]
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('supportedCounts', NvU64),
  ('fatalErrorCounts', (NvU8 * 63)),
]
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS
class struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE(Struct): pass
struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE._fields_ = [
  ('errorsPerMinute', NvU32),
  ('timestamp', NvU32),
]
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE = struct_NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE
class struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('numDailyMaxNonfatalErrorRates', NvU32),
  ('dailyMaxNonfatalErrorRates', (NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5)),
  ('numMonthlyMaxNonfatalErrorRates', NvU32),
  ('monthlyMaxNonfatalErrorRates', (NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE * 5)),
]
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS._fields_ = [
  ('bEnabled', NvBool),
]
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS
class struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS._fields_ = [
  ('linkId', NvU8),
  ('params', NvU32),
]
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('powerState', NvU32),
]
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('powerState', NvU32),
]
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS
enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = CEnum(ctypes.c_uint32)
TLC_RX_LNK = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_RX_LNK', 0)
TLC_TX_SYS = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE.define('TLC_TX_SYS', 1)

NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE
enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = CEnum(ctypes.c_uint32)
TX_SYS_TX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_HW_ERR', 0)
TX_SYS_TX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_UR_ERR', 1)
TX_SYS_TX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE.define('TX_SYS_TX_RSP_STATUS_PRIV_ERR', 2)

NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE
enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = CEnum(ctypes.c_uint32)
RX_LNK_RX_RSP_STATUS_HW_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_HW_ERR', 0)
RX_LNK_RX_RSP_STATUS_UR_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_UR_ERR', 1)
RX_LNK_RX_RSP_STATUS_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE.define('RX_LNK_RX_RSP_STATUS_PRIV_ERR', 2)

NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE = enum_NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE
class union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE(ctypes.Union): pass
union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE._fields_ = [
  ('txSysErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_TX_SYS_REPORT_ERROR_TYPE),
  ('rxLnkErrorType', NV2080_CTRL_NVLINK_INJECT_TLC_RX_LNK_REPORT_ERROR_TYPE),
]
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE = union_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE
class struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('device', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_DEVICE),
  ('bBroadcast', NvBool),
  ('errorType', NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE),
]
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS
class struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('numLanes', NvU8),
  ('figureOfMeritValues', (NvU16 * 4)),
]
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS._fields_ = [
  ('peerMask', NvU32),
  ('bEnable', NvBool),
]
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS = struct_NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS
class struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS._fields_ = [
  ('linkId', NvU8),
  ('lane', NvU8),
  ('addr', NvU16),
  ('phyConfigData', NvU32),
]
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS
class struct_NV2080_CTRL_NVLINK_LANE_ERROR(Struct): pass
struct_NV2080_CTRL_NVLINK_LANE_ERROR._fields_ = [
  ('bValid', NvBool),
  ('eccErrorValue', NvU32),
  ('overflowed', NvBool),
]
NV2080_CTRL_NVLINK_LANE_ERROR = struct_NV2080_CTRL_NVLINK_LANE_ERROR
class struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR(Struct): pass
struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR._fields_ = [
  ('errorLane', (NV2080_CTRL_NVLINK_LANE_ERROR * 4)),
  ('eccDecFailed', NvU32),
  ('eccDecFailedOverflowed', NvBool),
]
NV2080_CTRL_NVLINK_LINK_ECC_ERROR = struct_NV2080_CTRL_NVLINK_LINK_ECC_ERROR
class struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('errorLink', (NV2080_CTRL_NVLINK_LINK_ECC_ERROR * 64)),
]
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES(Struct): pass
struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES._fields_ = [
  ('value', (NvU64 * 4)),
]
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES
class struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS._fields_ = [
  ('counterMask', NvU16),
  ('linkMask', NvU64),
  ('counters', (NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES * 64)),
]
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS
class struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS._fields_ = [
  ('bLockPowerMode', NvBool),
]
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS = struct_NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('counterValidMask', NvU32),
  ('counterValues', (NvU32 * 16)),
]
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('loopbackMode', NvU8),
]
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS
class struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO(Struct): pass
struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO._fields_ = [
  ('bValid', NvBool),
  ('passCount', NvU16),
  ('failCount', NvU16),
]
NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO = struct_NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO
class struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('refreshCount', (NV2080_CTRL_NVLINK_PHY_REFRESH_STATUS_INFO * 32)),
]
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS._fields_ = [
  ('linkMask', NvU32),
]
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS._fields_ = [
  ('bGet', NvBool),
  ('addr', NvU64),
]
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS
class struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS._fields_ = [
  ('discoveredLinks', NvU64),
  ('connectedLinksMask', NvU32),
  ('bridgeSensableLinks', NvU64),
  ('bridgedLinks', NvU32),
  ('initDisabledLinksMask', NvU32),
  ('vbiosDisabledLinkMask', NvU64),
  ('initializedLinks', NvU32),
  ('bEnableTrainingAtLoad', NvBool),
  ('bEnableSafeModeAtLoad', NvBool),
]
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS
class struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS._fields_ = [
  ('initDisabledLinksMask', NvU32),
  ('bSkipHwNvlinkDisable', NvBool),
]
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS = struct_NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS
enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = CEnum(ctypes.c_uint32)
NVLINK_EOM_CONTROL_START_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_START_EOM', 0)
NVLINK_EOM_CONTROL_END_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_END_EOM', 1)
NVLINK_EOM_CONTROL_CONFIG_EOM = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_CONFIG_EOM', 2)
NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND.define('NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE', 3)

NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND = enum_NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND
class struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT(Struct): pass
struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT._fields_ = [
  ('upper', NvU8),
  ('middle', NvU8),
  ('lower', NvU8),
  ('composite', NvU8),
]
NV2080_CTRL_NVLINK_EOM_MEASUREMENT = struct_NV2080_CTRL_NVLINK_EOM_MEASUREMENT
class struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS._fields_ = [
  ('cmd', NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND),
  ('linkId', NvU32),
  ('params', NvU32),
  ('measurements', (NV2080_CTRL_NVLINK_EOM_MEASUREMENT * 4)),
]
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS = struct_NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS
class struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS._fields_ = [
  ('data', (NvU8 * 5120)),
  ('dataSize', NvU32),
]
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS._fields_ = [
  ('l1Threshold', NvU32),
  ('l1ExitThreshold', NvU32),
]
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS._fields_ = [
  ('l1Threshold', NvU32),
  ('l1ExitThreshold', NvU32),
]
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS
class struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS._fields_ = [
  ('buffer', (NvU8 * 5120)),
  ('dataSize', NvU32),
]
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS = struct_NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS
class struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS._fields_ = [
  ('linkId', NvU32),
  ('bIsGpuDegraded', NvBool),
]
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS = struct_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS
class struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS._fields_ = [
  ('bIsEnoughNvLink', NvBool),
  ('numBridge', NvU32),
  ('bridgePresenceMask', NvU32),
]
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS = struct_NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS
class struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS._fields_ = [
  ('linkId', NvU32),
]
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS = struct_NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS
class struct_NV2080_CTRL_NVLINK_PORT_EVENT(Struct): pass
struct_NV2080_CTRL_NVLINK_PORT_EVENT._fields_ = [
  ('portEventType', NvU32),
  ('gpuId', NvU32),
  ('linkId', NvU32),
  ('time', NvU64),
]
NV2080_CTRL_NVLINK_PORT_EVENT = struct_NV2080_CTRL_NVLINK_PORT_EVENT
class struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS._fields_ = [
  ('portEventIndex', NvU64),
  ('nextPortEventIndex', NvU64),
  ('portEventCount', NvU32),
  ('bOverflow', NvBool),
  ('portEvent', (NV2080_CTRL_NVLINK_PORT_EVENT * 64)),
]
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS
class struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS._fields_ = [
  ('linkId', NvU32),
]
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS = struct_NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS
class struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS._fields_ = [
  ('bReducedNvlinkConfig', NvBool),
]
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS = struct_NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_DATA(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_DATA._fields_ = [
  ('data', (NvU8 * 496)),
]
NV2080_CTRL_NVLINK_PRM_DATA = struct_NV2080_CTRL_NVLINK_PRM_DATA
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('plane_ind', NvU8),
  ('admin_status', NvU8),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('swid', NvU8),
  ('e', NvU8),
  ('fd', NvU8),
  ('ps_e', NvU8),
  ('ls_e', NvU8),
  ('ee_ps', NvU8),
  ('ee_ls', NvU8),
  ('ee', NvU8),
  ('ase', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('lane_mask', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('local_tx_precoding_admin', NvU8),
  ('local_rx_precoding_admin', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('test_mode', NvBool),
  ('plane_ind', NvU8),
  ('port_type', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('fec_override_admin_10g_40g', NvU8),
  ('fec_override_admin_25g', NvU8),
  ('fec_override_admin_50g', NvU8),
  ('fec_override_admin_100g', NvU8),
  ('fec_override_admin_56g', NvU8),
  ('rs_fec_correction_bypass_admin', NvU8),
  ('fec_override_admin_200g_4x', NvU16),
  ('fec_override_admin_400g_8x', NvU16),
  ('fec_override_admin_50g_1x', NvU16),
  ('fec_override_admin_100g_2x', NvU16),
  ('fec_override_admin_400g_4x', NvU16),
  ('fec_override_admin_800g_8x', NvU16),
  ('fec_override_admin_100g_1x', NvU16),
  ('fec_override_admin_200g_2x', NvU16),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('l1_req_en', NvBool),
  ('l1_fw_req_en', NvBool),
  ('l1_cap_adv', NvBool),
  ('l1_fw_cap_adv', NvBool),
  ('hp_queues_bitmap', NvU32),
  ('l1_hw_active_time', NvU16),
  ('l1_hw_inactive_time', NvU16),
  ('qem', (NvU8 * 8)),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('access_reg_group', NvU8),
  ('feature_group', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('slot_index', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('slot_index', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('slot_index', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('slot_index', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('itre', NvBool),
  ('i_e', NvU8),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('protocol', NvU8),
  ('admin_mtu', NvU16),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('width', NvU8),
  ('plane_ind', NvU8),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('m_lane_m', NvBool),
  ('rxtx', NvBool),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('trap_id', NvU16),
  ('action', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('port_type', NvU8),
  ('plane_ind', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('page_select', NvU8),
  ('module_info_ext', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('le', NvBool),
  ('port_type', NvU8),
  ('lane', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('sw', NvBool),
  ('dm_ig', NvBool),
  ('p', NvBool),
  ('e', NvBool),
  ('modulation', NvU8),
  ('prbs_mode_admin', NvU8),
  ('prbs_fec_admin', NvBool),
  ('lane_rate_admin', NvU16),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('grp', NvU8),
  ('port_type', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('swid', NvU8),
  ('prio_tc', NvU8),
  ('grp_profile', NvU8),
  ('plane_ind', NvU8),
  ('counters_cap', NvBool),
  ('lp_gl', NvBool),
  ('clr', NvBool),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('port_type', NvU8),
  ('phy_test_mode_admin', NvU8),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('swid', NvU8),
  ('plane_ind', NvU8),
  ('phy_status_admin', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('plane_ind', NvU8),
  ('port_type', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('hist_type', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('c_db', NvBool),
  ('port_type', NvU8),
  ('lane_speed', NvU8),
  ('lane', NvU8),
  ('tx_policy', NvBool),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('lp_msb', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('le', NvBool),
  ('port_type', NvU8),
  ('lane', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
  ('sw', NvBool),
  ('dm_ig', NvBool),
  ('p', NvBool),
  ('s', NvBool),
  ('e', NvBool),
  ('modulation', NvU8),
  ('prbs_mode_admin', NvU8),
  ('lane_rate_oper', NvU16),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('proto_mask', NvU8),
  ('transmit_allowed', NvBool),
  ('plane_ind', NvU8),
  ('port_type', NvU8),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('tx_ready_e', NvU8),
  ('ee_tx_ready', NvBool),
  ('an_disable_admin', NvBool),
  ('ext_eth_proto_admin', NvU32),
  ('eth_proto_admin', NvU32),
  ('ib_proto_admin', NvU16),
  ('ib_link_width_admin', NvU16),
  ('xdr_2x_slow_admin', NvBool),
  ('force_lt_frames_admin', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('port_type', NvU8),
  ('lane', NvU8),
  ('lp_msb', NvU8),
  ('pnat', NvU8),
  ('local_port', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('admin_status', NvU8),
  ('module', NvU8),
  ('slot_index', NvU8),
  ('rst', NvBool),
  ('e', NvU8),
  ('ee', NvBool),
  ('ase', NvBool),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('plane_ind', NvU8),
  ('port_type', NvU8),
  ('op_mod', NvBool),
  ('apply_im', NvBool),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('lb_en', NvU16),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS._fields_ = [
  ('counterMask', (NvU64 * 2)),
]
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('segment_type', NvU16),
  ('seq_num', NvU8),
  ('vhca_id_valid', NvBool),
  ('inline_dump', NvBool),
  ('vhca_id', NvU16),
  ('index1', NvU32),
  ('index2', NvU32),
  ('num_of_obj2', NvU16),
  ('num_of_obj1', NvU16),
  ('device_opaque', NvU64),
  ('mkey', NvU32),
  ('address', NvU64),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('trace_owner', NvBool),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('trace_mode', NvU8),
  ('log_trace_buffer_size', NvU8),
  ('trace_mkey', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('modify_field_select', NvU16),
  ('arm_event', NvBool),
  ('trace_status', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('enable_all', NvU8),
  ('log_delay', NvU8),
  ('source_id_bitmask', (NvU32 * 8)),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('log_level', NvU8),
  ('log_bit_mask', NvU32),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('warning_inactive_time', NvU8),
  ('warning_active_time', NvU8),
  ('critical_inactive_time', NvU8),
  ('critical_active_time', NvU8),
  ('cc', NvBool),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('cnt_64bit', NvU8),
  ('stop_at_ff', NvBool),
  ('counter_rst', NvBool),
  ('counter_en', NvBool),
  ('force_count_mask', NvU8),
  ('cnt_type', (NvU8 * 8)),
  ('cnt_val', (NvU8 * 8)),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS
class struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS._fields_ = [
  ('bWrite', NvBool),
  ('prm', NV2080_CTRL_NVLINK_PRM_DATA),
  ('ib_port', NvU16),
  ('lp_msb', NvU8),
  ('local_port', NvU8),
  ('split_num', NvU8),
]
NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS = struct_NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS._fields_ = [
  ('ibGuid', (NvU8 * 16)),
  ('rackGuid', (NvU8 * 16)),
  ('chassisPhysicalSlotNumber', NvU8),
  ('computeSlotIndex', NvU8),
  ('nodeIndex', NvU8),
  ('peerType', NvU8),
  ('moduleId', NvU8),
]
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS
class struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD(Struct): pass
struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD._fields_ = [
  ('pllIndex', NvU8),
  ('address', NvU16),
]
NV2080_CTRL_NVLINK_UPHY_CLN_CMD = struct_NV2080_CTRL_NVLINK_UPHY_CLN_CMD
class struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('uphyCmd', (NV2080_CTRL_NVLINK_UPHY_CLN_CMD * 18)),
  ('data', (NvU32 * 18)),
]
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS = struct_NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS._fields_ = [
  ('rbmModesList', (NvU8 * 23)),
  ('rbmTotalModes', NvU8),
]
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS
class struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS._fields_ = [
  ('rbmMode', NvU8),
]
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS._fields_ = [
  ('rbmMode', NvU8),
]
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS._fields_ = [
  ('localDeviceInfo', NV2080_CTRL_NVLINK_DEVICE_INFO),
]
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS = struct_NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS
enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = CEnum(ctypes.c_uint32)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL', 0)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL', 1)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL', 2)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION', 3)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT', 4)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL', 5)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE', 6)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL', 7)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL', 8)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR', 9)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL', 10)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL', 11)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL', 12)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL', 13)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL', 14)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL', 15)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL', 16)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL', 17)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL', 18)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL', 19)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL', 20)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY.define('NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX', 21)

NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY = enum_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY
class struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('severity', NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY),
]
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS = struct_NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS
enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = CEnum(ctypes.c_uint32)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED', 0)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE', 1)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED', 2)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED', 3)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE.define('NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE', 4)

NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE = enum_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE
class struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG(Struct): pass
struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG._fields_ = [
  ('mode', NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE),
  ('toggleActiveTime', NvU8),
  ('toggleInactiveTime', NvU8),
  ('bTrigger', NvBool),
]
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG = struct_NV2080_CTRL_NVLINK_L1_FORCE_CONFIG
class struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('config', NV2080_CTRL_NVLINK_L1_FORCE_CONFIG),
]
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS
class struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS(Struct): pass
struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS._fields_ = [
  ('linkMask', NvU32),
  ('config', (NV2080_CTRL_NVLINK_L1_FORCE_CONFIG * 32)),
]
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS = struct_NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS
class struct_NV2080_CTRL_PERF_BOOST_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_BOOST_PARAMS._fields_ = [
  ('flags', NvU32),
  ('duration', NvU32),
]
NV2080_CTRL_PERF_BOOST_PARAMS = struct_NV2080_CTRL_PERF_BOOST_PARAMS
class struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS._fields_ = [
  ('bAcquire', NvBool),
]
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS = struct_NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS
class struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS._fields_ = [
  ('powerState', NvU32),
]
NV2080_CTRL_PERF_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_POWERSTATE_PARAMS
class struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS._fields_ = [
  ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS),
]
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS
class struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS._fields_ = [
  ('powerState', NvU32),
]
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS = struct_NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS
enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT = CEnum(ctypes.c_uint32)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM', 0)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342 = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_WAR_BUG_1785342', 1)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_GLOBAL', 2)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_OS', 3)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_PROFILE', 4)
NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT.define('NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS', 5)

NV2080_CTRL_PERF_RATED_TDP_CLIENT = enum_NV2080_CTRL_PERF_RATED_TDP_CLIENT
enum_NV2080_CTRL_PERF_RATED_TDP_ACTION = CEnum(ctypes.c_uint32)
NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT', 0)
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED', 1)
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT', 2)
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LOCK', 3)
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION.define('NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR', 4)

NV2080_CTRL_PERF_RATED_TDP_ACTION = enum_NV2080_CTRL_PERF_RATED_TDP_ACTION
enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = CEnum(ctypes.c_uint32)
NV2080_CTRL_PERF_VPSTATE_RATED_TDP = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_RATED_TDP', 0)
NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST', 1)
NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE.define('NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES', 2)

NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE = enum_NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE
class struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST(Struct): pass
struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST._fields_ = [
  ('action', NV2080_CTRL_PERF_RATED_TDP_ACTION),
  ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE),
]
NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST = struct_NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS(Struct): pass
class struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm(Struct): pass
struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm._fields_ = [
  ('clientActiveMask', NvU32),
  ('bRegkeyLimitRatedTdp', NvU8),
]
struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS._fields_ = [
  ('rm', struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_rm),
  ('output', NV2080_CTRL_PERF_RATED_TDP_ACTION),
  ('outputVPstate', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE),
  ('inputs', (NV2080_CTRL_PERF_RATED_TDP_ACTION * 5)),
  ('vPstateTypes', (NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE * 5)),
]
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS
class struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS._fields_ = [
  ('client', NV2080_CTRL_PERF_RATED_TDP_CLIENT),
  ('input', NV2080_CTRL_PERF_RATED_TDP_ACTION),
  ('vPstateType', NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE),
]
NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS = struct_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS
class struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE(Struct): pass
struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE._fields_ = [
  ('util', NvU32),
  ('vgpuScale', NvU32),
  ('procId', NvU32),
  ('subProcessID', NvU32),
  ('subProcessName', (ctypes.c_char * 100)),
  ('pOsPidInfo', NvU64),
]
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE
class struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE(Struct): pass
struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE._fields_ = [
  ('base', NV2080_CTRL_GPUMON_SAMPLE),
  ('fb', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
  ('gr', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
  ('nvenc', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
  ('nvdec', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
  ('nvjpg', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
  ('nvofa', NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE),
]
NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE = struct_NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM = struct_NV2080_CTRL_GPUMON_SAMPLES
class struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS._fields_ = [
  ('type', NvU8),
  ('bufSize', NvU32),
  ('count', NvU32),
  ('tracker', NvU32),
  ('samples', (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE * 72)),
]
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS
class struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS._fields_ = [
  ('prevPstate', NvU32),
  ('action', NvU32),
]
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS = struct_NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS
class struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS._fields_ = [
  ('bGpuIsIdle', NvBool),
  ('bRestoreToMax', NvBool),
  ('idleTimeUs', NvU64),
  ('busyTimeUs', NvU64),
]
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS = struct_NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS
class struct_NV2080_CTRL_PERF_GET_CLK_INFO(Struct): pass
struct_NV2080_CTRL_PERF_GET_CLK_INFO._fields_ = [
  ('flags', NvU32),
  ('domain', NvU32),
  ('currentFreq', NvU32),
  ('defaultFreq', NvU32),
  ('minFreq', NvU32),
  ('maxFreq', NvU32),
]
NV2080_CTRL_PERF_GET_CLK_INFO = struct_NV2080_CTRL_PERF_GET_CLK_INFO
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS._fields_ = [
  ('level', NvU32),
  ('flags', NvU32),
  ('perfGetClkInfoList', NvP64),
  ('perfGetClkInfoListSize', NvU32),
]
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS
class struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS._fields_ = [
  ('level', NvU32),
  ('flags', NvU32),
  ('perfGetClkInfoList', (NV2080_CTRL_PERF_GET_CLK_INFO * 32)),
  ('perfGetClkInfoListSize', NvU32),
]
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS = struct_NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS
enum_NV2080_CTRL_CMD_PERF_VID_ENG = CEnum(ctypes.c_uint32)
NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVENC', 1)
NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC', 2)
NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG', 3)
NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = enum_NV2080_CTRL_CMD_PERF_VID_ENG.define('NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA', 4)

NV2080_CTRL_CMD_PERF_VID_ENG = enum_NV2080_CTRL_CMD_PERF_VID_ENG
class struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS._fields_ = [
  ('engineType', NV2080_CTRL_CMD_PERF_VID_ENG),
  ('clkPercentBusy', NvU32),
  ('samplingPeriodUs', NvU32),
]
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS = struct_NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS
class struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS._fields_ = [
  ('powerStateInfo', NV2080_CTRL_PERF_POWERSTATE_PARAMS),
]
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS
class struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS._fields_ = [
  ('videoEvent', NvU32),
]
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS = struct_NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS
NV2080_CTRL_PERF_PSTATES_ID = ctypes.c_uint32
class struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS(Struct): pass
struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS._fields_ = [
  ('currPstate', NvU32),
]
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS = struct_NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS
class struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS._fields_ = [
  ('moduleId', NvU32),
  ('nvswitchSupport', NvU8),
]
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS = struct_NV2080_CTRL_PMGR_MODULE_INFO_PARAMS
enum_NV2080_CTRL_GC6_FLAVOR_ID = CEnum(ctypes.c_uint32)
NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID', 0)
NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS', 1)
NV2080_CTRL_GC6_FLAVOR_ID_MAX = enum_NV2080_CTRL_GC6_FLAVOR_ID.define('NV2080_CTRL_GC6_FLAVOR_ID_MAX', 4)

NV2080_CTRL_GC6_FLAVOR_ID = enum_NV2080_CTRL_GC6_FLAVOR_ID
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS(Struct): pass
class struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params(Struct): pass
struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params._fields_ = [
  ('bIsRTD3Transition', NvBool),
  ('bIsRTD3CoreRailPowerCut', NvBool),
  ('bSkipPstateSanity', NvBool),
]
struct_NV2080_CTRL_GC6_ENTRY_PARAMS._fields_ = [
  ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID),
  ('stepMask', NvU32),
  ('params', struct_NV2080_CTRL_GC6_ENTRY_PARAMS_params),
]
NV2080_CTRL_GC6_ENTRY_PARAMS = struct_NV2080_CTRL_GC6_ENTRY_PARAMS
class struct_NV2080_CTRL_GC6_EXIT_PARAMS(Struct): pass
class struct_NV2080_CTRL_GC6_EXIT_PARAMS_params(Struct): pass
struct_NV2080_CTRL_GC6_EXIT_PARAMS_params._fields_ = [
  ('bIsGpuSelfWake', NvBool),
  ('bIsRTD3Transition', NvBool),
  ('bIsRTD3HotTransition', NvBool),
]
struct_NV2080_CTRL_GC6_EXIT_PARAMS._fields_ = [
  ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID),
  ('params', struct_NV2080_CTRL_GC6_EXIT_PARAMS_params),
]
NV2080_CTRL_GC6_EXIT_PARAMS = struct_NV2080_CTRL_GC6_EXIT_PARAMS
enum_NV2080_CTRL_GC6_STEP_ID = CEnum(ctypes.c_uint32)
NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_SR_ENTRY', 0)
NV2080_CTRL_GC6_STEP_ID_GPU_OFF = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_GPU_OFF', 1)
NV2080_CTRL_GC6_STEP_ID_MAX = enum_NV2080_CTRL_GC6_STEP_ID.define('NV2080_CTRL_GC6_STEP_ID_MAX', 2)

NV2080_CTRL_GC6_STEP_ID = enum_NV2080_CTRL_GC6_STEP_ID
class struct_NV2080_CTRL_GC6_FLAVOR_INFO(Struct): pass
struct_NV2080_CTRL_GC6_FLAVOR_INFO._fields_ = [
  ('flavorId', NV2080_CTRL_GC6_FLAVOR_ID),
  ('stepMask', NvU32),
]
NV2080_CTRL_GC6_FLAVOR_INFO = struct_NV2080_CTRL_GC6_FLAVOR_INFO
class struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS(Struct): pass
struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('virtAddress', NvU64),
  ('bufferPtr', NvP64),
  ('bufferSize', NvU32),
]
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS = struct_NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS
class struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS(Struct): pass
struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS._fields_ = [
  ('errorCount', NvU32),
]
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS
class struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS(Struct): pass
struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS._fields_ = [
  ('whichBuffer', NvU32),
  ('outputRecordSize', NvU32),
  ('recordBuffer', (NvU8 * 8192)),
]
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS = struct_NV2080_CTRL_RC_GET_ERROR_V2_PARAMS
class struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS._fields_ = [
  ('watchdogStatusFlags', NvU32),
]
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS = struct_NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS
class struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS._fields_ = [
  ('rcEnable', NvU32),
]
NV2080_CTRL_CMD_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
NV2080_CTRL_SET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
NV2080_CTRL_GET_RC_RECOVERY_PARAMS = struct_NV2080_CTRL_CMD_RC_RECOVERY_PARAMS
class struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS(Struct): pass
struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS._fields_ = [
  ('cmd', NvU32),
  ('status', NvS32),
]
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS = struct_NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS
class struct_NV2080_CTRL_CMD_RC_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_RC_INFO_PARAMS._fields_ = [
  ('rcMode', NvU32),
  ('rcBreak', NvU32),
]
NV2080_CTRL_CMD_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
NV2080_CTRL_SET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
NV2080_CTRL_GET_RC_INFO_PARAMS = struct_NV2080_CTRL_CMD_RC_INFO_PARAMS
class struct_RM_GSP_SPDM_CMD_CC_INIT(Struct): pass
struct_RM_GSP_SPDM_CMD_CC_INIT._fields_ = [
  ('cmdType', NvU8),
]
RM_GSP_SPDM_CMD_CC_INIT = struct_RM_GSP_SPDM_CMD_CC_INIT
PRM_GSP_SPDM_CMD_CC_INIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT)
class struct_RM_GSP_SPDM_CMD_CC_DEINIT(Struct): pass
struct_RM_GSP_SPDM_CMD_CC_DEINIT._fields_ = [
  ('cmdType', NvU8),
]
RM_GSP_SPDM_CMD_CC_DEINIT = struct_RM_GSP_SPDM_CMD_CC_DEINIT
PRM_GSP_SPDM_CMD_CC_DEINIT = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_DEINIT)
class struct_RM_GSP_SPDM_CMD_CC_CTRL(Struct): pass
struct_RM_GSP_SPDM_CMD_CC_CTRL._fields_ = [
  ('cmdType', NvU8),
]
RM_GSP_SPDM_CMD_CC_CTRL = struct_RM_GSP_SPDM_CMD_CC_CTRL
PRM_GSP_SPDM_CMD_CC_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_CTRL)
class struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA(Struct): pass
struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA._fields_ = [
  ('cmdType', NvU8),
  ('rsvd0', (NvU32 * 2)),
  ('rsvd1', NvU32),
  ('rsvd2', (ctypes.c_char * 9)),
  ('rsvd3', (ctypes.c_char * 5)),
  ('rsvd4', (ctypes.c_char * 5)),
  ('rsvd5', (ctypes.c_char * 5)),
  ('rsvd6', (ctypes.c_char * 2)),
  ('rsvd7', (ctypes.c_char * 16)),
  ('rsvd8', (NvU32 * 2)),
]
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA = struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA
PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_INIT_RM_DATA)
class struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL(Struct): pass
struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL._fields_ = [
  ('cmdType', NvU8),
  ('bEnable', NvBool),
]
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL
PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL)
class struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST(Struct): pass
class struct_CC_KMB(Struct): pass
CC_KMB = struct_CC_KMB
class struct_CC_AES_CRYPTOBUNDLE(Struct): pass
CC_AES_CRYPTOBUNDLE = struct_CC_AES_CRYPTOBUNDLE
struct_CC_AES_CRYPTOBUNDLE._fields_ = [
  ('iv', (NvU32 * 3)),
  ('key', (NvU32 * 8)),
  ('ivMask', (NvU32 * 3)),
]
class struct_CC_KMB_0(ctypes.Union): pass
class struct_CC_HMAC_CRYPTOBUNDLE(Struct): pass
CC_HMAC_CRYPTOBUNDLE = struct_CC_HMAC_CRYPTOBUNDLE
struct_CC_HMAC_CRYPTOBUNDLE._fields_ = [
  ('nonce', (NvU32 * 8)),
  ('key', (NvU32 * 8)),
]
struct_CC_KMB_0._fields_ = [
  ('hmacBundle', CC_HMAC_CRYPTOBUNDLE),
  ('decryptBundle', CC_AES_CRYPTOBUNDLE),
]
struct_CC_KMB._anonymous_ = ['_0']
struct_CC_KMB._fields_ = [
  ('encryptBundle', CC_AES_CRYPTOBUNDLE),
  ('_0', struct_CC_KMB_0),
  ('bIsWorkLaunch', NvBool),
]
struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST._fields_ = [
  ('cmdType', NvU8),
  ('isEnc', NvU8),
  ('kmb', CC_KMB),
  ('text', (NvU8 * 16)),
  ('authTag', (NvU8 * 16)),
]
RM_GSP_SPDM_CMD_FIPS_SELFTEST = struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST
PRM_GSP_SPDM_CMD_FIPS_SELFTEST = ctypes.POINTER(struct_RM_GSP_SPDM_CMD_FIPS_SELFTEST)
class union_RM_GSP_SPDM_CMD(ctypes.Union): pass
union_RM_GSP_SPDM_CMD._fields_ = [
  ('cmdType', NvU8),
  ('ccInit', RM_GSP_SPDM_CMD_CC_INIT),
  ('ccDeinit', RM_GSP_SPDM_CMD_CC_DEINIT),
  ('ccCtrl', RM_GSP_SPDM_CMD_CC_CTRL),
  ('rmDataInitCmd', RM_GSP_SPDM_CMD_CC_INIT_RM_DATA),
  ('ccHeartbeatCtrl', RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL),
  ('ccFipsTest', RM_GSP_SPDM_CMD_FIPS_SELFTEST),
]
RM_GSP_SPDM_CMD = union_RM_GSP_SPDM_CMD
PRM_GSP_SPDM_CMD = ctypes.POINTER(union_RM_GSP_SPDM_CMD)
class struct_RM_GSP_SPDM_MSG(Struct): pass
struct_RM_GSP_SPDM_MSG._fields_ = [
  ('msgType', NvU8),
  ('status', NvU32),
  ('rsvd1', NvU32),
  ('rsvd2', NvU32),
  ('rsvd3', NvU32),
  ('rsvd4', NvU32),
  ('rsvd5', NvU32),
]
RM_GSP_SPDM_MSG = struct_RM_GSP_SPDM_MSG
PRM_GSP_SPDM_MSG = ctypes.POINTER(struct_RM_GSP_SPDM_MSG)
class struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS._fields_ = [
  ('index', NvU8),
  ('cmd', RM_GSP_SPDM_CMD),
  ('msg', RM_GSP_SPDM_MSG),
]
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS
class struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS(Struct): pass
struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS._fields_ = [
  ('transcript', (NvU8 * 9216)),
  ('transcriptSize', NvU32),
]
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS = struct_NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS
class struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS._fields_ = [
  ('time_nsec', NvU64),
  ('flags', NvU32),
]
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS
class struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS(Struct): pass
struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS._fields_ = [
  ('time_nsec', NvU64),
]
NV2080_CTRL_TIMER_GET_TIME_PARAMS = struct_NV2080_CTRL_TIMER_GET_TIME_PARAMS
class struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS(Struct): pass
struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS._fields_ = [
  ('tmr_offset', NvU32),
]
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS = struct_NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS
class struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE(Struct): pass
struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE._fields_ = [
  ('cpuTime', NvU64),
  ('gpuTime', NvU64),
]
NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE = struct_NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE
class struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS._fields_ = [
  ('cpuClkId', NvU8),
  ('sampleCount', NvU8),
  ('samples', (NV2080_CTRL_TIMER_GPU_CPU_TIME_SAMPLE * 16)),
]
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS = struct_NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS
class struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS(Struct): pass
struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS._fields_ = [
  ('bSetMaxFreq', NvBool),
]
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS = struct_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS
class struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS._fields_ = [
  ('action', NvU32),
]
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS = struct_NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS
class struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS._fields_ = [
  ('action', NvU32),
]
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS = struct_NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS
class struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS._fields_ = [
  ('bEnter', NvBool),
]
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS = struct_NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS
class struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS._fields_ = [
  ('hNotifierResource', NvHandle),
  ('notifyDataSize', NvU32),
  ('hNotifyDataMemory', NvHandle),
  ('perfmonIdCount', NvU32),
  ('snapshotBufferSize', NvU32),
  ('hSnapshotMemory', NvHandle),
]
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS = struct_NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS
class struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS._fields_ = [
  ('bVidmemPersistent', NvBool),
]
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS
class struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS._fields_ = [
  ('bUpdateTGP', NvBool),
]
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS = struct_NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [
  ('dbdf', NvU32),
  ('gfid', NvU32),
  ('vgpuType', NvU32),
  ('vmPid', NvU32),
  ('swizzId', NvU32),
  ('numChannels', NvU32),
  ('numPluginChannels', NvU32),
  ('chidOffset', (NvU32 * 84)),
  ('bDisableDefaultSmcExecPartRestore', NvBool),
  ('numGuestFbSegments', NvU32),
  ('guestFbPhysAddrList', (NvU64 * 384)),
  ('guestFbLengthList', (NvU64 * 384)),
  ('pluginHeapMemoryPhysAddr', NvU64),
  ('pluginHeapMemoryLength', NvU64),
  ('ctrlBuffOffset', NvU64),
  ('initTaskLogBuffOffset', NvU64),
  ('initTaskLogBuffSize', NvU64),
  ('vgpuTaskLogBuffOffset', NvU64),
  ('vgpuTaskLogBuffSize', NvU64),
  ('kernelLogBuffOffset', NvU64),
  ('kernelLogBuffSize', NvU64),
  ('migRmHeapMemoryPhysAddr', NvU64),
  ('migRmHeapMemoryLength', NvU64),
  ('bDeviceProfilingEnabled', NvBool),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS._fields_ = [
  ('gfid', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS(Struct): pass
class struct_NVA081_CTRL_VGPU_INFO(Struct): pass
NVA081_CTRL_VGPU_INFO = struct_NVA081_CTRL_VGPU_INFO
struct_NVA081_CTRL_VGPU_INFO._fields_ = [
  ('vgpuType', NvU32),
  ('vgpuName', (NvU8 * 32)),
  ('vgpuClass', (NvU8 * 32)),
  ('vgpuSignature', (NvU8 * 128)),
  ('license', (NvU8 * 128)),
  ('maxInstance', NvU32),
  ('numHeads', NvU32),
  ('maxResolutionX', NvU32),
  ('maxResolutionY', NvU32),
  ('maxPixels', NvU32),
  ('frlConfig', NvU32),
  ('cudaEnabled', NvU32),
  ('eccSupported', NvU32),
  ('gpuInstanceSize', NvU32),
  ('multiVgpuSupported', NvU32),
  ('vdevId', NvU64),
  ('pdevId', NvU64),
  ('profileSize', NvU64),
  ('fbLength', NvU64),
  ('gspHeapSize', NvU64),
  ('fbReservation', NvU64),
  ('mappableVideoSize', NvU64),
  ('encoderCapacity', NvU32),
  ('bar1Length', NvU64),
  ('frlEnable', NvU32),
  ('adapterName', (NvU8 * 64)),
  ('adapterName_Unicode', (NvU16 * 64)),
  ('shortGpuNameString', (NvU8 * 64)),
  ('licensedProductName', (NvU8 * 128)),
  ('vgpuExtraParams', (NvU32 * 1024)),
  ('ftraceEnable', NvU32),
  ('gpuDirectSupported', NvU32),
  ('nvlinkP2PSupported', NvU32),
  ('multiVgpuExclusive', NvU32),
  ('exclusiveType', NvU32),
  ('exclusiveSize', NvU32),
  ('gpuInstanceProfileId', NvU32),
  ('placementSize', NvU32),
  ('homogeneousPlacementCount', NvU32),
  ('homogeneousPlacementIds', (NvU32 * 32)),
  ('heterogeneousPlacementCount', NvU32),
  ('heterogeneousPlacementIds', (NvU32 * 32)),
]
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS._fields_ = [
  ('discardVgpuTypes', NvBool),
  ('vgpuInfoCount', NvU32),
  ('vgpuInfo', (NVA081_CTRL_VGPU_INFO * 64)),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS
class struct_NV2080_GUEST_VM_INFO(Struct): pass
enum_GUEST_VM_INFO_STATE = CEnum(ctypes.c_uint32)
GUEST_VM_INFO_STATE_UNINITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_UNINITIALIZED', 0)
GUEST_VM_INFO_STATE_INITIALIZED = enum_GUEST_VM_INFO_STATE.define('GUEST_VM_INFO_STATE_INITIALIZED', 1)

GUEST_VM_INFO_STATE = enum_GUEST_VM_INFO_STATE
struct_NV2080_GUEST_VM_INFO._fields_ = [
  ('vmPid', NvU32),
  ('guestOs', NvU32),
  ('migrationProhibited', NvU32),
  ('guestNegotiatedVgpuVersion', NvU32),
  ('frameRateLimit', NvU32),
  ('licensed', NvBool),
  ('licenseState', NvU32),
  ('licenseExpiryTimestamp', NvU32),
  ('licenseExpiryStatus', NvU8),
  ('guestDriverVersion', (NvU8 * 32)),
  ('guestDriverBranch', (NvU8 * 32)),
  ('guestVmInfoState', GUEST_VM_INFO_STATE),
]
NV2080_GUEST_VM_INFO = struct_NV2080_GUEST_VM_INFO
class struct_NV2080_HOST_VGPU_DEVICE(Struct): pass
struct_NV2080_HOST_VGPU_DEVICE._fields_ = [
  ('gfid', NvU32),
  ('vgpuPciId', NvU64),
  ('vgpuDeviceInstanceId', NvU32),
  ('fbUsed', NvU64),
  ('encoderCapacity', NvU32),
  ('eccState', NvU32),
  ('bDriverLoaded', NvBool),
]
NV2080_HOST_VGPU_DEVICE = struct_NV2080_HOST_VGPU_DEVICE
class struct_NV2080_VGPU_GUEST(Struct): pass
struct_NV2080_VGPU_GUEST._fields_ = [
  ('guestVmInfo', NV2080_GUEST_VM_INFO),
  ('vgpuDevice', NV2080_HOST_VGPU_DEVICE),
]
NV2080_VGPU_GUEST = struct_NV2080_VGPU_GUEST
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS._fields_ = [
  ('numVgpu', NvU32),
  ('vgpuGuest', (NV2080_VGPU_GUEST * 32)),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS._fields_ = [
  ('gfid', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS
class struct_NV2080_VGPU_FB_USAGE(Struct): pass
struct_NV2080_VGPU_FB_USAGE._fields_ = [
  ('gfid', NvU32),
  ('fbUsed', NvU64),
]
NV2080_VGPU_FB_USAGE = struct_NV2080_VGPU_FB_USAGE
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS._fields_ = [
  ('vgpuCount', NvU32),
  ('vgpuFbUsage', (NV2080_VGPU_FB_USAGE * 32)),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('encoderCapacity', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS._fields_ = [
  ('gfid', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS._fields_ = [
  ('pgpuString', (NvU8 * 256)),
  ('pgpuStringSize', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS._fields_ = [
  ('bIsMigrationSupported', NvBool),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS._fields_ = [
  ('bSupportHeterogeneousTimeSlicedVgpuTypes', NvBool),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS._fields_ = [
  ('gfid', NvU32),
  ('flags', NvU32),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS._fields_ = [
  ('bFlrDisabled', NvBool),
]
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS = struct_NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS
class struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS(Struct): pass
struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS._fields_ = [
  ('bHeterogeneousMode', NvBool),
]
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS = struct_NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS._fields_ = [
  ('action', NvU32),
]
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS._fields_ = [
  ('value', NvU32),
]
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS._fields_ = [
  ('exceptionMask', NvU32),
]
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS
class struct_NV83DE_SM_ERROR_STATE_REGISTERS(Struct): pass
struct_NV83DE_SM_ERROR_STATE_REGISTERS._fields_ = [
  ('hwwGlobalEsr', NvU32),
  ('hwwWarpEsr', NvU32),
  ('hwwWarpEsrPc', NvU32),
  ('hwwGlobalEsrReportMask', NvU32),
  ('hwwWarpEsrReportMask', NvU32),
  ('hwwEsrAddr', NvU64),
  ('hwwWarpEsrPc64', NvU64),
  ('hwwCgaEsr', NvU32),
  ('hwwCgaEsrReportMask', NvU32),
]
NV83DE_SM_ERROR_STATE_REGISTERS = struct_NV83DE_SM_ERROR_STATE_REGISTERS
class struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [
  ('hTargetChannel', NvHandle),
  ('smID', NvU32),
  ('smErrorState', NV83DE_SM_ERROR_STATE_REGISTERS),
]
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS
class struct_NV83DE_MMU_FAULT_INFO(Struct): pass
struct_NV83DE_MMU_FAULT_INFO._fields_ = [
  ('valid', NvBool),
  ('faultInfo', NvU32),
]
NV83DE_MMU_FAULT_INFO = struct_NV83DE_MMU_FAULT_INFO
class struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS._fields_ = [
  ('hTargetChannel', NvHandle),
  ('numSMsToRead', NvU32),
  ('smErrorStateArray', (NV83DE_SM_ERROR_STATE_REGISTERS * 100)),
  ('mmuFaultInfo', NvU32),
  ('mmuFault', NV83DE_MMU_FAULT_INFO),
  ('startingSM', NvU32),
]
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS
class struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS._fields_ = [
  ('hTargetChannel', NvHandle),
  ('smID', NvU32),
]
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS
class struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS._fields_ = [
  ('hTargetChannel', NvHandle),
  ('numSMsToClear', NvU32),
]
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS = struct_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS
class struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS(Struct): pass
struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS._fields_ = [
  ('waitForEvent', NvU32),
  ('hResidentChannel', NvHandle),
]
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS._fields_ = [
  ('stopTriggerType', NvU32),
]
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS._fields_ = [
  ('singleStepHandling', NvU32),
]
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS
class struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS._fields_ = [
  ('hMemory', NvU32),
  ('length', NvU32),
  ('offset', NvU64),
  ('buffer', NvP64),
]
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS
class struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS._fields_ = [
  ('hMemory', NvU32),
  ('length', NvU32),
  ('offset', NvU64),
  ('buffer', NvP64),
]
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS = struct_NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS
class struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS._fields_ = [
  ('hChannel', NvHandle),
  ('hSubdevice', NvHandle),
]
NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_HANDLES_PARAMS
class struct_NV83DE_CTRL_DEBUG_ACCESS_OP(Struct): pass
struct_NV83DE_CTRL_DEBUG_ACCESS_OP._fields_ = [
  ('gpuVA', NvU64),
  ('pCpuVA', NvP64),
  ('size', NvU32),
  ('valid', NvU32),
]
NV83DE_CTRL_DEBUG_ACCESS_OP = struct_NV83DE_CTRL_DEBUG_ACCESS_OP
class struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS(Struct): pass
struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS._fields_ = [
  ('count', NvU32),
  ('opsBuffer', (NV83DE_CTRL_DEBUG_ACCESS_OP * 64)),
]
NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS = struct_NV83DE_CTRL_DEBUG_ACCESS_SURFACE_PARAMETERS
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP._fields_ = [
  ('gpuVA', NvU64),
  ('size', NvU32),
]
NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP
class struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS._fields_ = [
  ('vaLo', NvU64),
  ('vaHi', NvU64),
  ('count', NvU32),
  ('hasMore', NvU32),
  ('opsBuffer', (NV83DE_CTRL_DEBUG_GET_MAPPINGS_OP * 64)),
]
NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS = struct_NV83DE_CTRL_DEBUG_GET_MAPPINGS_PARAMETERS
class struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS._fields_ = [
  ('bNonTransactional', NvBool),
  ('regOpCount', NvU32),
  ('regOps', (NV2080_CTRL_GPU_REG_OP * 100)),
]
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS = struct_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [
  ('action', NvU32),
]
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS
class struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS._fields_ = [
  ('value', NvU32),
]
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS._fields_ = [
  ('smID', NvU32),
  ('bSingleStep', NvBool),
]
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS._fields_ = [
  ('smID', NvU32),
  ('bStopTrigger', NvBool),
]
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS._fields_ = [
  ('smID', NvU32),
  ('bRunTrigger', NvBool),
]
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS._fields_ = [
  ('smID', NvU32),
  ('bSkipIdleWarpDetect', NvBool),
]
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS
class struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS._fields_ = [
  ('bInTrapMode', NvBool),
  ('bCrsFlushDone', NvBool),
  ('bRunTriggerInProgress', NvBool),
  ('bComputeContext', NvBool),
  ('bLockedDown', NvBool),
]
NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS = struct_NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS
class struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS._fields_ = [
  ('smID', NvU32),
  ('smDebuggerStatus', NV83DE_CTRL_DEBUG_SINGLE_SM_DEBUGGER_STATUS),
]
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY(Struct): pass
struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY._fields_ = [
  ('hMemory', NvHandle),
  ('length', NvU32),
  ('memOffset', NvU64),
  ('dataOffset', NvU32),
  ('status', NV_STATUS),
]
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY
class struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS._fields_ = [
  ('pData', NvP64),
  ('dataLength', NvU32),
  ('count', NvU32),
  ('entries', (NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY * 150)),
]
NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS = struct_NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY(Struct): pass
struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY._fields_ = [
  ('faultAddress', NvU64),
  ('faultType', NvU32),
  ('accessType', NvU32),
]
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY
class struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS._fields_ = [
  ('mmuFaultInfoList', (NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY * 4)),
  ('count', NvU32),
]
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS = struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS._fields_ = [
  ('bDropDeferredRc', NvBool),
]
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS
class struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [
  ('action', NvU32),
]
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS
class struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS(Struct): pass
struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS._fields_ = [
  ('value', NvU32),
]
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS = struct_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS
nv_status_codes = CEnum(ctypes.c_uint32)
NV_OK = nv_status_codes.define('NV_OK', 0)
NV_ERR_GENERIC = nv_status_codes.define('NV_ERR_GENERIC', 65535)
NV_ERR_BROKEN_FB = nv_status_codes.define('NV_ERR_BROKEN_FB', 1)
NV_ERR_BUFFER_TOO_SMALL = nv_status_codes.define('NV_ERR_BUFFER_TOO_SMALL', 2)
NV_ERR_BUSY_RETRY = nv_status_codes.define('NV_ERR_BUSY_RETRY', 3)
NV_ERR_CALLBACK_NOT_SCHEDULED = nv_status_codes.define('NV_ERR_CALLBACK_NOT_SCHEDULED', 4)
NV_ERR_CARD_NOT_PRESENT = nv_status_codes.define('NV_ERR_CARD_NOT_PRESENT', 5)
NV_ERR_CYCLE_DETECTED = nv_status_codes.define('NV_ERR_CYCLE_DETECTED', 6)
NV_ERR_DMA_IN_USE = nv_status_codes.define('NV_ERR_DMA_IN_USE', 7)
NV_ERR_DMA_MEM_NOT_LOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_LOCKED', 8)
NV_ERR_DMA_MEM_NOT_UNLOCKED = nv_status_codes.define('NV_ERR_DMA_MEM_NOT_UNLOCKED', 9)
NV_ERR_DUAL_LINK_INUSE = nv_status_codes.define('NV_ERR_DUAL_LINK_INUSE', 10)
NV_ERR_ECC_ERROR = nv_status_codes.define('NV_ERR_ECC_ERROR', 11)
NV_ERR_FIFO_BAD_ACCESS = nv_status_codes.define('NV_ERR_FIFO_BAD_ACCESS', 12)
NV_ERR_FREQ_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_FREQ_NOT_SUPPORTED', 13)
NV_ERR_GPU_DMA_NOT_INITIALIZED = nv_status_codes.define('NV_ERR_GPU_DMA_NOT_INITIALIZED', 14)
NV_ERR_GPU_IS_LOST = nv_status_codes.define('NV_ERR_GPU_IS_LOST', 15)
NV_ERR_GPU_IN_FULLCHIP_RESET = nv_status_codes.define('NV_ERR_GPU_IN_FULLCHIP_RESET', 16)
NV_ERR_GPU_NOT_FULL_POWER = nv_status_codes.define('NV_ERR_GPU_NOT_FULL_POWER', 17)
NV_ERR_GPU_UUID_NOT_FOUND = nv_status_codes.define('NV_ERR_GPU_UUID_NOT_FOUND', 18)
NV_ERR_HOT_SWITCH = nv_status_codes.define('NV_ERR_HOT_SWITCH', 19)
NV_ERR_I2C_ERROR = nv_status_codes.define('NV_ERR_I2C_ERROR', 20)
NV_ERR_I2C_SPEED_TOO_HIGH = nv_status_codes.define('NV_ERR_I2C_SPEED_TOO_HIGH', 21)
NV_ERR_ILLEGAL_ACTION = nv_status_codes.define('NV_ERR_ILLEGAL_ACTION', 22)
NV_ERR_IN_USE = nv_status_codes.define('NV_ERR_IN_USE', 23)
NV_ERR_INFLATE_COMPRESSED_DATA_FAILED = nv_status_codes.define('NV_ERR_INFLATE_COMPRESSED_DATA_FAILED', 24)
NV_ERR_INSERT_DUPLICATE_NAME = nv_status_codes.define('NV_ERR_INSERT_DUPLICATE_NAME', 25)
NV_ERR_INSUFFICIENT_RESOURCES = nv_status_codes.define('NV_ERR_INSUFFICIENT_RESOURCES', 26)
NV_ERR_INSUFFICIENT_PERMISSIONS = nv_status_codes.define('NV_ERR_INSUFFICIENT_PERMISSIONS', 27)
NV_ERR_INSUFFICIENT_POWER = nv_status_codes.define('NV_ERR_INSUFFICIENT_POWER', 28)
NV_ERR_INVALID_ACCESS_TYPE = nv_status_codes.define('NV_ERR_INVALID_ACCESS_TYPE', 29)
NV_ERR_INVALID_ADDRESS = nv_status_codes.define('NV_ERR_INVALID_ADDRESS', 30)
NV_ERR_INVALID_ARGUMENT = nv_status_codes.define('NV_ERR_INVALID_ARGUMENT', 31)
NV_ERR_INVALID_BASE = nv_status_codes.define('NV_ERR_INVALID_BASE', 32)
NV_ERR_INVALID_CHANNEL = nv_status_codes.define('NV_ERR_INVALID_CHANNEL', 33)
NV_ERR_INVALID_CLASS = nv_status_codes.define('NV_ERR_INVALID_CLASS', 34)
NV_ERR_INVALID_CLIENT = nv_status_codes.define('NV_ERR_INVALID_CLIENT', 35)
NV_ERR_INVALID_COMMAND = nv_status_codes.define('NV_ERR_INVALID_COMMAND', 36)
NV_ERR_INVALID_DATA = nv_status_codes.define('NV_ERR_INVALID_DATA', 37)
NV_ERR_INVALID_DEVICE = nv_status_codes.define('NV_ERR_INVALID_DEVICE', 38)
NV_ERR_INVALID_DMA_SPECIFIER = nv_status_codes.define('NV_ERR_INVALID_DMA_SPECIFIER', 39)
NV_ERR_INVALID_EVENT = nv_status_codes.define('NV_ERR_INVALID_EVENT', 40)
NV_ERR_INVALID_FLAGS = nv_status_codes.define('NV_ERR_INVALID_FLAGS', 41)
NV_ERR_INVALID_FUNCTION = nv_status_codes.define('NV_ERR_INVALID_FUNCTION', 42)
NV_ERR_INVALID_HEAP = nv_status_codes.define('NV_ERR_INVALID_HEAP', 43)
NV_ERR_INVALID_INDEX = nv_status_codes.define('NV_ERR_INVALID_INDEX', 44)
NV_ERR_INVALID_IRQ_LEVEL = nv_status_codes.define('NV_ERR_INVALID_IRQ_LEVEL', 45)
NV_ERR_INVALID_LIMIT = nv_status_codes.define('NV_ERR_INVALID_LIMIT', 46)
NV_ERR_INVALID_LOCK_STATE = nv_status_codes.define('NV_ERR_INVALID_LOCK_STATE', 47)
NV_ERR_INVALID_METHOD = nv_status_codes.define('NV_ERR_INVALID_METHOD', 48)
NV_ERR_INVALID_OBJECT = nv_status_codes.define('NV_ERR_INVALID_OBJECT', 49)
NV_ERR_INVALID_OBJECT_BUFFER = nv_status_codes.define('NV_ERR_INVALID_OBJECT_BUFFER', 50)
NV_ERR_INVALID_OBJECT_HANDLE = nv_status_codes.define('NV_ERR_INVALID_OBJECT_HANDLE', 51)
NV_ERR_INVALID_OBJECT_NEW = nv_status_codes.define('NV_ERR_INVALID_OBJECT_NEW', 52)
NV_ERR_INVALID_OBJECT_OLD = nv_status_codes.define('NV_ERR_INVALID_OBJECT_OLD', 53)
NV_ERR_INVALID_OBJECT_PARENT = nv_status_codes.define('NV_ERR_INVALID_OBJECT_PARENT', 54)
NV_ERR_INVALID_OFFSET = nv_status_codes.define('NV_ERR_INVALID_OFFSET', 55)
NV_ERR_INVALID_OPERATION = nv_status_codes.define('NV_ERR_INVALID_OPERATION', 56)
NV_ERR_INVALID_OWNER = nv_status_codes.define('NV_ERR_INVALID_OWNER', 57)
NV_ERR_INVALID_PARAM_STRUCT = nv_status_codes.define('NV_ERR_INVALID_PARAM_STRUCT', 58)
NV_ERR_INVALID_PARAMETER = nv_status_codes.define('NV_ERR_INVALID_PARAMETER', 59)
NV_ERR_INVALID_PATH = nv_status_codes.define('NV_ERR_INVALID_PATH', 60)
NV_ERR_INVALID_POINTER = nv_status_codes.define('NV_ERR_INVALID_POINTER', 61)
NV_ERR_INVALID_REGISTRY_KEY = nv_status_codes.define('NV_ERR_INVALID_REGISTRY_KEY', 62)
NV_ERR_INVALID_REQUEST = nv_status_codes.define('NV_ERR_INVALID_REQUEST', 63)
NV_ERR_INVALID_STATE = nv_status_codes.define('NV_ERR_INVALID_STATE', 64)
NV_ERR_INVALID_STRING_LENGTH = nv_status_codes.define('NV_ERR_INVALID_STRING_LENGTH', 65)
NV_ERR_INVALID_READ = nv_status_codes.define('NV_ERR_INVALID_READ', 66)
NV_ERR_INVALID_WRITE = nv_status_codes.define('NV_ERR_INVALID_WRITE', 67)
NV_ERR_INVALID_XLATE = nv_status_codes.define('NV_ERR_INVALID_XLATE', 68)
NV_ERR_IRQ_NOT_FIRING = nv_status_codes.define('NV_ERR_IRQ_NOT_FIRING', 69)
NV_ERR_IRQ_EDGE_TRIGGERED = nv_status_codes.define('NV_ERR_IRQ_EDGE_TRIGGERED', 70)
NV_ERR_MEMORY_TRAINING_FAILED = nv_status_codes.define('NV_ERR_MEMORY_TRAINING_FAILED', 71)
NV_ERR_MISMATCHED_SLAVE = nv_status_codes.define('NV_ERR_MISMATCHED_SLAVE', 72)
NV_ERR_MISMATCHED_TARGET = nv_status_codes.define('NV_ERR_MISMATCHED_TARGET', 73)
NV_ERR_MISSING_TABLE_ENTRY = nv_status_codes.define('NV_ERR_MISSING_TABLE_ENTRY', 74)
NV_ERR_MODULE_LOAD_FAILED = nv_status_codes.define('NV_ERR_MODULE_LOAD_FAILED', 75)
NV_ERR_MORE_DATA_AVAILABLE = nv_status_codes.define('NV_ERR_MORE_DATA_AVAILABLE', 76)
NV_ERR_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_ERR_MORE_PROCESSING_REQUIRED', 77)
NV_ERR_MULTIPLE_MEMORY_TYPES = nv_status_codes.define('NV_ERR_MULTIPLE_MEMORY_TYPES', 78)
NV_ERR_NO_FREE_FIFOS = nv_status_codes.define('NV_ERR_NO_FREE_FIFOS', 79)
NV_ERR_NO_INTR_PENDING = nv_status_codes.define('NV_ERR_NO_INTR_PENDING', 80)
NV_ERR_NO_MEMORY = nv_status_codes.define('NV_ERR_NO_MEMORY', 81)
NV_ERR_NO_SUCH_DOMAIN = nv_status_codes.define('NV_ERR_NO_SUCH_DOMAIN', 82)
NV_ERR_NO_VALID_PATH = nv_status_codes.define('NV_ERR_NO_VALID_PATH', 83)
NV_ERR_NOT_COMPATIBLE = nv_status_codes.define('NV_ERR_NOT_COMPATIBLE', 84)
NV_ERR_NOT_READY = nv_status_codes.define('NV_ERR_NOT_READY', 85)
NV_ERR_NOT_SUPPORTED = nv_status_codes.define('NV_ERR_NOT_SUPPORTED', 86)
NV_ERR_OBJECT_NOT_FOUND = nv_status_codes.define('NV_ERR_OBJECT_NOT_FOUND', 87)
NV_ERR_OBJECT_TYPE_MISMATCH = nv_status_codes.define('NV_ERR_OBJECT_TYPE_MISMATCH', 88)
NV_ERR_OPERATING_SYSTEM = nv_status_codes.define('NV_ERR_OPERATING_SYSTEM', 89)
NV_ERR_OTHER_DEVICE_FOUND = nv_status_codes.define('NV_ERR_OTHER_DEVICE_FOUND', 90)
NV_ERR_OUT_OF_RANGE = nv_status_codes.define('NV_ERR_OUT_OF_RANGE', 91)
NV_ERR_OVERLAPPING_UVM_COMMIT = nv_status_codes.define('NV_ERR_OVERLAPPING_UVM_COMMIT', 92)
NV_ERR_PAGE_TABLE_NOT_AVAIL = nv_status_codes.define('NV_ERR_PAGE_TABLE_NOT_AVAIL', 93)
NV_ERR_PID_NOT_FOUND = nv_status_codes.define('NV_ERR_PID_NOT_FOUND', 94)
NV_ERR_PROTECTION_FAULT = nv_status_codes.define('NV_ERR_PROTECTION_FAULT', 95)
NV_ERR_RC_ERROR = nv_status_codes.define('NV_ERR_RC_ERROR', 96)
NV_ERR_REJECTED_VBIOS = nv_status_codes.define('NV_ERR_REJECTED_VBIOS', 97)
NV_ERR_RESET_REQUIRED = nv_status_codes.define('NV_ERR_RESET_REQUIRED', 98)
NV_ERR_STATE_IN_USE = nv_status_codes.define('NV_ERR_STATE_IN_USE', 99)
NV_ERR_SIGNAL_PENDING = nv_status_codes.define('NV_ERR_SIGNAL_PENDING', 100)
NV_ERR_TIMEOUT = nv_status_codes.define('NV_ERR_TIMEOUT', 101)
NV_ERR_TIMEOUT_RETRY = nv_status_codes.define('NV_ERR_TIMEOUT_RETRY', 102)
NV_ERR_TOO_MANY_PRIMARIES = nv_status_codes.define('NV_ERR_TOO_MANY_PRIMARIES', 103)
NV_ERR_UVM_ADDRESS_IN_USE = nv_status_codes.define('NV_ERR_UVM_ADDRESS_IN_USE', 104)
NV_ERR_MAX_SESSION_LIMIT_REACHED = nv_status_codes.define('NV_ERR_MAX_SESSION_LIMIT_REACHED', 105)
NV_ERR_LIB_RM_VERSION_MISMATCH = nv_status_codes.define('NV_ERR_LIB_RM_VERSION_MISMATCH', 106)
NV_ERR_PRIV_SEC_VIOLATION = nv_status_codes.define('NV_ERR_PRIV_SEC_VIOLATION', 107)
NV_ERR_GPU_IN_DEBUG_MODE = nv_status_codes.define('NV_ERR_GPU_IN_DEBUG_MODE', 108)
NV_ERR_FEATURE_NOT_ENABLED = nv_status_codes.define('NV_ERR_FEATURE_NOT_ENABLED', 109)
NV_ERR_RESOURCE_LOST = nv_status_codes.define('NV_ERR_RESOURCE_LOST', 110)
NV_ERR_PMU_NOT_READY = nv_status_codes.define('NV_ERR_PMU_NOT_READY', 111)
NV_ERR_FLCN_ERROR = nv_status_codes.define('NV_ERR_FLCN_ERROR', 112)
NV_ERR_FATAL_ERROR = nv_status_codes.define('NV_ERR_FATAL_ERROR', 113)
NV_ERR_MEMORY_ERROR = nv_status_codes.define('NV_ERR_MEMORY_ERROR', 114)
NV_ERR_INVALID_LICENSE = nv_status_codes.define('NV_ERR_INVALID_LICENSE', 115)
NV_ERR_NVLINK_INIT_ERROR = nv_status_codes.define('NV_ERR_NVLINK_INIT_ERROR', 116)
NV_ERR_NVLINK_MINION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_MINION_ERROR', 117)
NV_ERR_NVLINK_CLOCK_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CLOCK_ERROR', 118)
NV_ERR_NVLINK_TRAINING_ERROR = nv_status_codes.define('NV_ERR_NVLINK_TRAINING_ERROR', 119)
NV_ERR_NVLINK_CONFIGURATION_ERROR = nv_status_codes.define('NV_ERR_NVLINK_CONFIGURATION_ERROR', 120)
NV_ERR_RISCV_ERROR = nv_status_codes.define('NV_ERR_RISCV_ERROR', 121)
NV_ERR_FABRIC_MANAGER_NOT_PRESENT = nv_status_codes.define('NV_ERR_FABRIC_MANAGER_NOT_PRESENT', 122)
NV_ERR_ALREADY_SIGNALLED = nv_status_codes.define('NV_ERR_ALREADY_SIGNALLED', 123)
NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE', 124)
NV_ERR_KEY_ROTATION_IN_PROGRESS = nv_status_codes.define('NV_ERR_KEY_ROTATION_IN_PROGRESS', 125)
NV_ERR_TEST_ONLY_CODE_NOT_ENABLED = nv_status_codes.define('NV_ERR_TEST_ONLY_CODE_NOT_ENABLED', 126)
NV_ERR_SECURE_BOOT_FAILED = nv_status_codes.define('NV_ERR_SECURE_BOOT_FAILED', 127)
NV_ERR_INSUFFICIENT_ZBC_ENTRY = nv_status_codes.define('NV_ERR_INSUFFICIENT_ZBC_ENTRY', 128)
NV_ERR_NVLINK_FABRIC_NOT_READY = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_NOT_READY', 129)
NV_ERR_NVLINK_FABRIC_FAILURE = nv_status_codes.define('NV_ERR_NVLINK_FABRIC_FAILURE', 130)
NV_ERR_GPU_MEMORY_ONLINING_FAILURE = nv_status_codes.define('NV_ERR_GPU_MEMORY_ONLINING_FAILURE', 131)
NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE = nv_status_codes.define('NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE', 132)
NV_WARN_HOT_SWITCH = nv_status_codes.define('NV_WARN_HOT_SWITCH', 65537)
NV_WARN_INCORRECT_PERFMON_DATA = nv_status_codes.define('NV_WARN_INCORRECT_PERFMON_DATA', 65538)
NV_WARN_MISMATCHED_SLAVE = nv_status_codes.define('NV_WARN_MISMATCHED_SLAVE', 65539)
NV_WARN_MISMATCHED_TARGET = nv_status_codes.define('NV_WARN_MISMATCHED_TARGET', 65540)
NV_WARN_MORE_PROCESSING_REQUIRED = nv_status_codes.define('NV_WARN_MORE_PROCESSING_REQUIRED', 65541)
NV_WARN_NOTHING_TO_DO = nv_status_codes.define('NV_WARN_NOTHING_TO_DO', 65542)
NV_WARN_NULL_OBJECT = nv_status_codes.define('NV_WARN_NULL_OBJECT', 65543)
NV_WARN_OUT_OF_RANGE = nv_status_codes.define('NV_WARN_OUT_OF_RANGE', 65544)

NVC6C0_QMDV02_03_OUTER_PUT = (30, 0)
NVC6C0_QMDV02_03_OUTER_OVERFLOW = (31, 31)
NVC6C0_QMDV02_03_OUTER_GET = (62, 32)
NVC6C0_QMDV02_03_OUTER_STICKY_OVERFLOW = (63, 63)
NVC6C0_QMDV02_03_INNER_GET = (94, 64)
NVC6C0_QMDV02_03_INNER_OVERFLOW = (95, 95)
NVC6C0_QMDV02_03_INNER_PUT = (126, 96)
NVC6C0_QMDV02_03_INNER_STICKY_OVERFLOW = (127, 127)
NVC6C0_QMDV02_03_QMD_GROUP_ID = (133, 128)
NVC6C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE = (134, 134)
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
NVC6C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
NVC6C0_QMDV02_03_IS_QUEUE = (136, 136)
NVC6C0_QMDV02_03_IS_QUEUE_FALSE = 0x00000000
NVC6C0_QMDV02_03_IS_QUEUE_TRUE = 0x00000001
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVC6C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 = (138, 138)
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 = (139, 139)
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000
NVC6C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS = (140, 140)
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVC6C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE = (141, 141)
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE = (142, 142)
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE = 0x00000000
NVC6C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID = 0x00000001
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY = (143, 143)
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE = 0x00000000
NVC6C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE = 0x00000001
NVC6C0_QMDV02_03_QMD_RESERVED_B = (159, 144)
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_SIZE = (184, 160)
NVC6C0_QMDV02_03_QMD_RESERVED_C = (185, 185)
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME = (223, 192)
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME = (239, 224)
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME = (255, 240)
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
NVC6C0_QMDV02_03_QMD_RESERVED_D = (335, 328)
NVC6C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_ID = (357, 352)
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE = (366, 366)
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
NVC6C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE = (369, 368)
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVC6C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS = (370, 370)
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
NVC6C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT = (378, 378)
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVC6C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVC6C0_QMDV02_03_SAMPLER_INDEX = (382, 382)
NVC6C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVC6C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVC6C0_QMDV02_03_CTA_RASTER_WIDTH = (415, 384)
NVC6C0_QMDV02_03_CTA_RASTER_HEIGHT = (431, 416)
NVC6C0_QMDV02_03_QMD_RESERVED13A = (447, 432)
NVC6C0_QMDV02_03_CTA_RASTER_DEPTH = (463, 448)
NVC6C0_QMDV02_03_QMD_RESERVED14A = (479, 464)
NVC6C0_QMDV02_03_DEPENDENT_QMD_POINTER = (511, 480)
NVC6C0_QMDV02_03_COALESCE_WAITING_PERIOD = (529, 522)
NVC6C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
NVC6C0_QMDV02_03_SHARED_MEMORY_SIZE = (561, 544)
NVC6C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562)
NVC6C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569)
NVC6C0_QMDV02_03_QMD_VERSION = (579, 576)
NVC6C0_QMDV02_03_QMD_MAJOR_VERSION = (583, 580)
NVC6C0_QMDV02_03_QMD_RESERVED_H = (591, 584)
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION0 = (607, 592)
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION1 = (623, 608)
NVC6C0_QMDV02_03_CTA_THREAD_DIMENSION2 = (639, 624)
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1))
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
NVC6C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
NVC6C0_QMDV02_03_REGISTER_COUNT_V = (656, 648)
NVC6C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657)
NVC6C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
NVC6C0_QMDV02_03_SM_DISABLE_MASK_LOWER = (703, 672)
NVC6C0_QMDV02_03_SM_DISABLE_MASK_UPPER = (735, 704)
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_LOWER = (767, 736)
NVC6C0_QMDV02_03_RELEASE0_ADDRESS_UPPER = (775, 768)
NVC6C0_QMDV02_03_QMD_RESERVED_J = (783, 776)
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP = (790, 788)
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV02_03_QMD_RESERVED_K = (791, 791)
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT = (793, 792)
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE = (794, 794)
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE = (799, 799)
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001
NVC6C0_QMDV02_03_RELEASE0_PAYLOAD = (831, 800)
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_LOWER = (863, 832)
NVC6C0_QMDV02_03_RELEASE1_ADDRESS_UPPER = (871, 864)
NVC6C0_QMDV02_03_QMD_RESERVED_L = (879, 872)
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP = (886, 884)
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV02_03_QMD_RESERVED_M = (887, 887)
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT = (889, 888)
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE = (890, 890)
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE = (895, 895)
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001
NVC6C0_QMDV02_03_RELEASE1_PAYLOAD = (927, 896)
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928)
NVC6C0_QMDV02_03_QMD_RESERVED_N = (954, 952)
NVC6C0_QMDV02_03_BARRIER_COUNT = (959, 955)
NVC6C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960)
NVC6C0_QMDV02_03_REGISTER_COUNT = (991, 984)
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992)
NVC6C0_QMDV02_03_PROGRAM_PREFETCH_SIZE = (1009, 1001)
NVC6C0_QMDV02_03_QMD_RESERVED_A = (1015, 1010)
NVC6C0_QMDV02_03_SASS_VERSION = (1023, 1016)
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64))
NVC6C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64))
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64))
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
NVC6C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64))
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
NVC6C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
NVC6C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64))
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_LOWER = (1567, 1536)
NVC6C0_QMDV02_03_PROGRAM_ADDRESS_UPPER = (1584, 1568)
NVC6C0_QMDV02_03_QMD_RESERVED_S = (1599, 1585)
NVC6C0_QMDV02_03_HW_ONLY_INNER_GET = (1630, 1600)
NVC6C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631)
NVC6C0_QMDV02_03_HW_ONLY_INNER_PUT = (1662, 1632)
NVC6C0_QMDV02_03_HW_ONLY_SCG_TYPE = (1663, 1663)
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664)
NVC6C0_QMDV02_03_QMD_RESERVED_Q = (1694, 1694)
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695)
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVC6C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVC6C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696)
NVC6C0_QMDV02_03_QMD_SPARE_G = (1759, 1728)
NVC6C0_QMDV02_03_QMD_SPARE_H = (1791, 1760)
NVC6C0_QMDV02_03_QMD_SPARE_I = (1823, 1792)
NVC6C0_QMDV02_03_QMD_SPARE_J = (1855, 1824)
NVC6C0_QMDV02_03_QMD_SPARE_K = (1887, 1856)
NVC6C0_QMDV02_03_QMD_SPARE_L = (1919, 1888)
NVC6C0_QMDV02_03_QMD_SPARE_M = (1951, 1920)
NVC6C0_QMDV02_03_QMD_SPARE_N = (1983, 1952)
NVC6C0_QMDV02_03_DEBUG_ID_UPPER = (2015, 1984)
NVC6C0_QMDV02_03_DEBUG_ID_LOWER = (2047, 2016)
NVC6C0_QMDV02_04_OUTER_PUT = (30, 0)
NVC6C0_QMDV02_04_OUTER_OVERFLOW = (31, 31)
NVC6C0_QMDV02_04_OUTER_GET = (62, 32)
NVC6C0_QMDV02_04_OUTER_STICKY_OVERFLOW = (63, 63)
NVC6C0_QMDV02_04_INNER_GET = (94, 64)
NVC6C0_QMDV02_04_INNER_OVERFLOW = (95, 95)
NVC6C0_QMDV02_04_INNER_PUT = (126, 96)
NVC6C0_QMDV02_04_INNER_STICKY_OVERFLOW = (127, 127)
NVC6C0_QMDV02_04_QMD_GROUP_ID = (133, 128)
NVC6C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE = (134, 134)
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
NVC6C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
NVC6C0_QMDV02_04_IS_QUEUE = (136, 136)
NVC6C0_QMDV02_04_IS_QUEUE_FALSE = 0x00000000
NVC6C0_QMDV02_04_IS_QUEUE_TRUE = 0x00000001
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVC6C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 = (138, 138)
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE = 0x00000000
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE = 0x00000001
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 = (139, 139)
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE = 0x00000000
NVC6C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE = 0x00000001
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS = (140, 140)
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVC6C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE = (141, 141)
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION = (144, 142)
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVC6C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH = (145, 145)
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE = (146, 146)
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION = (149, 147)
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVC6C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH = (150, 150)
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
NVC6C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
NVC6C0_QMDV02_04_DEPENDENCE_COUNTER = (157, 151)
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION = (158, 158)
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
NVC6C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
NVC6C0_QMDV02_04_QMD_RESERVED_B = (159, 159)
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_SIZE = (184, 160)
NVC6C0_QMDV02_04_DEMOTE_L2_EVICT_LAST = (185, 185)
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVC6C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME = (223, 192)
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME = (239, 224)
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME = (255, 240)
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
NVC6C0_QMDV02_04_QMD_RESERVED_D = (335, 328)
NVC6C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_ID = (357, 352)
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE = (366, 366)
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
NVC6C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE = (369, 368)
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVC6C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS = (370, 370)
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
NVC6C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT = (378, 378)
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVC6C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVC6C0_QMDV02_04_SAMPLER_INDEX = (382, 382)
NVC6C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVC6C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE = (383, 383)
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
NVC6C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
NVC6C0_QMDV02_04_CTA_RASTER_WIDTH = (415, 384)
NVC6C0_QMDV02_04_CTA_RASTER_HEIGHT = (431, 416)
NVC6C0_QMDV02_04_QMD_RESERVED13A = (447, 432)
NVC6C0_QMDV02_04_CTA_RASTER_DEPTH = (463, 448)
NVC6C0_QMDV02_04_QMD_RESERVED14A = (479, 464)
NVC6C0_QMDV02_04_DEPENDENT_QMD0_POINTER = (511, 480)
NVC6C0_QMDV02_04_COALESCE_WAITING_PERIOD = (529, 522)
NVC6C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
NVC6C0_QMDV02_04_SHARED_MEMORY_SIZE = (561, 544)
NVC6C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE = (568, 562)
NVC6C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE = (575, 569)
NVC6C0_QMDV02_04_QMD_VERSION = (579, 576)
NVC6C0_QMDV02_04_QMD_MAJOR_VERSION = (583, 580)
NVC6C0_QMDV02_04_QMD_RESERVED_H = (591, 584)
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION0 = (607, 592)
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION1 = (623, 608)
NVC6C0_QMDV02_04_CTA_THREAD_DIMENSION2 = (639, 624)
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1))
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
NVC6C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
NVC6C0_QMDV02_04_REGISTER_COUNT_V = (656, 648)
NVC6C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (663, 657)
NVC6C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
NVC6C0_QMDV02_04_SM_DISABLE_MASK_LOWER = (703, 672)
NVC6C0_QMDV02_04_SM_DISABLE_MASK_UPPER = (735, 704)
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_LOWER = (767, 736)
NVC6C0_QMDV02_04_RELEASE0_ADDRESS_UPPER = (775, 768)
NVC6C0_QMDV02_04_QMD_RESERVED_J = (783, 776)
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP = (790, 788)
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV02_04_QMD_RESERVED_K = (791, 791)
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT = (793, 792)
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE = (794, 794)
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE = (799, 799)
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD = 0x00000001
NVC6C0_QMDV02_04_RELEASE0_PAYLOAD = (831, 800)
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_LOWER = (863, 832)
NVC6C0_QMDV02_04_RELEASE1_ADDRESS_UPPER = (871, 864)
NVC6C0_QMDV02_04_QMD_RESERVED_L = (879, 872)
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP = (886, 884)
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV02_04_QMD_RESERVED_M = (887, 887)
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT = (889, 888)
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE = (890, 890)
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE = (895, 895)
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD = 0x00000001
NVC6C0_QMDV02_04_RELEASE1_PAYLOAD = (927, 896)
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE = (951, 928)
NVC6C0_QMDV02_04_QMD_RESERVED_N = (954, 952)
NVC6C0_QMDV02_04_BARRIER_COUNT = (959, 955)
NVC6C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE = (983, 960)
NVC6C0_QMDV02_04_QMD_RESERVED_G = (991, 984)
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1000, 992)
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_SIZE = (1009, 1001)
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE = (1011, 1010)
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
NVC6C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
NVC6C0_QMDV02_04_QMD_RESERVED_A = (1015, 1012)
NVC6C0_QMDV02_04_SASS_VERSION = (1023, 1016)
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64))
NVC6C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64))
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64))
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
NVC6C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64))
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
NVC6C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
NVC6C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64))
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_LOWER = (1567, 1536)
NVC6C0_QMDV02_04_PROGRAM_ADDRESS_UPPER = (1584, 1568)
NVC6C0_QMDV02_04_QMD_RESERVED_S = (1599, 1585)
NVC6C0_QMDV02_04_HW_ONLY_INNER_GET = (1630, 1600)
NVC6C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1631, 1631)
NVC6C0_QMDV02_04_HW_ONLY_INNER_PUT = (1662, 1632)
NVC6C0_QMDV02_04_HW_ONLY_SCG_TYPE = (1663, 1663)
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1693, 1664)
NVC6C0_QMDV02_04_QMD_RESERVED_Q = (1694, 1694)
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1695, 1695)
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVC6C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVC6C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER = (1727, 1696)
NVC6C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER = (1734, 1728)
NVC6C0_QMDV02_04_QMD_RESERVED_I = (1759, 1735)
NVC6C0_QMDV02_04_QMD_SPARE_H = (1791, 1760)
NVC6C0_QMDV02_04_QMD_SPARE_I = (1823, 1792)
NVC6C0_QMDV02_04_QMD_SPARE_J = (1855, 1824)
NVC6C0_QMDV02_04_QMD_SPARE_K = (1887, 1856)
NVC6C0_QMDV02_04_QMD_SPARE_L = (1919, 1888)
NVC6C0_QMDV02_04_QMD_SPARE_M = (1951, 1920)
NVC6C0_QMDV02_04_QMD_SPARE_N = (1983, 1952)
NVC6C0_QMDV02_04_DEBUG_ID_UPPER = (2015, 1984)
NVC6C0_QMDV02_04_DEBUG_ID_LOWER = (2047, 2016)
NVC6C0_QMDV03_00_OUTER_PUT = (30, 0)
NVC6C0_QMDV03_00_OUTER_OVERFLOW = (31, 31)
NVC6C0_QMDV03_00_OUTER_GET = (62, 32)
NVC6C0_QMDV03_00_OUTER_STICKY_OVERFLOW = (63, 63)
NVC6C0_QMDV03_00_INNER_GET = (94, 64)
NVC6C0_QMDV03_00_INNER_OVERFLOW = (95, 95)
NVC6C0_QMDV03_00_INNER_PUT = (126, 96)
NVC6C0_QMDV03_00_INNER_STICKY_OVERFLOW = (127, 127)
NVC6C0_QMDV03_00_QMD_GROUP_ID = (133, 128)
NVC6C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE = (134, 134)
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION = (135, 135)
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE = 0x00000000
NVC6C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE = 0x00000001
NVC6C0_QMDV03_00_IS_QUEUE = (136, 136)
NVC6C0_QMDV03_00_IS_QUEUE_FALSE = 0x00000000
NVC6C0_QMDV03_00_IS_QUEUE_TRUE = 0x00000001
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (137, 137)
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVC6C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVC6C0_QMDV03_00_QMD_RESERVED04A = (139, 138)
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS = (140, 140)
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVC6C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVC6C0_QMDV03_00_QMD_RESERVED04B = (141, 141)
NVC6C0_QMDV03_00_DEPENDENCE_COUNTER = (157, 142)
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION = (158, 158)
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
NVC6C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
NVC6C0_QMDV03_00_QMD_RESERVED04C = (159, 159)
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_SIZE = (184, 160)
NVC6C0_QMDV03_00_DEMOTE_L2_EVICT_LAST = (185, 185)
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE = (186, 186)
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (187, 187)
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE = (188, 188)
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE = (189, 189)
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE = (190, 190)
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE = (191, 191)
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVC6C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME = (223, 192)
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME = (239, 224)
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME = (255, 240)
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (287, 256)
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER = (319, 288)
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER = (327, 320)
NVC6C0_QMDV03_00_QMD_RESERVED_D = (335, 328)
NVC6C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE = (351, 336)
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_ID = (357, 352)
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (365, 358)
NVC6C0_QMDV03_00_QMD_RESERVED11A = (366, 366)
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (367, 367)
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE = (369, 368)
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVC6C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS = (370, 370)
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
NVC6C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (371, 371)
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_QMD_RESERVED11B = (377, 372)
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT = (378, 378)
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVC6C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVC6C0_QMDV03_00_QMD_RESERVED11C = (381, 379)
NVC6C0_QMDV03_00_SAMPLER_INDEX = (382, 382)
NVC6C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVC6C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE = (383, 383)
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
NVC6C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
NVC6C0_QMDV03_00_CTA_RASTER_WIDTH = (415, 384)
NVC6C0_QMDV03_00_CTA_RASTER_HEIGHT = (431, 416)
NVC6C0_QMDV03_00_CTA_RASTER_DEPTH = (463, 448)
NVC6C0_QMDV03_00_DEPENDENT_QMD0_POINTER = (511, 480)
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE = (512, 512)
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION = (515, 513)
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVC6C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH = (516, 516)
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE = (517, 517)
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION = (520, 518)
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVC6C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH = (521, 521)
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
NVC6C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
NVC6C0_QMDV03_00_COALESCE_WAITING_PERIOD = (529, 522)
NVC6C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (534, 530)
NVC6C0_QMDV03_00_SHARED_MEMORY_SIZE = (561, 544)
NVC6C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (567, 562)
NVC6C0_QMDV03_00_QMD_RESERVED17A = (568, 568)
NVC6C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (574, 569)
NVC6C0_QMDV03_00_QMD_RESERVED17B = (575, 575)
NVC6C0_QMDV03_00_QMD_VERSION = (579, 576)
NVC6C0_QMDV03_00_QMD_MAJOR_VERSION = (583, 580)
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION0 = (607, 592)
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION1 = (623, 608)
NVC6C0_QMDV03_00_CTA_THREAD_DIMENSION2 = (639, 624)
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID = lambda i: ((640+(i)*1), (640+(i)*1))
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
NVC6C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
NVC6C0_QMDV03_00_REGISTER_COUNT_V = (656, 648)
NVC6C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (662, 657)
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE = (663, 663)
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM = (671, 664)
NVC6C0_QMDV03_00_SM_DISABLE_MASK_LOWER = (703, 672)
NVC6C0_QMDV03_00_SM_DISABLE_MASK_UPPER = (735, 704)
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE = (759, 736)
NVC6C0_QMDV03_00_BARRIER_COUNT = (767, 763)
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_LOWER = (799, 768)
NVC6C0_QMDV03_00_RELEASE0_ADDRESS_UPPER = (807, 800)
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED25A = (818, 808)
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE = (819, 819)
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP = (822, 820)
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV03_00_RELEASE0_ENABLE = (823, 823)
NVC6C0_QMDV03_00_RELEASE0_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT = (825, 824)
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE = (826, 826)
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE = (828, 827)
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B = (829, 829)
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE = (831, 830)
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVC6C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER = (863, 832)
NVC6C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER = (895, 864)
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_LOWER = (927, 896)
NVC6C0_QMDV03_00_RELEASE1_ADDRESS_UPPER = (935, 928)
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED29A = (946, 936)
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE = (947, 947)
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP = (950, 948)
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV03_00_RELEASE1_ENABLE = (951, 951)
NVC6C0_QMDV03_00_RELEASE1_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT = (953, 952)
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE = (954, 954)
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE = (956, 955)
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B = (957, 957)
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE = (959, 958)
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVC6C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER = (991, 960)
NVC6C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER = (1023, 992)
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER = lambda i: ((1055+(i)*64), (1024+(i)*64))
NVC6C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER = lambda i: ((1072+(i)*64), (1056+(i)*64))
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST = lambda i: ((1073+(i)*64), (1073+(i)*64))
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE = 0x00000000
NVC6C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE = 0x00000001
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1074+(i)*64), (1074+(i)*64))
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
NVC6C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
NVC6C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1087+(i)*64), (1075+(i)*64))
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_LOWER = (1567, 1536)
NVC6C0_QMDV03_00_PROGRAM_ADDRESS_UPPER = (1584, 1568)
NVC6C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE = (1623, 1600)
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1640, 1632)
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_SIZE = (1649, 1641)
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE = (1651, 1650)
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
NVC6C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
NVC6C0_QMDV03_00_SASS_VERSION = (1663, 1656)
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_LOWER = (1695, 1664)
NVC6C0_QMDV03_00_RELEASE2_ADDRESS_UPPER = (1703, 1696)
NVC6C0_QMDV03_00_SEMAPHORE_RESERVED53A = (1714, 1704)
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE = (1715, 1715)
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP = (1718, 1716)
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_QMDV03_00_RELEASE2_ENABLE = (1719, 1719)
NVC6C0_QMDV03_00_RELEASE2_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT = (1721, 1720)
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE = (1722, 1722)
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE = (1724, 1723)
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_NONE = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_TRAP = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_NON_BLOCKING_INTR_TYPE_CONDITIONAL_TRAP = 0x00000002
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B = (1725, 1725)
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE = (1727, 1726)
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVC6C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER = (1759, 1728)
NVC6C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER = (1791, 1760)
NVC6C0_QMDV03_00_QMD_SPARE_I = (1823, 1792)
NVC6C0_QMDV03_00_HW_ONLY_INNER_GET = (1854, 1824)
NVC6C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (1855, 1855)
NVC6C0_QMDV03_00_HW_ONLY_INNER_PUT = (1886, 1856)
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (1917, 1888)
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (1919, 1919)
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVC6C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVC6C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (1951, 1920)
NVC6C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER = (1958, 1952)
NVC6C0_QMDV03_00_DEBUG_ID_UPPER = (2015, 1984)
NVC6C0_QMDV03_00_DEBUG_ID_LOWER = (2047, 2016)
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0)
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30)
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31)
NVCEC0_QMDV05_00_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32)
NVCEC0_QMDV05_00_INNER_GET = (94, 64)
NVCEC0_QMDV05_00_INNER_OVERFLOW = (95, 95)
NVCEC0_QMDV05_00_INNER_PUT = (126, 96)
NVCEC0_QMDV05_00_INNER_STICKY_OVERFLOW = (127, 127)
NVCEC0_QMDV05_00_DEPENDENCE_COUNTER = (143, 128)
NVCEC0_QMDV05_00_QMD_GROUP_ID = (149, 144)
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150)
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVCEC0_QMDV05_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVCEC0_QMDV05_00_QMD_TYPE = (153, 151)
NVCEC0_QMDV05_00_QMD_TYPE_QUEUE = 0x00000000
NVCEC0_QMDV05_00_QMD_TYPE_GRID_NULL = 0x00000001
NVCEC0_QMDV05_00_QMD_TYPE_GRID_CTA = 0x00000002
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPC_CGA = 0x00000003
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_CGA = 0x00000004
NVCEC0_QMDV05_00_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
NVCEC0_QMDV05_00_NUM_SUB_TASKS_PER_TASK = (157, 154)
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS = (158, 158)
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVCEC0_QMDV05_00_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID = (159, 159)
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_00_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_00_CIRCULAR_QUEUE_SIZE = (184, 160)
NVCEC0_QMDV05_00_HW_ONLY_DEPENDENCE_COUNTER = (207, 192)
NVCEC0_QMDV05_00_RESUME_SUB_TASK_ID = (210, 208)
NVCEC0_QMDV05_00_COMPLETED_SUB_TASK_MASK = (218, 211)
NVCEC0_QMDV05_00_GRID_WIDTH_RESUME = (255, 224)
NVCEC0_QMDV05_00_GRID_HEIGHT_RESUME = (271, 256)
NVCEC0_QMDV05_00_GRID_DEPTH_RESUME = (287, 272)
NVCEC0_QMDV05_00_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16))
NVCEC0_QMDV05_00_RELEASE0_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(0)
NVCEC0_QMDV05_00_RELEASE1_ENABLE = NVCEC0_QMDV05_00_RELEASE_ENABLE(1)
NVCEC0_QMDV05_00_RELEASE_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_RELEASE_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16))
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVCEC0_QMDV05_00_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16))
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
NVCEC0_QMDV05_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16))
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16))
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
NVCEC0_QMDV05_00_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16))
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
NVCEC0_QMDV05_00_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16))
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
NVCEC0_QMDV05_00_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16))
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_FALSE = 0x00000000
NVCEC0_QMDV05_00_RELEASE_PAYLOAD64B_TRUE = 0x00000001
NVCEC0_QMDV05_00_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16))
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE = (336, 336)
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION = (339, 337)
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH = (340, 340)
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION = (341, 341)
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
NVCEC0_QMDV05_00_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST = (342, 342)
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE = (343, 343)
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_00_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE = (344, 344)
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION = (347, 345)
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH = (348, 348)
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL = (349, 349)
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
NVCEC0_QMDV05_00_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350)
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE = (351, 351)
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_CORRELATION_ID = (383, 352)
NVCEC0_QMDV05_00_DEPENDENT_QMD0_POINTER = (415, 384)
NVCEC0_QMDV05_00_DEPENDENT_QMD1_POINTER = (447, 416)
NVCEC0_QMDV05_00_SASS_VERSION = (455, 448)
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT = (456, 456)
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVCEC0_QMDV05_00_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVCEC0_QMDV05_00_SAMPLER_INDEX = (457, 457)
NVCEC0_QMDV05_00_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVCEC0_QMDV05_00_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVCEC0_QMDV05_00_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458)
NVCEC0_QMDV05_00_QMD_MINOR_VERSION = (467, 464)
NVCEC0_QMDV05_00_QMD_MAJOR_VERSION = (471, 468)
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472)
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473)
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474)
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE = (475, 475)
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE = (476, 476)
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477)
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478)
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479)
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576)
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608)
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_ID = (621, 616)
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622)
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623)
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE = (625, 624)
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVCEC0_QMDV05_00_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626)
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_00_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_00_CTA_LAUNCH_QUEUE = (627, 627)
NVCEC0_QMDV05_00_FREE_CTA_SLOTS_EMPTY_SM = (635, 628)
NVCEC0_QMDV05_00_SYNC_DOMAIN_ID = (637, 636)
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638)
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
NVCEC0_QMDV05_00_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT = (639, 639)
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
NVCEC0_QMDV05_00_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_ID = (671, 640)
NVCEC0_QMDV05_00_WAIT_ON_LATCH_ID = (703, 672)
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714)
NVCEC0_QMDV05_00_OCCUPANCY_MAX_SHARED_MEM = (729, 722)
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID = (730, 730)
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_00_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID = (731, 731)
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_00_WAIT_ON_LATCH_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732)
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733)
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000
NVCEC0_QMDV05_00_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734)
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
NVCEC0_QMDV05_00_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735)
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
NVCEC0_QMDV05_00_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_WARP = (743, 736)
NVCEC0_QMDV05_00_OCCUPANCY_MAX_WARP = (751, 744)
NVCEC0_QMDV05_00_OCCUPANCY_THRESHOLD_REGISTER = (759, 752)
NVCEC0_QMDV05_00_OCCUPANCY_MAX_REGISTER = (767, 760)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960)
NVCEC0_QMDV05_00_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992)
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_LOWER_SHIFTED4 = (1055, 1024)
NVCEC0_QMDV05_00_PROGRAM_ADDRESS_UPPER_SHIFTED4 = (1076, 1056)
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_SIZE = (1085, 1077)
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE = (1087, 1086)
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION0 = (1103, 1088)
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION1 = (1119, 1104)
NVCEC0_QMDV05_00_CTA_THREAD_DIMENSION2 = (1127, 1120)
NVCEC0_QMDV05_00_REGISTER_COUNT = (1136, 1128)
NVCEC0_QMDV05_00_BARRIER_COUNT = (1141, 1137)
NVCEC0_QMDV05_00_ICC_PREFETCH_SIZE = (1147, 1142)
NVCEC0_QMDV05_00_SHARED_MEMORY_SIZE_SHIFTED7 = (1162, 1152)
NVCEC0_QMDV05_00_MIN_SM_CONFIG_SHARED_MEM_SIZE = (1168, 1163)
NVCEC0_QMDV05_00_MAX_SM_CONFIG_SHARED_MEM_SIZE = (1174, 1169)
NVCEC0_QMDV05_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (1180, 1175)
NVCEC0_QMDV05_00_SHARED_MEM_BARRIER_INIT_ENABLE = (1181, 1181)
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = (1199, 1184)
NVCEC0_QMDV05_00_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = (1215, 1200)
NVCEC0_QMDV05_00_VIRTUAL_RESOURCE_COUNT = (1223, 1216)
NVCEC0_QMDV05_00_GRID_WIDTH = (1279, 1248)
NVCEC0_QMDV05_00_GRID_HEIGHT = (1295, 1280)
NVCEC0_QMDV05_00_GRID_DEPTH = (1327, 1312)
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1375+(i)*64), (1344+(i)*64))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1394+(i)*64), (1376+(i)*64))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1407+(i)*64), (1395+(i)*64))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID = lambda i: ((1856+(i)*4), (1856+(i)*4))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_00_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH = lambda i: ((1858+(i)*4), (1857+(i)*4))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001
NVCEC0_QMDV05_00_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE = lambda i: ((1859+(i)*4), (1859+(i)*4))
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_00_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1919, 1888)
NVCEC0_QMDV05_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1936, 1920)
NVCEC0_QMDV05_00_GPC_CGA_WIDTH = (2053, 2048)
NVCEC0_QMDV05_00_GPC_CGA_HEIGHT = (2061, 2056)
NVCEC0_QMDV05_00_GPC_CGA_DEPTH = (2069, 2064)
NVCEC0_QMDV05_00_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2075, 2072)
NVCEC0_QMDV05_00_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2079, 2076)
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE = (2111, 2111)
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000
NVCEC0_QMDV05_00_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001
NVCEC0_QMDV05_00_GPU_CGA_WIDTH = (2127, 2112)
NVCEC0_QMDV05_00_GPU_CGA_HEIGHT = (2143, 2128)
NVCEC0_QMDV05_00_GPU_CGA_DEPTH = (2159, 2144)
NVCEC0_QMDV05_00_DEBUG_ID_LOWER = (2207, 2176)
NVCEC0_QMDV05_00_DEBUG_ID_UPPER = (2239, 2208)
NVCEC0_QMDV05_00_TPC_DISABLE_MASK = lambda i: ((2271+(i)*32), (2240+(i)*32))
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2527, 2496)
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2543, 2528)
NVCEC0_QMDV05_00_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2559, 2544)
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2563, 2560)
NVCEC0_QMDV05_00_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2567, 2564)
NVCEC0_QMDV05_00_QUEUE_ENTRIES_PER_CTA_LOG2 = (2596, 2592)
NVCEC0_QMDV05_00_HW_ONLY_INNER_GET = (2654, 2624)
NVCEC0_QMDV05_00_HW_ONLY_INNER_PUT = (2686, 2656)
NVCEC0_QMDV05_00_OUTER_PUT = (3038, 3008)
NVCEC0_QMDV05_00_OUTER_OVERFLOW = (3039, 3039)
NVCEC0_QMDV05_00_OUTER_GET = (3070, 3040)
NVCEC0_QMDV05_00_OUTER_STICKY_OVERFLOW = (3071, 3071)
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8))
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8))
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_00_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8))
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_00_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_00_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32))
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (29, 0)
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (30, 30)
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (31, 31)
NVCEC0_QMDV05_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (63, 32)
NVCEC0_QMDV05_01_INNER_GET = (94, 64)
NVCEC0_QMDV05_01_INNER_OVERFLOW = (95, 95)
NVCEC0_QMDV05_01_INNER_PUT = (126, 96)
NVCEC0_QMDV05_01_INNER_STICKY_OVERFLOW = (127, 127)
NVCEC0_QMDV05_01_DEPENDENCE_COUNTER = (143, 128)
NVCEC0_QMDV05_01_QMD_GROUP_ID = (149, 144)
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (150, 150)
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVCEC0_QMDV05_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVCEC0_QMDV05_01_QMD_TYPE = (153, 151)
NVCEC0_QMDV05_01_QMD_TYPE_QUEUE = 0x00000000
NVCEC0_QMDV05_01_QMD_TYPE_GRID_NULL = 0x00000001
NVCEC0_QMDV05_01_QMD_TYPE_GRID_CTA = 0x00000002
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004
NVCEC0_QMDV05_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
NVCEC0_QMDV05_01_NUM_SUB_TASKS_PER_TASK = (157, 154)
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS = (158, 158)
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVCEC0_QMDV05_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID = (159, 159)
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_CIRCULAR_QUEUE_SIZE = (184, 160)
NVCEC0_QMDV05_01_HW_ONLY_DEPENDENCE_COUNTER = (207, 192)
NVCEC0_QMDV05_01_RESUME_SUB_TASK_ID = (210, 208)
NVCEC0_QMDV05_01_COMPLETED_SUB_TASK_MASK = (218, 211)
NVCEC0_QMDV05_01_GRID_WIDTH_RESUME = (255, 224)
NVCEC0_QMDV05_01_GRID_HEIGHT_RESUME = (271, 256)
NVCEC0_QMDV05_01_GRID_DEPTH_RESUME = (287, 272)
NVCEC0_QMDV05_01_RELEASE_ENABLE = lambda i: ((288+(i)*16), (288+(i)*16))
NVCEC0_QMDV05_01_RELEASE_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_RELEASE_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE = lambda i: ((290+(i)*16), (289+(i)*16))
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVCEC0_QMDV05_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE = lambda i: ((291+(i)*16), (291+(i)*16))
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
NVCEC0_QMDV05_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE = lambda i: ((292+(i)*16), (292+(i)*16))
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP = lambda i: ((295+(i)*16), (293+(i)*16))
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
NVCEC0_QMDV05_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT = lambda i: ((297+(i)*16), (296+(i)*16))
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
NVCEC0_QMDV05_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE = lambda i: ((299+(i)*16), (298+(i)*16))
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
NVCEC0_QMDV05_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B = lambda i: ((300+(i)*16), (300+(i)*16))
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000
NVCEC0_QMDV05_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001
NVCEC0_QMDV05_01_RELEASE_RESERVED_INFO = lambda i: ((303+(i)*16), (301+(i)*16))
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE = (336, 336)
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION = (339, 337)
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_01_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH = (340, 340)
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD0_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION = (341, 341)
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
NVCEC0_QMDV05_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST = (342, 342)
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE = (343, 343)
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE = (344, 344)
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION = (347, 345)
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_01_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH = (348, 348)
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD1_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL = (349, 349)
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
NVCEC0_QMDV05_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (350, 350)
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE = (351, 351)
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_CORRELATION_ID = (383, 352)
NVCEC0_QMDV05_01_DEPENDENT_QMD0_POINTER = (415, 384)
NVCEC0_QMDV05_01_DEPENDENT_QMD1_POINTER = (447, 416)
NVCEC0_QMDV05_01_SASS_VERSION = (455, 448)
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT = (456, 456)
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVCEC0_QMDV05_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVCEC0_QMDV05_01_SAMPLER_INDEX = (457, 457)
NVCEC0_QMDV05_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVCEC0_QMDV05_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVCEC0_QMDV05_01_CONSTANT_BANK_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (463, 458)
NVCEC0_QMDV05_01_QMD_MINOR_VERSION = (467, 464)
NVCEC0_QMDV05_01_QMD_MAJOR_VERSION = (471, 468)
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE = (472, 472)
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (473, 473)
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE = (474, 474)
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE = (475, 475)
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE = (476, 476)
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE = (477, 477)
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (478, 478)
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (479, 479)
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (511, 480)
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (536, 512)
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (575, 544)
NVCEC0_QMDV05_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (607, 576)
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (615, 608)
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_ID = (621, 616)
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (622, 622)
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (623, 623)
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE = (625, 624)
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVCEC0_QMDV05_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE = (626, 626)
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_FALSE = 0x00000000
NVCEC0_QMDV05_01_LATCH_ACQUIRE_INVALIDATE_CONSTANT_CACHE_TRUE = 0x00000001
NVCEC0_QMDV05_01_CTA_LAUNCH_QUEUE = (627, 627)
NVCEC0_QMDV05_01_FREE_CTA_SLOTS_EMPTY_SM = (635, 628)
NVCEC0_QMDV05_01_SYNC_DOMAIN_ID = (637, 636)
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (638, 638)
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
NVCEC0_QMDV05_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT = (639, 639)
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
NVCEC0_QMDV05_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_ID = (671, 640)
NVCEC0_QMDV05_01_WAIT_ON_LATCH_ID = (703, 672)
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (721, 714)
NVCEC0_QMDV05_01_OCCUPANCY_MAX_SHARED_MEM = (729, 722)
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID = (730, 730)
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_ARRIVE_AT_LATCH_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID = (731, 731)
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_WAIT_ON_LATCH_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE = (732, 732)
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_LATCH_RELEASE_INVALIDATE_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE = (733, 733)
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_FALSE = 0x00000000
NVCEC0_QMDV05_01_HOLD_CTA_LAUNCH_UNTIL_PARENT_LATCH_ACQUIRE_AND_CTA_COMPLETE_TRUE = 0x00000001
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE = (734, 734)
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
NVCEC0_QMDV05_01_HOLD_MEMBAR_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE = (735, 735)
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_FALSE = 0x00000000
NVCEC0_QMDV05_01_PRIORITY_DEMOTE_UNTIL_LATCH_ACQUIRE_TRUE = 0x00000001
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_WARP = (743, 736)
NVCEC0_QMDV05_01_OCCUPANCY_MAX_WARP = (751, 744)
NVCEC0_QMDV05_01_OCCUPANCY_THRESHOLD_REGISTER = (759, 752)
NVCEC0_QMDV05_01_OCCUPANCY_MAX_REGISTER = (767, 760)
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_LOWER_SHIFTED4 = lambda i: ((799+(i)*416), (768+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_ADDRESS_UPPER_SHIFTED4 = lambda i: ((820+(i)*416), (800+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_SIZE = lambda i: ((829+(i)*416), (821+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE = lambda i: ((831+(i)*416), (830+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION0 = lambda i: ((847+(i)*416), (832+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION1 = lambda i: ((863+(i)*416), (848+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CTA_THREAD_DIMENSION2 = lambda i: ((871+(i)*416), (864+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_REGISTER_COUNT = lambda i: ((880+(i)*416), (872+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_BARRIER_COUNT = lambda i: ((885+(i)*416), (881+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID = lambda i: ((886+(i)*416), (886+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH = lambda i: ((888+(i)*416), (887+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_NONE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_PRE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_PREFETCH_PREFETCH_POST = 0x00000002
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE = lambda i: ((889+(i)*416), (889+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_ICC_PREFETCH_SIZE = lambda i: ((895+(i)*416), (890+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEMORY_SIZE_SHIFTED7 = lambda i: ((906+(i)*416), (896+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_MIN_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((912+(i)*416), (907+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_MAX_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((918+(i)*416), (913+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_TARGET_SM_CONFIG_SHARED_MEM_SIZE = lambda i: ((924+(i)*416), (919+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_SHARED_MEM_BARRIER_INIT_ENABLE = lambda i: ((925+(i)*416), (925+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_LOW_SIZE_SHIFTED4 = lambda i: ((943+(i)*416), (928+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_SHADER_LOCAL_MEMORY_HIGH_SIZE_SHIFTED4 = lambda i: ((959+(i)*416), (944+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_LOWER_SHIFTED6 = lambda i: ((991+(i)*416), (960+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_ADDR_UPPER_SHIFTED6 = lambda i: ((1010+(i)*416), (992+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK0_SIZE_SHIFTED4 = lambda i: ((1023+(i)*416), (1011+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_LOWER_SHIFTED6 = lambda i: ((1055+(i)*416), (1024+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_ADDR_UPPER_SHIFTED6 = lambda i: ((1074+(i)*416), (1056+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_SIZE_SHIFTED4 = lambda i: ((1087+(i)*416), (1075+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID = lambda i: ((1088+(i)*416), (1088+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH = lambda i: ((1090+(i)*416), (1089+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_NONE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_PRE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_PREFETCH_PREFETCH_POST = 0x00000002
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE = lambda i: ((1091+(i)*416), (1091+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK1_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_VIRTUAL_RESOURCE_COUNT = lambda i: ((1099+(i)*416), (1092+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_GRID_WIDTH = lambda i: ((1151+(i)*416), (1120+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_GRID_HEIGHT = lambda i: ((1167+(i)*416), (1152+(i)*416))
NVCEC0_QMDV05_01_SUB_TASK_GRID_DEPTH = lambda i: ((1183+(i)*416), (1168+(i)*416))
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE = lambda i: ((336+(i)*8), (336+(i)*8))
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION = lambda i: ((339+(i)*8), (337+(i)*8))
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV05_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH = lambda i: ((340+(i)*8), (340+(i)*8))
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV05_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV05_01_DEPENDENT_QMD_POINTER = lambda i: ((415+(i)*32), (384+(i)*32))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID = lambda i,j: ((886+(i)*416+(j)*202), (886+(i)*416+(j)*202))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_VALID_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH = lambda i,j: ((888+(i)*416+(j)*202), (887+(i)*416+(j)*202))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_NONE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_PRE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_PREFETCH_PREFETCH_POST = 0x00000002
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE = lambda i,j: ((889+(i)*416+(j)*202), (889+(i)*416+(j)*202))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_LOWER_SHIFTED6 = lambda i,j: ((991+(i)*416+(j)*64), (960+(i)*416+(j)*64))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_ADDR_UPPER_SHIFTED6 = lambda i,j: ((1010+(i)*416+(j)*64), (992+(i)*416+(j)*64))
NVCEC0_QMDV05_01_SUB_TASK_CONSTANT_BANK_SIZE_SHIFTED4 = lambda i,j: ((1023+(i)*416+(j)*64), (1011+(i)*416+(j)*64))
NVCEC0_QMDV04_01_DEPENDENCE_COUNTER = (15, 0)
NVCEC0_QMDV04_01_QMD_GROUP_ID = (21, 16)
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST = (22, 22)
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE = 0x00000000
NVCEC0_QMDV04_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE = 0x00000001
NVCEC0_QMDV04_01_QMD_TYPE = (25, 23)
NVCEC0_QMDV04_01_QMD_TYPE_QUEUE = 0x00000000
NVCEC0_QMDV04_01_QMD_TYPE_GRID_NULL = 0x00000001
NVCEC0_QMDV04_01_QMD_TYPE_GRID_CTA = 0x00000002
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPC_CGA = 0x00000003
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_CGA = 0x00000004
NVCEC0_QMDV04_01_QMD_TYPE_GRID_GPU_GPC_CGA = 0x00000005
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_VALID = (28, 28)
NVCEC0_QMDV04_01_WAIT_ON_LATCH_VALID = (29, 29)
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS = (30, 30)
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_FALSE = 0x00000000
NVCEC0_QMDV04_01_REQUIRE_SCHEDULING_PCAS_TRUE = 0x00000001
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID = (31, 31)
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_FALSE = 0x00000000
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_VALID_TRUE = 0x00000001
NVCEC0_QMDV04_01_CIRCULAR_QUEUE_SIZE = (56, 32)
NVCEC0_QMDV04_01_INNER_GET = (94, 64)
NVCEC0_QMDV04_01_INNER_OVERFLOW = (95, 95)
NVCEC0_QMDV04_01_INNER_PUT = (126, 96)
NVCEC0_QMDV04_01_INNER_STICKY_OVERFLOW = (127, 127)
NVCEC0_QMDV04_01_HW_ONLY_INNER_GET = (190, 160)
NVCEC0_QMDV04_01_HW_ONLY_INNER_PUT = (222, 192)
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX = (253, 224)
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID = (254, 254)
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE = 0x00000000
NVCEC0_QMDV04_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE = 0x00000001
NVCEC0_QMDV04_01_HW_ONLY_SKED_NEXT_QMD_POINTER = (287, 256)
NVCEC0_QMDV04_01_HW_ONLY_DEPENDENCE_COUNTER = (303, 288)
NVCEC0_QMDV04_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS = (304, 304)
NVCEC0_QMDV04_01_RELEASE_ENABLE = lambda i: ((320+(i)*16), (320+(i)*16))
NVCEC0_QMDV04_01_RELEASE_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_RELEASE_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE = lambda i: ((322+(i)*16), (321+(i)*16))
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS = 0x00000000
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD = 0x00000001
NVCEC0_QMDV04_01_RELEASE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS = 0x00000002
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE = lambda i: ((323+(i)*16), (323+(i)*16))
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_NONE = 0x00000000
NVCEC0_QMDV04_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR = 0x00000001
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE = lambda i: ((324+(i)*16), (324+(i)*16))
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_RELEASE_REDUCTION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP = lambda i: ((327+(i)*16), (325+(i)*16))
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_ADD = 0x00000000
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MIN = 0x00000001
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_MAX = 0x00000002
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_INC = 0x00000003
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_DEC = 0x00000004
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_AND = 0x00000005
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_OR = 0x00000006
NVCEC0_QMDV04_01_RELEASE_REDUCTION_OP_RED_XOR = 0x00000007
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT = lambda i: ((329+(i)*16), (328+(i)*16))
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_UNSIGNED = 0x00000000
NVCEC0_QMDV04_01_RELEASE_REDUCTION_FORMAT_SIGNED = 0x00000001
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE = lambda i: ((331+(i)*16), (330+(i)*16))
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_NONE = 0x00000000
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_UNCONDITIONAL = 0x00000001
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL = 0x00000002
NVCEC0_QMDV04_01_RELEASE_TRAP_TYPE_TRAP_CONDITIONAL_EXT = 0x00000003
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B = lambda i: ((332+(i)*16), (332+(i)*16))
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_FALSE = 0x00000000
NVCEC0_QMDV04_01_RELEASE_PAYLOAD64B_TRUE = 0x00000001
NVCEC0_QMDV04_01_RELEASE_RESERVED_INFO = lambda i: ((335+(i)*16), (333+(i)*16))
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE = lambda i: ((368+(i)*5), (368+(i)*5))
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_DEPENDENT_QMD_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION = lambda i: ((371+(i)*5), (369+(i)*5))
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INCREMENT_PUT = 0x00000000
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_SCHEDULE = 0x00000001
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVCEC0_QMDV04_01_DEPENDENT_QMD_ACTION_QMD_DECREMENT_DEPENDENCE = 0x00000004
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH = lambda i: ((372+(i)*5), (372+(i)*5))
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_FALSE = 0x00000000
NVCEC0_QMDV04_01_DEPENDENT_QMD_PREFETCH_TRUE = 0x00000001
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION = (378, 378)
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_FALSE = 0x00000000
NVCEC0_QMDV04_01_SELF_COPY_ON_COMPLETION_TRUE = 0x00000001
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST = (379, 379)
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_FALSE = 0x00000000
NVCEC0_QMDV04_01_DEMOTE_L2_EVICT_LAST_TRUE = 0x00000001
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE = (380, 380)
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV04_01_DISABLE_AUTO_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL = (381, 381)
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_FALSE = 0x00000000
NVCEC0_QMDV04_01_CORRELATION_ID_INTERNAL_TRUE = 0x00000001
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE = (382, 382)
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_CWD_MEMBAR_TASK_CHASING_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_CORRELATION_ID = (415, 384)
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID = lambda i: ((416+(i)*4), (416+(i)*4))
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_FALSE = 0x00000000
NVCEC0_QMDV04_01_CONSTANT_BUFFER_VALID_TRUE = 0x00000001
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH = lambda i: ((418+(i)*4), (417+(i)*4))
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_NONE = 0x00000000
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_PRE = 0x00000001
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PREFETCH_POST = 0x00000002
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE = lambda i: ((419+(i)*4), (419+(i)*4))
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_FALSE = 0x00000000
NVCEC0_QMDV04_01_CONSTANT_BUFFER_INVALIDATE_TRUE = 0x00000001
NVCEC0_QMDV04_01_DEPENDENT_QMD0_POINTER = (479, 448)
NVCEC0_QMDV04_01_DEPENDENT_QMD1_POINTER = (511, 480)
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_LOW_SIZE = (535, 512)
NVCEC0_QMDV04_01_SASS_VERSION = (543, 536)
NVCEC0_QMDV04_01_SHADER_LOCAL_MEMORY_HIGH_SIZE = (567, 544)
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT = (568, 568)
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT__32 = 0x00000000
NVCEC0_QMDV04_01_API_VISIBLE_CALL_LIMIT_NO_CHECK = 0x00000001
NVCEC0_QMDV04_01_SAMPLER_INDEX = (569, 569)
NVCEC0_QMDV04_01_SAMPLER_INDEX_INDEPENDENTLY = 0x00000000
NVCEC0_QMDV04_01_SAMPLER_INDEX_VIA_HEADER_INDEX = 0x00000001
NVCEC0_QMDV04_01_CONSTANT_BUFFER_PREFETCH_PRE_MAX_SIZE_SHIFTED8 = (575, 570)
NVCEC0_QMDV04_01_QMD_MINOR_VERSION = (579, 576)
NVCEC0_QMDV04_01_QMD_MAJOR_VERSION = (583, 580)
NVCEC0_QMDV04_01_SHARED_MEMORY_SIZE = (601, 584)
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE = (602, 602)
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE = (603, 603)
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE = (604, 604)
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE = (605, 605)
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE = (606, 606)
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_INSTRUCTION_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE = (607, 607)
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_MIN_SM_CONFIG_SHARED_MEM_SIZE = (613, 608)
NVCEC0_QMDV04_01_MAX_SM_CONFIG_SHARED_MEM_SIZE = (619, 614)
NVCEC0_QMDV04_01_TARGET_SM_CONFIG_SHARED_MEM_SIZE = (625, 620)
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE = (626, 626)
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_SHARED_ALLOCATION_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_LOWER = (671, 640)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_ADDR_UPPER = (696, 672)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_LOWER = (735, 704)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE0_PAYLOAD_UPPER = (767, 736)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_LOWER = (799, 768)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_ADDR_UPPER = (824, 800)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_LOWER = (863, 832)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE1_PAYLOAD_UPPER = (895, 864)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_LOWER = (927, 896)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_ADDR_UPPER = (952, 928)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_LOWER = (991, 960)
NVCEC0_QMDV04_01_RELEASE_SEMAPHORE2_PAYLOAD_UPPER = (1023, 992)
NVCEC0_QMDV04_01_GRID_WIDTH = (1055, 1024)
NVCEC0_QMDV04_01_GRID_HEIGHT = (1071, 1056)
NVCEC0_QMDV04_01_GRID_DEPTH = (1103, 1088)
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE = (1127, 1120)
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_ID = (1133, 1128)
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE = (1134, 1134)
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE = (1135, 1135)
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE = 0x00000000
NVCEC0_QMDV04_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE = 0x00000001
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE = (1137, 1136)
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_NONE = 0x00000000
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR = 0x00000001
NVCEC0_QMDV04_01_CWD_MEMBAR_TYPE_L1_MEMBAR = 0x00000003
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS = (1138, 1138)
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_FALSE = 0x00000000
NVCEC0_QMDV04_01_SEQUENTIALLY_RUN_CTAS_TRUE = 0x00000001
NVCEC0_QMDV04_01_CTA_LAUNCH_QUEUE = (1139, 1139)
NVCEC0_QMDV04_01_FREE_CTA_SLOTS_EMPTY_SM = (1147, 1140)
NVCEC0_QMDV04_01_SYNC_DOMAIN_ID = (1149, 1148)
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH = (1150, 1150)
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_FALSE = 0x00000000
NVCEC0_QMDV04_01_PRE_EXIT_AT_LAST_CTA_LAUNCH_TRUE = 0x00000001
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT = (1151, 1151)
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_FALSE = 0x00000000
NVCEC0_QMDV04_01_ENABLE_PROGRAM_PRE_EXIT_TRUE = 0x00000001
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION0 = (1167, 1152)
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION1 = (1183, 1168)
NVCEC0_QMDV04_01_CTA_THREAD_DIMENSION2 = (1191, 1184)
NVCEC0_QMDV04_01_VIRTUAL_RESOURCE_COUNT = (1199, 1192)
NVCEC0_QMDV04_01_REGISTER_COUNT = (1208, 1200)
NVCEC0_QMDV04_01_SHARED_MEM_BARRIER_INIT_ENABLE = (1210, 1210)
NVCEC0_QMDV04_01_BARRIER_COUNT = (1215, 1211)
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_LOWER = (1247, 1216)
NVCEC0_QMDV04_01_PROGRAM_ADDRESS_UPPER = (1272, 1248)
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_WARP = (1287, 1280)
NVCEC0_QMDV04_01_OCCUPANCY_MAX_WARP = (1295, 1288)
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_REGISTER = (1303, 1296)
NVCEC0_QMDV04_01_OCCUPANCY_MAX_REGISTER = (1311, 1304)
NVCEC0_QMDV04_01_OCCUPANCY_THRESHOLD_SHARED_MEM = (1319, 1312)
NVCEC0_QMDV04_01_OCCUPANCY_MAX_SHARED_MEM = (1327, 1320)
NVCEC0_QMDV04_01_ICC_PREFETCH_SIZE = (1333, 1328)
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED = (1375, 1344)
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED = (1392, 1376)
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_SIZE = (1401, 1393)
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE = (1403, 1402)
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH = 0x00000000
NVCEC0_QMDV04_01_PROGRAM_PREFETCH_TYPE_PREFTECH_POST = 0x00000001
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE = (1406, 1406)
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_SHADER_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE = (1407, 1407)
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_FALSE = 0x00000000
NVCEC0_QMDV04_01_LATCH_ACQUIRE_INVALIDATE_TEXTURE_DATA_CACHE_TRUE = 0x00000001
NVCEC0_QMDV04_01_GRID_WIDTH_RESUME = (1439, 1408)
NVCEC0_QMDV04_01_GRID_HEIGHT_RESUME = (1455, 1440)
NVCEC0_QMDV04_01_GRID_DEPTH_RESUME = (1471, 1456)
NVCEC0_QMDV04_01_ARRIVE_AT_LATCH_ID = (1503, 1472)
NVCEC0_QMDV04_01_WAIT_ON_LATCH_ID = (1535, 1504)
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_LOWER_SHIFTED6 = lambda i: ((1567+(i)*64), (1536+(i)*64))
NVCEC0_QMDV04_01_CONSTANT_BUFFER_ADDR_UPPER_SHIFTED6 = lambda i: ((1586+(i)*64), (1568+(i)*64))
NVCEC0_QMDV04_01_CONSTANT_BUFFER_SIZE_SHIFTED4 = lambda i: ((1599+(i)*64), (1587+(i)*64))
NVCEC0_QMDV04_01_COALESCE_WAITING_PERIOD = (2135, 2128)
NVCEC0_QMDV04_01_QUEUE_ENTRIES_PER_CTA_LOG2 = (2140, 2136)
NVCEC0_QMDV04_01_GPC_CGA_WIDTH = (2149, 2144)
NVCEC0_QMDV04_01_GPC_CGA_HEIGHT = (2157, 2152)
NVCEC0_QMDV04_01_GPC_CGA_DEPTH = (2165, 2160)
NVCEC0_QMDV04_01_LARGE_GPC_CGA_WIDTH_MINUS_ONE = (2171, 2168)
NVCEC0_QMDV04_01_LARGE_GPC_CGA_HEIGHT_MINUS_ONE = (2175, 2172)
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE = (2207, 2207)
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_LOAD_BALANCING = 0x00000000
NVCEC0_QMDV04_01_CGA_CTA_DISTRIBUTION_MODE_MULTI_CAST = 0x00000001
NVCEC0_QMDV04_01_GPU_CGA_WIDTH = (2223, 2208)
NVCEC0_QMDV04_01_GPU_CGA_HEIGHT = (2239, 2224)
NVCEC0_QMDV04_01_GPU_CGA_DEPTH = (2255, 2240)
NVCEC0_QMDV04_01_DEBUG_ID_LOWER = (2399, 2368)
NVCEC0_QMDV04_01_DEBUG_ID_UPPER = (2431, 2400)
NVCEC0_QMDV04_01_TPC_DISABLE_MASK = lambda i: ((2463+(i)*32), (2432+(i)*32))
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_WIDTH_RESUME = (2591, 2560)
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_HEIGHT_RESUME = (2607, 2592)
NVCEC0_QMDV04_01_INCOMPLETE_BOX_BASE_DEPTH_RESUME = (2623, 2608)
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_WIDTH_RESUME = (2627, 2624)
NVCEC0_QMDV04_01_INCOMPLETE_BOX_OFFSET_HEIGHT_RESUME = (2631, 2628)
NVCEC0_QMDV04_01_TPC_DISABLE_MASK_UPPER = lambda i: ((2719+(i)*32), (2688+(i)*32))
NVCEC0_QMDV04_01_OUTER_PUT = (3038, 3008)
NVCEC0_QMDV04_01_OUTER_OVERFLOW = (3039, 3039)
NVCEC0_QMDV04_01_OUTER_GET = (3070, 3040)
NVCEC0_QMDV04_01_OUTER_STICKY_OVERFLOW = (3071, 3071)
NVBIT = lambda b: (1<<(b))
NVBIT32 = lambda b: NVBIT_TYPE(b, NvU32)
NVBIT64 = lambda b: NVBIT_TYPE(b, NvU64)
NV_BITMASK32_IDX = lambda chId: (((chId) & ~(0x1F)) >> 5)
NV_BITMASK32_OFFSET = lambda chId: ((chId) & (0x1F))
NV_BITMASK32_GET = lambda pChannelMask,chId: ((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId)))
DRF_SHIFT = lambda drf: ((DRF_ISBIT(0,drf)) % 32)
DRF_SHIFT_RT = lambda drf: ((DRF_ISBIT(1,drf)) % 32)
DRF_SIZE = lambda drf: (DRF_EXTENT(drf)-DRF_BASE(drf)+1)
DRF_MASK = lambda drf: (0xFFFFFFFF>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32)))
DRF_SHIFTMASK = lambda drf: (DRF_MASK(drf)<<(DRF_SHIFT(drf)))
DRF_SHIFT64 = lambda drf: ((DRF_ISBIT(0,drf)) % 64)
DRF_MASK64 = lambda drf: (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64)))
DRF_SHIFTMASK64 = lambda drf: (DRF_MASK64(drf)<<(DRF_SHIFT64(drf)))
FLD_TEST_DRF_NUM64 = lambda d,r,f,n,v: (DRF_VAL64(d, r, f, (v)) == (n))
REF_VAL64 = lambda drf,v: (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf))
REF_NUM64 = lambda drf,n: (((NvU64)(n)&DRF_MASK64(drf))<<DRF_SHIFT64(drf))
FLD_SET_REF_NUM64 = lambda drf,n,v: (((NvU64)(v) & ~DRF_SHIFTMASK64(drf)) | REF_NUM64(drf,n))
FLD_TEST_DRF_NUM = lambda d,r,f,n,v: ((DRF_VAL(d, r, f, (v)) == (n)))
REF_VAL = lambda drf,v: (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf))
REF_NUM = lambda drf,n: (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf))
FLD_SET_REF_NUM = lambda drf,n,v: (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n))
DRF_EXPAND_MW = lambda drf: drf
DRF_WORD_MW = lambda drf: (DRF_PICK_MW(drf,0)/32)
DRF_BASE_MW = lambda drf: (DRF_PICK_MW(drf,0)%32)
DRF_EXTENT_MW = lambda drf: (DRF_PICK_MW(drf,1)%32)
DRF_SHIFT_MW = lambda drf: (DRF_PICK_MW(drf,0)%32)
DRF_MASK_MW = lambda drf: (0xFFFFFFFF>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32))
DRF_SHIFTMASK_MW = lambda drf: ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf)))
DRF_SIZE_MW = lambda drf: (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1)
DRF_WORD_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)/32)
DRF_WORD_MW_HIGH = lambda drf: (DRF_PICK_MW(drf,1)/32)
DRF_MASK_MW_LOW = lambda drf: (0xFFFFFFFF)
DRF_MASK_MW_HIGH = lambda drf: (0xFFFFFFFF>>(31-(DRF_EXTENT_MW(drf))))
DRF_SHIFT_MW_LOW = lambda drf: (DRF_PICK_MW(drf,0)%32)
DRF_SHIFT_MW_HIGH = lambda drf: (0)
DRF_MERGE_SHIFT = lambda drf: ((32-((DRF_PICK_MW(drf,0)%32)))%32)
FLD_MERGE_MW = lambda drf,n,v: (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n)
FLD_IDX_MERGE_MW = lambda drf,i,n,v: (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n)
FLD_TEST_DRF_NUM_MW = lambda d,r,f,n,v: ((DRF_VAL_MW(d, r, f, (v)) == n))
NV_TWO_N_MINUS_ONE = lambda n: (((1<<(n/2))<<((n+1)/2))-1)
LOWESTBIT = lambda x: ( (x) &  (((x) - 1) ^ (x)) )
NV_ANYSIZE_ARRAY = 1
NV_CEIL = lambda a,b: (((a)+(b)-1)/(b))
NV_DIV_AND_CEIL = lambda a,b: NV_CEIL(a,b)
NV_SIGN = lambda s: ((NvS8)(((s) > 0) - ((s) < 0)))
NV_ZERO_SIGN = lambda s: ((NvS8)((((s) >= 0) * 2) - 1))
NV_UNSIGNED_ROUNDED_DIV = lambda a,b: (((a) + ((b) / 2)) / (b))
NV_UNSIGNED_DIV_CEIL = lambda a,b: (((a) + (b - 1)) / (b))
NV_ALIGN_DOWN = lambda v,gran: ((v) & ~((v) - (v) + (gran) - 1))
NV_ALIGN_UP = lambda v,gran: (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1))
NV_IS_ALIGNED = lambda v,gran: (0 == ((v) & ((gran) - 1)))
NV_BIT_GET = lambda k,x: (((x) >> (k)) & 1)
NV_ARRAY_ELEMENTS = lambda x: ((sizeof(x)/sizeof((x)[0])))
BIT = lambda b: (1<<(b))
NV01_NULL_OBJECT = (0x0)
NV1_NULL_OBJECT = NV01_NULL_OBJECT
NV01_ROOT = (0x0)
NV0000_ALLOC_PARAMETERS_MESSAGE_ID = (0x0000)
NV01_DEVICE_0 = (0x80)
NV0080_ALLOC_PARAMETERS_MESSAGE_ID = (0x0080)
NV20_SUBDEVICE_0 = (0x2080)
NV2080_ALLOC_PARAMETERS_MESSAGE_ID = (0x2080)
NV2080_NOTIFIERS_SW = (0)
NV2080_NOTIFIERS_HOTPLUG = (1)
NV2080_NOTIFIERS_POWER_CONNECTOR = (2)
NV2080_NOTIFIERS_THERMAL_SW = (3)
NV2080_NOTIFIERS_THERMAL_HW = (4)
NV2080_NOTIFIERS_FULL_SCREEN_CHANGE = (5)
NV2080_NOTIFIERS_EVENTBUFFER = (6)
NV2080_NOTIFIERS_DP_IRQ = (7)
NV2080_NOTIFIERS_GR_DEBUG_INTR = (8)
NV2080_NOTIFIERS_PMU_EVENT = (9)
NV2080_NOTIFIERS_PMU_COMMAND = (10)
NV2080_NOTIFIERS_TIMER = (11)
NV2080_NOTIFIERS_GRAPHICS = (12)
NV2080_NOTIFIERS_PPP = (13)
NV2080_NOTIFIERS_VLD = (14)
NV2080_NOTIFIERS_NVDEC0 = NV2080_NOTIFIERS_VLD
NV2080_NOTIFIERS_NVDEC1 = (15)
NV2080_NOTIFIERS_NVDEC2 = (16)
NV2080_NOTIFIERS_NVDEC3 = (17)
NV2080_NOTIFIERS_NVDEC4 = (18)
NV2080_NOTIFIERS_NVDEC5 = (19)
NV2080_NOTIFIERS_NVDEC6 = (20)
NV2080_NOTIFIERS_NVDEC7 = (21)
NV2080_NOTIFIERS_PDEC = (22)
NV2080_NOTIFIERS_CE0 = (23)
NV2080_NOTIFIERS_CE1 = (24)
NV2080_NOTIFIERS_CE2 = (25)
NV2080_NOTIFIERS_CE3 = (26)
NV2080_NOTIFIERS_CE4 = (27)
NV2080_NOTIFIERS_CE5 = (28)
NV2080_NOTIFIERS_CE6 = (29)
NV2080_NOTIFIERS_CE7 = (30)
NV2080_NOTIFIERS_CE8 = (31)
NV2080_NOTIFIERS_CE9 = (32)
NV2080_NOTIFIERS_PSTATE_CHANGE = (33)
NV2080_NOTIFIERS_HDCP_STATUS_CHANGE = (34)
NV2080_NOTIFIERS_FIFO_EVENT_MTHD = (35)
NV2080_NOTIFIERS_PRIV_RING_HANG = (36)
NV2080_NOTIFIERS_RC_ERROR = (37)
NV2080_NOTIFIERS_MSENC = (38)
NV2080_NOTIFIERS_NVENC0 = NV2080_NOTIFIERS_MSENC
NV2080_NOTIFIERS_NVENC1 = (39)
NV2080_NOTIFIERS_NVENC2 = (40)
NV2080_NOTIFIERS_UNUSED_0 = (41)
NV2080_NOTIFIERS_ACPI_NOTIFY = (42)
NV2080_NOTIFIERS_COOLER_DIAG_ZONE = (43)
NV2080_NOTIFIERS_THERMAL_DIAG_ZONE = (44)
NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST = (45)
NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE = (46)
NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT = (47)
NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT = (48)
NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT = (49)
NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT = (50)
NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT = (51)
NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT = (52)
NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT = (53)
NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT = (54)
NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT = (55)
NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT = (56)
NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT = (57)
NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT = (58)
NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT = (59)
NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT = (60)
NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT = (61)
NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT = (62)
NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT = (63)
NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT = (64)
NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT = (65)
NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT = (66)
NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT = (67)
NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT = (68)
NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT = (69)
NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT = (70)
NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT = (71)
NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT = (72)
NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT = (73)
NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT = (74)
NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT = (75)
NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT = (76)
NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT = (77)
NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT = (78)
NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT = (79)
NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT = (80)
NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT = (81)
NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT = (82)
NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT = (83)
NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT = (84)
NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT = (85)
NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT = (86)
NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT = (87)
NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT = (88)
NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT = (89)
NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT = (90)
NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT = (91)
NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT = (92)
NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT = (93)
NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT = (94)
NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT = (95)
NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT = (96)
NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT = (97)
NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT = (98)
NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT = (99)
NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT = (100)
NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT = (101)
NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT = (102)
NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT = (103)
NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT = (104)
NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT = (105)
NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT = (106)
NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT = (107)
NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT = (108)
NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT = (109)
NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT = (110)
NV2080_NOTIFIERS_ECC_SBE = (111)
NV2080_NOTIFIERS_ECC_DBE = (112)
NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION = (113)
NV2080_NOTIFIERS_GC5_GPU_READY = (114)
NV2080_NOTIFIERS_SEC2 = (115)
NV2080_NOTIFIERS_GC6_REFCOUNT_INC = (116)
NV2080_NOTIFIERS_GC6_REFCOUNT_DEC = (117)
NV2080_NOTIFIERS_POWER_EVENT = (118)
NV2080_NOTIFIERS_CLOCKS_CHANGE = (119)
NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE = (120)
NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT = (121)
NV2080_NOTIFIERS_RESERVED122 = (122)
NV2080_NOTIFIERS_NVLINK_ERROR_FATAL = (123)
NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT = (124)
NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED = (125)
NV2080_NOTIFIERS_NVJPG = (126)
NV2080_NOTIFIERS_NVJPEG0 = NV2080_NOTIFIERS_NVJPG
NV2080_NOTIFIERS_NVJPEG1 = (127)
NV2080_NOTIFIERS_NVJPEG2 = (128)
NV2080_NOTIFIERS_NVJPEG3 = (129)
NV2080_NOTIFIERS_NVJPEG4 = (130)
NV2080_NOTIFIERS_NVJPEG5 = (131)
NV2080_NOTIFIERS_NVJPEG6 = (132)
NV2080_NOTIFIERS_NVJPEG7 = (133)
NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE = (134)
NV2080_NOTIFIERS_RUNLIST_ACQUIRE = (135)
NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE = (136)
NV2080_NOTIFIERS_RUNLIST_IDLE = (137)
NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE = (138)
NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE = (139)
NV2080_NOTIFIERS_CTXSW_TIMEOUT = (140)
NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED = (141)
NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT = (142)
NV2080_NOTIFIERS_DSTATE_XUSB_PPC = (143)
NV2080_NOTIFIERS_FECS_CTX_SWITCH = (144)
NV2080_NOTIFIERS_XUSB_PPC_CONNECTED = (145)
NV2080_NOTIFIERS_GR0 = NV2080_NOTIFIERS_GRAPHICS
NV2080_NOTIFIERS_GR1 = (146)
NV2080_NOTIFIERS_GR2 = (147)
NV2080_NOTIFIERS_GR3 = (148)
NV2080_NOTIFIERS_GR4 = (149)
NV2080_NOTIFIERS_GR5 = (150)
NV2080_NOTIFIERS_GR6 = (151)
NV2080_NOTIFIERS_GR7 = (152)
NV2080_NOTIFIERS_OFA = (153)
NV2080_NOTIFIERS_OFA0 = NV2080_NOTIFIERS_OFA
NV2080_NOTIFIERS_DSTATE_HDA = (154)
NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL = (155)
NV2080_NOTIFIERS_POISON_ERROR_FATAL = (156)
NV2080_NOTIFIERS_UCODE_RESET = (157)
NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE = (158)
NV2080_NOTIFIERS_SMC_CONFIG_UPDATE = (159)
NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED = (160)
NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED = (161)
NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST = (162)
NV2080_NOTIFIERS_SEC_FAULT_ERROR = (163)
NV2080_NOTIFIERS_UNUSED_1 = (164)
NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP = (165)
NV2080_NOTIFIERS_CE10 = (166)
NV2080_NOTIFIERS_CE11 = (167)
NV2080_NOTIFIERS_CE12 = (168)
NV2080_NOTIFIERS_CE13 = (169)
NV2080_NOTIFIERS_CE14 = (170)
NV2080_NOTIFIERS_CE15 = (171)
NV2080_NOTIFIERS_CE16 = (172)
NV2080_NOTIFIERS_CE17 = (173)
NV2080_NOTIFIERS_CE18 = (174)
NV2080_NOTIFIERS_CE19 = (175)
NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN = (176)
NV2080_NOTIFIERS_NVPCF_EVENTS = (177)
NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST = (178)
NV2080_NOTIFIERS_VRR_SET_TIMEOUT = (179)
NV2080_NOTIFIERS_OFA1 = (180)
NV2080_NOTIFIERS_AUX_POWER_EVENT = (181)
NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE = (182)
NV2080_NOTIFIERS_NVENC3 = (183)
NV2080_NOTIFIERS_GSP_PERF_TRACE = (184)
NV2080_NOTIFIERS_INBAND_RESPONSE = (185)
NV2080_NOTIFIERS_RESERVED_186 = (186)
NV2080_NOTIFIERS_ECC_SBE_STORM = (187)
NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT = (188)
NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE = (189)
NV2080_NOTIFIERS_NVLINK_UNCONTAINED_ERROR = (190)
NV2080_NOTIFIERS_GPU_UNAVAILABLE = (191)
NV2080_NOTIFIERS_GPU_RECOVERY_ACTION = (192)
NV2080_NOTIFIERS_POWER_SUSPEND = (193)
NV2080_NOTIFIERS_POWER_RESUME = (194)
NV2080_NOTIFIERS_CTXSW_UCODE_ERROR = (195)
NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD = (196)
NV2080_NOTIFIERS_MAXCOUNT = (197)
NV2080_NOTIFIERS_GR_IDX = lambda x: ((x) - NV2080_NOTIFIERS_GR0)
NV2080_NOTIFIER_TYPE_IS_GR = lambda x: (((x) == NV2080_NOTIFIERS_GR0) or (((x) >= NV2080_NOTIFIERS_GR1) and ((x) <= NV2080_NOTIFIERS_GR7)))
NV2080_NOTIFIER_TYPE_IS_CE = lambda x: ((((x) >= NV2080_NOTIFIERS_CE0) and ((x) <= NV2080_NOTIFIERS_CE9)) or (((x) >= NV2080_NOTIFIERS_CE10) and ((x) <= NV2080_NOTIFIERS_CE19)))
NV2080_NOTIFIER_TYPE_IS_NVENC = lambda x: ((((x) >= NV2080_NOTIFIERS_NVENC0) and ((x) <= NV2080_NOTIFIERS_NVENC2)) or (((x) == NV2080_NOTIFIERS_NVENC3)))
NV2080_NOTIFIERS_NVDEC = lambda x: (NV2080_NOTIFIERS_NVDEC0 + (x))
NV2080_NOTIFIERS_NVDEC_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVDEC0)
NV2080_NOTIFIER_TYPE_IS_NVDEC = lambda x: (((x) >= NV2080_NOTIFIERS_NVDEC0) and ((x) <= NV2080_NOTIFIERS_NVDEC7))
NV2080_NOTIFIERS_NVJPEG = lambda x: (NV2080_NOTIFIERS_NVJPEG0 + (x))
NV2080_NOTIFIERS_NVJPEG_IDX = lambda x: ((x) - NV2080_NOTIFIERS_NVJPEG0)
NV2080_NOTIFIER_TYPE_IS_NVJPEG = lambda x: (((x) >= NV2080_NOTIFIERS_NVJPEG0) and ((x) <= NV2080_NOTIFIERS_NVJPEG7))
NV2080_NOTIFIER_TYPE_IS_OFA = lambda x: (((x) == NV2080_NOTIFIERS_OFA0) or ((x) == NV2080_NOTIFIERS_OFA1))
NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin))
NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT = lambda pin: (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin))
NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS = (0x8000)
NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT = (0x4000)
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE = (0x2000)
NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE = (0x1000)
NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS = (0x0000)
NV2080_ENGINE_TYPE_NULL = (0x00000000)
NV2080_ENGINE_TYPE_GRAPHICS = (0x00000001)
NV2080_ENGINE_TYPE_GR0 = NV2080_ENGINE_TYPE_GRAPHICS
NV2080_ENGINE_TYPE_GR1 = (0x00000002)
NV2080_ENGINE_TYPE_GR2 = (0x00000003)
NV2080_ENGINE_TYPE_GR3 = (0x00000004)
NV2080_ENGINE_TYPE_GR4 = (0x00000005)
NV2080_ENGINE_TYPE_GR5 = (0x00000006)
NV2080_ENGINE_TYPE_GR6 = (0x00000007)
NV2080_ENGINE_TYPE_GR7 = (0x00000008)
NV2080_ENGINE_TYPE_COPY0 = (0x00000009)
NV2080_ENGINE_TYPE_COPY1 = (0x0000000a)
NV2080_ENGINE_TYPE_COPY2 = (0x0000000b)
NV2080_ENGINE_TYPE_COPY3 = (0x0000000c)
NV2080_ENGINE_TYPE_COPY4 = (0x0000000d)
NV2080_ENGINE_TYPE_COPY5 = (0x0000000e)
NV2080_ENGINE_TYPE_COPY6 = (0x0000000f)
NV2080_ENGINE_TYPE_COPY7 = (0x00000010)
NV2080_ENGINE_TYPE_COPY8 = (0x00000011)
NV2080_ENGINE_TYPE_COPY9 = (0x00000012)
NV2080_ENGINE_TYPE_BSP = (0x00000013)
NV2080_ENGINE_TYPE_NVDEC0 = NV2080_ENGINE_TYPE_BSP
NV2080_ENGINE_TYPE_NVDEC1 = (0x00000014)
NV2080_ENGINE_TYPE_NVDEC2 = (0x00000015)
NV2080_ENGINE_TYPE_NVDEC3 = (0x00000016)
NV2080_ENGINE_TYPE_NVDEC4 = (0x00000017)
NV2080_ENGINE_TYPE_NVDEC5 = (0x00000018)
NV2080_ENGINE_TYPE_NVDEC6 = (0x00000019)
NV2080_ENGINE_TYPE_NVDEC7 = (0x0000001a)
NV2080_ENGINE_TYPE_MSENC = (0x0000001b)
NV2080_ENGINE_TYPE_NVENC0 = NV2080_ENGINE_TYPE_MSENC
NV2080_ENGINE_TYPE_NVENC1 = (0x0000001c)
NV2080_ENGINE_TYPE_NVENC2 = (0x0000001d)
NV2080_ENGINE_TYPE_VP = (0x0000001e)
NV2080_ENGINE_TYPE_ME = (0x0000001f)
NV2080_ENGINE_TYPE_PPP = (0x00000020)
NV2080_ENGINE_TYPE_MPEG = (0x00000021)
NV2080_ENGINE_TYPE_SW = (0x00000022)
NV2080_ENGINE_TYPE_CIPHER = (0x00000023)
NV2080_ENGINE_TYPE_TSEC = NV2080_ENGINE_TYPE_CIPHER
NV2080_ENGINE_TYPE_VIC = (0x00000024)
NV2080_ENGINE_TYPE_MP = (0x00000025)
NV2080_ENGINE_TYPE_SEC2 = (0x00000026)
NV2080_ENGINE_TYPE_HOST = (0x00000027)
NV2080_ENGINE_TYPE_DPU = (0x00000028)
NV2080_ENGINE_TYPE_PMU = (0x00000029)
NV2080_ENGINE_TYPE_FBFLCN = (0x0000002a)
NV2080_ENGINE_TYPE_NVJPG = (0x0000002b)
NV2080_ENGINE_TYPE_NVJPEG0 = NV2080_ENGINE_TYPE_NVJPG
NV2080_ENGINE_TYPE_NVJPEG1 = (0x0000002c)
NV2080_ENGINE_TYPE_NVJPEG2 = (0x0000002d)
NV2080_ENGINE_TYPE_NVJPEG3 = (0x0000002e)
NV2080_ENGINE_TYPE_NVJPEG4 = (0x0000002f)
NV2080_ENGINE_TYPE_NVJPEG5 = (0x00000030)
NV2080_ENGINE_TYPE_NVJPEG6 = (0x00000031)
NV2080_ENGINE_TYPE_NVJPEG7 = (0x00000032)
NV2080_ENGINE_TYPE_OFA = (0x00000033)
NV2080_ENGINE_TYPE_OFA0 = NV2080_ENGINE_TYPE_OFA
NV2080_ENGINE_TYPE_COPY10 = (0x00000034)
NV2080_ENGINE_TYPE_COPY11 = (0x00000035)
NV2080_ENGINE_TYPE_COPY12 = (0x00000036)
NV2080_ENGINE_TYPE_COPY13 = (0x00000037)
NV2080_ENGINE_TYPE_COPY14 = (0x00000038)
NV2080_ENGINE_TYPE_COPY15 = (0x00000039)
NV2080_ENGINE_TYPE_COPY16 = (0x0000003a)
NV2080_ENGINE_TYPE_COPY17 = (0x0000003b)
NV2080_ENGINE_TYPE_COPY18 = (0x0000003c)
NV2080_ENGINE_TYPE_COPY19 = (0x0000003d)
NV2080_ENGINE_TYPE_OFA1 = (0x0000003e)
NV2080_ENGINE_TYPE_NVENC3 = (0x0000003f)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 = (0x00000040)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 = (0x00000041)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 = (0x00000042)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 = (0x00000043)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 = (0x00000044)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 = (0x00000045)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 = (0x00000046)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 = (0x00000047)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 = (0x00000048)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 = (0x00000049)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 = (0x0000004a)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 = (0x0000004b)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 = (0x0000004c)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 = (0x0000004d)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 = (0x0000004e)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 = (0x0000004f)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 = (0x00000050)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 = (0x00000051)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 = (0x00000052)
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 = (0x00000053)
NV2080_ENGINE_TYPE_LAST = (0x00000054)
NV2080_ENGINE_TYPE_ALLENGINES = (0xffffffff)
NV2080_ENGINE_TYPE_COPY_SIZE = 64
NV2080_ENGINE_TYPE_NVENC_SIZE = 4
NV2080_ENGINE_TYPE_NVJPEG_SIZE = 8
NV2080_ENGINE_TYPE_NVDEC_SIZE = 8
NV2080_ENGINE_TYPE_GR_SIZE = 8
NV2080_ENGINE_TYPE_OFA_SIZE = 2
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY = lambda i: (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i))
NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY = lambda i: (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19))
NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0)
NV2080_ENGINE_TYPE_IS_COPY = lambda i: ((((i) >= NV2080_ENGINE_TYPE_COPY0) and ((i) <= NV2080_ENGINE_TYPE_COPY9)) or (((i) >= NV2080_ENGINE_TYPE_COPY10) and ((i) <= NV2080_ENGINE_TYPE_COPY19)))
NV2080_ENGINE_TYPE_IS_NVENC = lambda i: ((((i) >= NV2080_ENGINE_TYPE_NVENC0) and ((i) <= NV2080_ENGINE_TYPE_NVENC2)) or (((i) == NV2080_ENGINE_TYPE_NVENC3)))
NV2080_ENGINE_TYPE_NVDEC = lambda i: (NV2080_ENGINE_TYPE_NVDEC0+(i))
NV2080_ENGINE_TYPE_IS_NVDEC = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVDEC0) and ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
NV2080_ENGINE_TYPE_NVDEC_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVDEC0)
NV2080_ENGINE_TYPE_NVJPEG = lambda i: (NV2080_ENGINE_TYPE_NVJPEG0+(i))
NV2080_ENGINE_TYPE_IS_NVJPEG = lambda i: (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) and ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE)))
NV2080_ENGINE_TYPE_NVJPEG_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_NVJPEG0)
NV2080_ENGINE_TYPE_GR = lambda i: (NV2080_ENGINE_TYPE_GR0 + (i))
NV2080_ENGINE_TYPE_IS_GR = lambda i: (((i) >= NV2080_ENGINE_TYPE_GR0) and ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
NV2080_ENGINE_TYPE_GR_IDX = lambda i: ((i) - NV2080_ENGINE_TYPE_GR0)
NV2080_ENGINE_TYPE_IS_OFA = lambda i: (((i) == NV2080_ENGINE_TYPE_OFA0) or ((i) == NV2080_ENGINE_TYPE_OFA1))
NV2080_ENGINE_TYPE_IS_VALID = lambda i: (((i) > (NV2080_ENGINE_TYPE_NULL)) and ((i) < (NV2080_ENGINE_TYPE_LAST)))
NV2080_CLIENT_TYPE_TEX = (0x00000001)
NV2080_CLIENT_TYPE_COLOR = (0x00000002)
NV2080_CLIENT_TYPE_DEPTH = (0x00000003)
NV2080_CLIENT_TYPE_DA = (0x00000004)
NV2080_CLIENT_TYPE_FE = (0x00000005)
NV2080_CLIENT_TYPE_SCC = (0x00000006)
NV2080_CLIENT_TYPE_WID = (0x00000007)
NV2080_CLIENT_TYPE_MSVLD = (0x00000008)
NV2080_CLIENT_TYPE_MSPDEC = (0x00000009)
NV2080_CLIENT_TYPE_MSPPP = (0x0000000a)
NV2080_CLIENT_TYPE_VIC = (0x0000000b)
NV2080_CLIENT_TYPE_ALLCLIENTS = (0xffffffff)
NV2080_GC5_EXIT_COMPLETE = (0x00000001)
NV2080_GC5_ENTRY_ABORTED = (0x00000002)
NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION = (0x00000000)
NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION = (0x00000001)
NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT = (0x4000)
NV2080_TYPEDEF = Nv20Subdevice0
AMPERE_CHANNEL_GPFIFO_A = (0x0000C56F)
NVC56F_NUMBER_OF_SUBCHANNELS = (8)
NVC56F_SET_OBJECT = (0x00000000)
NVC56F_SET_OBJECT_ENGINE_SW = 0x0000001f
NVC56F_ILLEGAL = (0x00000004)
NVC56F_NOP = (0x00000008)
NVC56F_SEMAPHOREA = (0x00000010)
NVC56F_SEMAPHOREB = (0x00000014)
NVC56F_SEMAPHOREC = (0x00000018)
NVC56F_SEMAPHORED = (0x0000001C)
NVC56F_SEMAPHORED_OPERATION_ACQUIRE = 0x00000001
NVC56F_SEMAPHORED_OPERATION_RELEASE = 0x00000002
NVC56F_SEMAPHORED_OPERATION_ACQ_GEQ = 0x00000004
NVC56F_SEMAPHORED_OPERATION_ACQ_AND = 0x00000008
NVC56F_SEMAPHORED_OPERATION_REDUCTION = 0x00000010
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED = 0x00000000
NVC56F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED = 0x00000001
NVC56F_SEMAPHORED_RELEASE_WFI_EN = 0x00000000
NVC56F_SEMAPHORED_RELEASE_WFI_DIS = 0x00000001
NVC56F_SEMAPHORED_RELEASE_SIZE_16BYTE = 0x00000000
NVC56F_SEMAPHORED_RELEASE_SIZE_4BYTE = 0x00000001
NVC56F_SEMAPHORED_REDUCTION_MIN = 0x00000000
NVC56F_SEMAPHORED_REDUCTION_MAX = 0x00000001
NVC56F_SEMAPHORED_REDUCTION_XOR = 0x00000002
NVC56F_SEMAPHORED_REDUCTION_AND = 0x00000003
NVC56F_SEMAPHORED_REDUCTION_OR = 0x00000004
NVC56F_SEMAPHORED_REDUCTION_ADD = 0x00000005
NVC56F_SEMAPHORED_REDUCTION_INC = 0x00000006
NVC56F_SEMAPHORED_REDUCTION_DEC = 0x00000007
NVC56F_SEMAPHORED_FORMAT_SIGNED = 0x00000000
NVC56F_SEMAPHORED_FORMAT_UNSIGNED = 0x00000001
NVC56F_NON_STALL_INTERRUPT = (0x00000020)
NVC56F_FB_FLUSH = (0x00000024)
NVC56F_MEM_OP_A = (0x00000028)
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2
NVC56F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001
NVC56F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000
NVC56F_MEM_OP_B = (0x0000002c)
NVC56F_MEM_OP_C = (0x00000030)
NVC56F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000
NVC56F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004
NVC56F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6
NVC56F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006
NVC56F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002
NVC56F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003
NVC56F_MEM_OP_D = (0x00000034)
NVC56F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009
NVC56F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a
NVC56F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d
NVC56F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e
NVC56F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e
NVC56F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f
NVC56F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010
NVC56F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015
NVC56F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000
NVC56F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001
NVC56F_SET_REFERENCE = (0x00000050)
NVC56F_SEM_ADDR_LO = (0x0000005c)
NVC56F_SEM_ADDR_HI = (0x00000060)
NVC56F_SEM_PAYLOAD_LO = (0x00000064)
NVC56F_SEM_PAYLOAD_HI = (0x00000068)
NVC56F_SEM_EXECUTE = (0x0000006c)
NVC56F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
NVC56F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
NVC56F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ = 0x00000002
NVC56F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ = 0x00000003
NVC56F_SEM_EXECUTE_OPERATION_ACQ_AND = 0x00000004
NVC56F_SEM_EXECUTE_OPERATION_ACQ_NOR = 0x00000005
NVC56F_SEM_EXECUTE_OPERATION_REDUCTION = 0x00000006
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS = 0x00000000
NVC56F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN = 0x00000001
NVC56F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
NVC56F_SEM_EXECUTE_RELEASE_WFI_EN = 0x00000001
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
NVC56F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT = 0x00000001
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS = 0x00000000
NVC56F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN = 0x00000001
NVC56F_SEM_EXECUTE_REDUCTION_IMIN = 0x00000000
NVC56F_SEM_EXECUTE_REDUCTION_IMAX = 0x00000001
NVC56F_SEM_EXECUTE_REDUCTION_IXOR = 0x00000002
NVC56F_SEM_EXECUTE_REDUCTION_IAND = 0x00000003
NVC56F_SEM_EXECUTE_REDUCTION_IOR = 0x00000004
NVC56F_SEM_EXECUTE_REDUCTION_IADD = 0x00000005
NVC56F_SEM_EXECUTE_REDUCTION_INC = 0x00000006
NVC56F_SEM_EXECUTE_REDUCTION_DEC = 0x00000007
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED = 0x00000000
NVC56F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED = 0x00000001
NVC56F_WFI = (0x00000078)
NVC56F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000
NVC56F_WFI_SCOPE_CURRENT_VEID = 0x00000000
NVC56F_WFI_SCOPE_ALL = 0x00000001
NVC56F_YIELD = (0x00000080)
NVC56F_YIELD_OP_NOP = 0x00000000
NVC56F_YIELD_OP_TSG = 0x00000003
NVC56F_CLEAR_FAULTED = (0x00000084)
NVC56F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED = 0x00000000
NVC56F_CLEAR_FAULTED_TYPE_ENG_FAULTED = 0x00000001
NVC56F_GP_ENTRY__SIZE = 8
NVC56F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
NVC56F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
NVC56F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
NVC56F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
NVC56F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
NVC56F_GP_ENTRY1_SYNC_WAIT = 0x00000001
NVC56F_GP_ENTRY1_OPCODE_NOP = 0x00000000
NVC56F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
NVC56F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
NVC56F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
NVC56F_DMA_TERT_OP_GRP0_INC_METHOD = (0x00000000)
NVC56F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK = (0x00000001)
NVC56F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK = (0x00000002)
NVC56F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK = (0x00000003)
NVC56F_DMA_TERT_OP_GRP2_NON_INC_METHOD = (0x00000000)
NVC56F_DMA_SEC_OP_GRP0_USE_TERT = (0x00000000)
NVC56F_DMA_SEC_OP_INC_METHOD = (0x00000001)
NVC56F_DMA_SEC_OP_GRP2_USE_TERT = (0x00000002)
NVC56F_DMA_SEC_OP_NON_INC_METHOD = (0x00000003)
NVC56F_DMA_SEC_OP_IMMD_DATA_METHOD = (0x00000004)
NVC56F_DMA_SEC_OP_ONE_INC = (0x00000005)
NVC56F_DMA_SEC_OP_RESERVED6 = (0x00000006)
NVC56F_DMA_SEC_OP_END_PB_SEGMENT = (0x00000007)
NVC56F_DMA_INCR_OPCODE_VALUE = (0x00000001)
NVC56F_DMA_NONINCR_OPCODE_VALUE = (0x00000003)
NVC56F_DMA_ONEINCR_OPCODE_VALUE = (0x00000005)
NVC56F_DMA_NOP = (0x00000000)
NVC56F_DMA_IMMD_OPCODE_VALUE = (0x00000004)
NVC56F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000001)
NVC56F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000002)
NVC56F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE = (0x00000003)
NVC56F_DMA_ENDSEG_OPCODE_VALUE = (0x00000007)
NVC56F_DMA_OPCODE3_NONE = (0x00000000)
NVC56F_DMA_OPCODE_METHOD = (0x00000000)
NVC56F_DMA_OPCODE_NONINC_METHOD = (0x00000002)
HOPPER_CHANNEL_GPFIFO_A = (0x0000C86F)
NVC86F_SET_OBJECT = (0x00000000)
NVC86F_SEM_ADDR_LO = (0x0000005c)
NVC86F_SEM_ADDR_HI = (0x00000060)
NVC86F_SEM_PAYLOAD_LO = (0x00000064)
NVC86F_SEM_PAYLOAD_HI = (0x00000068)
NVC86F_SEM_EXECUTE = (0x0000006c)
NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
NVC86F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
NVC86F_GP_ENTRY__SIZE = 8
NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
NVC86F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
NVC86F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
NVC86F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
NVC86F_GP_ENTRY1_SYNC_WAIT = 0x00000001
NVC86F_GP_ENTRY1_OPCODE_NOP = 0x00000000
NVC86F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
NVC86F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
NVC86F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004
NVC86F_WFI = (0x00000078)
NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE = 0x00000000
NVC86F_WFI_SCOPE_CURRENT_VEID = 0x00000000
NVC86F_WFI_SCOPE_ALL = 0x00000001
NVC86F_MEM_OP_A = (0x00000028)
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS = 0
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS = 1
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS = 2
NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD = 3
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN = 0x00000001
NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS = 0x00000000
NVC86F_MEM_OP_B = (0x0000002c)
NVC86F_MEM_OP_C = (0x00000030)
NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR = 0x00000000
NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL = 0x00000002
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED = 0x00000003
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL = 0x00000004
NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL = 0x00000005
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE = 0x00000002
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ = 0
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE = 1
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 2
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD = 3
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 4
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL = 5
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC = 6
NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL = 7
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY = 0x00000001
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 = 0x00000002
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 = 0x00000003
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 = 0x00000004
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 = 0x00000005
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 = 0x00000006
NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 = 0x00000007
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM = 0x00000000
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT = 0x00000002
NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT = 0x00000003
NVC86F_MEM_OP_D = (0x00000034)
NVC86F_MEM_OP_D_OPERATION_MEMBAR = 0x00000005
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE = 0x00000009
NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED = 0x0000000a
NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION = 0x0000000b
NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE = 0x0000000d
NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE = 0x0000000e
NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES = 0x0000000e
NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS = 0x0000000f
NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY = 0x00000010
NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS = 0x00000015
NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR = 0x00000016
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC = 0x00000000
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC = 0x00000001
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL = 0x00000002
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED = 0x00000003
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC = 0x00000000
NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC = 0x00000001
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED = 0x00000000
NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP = 0x00000001
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000C96F)
NVC96F_SET_OBJECT = (0x00000000)
NVC96F_SEM_ADDR_LO = (0x0000005c)
NVC96F_SEM_ADDR_HI = (0x00000060)
NVC96F_SEM_PAYLOAD_LO = (0x00000064)
NVC96F_SEM_PAYLOAD_HI = (0x00000068)
NVC96F_SEM_EXECUTE = (0x0000006c)
NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE = 0x00000000
NVC96F_SEM_EXECUTE_OPERATION_RELEASE = 0x00000001
NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS = 0x00000000
NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT = 0x00000000
NVC96F_GP_ENTRY__SIZE = 8
NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL = 0x00000000
NVC96F_GP_ENTRY0_FETCH_CONDITIONAL = 0x00000001
NVC96F_GP_ENTRY1_LEVEL_MAIN = 0x00000000
NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE = 0x00000001
NVC96F_GP_ENTRY1_SYNC_PROCEED = 0x00000000
NVC96F_GP_ENTRY1_SYNC_WAIT = 0x00000001
NVC96F_GP_ENTRY1_OPCODE_NOP = 0x00000000
NVC96F_GP_ENTRY1_OPCODE_ILLEGAL = 0x00000001
NVC96F_GP_ENTRY1_OPCODE_GP_CRC = 0x00000002
NVC96F_GP_ENTRY1_OPCODE_PB_CRC = 0x00000003
NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE = 0x00000004
BLACKWELL_USERMODE_A = (0xc761)
GT200_DEBUGGER = (0x83de)
NV83DE_ALLOC_PARAMETERS_MESSAGE_ID = (0x83de)
AMPERE_COMPUTE_A = 0xC6C0
NVC6C0_SET_OBJECT = 0x0000
NVC6C0_NO_OPERATION = 0x0100
NVC6C0_SET_NOTIFY_A = 0x0104
NVC6C0_SET_NOTIFY_B = 0x0108
NVC6C0_NOTIFY = 0x010c
NVC6C0_NOTIFY_TYPE_WRITE_ONLY = 0x00000000
NVC6C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN = 0x00000001
NVC6C0_WAIT_FOR_IDLE = 0x0110
NVC6C0_SET_GLOBAL_RENDER_ENABLE_A = 0x0130
NVC6C0_SET_GLOBAL_RENDER_ENABLE_B = 0x0134
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C = 0x0138
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
NVC6C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
NVC6C0_SEND_GO_IDLE = 0x013c
NVC6C0_PM_TRIGGER = 0x0140
NVC6C0_PM_TRIGGER_WFI = 0x0144
NVC6C0_FE_ATOMIC_SEQUENCE_BEGIN = 0x0148
NVC6C0_FE_ATOMIC_SEQUENCE_END = 0x014c
NVC6C0_SET_INSTRUMENTATION_METHOD_HEADER = 0x0150
NVC6C0_SET_INSTRUMENTATION_METHOD_DATA = 0x0154
NVC6C0_LINE_LENGTH_IN = 0x0180
NVC6C0_LINE_COUNT = 0x0184
NVC6C0_OFFSET_OUT_UPPER = 0x0188
NVC6C0_OFFSET_OUT = 0x018c
NVC6C0_PITCH_OUT = 0x0190
NVC6C0_SET_DST_BLOCK_SIZE = 0x0194
NVC6C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = 0x00000000
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = 0x00000000
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = 0x00000001
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = 0x00000002
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = 0x00000003
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = 0x00000004
NVC6C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = 0x00000005
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = 0x00000000
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = 0x00000001
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = 0x00000002
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = 0x00000003
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = 0x00000004
NVC6C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = 0x00000005
NVC6C0_SET_DST_WIDTH = 0x0198
NVC6C0_SET_DST_HEIGHT = 0x019c
NVC6C0_SET_DST_DEPTH = 0x01a0
NVC6C0_SET_DST_LAYER = 0x01a4
NVC6C0_SET_DST_ORIGIN_BYTES_X = 0x01a8
NVC6C0_SET_DST_ORIGIN_SAMPLES_Y = 0x01ac
NVC6C0_LAUNCH_DMA = 0x01b0
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = 0x00000000
NVC6C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = 0x00000001
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE = 0x00000000
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY = 0x00000001
NVC6C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE = 0x00000002
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE = 0x00000000
NVC6C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT = 0x00000001
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD = 0x00000001
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE = 0x00000000
NVC6C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE = 0x00000001
NVC6C0_LOAD_INLINE_DATA = 0x01b4
NVC6C0_SET_I2M_SEMAPHORE_A = 0x01dc
NVC6C0_SET_I2M_SEMAPHORE_B = 0x01e0
NVC6C0_SET_I2M_SEMAPHORE_C = 0x01e4
NVC6C0_SET_SM_SCG_CONTROL = 0x01e8
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE = 0x00000000
NVC6C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE = 0x00000001
NVC6C0_SET_I2M_SPARE_NOOP00 = 0x01f0
NVC6C0_SET_I2M_SPARE_NOOP01 = 0x01f4
NVC6C0_SET_I2M_SPARE_NOOP02 = 0x01f8
NVC6C0_SET_I2M_SPARE_NOOP03 = 0x01fc
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_A = 0x0200
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_B = 0x0204
NVC6C0_SET_VALID_SPAN_OVERFLOW_AREA_C = 0x0208
NVC6C0_PERFMON_TRANSFER = 0x0210
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_A = 0x0214
NVC6C0_SET_QMD_VIRTUALIZATION_BASE_B = 0x0218
NVC6C0_INVALIDATE_SHADER_CACHES = 0x021c
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_DATA_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE = 0x00000001
NVC6C0_SET_RESERVED_SW_METHOD00 = 0x0220
NVC6C0_SET_RESERVED_SW_METHOD01 = 0x0224
NVC6C0_SET_RESERVED_SW_METHOD02 = 0x0228
NVC6C0_SET_RESERVED_SW_METHOD03 = 0x022c
NVC6C0_SET_RESERVED_SW_METHOD04 = 0x0230
NVC6C0_SET_RESERVED_SW_METHOD05 = 0x0234
NVC6C0_SET_RESERVED_SW_METHOD06 = 0x0238
NVC6C0_SET_RESERVED_SW_METHOD07 = 0x023c
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI = 0x0244
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE = 0x00000001
NVC6C0_SET_CWD_REF_COUNTER = 0x0248
NVC6C0_SET_RESERVED_SW_METHOD08 = 0x024c
NVC6C0_SET_RESERVED_SW_METHOD09 = 0x0250
NVC6C0_SET_RESERVED_SW_METHOD10 = 0x0254
NVC6C0_SET_RESERVED_SW_METHOD11 = 0x0258
NVC6C0_SET_RESERVED_SW_METHOD12 = 0x025c
NVC6C0_SET_RESERVED_SW_METHOD13 = 0x0260
NVC6C0_SET_RESERVED_SW_METHOD14 = 0x0264
NVC6C0_SET_RESERVED_SW_METHOD15 = 0x0268
NVC6C0_SET_SCG_CONTROL = 0x0270
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = 0x00000000
NVC6C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = 0x00000001
NVC6C0_SET_COMPUTE_CLASS_VERSION = 0x0280
NVC6C0_CHECK_COMPUTE_CLASS_VERSION = 0x0284
NVC6C0_SET_QMD_VERSION = 0x0288
NVC6C0_CHECK_QMD_VERSION = 0x0290
NVC6C0_INVALIDATE_SKED_CACHES = 0x0298
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL = 0x029c
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE = 0x00000000
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE = 0x00000001
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE = 0x00000000
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE = 0x00000001
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE = 0x00000000
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE = 0x00000001
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE = 0x00000000
NVC6C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE = 0x00000001
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_A = 0x02a0
NVC6C0_SET_SHADER_SHARED_MEMORY_WINDOW_B = 0x02a4
NVC6C0_SCG_HYSTERESIS_CONTROL = 0x02a8
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE = 0x00000000
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE = 0x00000001
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE = 0x00000000
NVC6C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE = 0x00000001
NVC6C0_SET_CWD_SLOT_COUNT = 0x02b0
NVC6C0_SEND_PCAS_A = 0x02b4
NVC6C0_SEND_PCAS_B = 0x02b8
NVC6C0_SEND_SIGNALING_PCAS_B = 0x02bc
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE = 0x00000000
NVC6C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE = 0x00000001
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE = 0x00000000
NVC6C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE = 0x00000001
NVC6C0_SEND_SIGNALING_PCAS2_B = 0x02c0
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_NOP = 0x00000000
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE = 0x00000001
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_SCHEDULE = 0x00000002
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_COPY_SCHEDULE = 0x00000003
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INCREMENT_PUT = 0x00000006
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_DECREMENT_DEPENDENCE = 0x00000007
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH = 0x00000008
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_PREFETCH_SCHEDULE = 0x00000009
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_SCHEDULE = 0x0000000A
NVC6C0_SEND_SIGNALING_PCAS2_B_PCAS_ACTION_INVALIDATE_PREFETCH_COPY_FORCE_REQUIRE_SCHEDULING = 0x0000000B
NVC6C0_SET_SKED_CACHE_CONTROL = 0x02cc
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE = 0x00000000
NVC6C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE = 0x00000001
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A = 0x02e4
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B = 0x02e8
NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C = 0x02ec
NVC6C0_SET_SPA_VERSION = 0x0310
NVC6C0_SET_INLINE_QMD_ADDRESS_A = 0x0318
NVC6C0_SET_INLINE_QMD_ADDRESS_B = 0x031c
NVC6C0_LOAD_INLINE_QMD_DATA = lambda i: (0x0320+(i)*4)
NVC6C0_SET_FALCON00 = 0x0500
NVC6C0_SET_FALCON01 = 0x0504
NVC6C0_SET_FALCON02 = 0x0508
NVC6C0_SET_FALCON03 = 0x050c
NVC6C0_SET_FALCON04 = 0x0510
NVC6C0_SET_FALCON05 = 0x0514
NVC6C0_SET_FALCON06 = 0x0518
NVC6C0_SET_FALCON07 = 0x051c
NVC6C0_SET_FALCON08 = 0x0520
NVC6C0_SET_FALCON09 = 0x0524
NVC6C0_SET_FALCON10 = 0x0528
NVC6C0_SET_FALCON11 = 0x052c
NVC6C0_SET_FALCON12 = 0x0530
NVC6C0_SET_FALCON13 = 0x0534
NVC6C0_SET_FALCON14 = 0x0538
NVC6C0_SET_FALCON15 = 0x053c
NVC6C0_SET_SHADER_LOCAL_MEMORY_A = 0x0790
NVC6C0_SET_SHADER_LOCAL_MEMORY_B = 0x0794
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A = 0x07b0
NVC6C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B = 0x07b4
NVC6C0_SET_SHADER_CACHE_CONTROL = 0x0d94
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE = 0x00000000
NVC6C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE = 0x00000001
NVC6C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS = lambda i: (0x0da0+(i)*4)
NVC6C0_SET_SM_TIMEOUT_INTERVAL = 0x0de4
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI = 0x1288
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE = 0x00000001
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT = 0x12a8
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE = 0x00000000
NVC6C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE = 0x00000001
NVC6C0_INVALIDATE_SAMPLER_CACHE = 0x1330
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE = 0x00000001
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE = 0x1334
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE = 0x00000001
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE = 0x1338
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE = 0x00000001
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI = 0x1424
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL = 0x00000000
NVC6C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE = 0x00000001
NVC6C0_SET_SHADER_EXCEPTIONS = 0x1528
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE = 0x00000000
NVC6C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE = 0x00000001
NVC6C0_SET_RENDER_ENABLE_A = 0x1550
NVC6C0_SET_RENDER_ENABLE_B = 0x1554
NVC6C0_SET_RENDER_ENABLE_C = 0x1558
NVC6C0_SET_RENDER_ENABLE_C_MODE_FALSE = 0x00000000
NVC6C0_SET_RENDER_ENABLE_C_MODE_TRUE = 0x00000001
NVC6C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = 0x00000002
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = 0x00000003
NVC6C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = 0x00000004
NVC6C0_SET_TEX_SAMPLER_POOL_A = 0x155c
NVC6C0_SET_TEX_SAMPLER_POOL_B = 0x1560
NVC6C0_SET_TEX_SAMPLER_POOL_C = 0x1564
NVC6C0_SET_TEX_HEADER_POOL_A = 0x1574
NVC6C0_SET_TEX_HEADER_POOL_B = 0x1578
NVC6C0_SET_TEX_HEADER_POOL_C = 0x157c
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI = 0x1698
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE = 0x00000001
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE = 0x00000000
NVC6C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE = 0x00000001
NVC6C0_SET_RENDER_ENABLE_OVERRIDE = 0x1944
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE = 0x00000000
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER = 0x00000001
NVC6C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER = 0x00000002
NVC6C0_PIPE_NOP = 0x1a2c
NVC6C0_SET_SPARE00 = 0x1a30
NVC6C0_SET_SPARE01 = 0x1a34
NVC6C0_SET_SPARE02 = 0x1a38
NVC6C0_SET_SPARE03 = 0x1a3c
NVC6C0_SET_REPORT_SEMAPHORE_A = 0x1b00
NVC6C0_SET_REPORT_SEMAPHORE_B = 0x1b04
NVC6C0_SET_REPORT_SEMAPHORE_C = 0x1b08
NVC6C0_SET_REPORT_SEMAPHORE_D = 0x1b0c
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP = 0x00000003
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX = 0x00000002
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC = 0x00000003
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC = 0x00000004
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND = 0x00000005
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR = 0x00000006
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR = 0x00000007
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 = 0x00000001
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE = 0x00000000
NVC6C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE = 0x00000001
NVC6C0_SET_TRAP_HANDLER_A = 0x25f8
NVC6C0_SET_TRAP_HANDLER_B = 0x25fc
NVC6C0_SET_BINDLESS_TEXTURE = 0x2608
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE = lambda i: (0x32f4+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER = lambda i: (0x3314+(i)*4)
NVC6C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3334
NVC6C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER = 0x3338
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER = lambda i: (0x333c+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE = lambda i: (0x335c+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT = lambda i: (0x337c+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A = lambda i: (0x339c+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B = lambda i: (0x33bc+(i)*4)
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL = 0x33dc
NVC6C0_START_SHADER_PERFORMANCE_COUNTER = 0x33e0
NVC6C0_STOP_SHADER_PERFORMANCE_COUNTER = 0x33e4
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER = 0x33e8
NVC6C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER = 0x33ec
NVC6C0_SET_MME_SHADOW_SCRATCH = lambda i: (0x3400+(i)*4)
BLACKWELL_COMPUTE_A = 0xCDC0
AMPERE_DMA_COPY_A = (0x0000C6B5)
NVC6B5_NOP = (0x00000100)
NVC6B5_PM_TRIGGER = (0x00000140)
NVC6B5_SET_SEMAPHORE_A = (0x00000240)
NVC6B5_SET_SEMAPHORE_B = (0x00000244)
NVC6B5_SET_SEMAPHORE_PAYLOAD = (0x00000248)
NVC6B5_SET_RENDER_ENABLE_A = (0x00000254)
NVC6B5_SET_RENDER_ENABLE_B = (0x00000258)
NVC6B5_SET_RENDER_ENABLE_C = (0x0000025C)
NVC6B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000)
NVC6B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001)
NVC6B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002)
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003)
NVC6B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004)
NVC6B5_SET_SRC_PHYS_MODE = (0x00000260)
NVC6B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
NVC6B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC6B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC6B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
NVC6B5_SET_DST_PHYS_MODE = (0x00000264)
NVC6B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
NVC6B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC6B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC6B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
NVC6B5_LAUNCH_DMA = (0x00000300)
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000)
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001)
NVC6B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002)
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001)
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000)
NVC6B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001)
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000)
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001)
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002)
NVC6B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003)
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000)
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001)
NVC6B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002)
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
NVC6B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001)
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
NVC6B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001)
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001)
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001)
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE = (0x00000001)
NVC6B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000)
NVC6B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001)
NVC6B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000)
NVC6B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001)
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000)
NVC6B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001)
NVC6B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000)
NVC6B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001)
NVC6B5_OFFSET_IN_UPPER = (0x00000400)
NVC6B5_OFFSET_IN_LOWER = (0x00000404)
NVC6B5_OFFSET_OUT_UPPER = (0x00000408)
NVC6B5_OFFSET_OUT_LOWER = (0x0000040C)
NVC6B5_PITCH_IN = (0x00000410)
NVC6B5_PITCH_OUT = (0x00000414)
NVC6B5_LINE_LENGTH_IN = (0x00000418)
NVC6B5_LINE_COUNT = (0x0000041C)
NVC6B5_SET_REMAP_CONST_A = (0x00000700)
NVC6B5_SET_REMAP_CONST_B = (0x00000704)
NVC6B5_SET_REMAP_COMPONENTS = (0x00000708)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005)
NVC6B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005)
NVC6B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005)
NVC6B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005)
NVC6B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006)
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003)
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000)
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001)
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002)
NVC6B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003)
NVC6B5_SET_DST_BLOCK_SIZE = (0x0000070C)
NVC6B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
NVC6B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
NVC6B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
NVC6B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
NVC6B5_SET_DST_WIDTH = (0x00000710)
NVC6B5_SET_DST_HEIGHT = (0x00000714)
NVC6B5_SET_DST_DEPTH = (0x00000718)
NVC6B5_SET_DST_LAYER = (0x0000071C)
NVC6B5_SET_DST_ORIGIN = (0x00000720)
NVC6B5_SET_SRC_BLOCK_SIZE = (0x00000728)
NVC6B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
NVC6B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
NVC6B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
NVC6B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
NVC6B5_SET_SRC_WIDTH = (0x0000072C)
NVC6B5_SET_SRC_HEIGHT = (0x00000730)
NVC6B5_SET_SRC_DEPTH = (0x00000734)
NVC6B5_SET_SRC_LAYER = (0x00000738)
NVC6B5_SET_SRC_ORIGIN = (0x0000073C)
NVC6B5_SRC_ORIGIN_X = (0x00000744)
NVC6B5_SRC_ORIGIN_Y = (0x00000748)
NVC6B5_DST_ORIGIN_X = (0x0000074C)
NVC6B5_DST_ORIGIN_Y = (0x00000750)
NVC6B5_PM_TRIGGER_END = (0x00001114)
BLACKWELL_DMA_COPY_A = (0x0000C9B5)
NVC9B5_NOP = (0x00000100)
NVC9B5_PM_TRIGGER = (0x00000140)
NVC9B5_SET_MONITORED_FENCE_TYPE = (0x0000021C)
NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE = (0x00000000)
NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT = (0x00000001)
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER = (0x00000220)
NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER = (0x00000224)
NVC9B5_SET_SEMAPHORE_A = (0x00000240)
NVC9B5_SET_SEMAPHORE_B = (0x00000244)
NVC9B5_SET_SEMAPHORE_PAYLOAD = (0x00000248)
NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER = (0x0000024C)
NVC9B5_SET_RENDER_ENABLE_A = (0x00000254)
NVC9B5_SET_RENDER_ENABLE_B = (0x00000258)
NVC9B5_SET_RENDER_ENABLE_C = (0x0000025C)
NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE = (0x00000000)
NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE = (0x00000001)
NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL = (0x00000002)
NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL = (0x00000003)
NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL = (0x00000004)
NVC9B5_SET_SRC_PHYS_MODE = (0x00000260)
NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
NVC9B5_SET_DST_PHYS_MODE = (0x00000264)
NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB = (0x00000000)
NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM = (0x00000003)
NVC9B5_LAUNCH_DMA = (0x00000300)
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE = (0x00000000)
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED = (0x00000001)
NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED = (0x00000002)
NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS = (0x00000000)
NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE = (0x00000000)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP = (0x00000002)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE = (0x00000002)
NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE = (0x00000003)
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE = (0x00000000)
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING = (0x00000001)
NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING = (0x00000002)
NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH = (0x00000001)
NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR = (0x00000000)
NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH = (0x00000001)
NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL = (0x00000000)
NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL = (0x00000001)
NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL = (0x00000000)
NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN = (0x00000000)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR = (0x00000002)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND = (0x00000003)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR = (0x00000004)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD = (0x00000005)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC = (0x00000006)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC = (0x00000007)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA = (0x00000008)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB = (0x00000009)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD = (0x0000000A)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN = (0x0000000B)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX = (0x0000000C)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC = (0x0000000D)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD = (0x0000000E)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE = (0x0000000F)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED = (0x00000000)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT = (0x00000000)
NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT = (0x00000000)
NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE = (0x00000001)
NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT = (0x00000002)
NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED = (0x00000003)
NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE = (0x00000000)
NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID = (0x00000001)
NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE = (0x00000000)
NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE = (0x00000001)
NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD = (0x00000000)
NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD = (0x00000001)
NVC9B5_OFFSET_IN_UPPER = (0x00000400)
NVC9B5_OFFSET_IN_LOWER = (0x00000404)
NVC9B5_OFFSET_OUT_UPPER = (0x00000408)
NVC9B5_OFFSET_OUT_LOWER = (0x0000040C)
NVC9B5_PITCH_IN = (0x00000410)
NVC9B5_PITCH_OUT = (0x00000414)
NVC9B5_LINE_LENGTH_IN = (0x00000418)
NVC9B5_LINE_COUNT = (0x0000041C)
NVC9B5_SET_SECURE_COPY_MODE = (0x00000500)
NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT = (0x00000000)
NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT = (0x00000001)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB = (0x00000000)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM = (0x00000003)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB = (0x00000000)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM = (0x00000001)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM = (0x00000002)
NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM = (0x00000003)
NVC9B5_SET_DECRYPT_IV0 = (0x00000504)
NVC9B5_SET_DECRYPT_IV1 = (0x00000508)
NVC9B5_SET_DECRYPT_IV2 = (0x0000050C)
NVC9B5_RESERVED_SET_AESCOUNTER = (0x00000510)
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER = (0x00000514)
NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER = (0x00000518)
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER = (0x00000530)
NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER = (0x00000534)
NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER = (0x00000538)
NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER = (0x0000053C)
NVC9B5_SET_COMPRESSION_PARAMETERS = (0x00000580)
NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS = (0x00000000)
NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS = (0x00000001)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY = (0x00000000)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY = (0x00000001)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK = (0x00000002)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM = (0x00000003)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE = (0x00000004)
NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH = (0x00000005)
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE = (0x00000000)
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32 = (0x00000001)
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32 = (0x00000002)
NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC = (0x00000003)
NVC9B5_SET_DECOMPRESS_OUT_LENGTH = (0x00000584)
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER = (0x00000588)
NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER = (0x0000058C)
NVC9B5_SET_DECOMPRESS_CHECKSUM = (0x00000590)
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS = (0x000006FC)
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE = (0x00000000)
NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE = (0x00000001)
NVC9B5_SET_REMAP_CONST_A = (0x00000700)
NVC9B5_SET_REMAP_CONST_B = (0x00000704)
NVC9B5_SET_REMAP_COMPONENTS = (0x00000708)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A = (0x00000004)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B = (0x00000005)
NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE = (0x00000006)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A = (0x00000004)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B = (0x00000005)
NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE = (0x00000006)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A = (0x00000004)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B = (0x00000005)
NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE = (0x00000006)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A = (0x00000004)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B = (0x00000005)
NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE = (0x00000006)
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR = (0x00000003)
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE = (0x00000000)
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO = (0x00000001)
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE = (0x00000002)
NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR = (0x00000003)
NVC9B5_SET_DST_BLOCK_SIZE = (0x0000070C)
NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
NVC9B5_SET_DST_WIDTH = (0x00000710)
NVC9B5_SET_DST_HEIGHT = (0x00000714)
NVC9B5_SET_DST_DEPTH = (0x00000718)
NVC9B5_SET_DST_LAYER = (0x0000071C)
NVC9B5_SET_DST_ORIGIN = (0x00000720)
NVC9B5_SET_SRC_BLOCK_SIZE = (0x00000728)
NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB = (0x00000000)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB = (0x00000000)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS = (0x00000001)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS = (0x00000002)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS = (0x00000003)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS = (0x00000004)
NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS = (0x00000005)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB = (0x00000000)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS = (0x00000001)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS = (0x00000002)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS = (0x00000003)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS = (0x00000004)
NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS = (0x00000005)
NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 = (0x00000001)
NVC9B5_SET_SRC_WIDTH = (0x0000072C)
NVC9B5_SET_SRC_HEIGHT = (0x00000730)
NVC9B5_SET_SRC_DEPTH = (0x00000734)
NVC9B5_SET_SRC_LAYER = (0x00000738)
NVC9B5_SET_SRC_ORIGIN = (0x0000073C)
NVC9B5_SRC_ORIGIN_X = (0x00000744)
NVC9B5_SRC_ORIGIN_Y = (0x00000748)
NVC9B5_DST_ORIGIN_X = (0x0000074C)
NVC9B5_DST_ORIGIN_Y = (0x00000750)
NVC9B5_PM_TRIGGER_END = (0x00001114)
UVM_IOCTL_BASE = lambda i: i
UVM_RESERVE_VA = UVM_IOCTL_BASE(1)
UVM_RELEASE_VA = UVM_IOCTL_BASE(2)
UVM_REGION_COMMIT = UVM_IOCTL_BASE(3)
UVM_REGION_DECOMMIT = UVM_IOCTL_BASE(4)
UVM_REGION_SET_STREAM = UVM_IOCTL_BASE(5)
UVM_SET_STREAM_RUNNING = UVM_IOCTL_BASE(6)
UVM_MAX_STREAMS_PER_IOCTL_CALL = 32
UVM_SET_STREAM_STOPPED = UVM_IOCTL_BASE(7)
UVM_RUN_TEST = UVM_IOCTL_BASE(9)
UVM_EVENTS_OFFSET_BASE = (1 << 63)
UVM_COUNTERS_OFFSET_BASE = (1 << 62)
UVM_ADD_SESSION = UVM_IOCTL_BASE(10)
UVM_REMOVE_SESSION = UVM_IOCTL_BASE(11)
UVM_MAX_COUNTERS_PER_IOCTL_CALL = 32
UVM_ENABLE_COUNTERS = UVM_IOCTL_BASE(12)
UVM_MAP_COUNTER = UVM_IOCTL_BASE(13)
UVM_CREATE_EVENT_QUEUE = UVM_IOCTL_BASE(14)
UVM_REMOVE_EVENT_QUEUE = UVM_IOCTL_BASE(15)
UVM_MAP_EVENT_QUEUE = UVM_IOCTL_BASE(16)
UVM_EVENT_CTRL = UVM_IOCTL_BASE(17)
UVM_REGISTER_MPS_SERVER = UVM_IOCTL_BASE(18)
UVM_REGISTER_MPS_CLIENT = UVM_IOCTL_BASE(19)
UVM_GET_GPU_UUID_TABLE = UVM_IOCTL_BASE(20)
UVM_CREATE_RANGE_GROUP = UVM_IOCTL_BASE(23)
UVM_DESTROY_RANGE_GROUP = UVM_IOCTL_BASE(24)
UVM_REGISTER_GPU_VASPACE = UVM_IOCTL_BASE(25)
UVM_UNREGISTER_GPU_VASPACE = UVM_IOCTL_BASE(26)
UVM_REGISTER_CHANNEL = UVM_IOCTL_BASE(27)
UVM_UNREGISTER_CHANNEL = UVM_IOCTL_BASE(28)
UVM_ENABLE_PEER_ACCESS = UVM_IOCTL_BASE(29)
UVM_DISABLE_PEER_ACCESS = UVM_IOCTL_BASE(30)
UVM_SET_RANGE_GROUP = UVM_IOCTL_BASE(31)
UVM_MAP_EXTERNAL_ALLOCATION = UVM_IOCTL_BASE(33)
UVM_FREE = UVM_IOCTL_BASE(34)
UVM_MEM_MAP = UVM_IOCTL_BASE(35)
UVM_DEBUG_ACCESS_MEMORY = UVM_IOCTL_BASE(36)
UVM_REGISTER_GPU = UVM_IOCTL_BASE(37)
UVM_UNREGISTER_GPU = UVM_IOCTL_BASE(38)
UVM_PAGEABLE_MEM_ACCESS = UVM_IOCTL_BASE(39)
UVM_MAX_RANGE_GROUPS_PER_IOCTL_CALL = 32
UVM_PREVENT_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(40)
UVM_ALLOW_MIGRATION_RANGE_GROUPS = UVM_IOCTL_BASE(41)
UVM_SET_PREFERRED_LOCATION = UVM_IOCTL_BASE(42)
UVM_UNSET_PREFERRED_LOCATION = UVM_IOCTL_BASE(43)
UVM_ENABLE_READ_DUPLICATION = UVM_IOCTL_BASE(44)
UVM_DISABLE_READ_DUPLICATION = UVM_IOCTL_BASE(45)
UVM_SET_ACCESSED_BY = UVM_IOCTL_BASE(46)
UVM_UNSET_ACCESSED_BY = UVM_IOCTL_BASE(47)
UVM_MIGRATE_FLAG_ASYNC = 0x00000001
UVM_MIGRATE_FLAG_SKIP_CPU_MAP = 0x00000002
UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE = 0x00000004
UVM_MIGRATE_FLAGS_TEST_ALL = (UVM_MIGRATE_FLAG_SKIP_CPU_MAP      | UVM_MIGRATE_FLAG_NO_GPU_VA_SPACE)
UVM_MIGRATE_FLAGS_ALL = (UVM_MIGRATE_FLAG_ASYNC | UVM_MIGRATE_FLAGS_TEST_ALL)
UVM_MIGRATE = UVM_IOCTL_BASE(51)
UVM_MIGRATE_RANGE_GROUP = UVM_IOCTL_BASE(53)
UVM_ENABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(54)
UVM_DISABLE_SYSTEM_WIDE_ATOMICS = UVM_IOCTL_BASE(55)
UVM_TOOLS_INIT_EVENT_TRACKER = UVM_IOCTL_BASE(56)
UVM_TOOLS_SET_NOTIFICATION_THRESHOLD = UVM_IOCTL_BASE(57)
UVM_TOOLS_EVENT_QUEUE_ENABLE_EVENTS = UVM_IOCTL_BASE(58)
UVM_TOOLS_EVENT_QUEUE_DISABLE_EVENTS = UVM_IOCTL_BASE(59)
UVM_TOOLS_ENABLE_COUNTERS = UVM_IOCTL_BASE(60)
UVM_TOOLS_DISABLE_COUNTERS = UVM_IOCTL_BASE(61)
UVM_TOOLS_READ_PROCESS_MEMORY = UVM_IOCTL_BASE(62)
UVM_TOOLS_WRITE_PROCESS_MEMORY = UVM_IOCTL_BASE(63)
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE = UVM_IOCTL_BASE(64)
UVM_MAP_DYNAMIC_PARALLELISM_REGION = UVM_IOCTL_BASE(65)
UVM_UNMAP_EXTERNAL = UVM_IOCTL_BASE(66)
UVM_TOOLS_FLUSH_EVENTS = UVM_IOCTL_BASE(67)
UVM_ALLOC_SEMAPHORE_POOL = UVM_IOCTL_BASE(68)
UVM_CLEAN_UP_ZOMBIE_RESOURCES = UVM_IOCTL_BASE(69)
UVM_PAGEABLE_MEM_ACCESS_ON_GPU = UVM_IOCTL_BASE(70)
UVM_POPULATE_PAGEABLE = UVM_IOCTL_BASE(71)
UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED = 0x00000001
UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK = 0x00000002
UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL = (UVM_POPULATE_PAGEABLE_FLAG_ALLOW_MANAGED | UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK)
UVM_POPULATE_PAGEABLE_FLAGS_ALL = UVM_POPULATE_PAGEABLE_FLAGS_TEST_ALL
UVM_VALIDATE_VA_RANGE = UVM_IOCTL_BASE(72)
UVM_CREATE_EXTERNAL_RANGE = UVM_IOCTL_BASE(73)
UVM_MAP_EXTERNAL_SPARSE = UVM_IOCTL_BASE(74)
UVM_MM_INITIALIZE = UVM_IOCTL_BASE(75)
UVM_TOOLS_INIT_EVENT_TRACKER_V2 = UVM_IOCTL_BASE(76)
UVM_TOOLS_GET_PROCESSOR_UUID_TABLE_V2 = UVM_IOCTL_BASE(77)
UVM_ALLOC_DEVICE_P2P = UVM_IOCTL_BASE(78)
UVM_CLEAR_ALL_ACCESS_COUNTERS = UVM_IOCTL_BASE(79)
UVM_IS_8_SUPPORTED = UVM_IOCTL_BASE(2047)
UVM_INITIALIZE = 0x30000001
UVM_DEINITIALIZE = 0x30000002
NV_PFAULT_MMU_ENG_ID_GRAPHICS = 64
NV_PFAULT_MMU_ENG_ID_DISPLAY = 1
NV_PFAULT_MMU_ENG_ID_GSP = 2
NV_PFAULT_MMU_ENG_ID_IFB = 9
NV_PFAULT_MMU_ENG_ID_FLA = 4
NV_PFAULT_MMU_ENG_ID_BAR1 = 128
NV_PFAULT_MMU_ENG_ID_BAR2 = 192
NV_PFAULT_MMU_ENG_ID_SEC = 14
NV_PFAULT_MMU_ENG_ID_PERF = 8
NV_PFAULT_MMU_ENG_ID_NVDEC = 25
NV_PFAULT_MMU_ENG_ID_NVDEC0 = 25
NV_PFAULT_MMU_ENG_ID_NVDEC1 = 26
NV_PFAULT_MMU_ENG_ID_NVDEC2 = 27
NV_PFAULT_MMU_ENG_ID_NVDEC3 = 28
NV_PFAULT_MMU_ENG_ID_NVDEC4 = 29
NV_PFAULT_MMU_ENG_ID_NVJPG0 = 30
NV_PFAULT_MMU_ENG_ID_GRCOPY = 15
NV_PFAULT_MMU_ENG_ID_CE0 = 15
NV_PFAULT_MMU_ENG_ID_CE1 = 16
NV_PFAULT_MMU_ENG_ID_CE2 = 17
NV_PFAULT_MMU_ENG_ID_CE3 = 18
NV_PFAULT_MMU_ENG_ID_CE4 = 19
NV_PFAULT_MMU_ENG_ID_CE5 = 20
NV_PFAULT_MMU_ENG_ID_CE6 = 21
NV_PFAULT_MMU_ENG_ID_CE7 = 22
NV_PFAULT_MMU_ENG_ID_CE8 = 23
NV_PFAULT_MMU_ENG_ID_CE9 = 24
NV_PFAULT_MMU_ENG_ID_PWR_PMU = 6
NV_PFAULT_MMU_ENG_ID_PTP = 3
NV_PFAULT_MMU_ENG_ID_NVENC0 = 11
NV_PFAULT_MMU_ENG_ID_NVENC1 = 12
NV_PFAULT_MMU_ENG_ID_NVENC2 = 13
NV_PFAULT_MMU_ENG_ID_OFA0 = 10
NV_PFAULT_MMU_ENG_ID_PHYSICAL = 31
NV_PFAULT_MMU_ENG_ID_HOST0 = 32
NV_PFAULT_MMU_ENG_ID_HOST1 = 33
NV_PFAULT_MMU_ENG_ID_HOST2 = 34
NV_PFAULT_MMU_ENG_ID_HOST3 = 35
NV_PFAULT_MMU_ENG_ID_HOST4 = 36
NV_PFAULT_MMU_ENG_ID_HOST5 = 37
NV_PFAULT_MMU_ENG_ID_HOST6 = 38
NV_PFAULT_MMU_ENG_ID_HOST7 = 39
NV_PFAULT_MMU_ENG_ID_HOST8 = 40
NV_PFAULT_MMU_ENG_ID_HOST9 = 41
NV_PFAULT_MMU_ENG_ID_HOST10 = 42
NV_PFAULT_MMU_ENG_ID_HOST11 = 43
NV_PFAULT_MMU_ENG_ID_HOST12 = 44
NV_PFAULT_MMU_ENG_ID_HOST13 = 45
NV_PFAULT_MMU_ENG_ID_HOST14 = 46
NV_PFAULT_MMU_ENG_ID_HOST15 = 47
NV_PFAULT_MMU_ENG_ID_HOST16 = 48
NV_PFAULT_MMU_ENG_ID_HOST17 = 49
NV_PFAULT_MMU_ENG_ID_HOST18 = 50
NV_PFAULT_MMU_ENG_ID_HOST19 = 51
NV_PFAULT_MMU_ENG_ID_HOST20 = 52
NV_PFAULT_MMU_ENG_ID_HOST21 = 53
NV_PFAULT_MMU_ENG_ID_HOST22 = 54
NV_PFAULT_MMU_ENG_ID_HOST23 = 55
NV_PFAULT_MMU_ENG_ID_HOST24 = 56
NV_PFAULT_MMU_ENG_ID_HOST25 = 57
NV_PFAULT_MMU_ENG_ID_HOST26 = 58
NV_PFAULT_MMU_ENG_ID_HOST27 = 59
NV_PFAULT_MMU_ENG_ID_HOST28 = 60
NV_PFAULT_MMU_ENG_ID_HOST29 = 61
NV_PFAULT_MMU_ENG_ID_HOST30 = 62
NV_PFAULT_MMU_ENG_ID_HOST31 = 63
NV_PFAULT_MMU_ENG_ID_BAR1_FN0 = 128
NV_PFAULT_MMU_ENG_ID_BAR1_FN1 = 129
NV_PFAULT_MMU_ENG_ID_BAR1_FN2 = 130
NV_PFAULT_MMU_ENG_ID_BAR1_FN3 = 131
NV_PFAULT_MMU_ENG_ID_BAR1_FN4 = 132
NV_PFAULT_MMU_ENG_ID_BAR1_FN5 = 133
NV_PFAULT_MMU_ENG_ID_BAR1_FN6 = 134
NV_PFAULT_MMU_ENG_ID_BAR1_FN7 = 135
NV_PFAULT_MMU_ENG_ID_BAR1_FN8 = 136
NV_PFAULT_MMU_ENG_ID_BAR1_FN9 = 137
NV_PFAULT_MMU_ENG_ID_BAR1_FN10 = 138
NV_PFAULT_MMU_ENG_ID_BAR1_FN11 = 139
NV_PFAULT_MMU_ENG_ID_BAR1_FN12 = 140
NV_PFAULT_MMU_ENG_ID_BAR1_FN13 = 141
NV_PFAULT_MMU_ENG_ID_BAR1_FN14 = 142
NV_PFAULT_MMU_ENG_ID_BAR1_FN15 = 143
NV_PFAULT_MMU_ENG_ID_BAR1_FN16 = 144
NV_PFAULT_MMU_ENG_ID_BAR1_FN17 = 145
NV_PFAULT_MMU_ENG_ID_BAR1_FN18 = 146
NV_PFAULT_MMU_ENG_ID_BAR1_FN19 = 147
NV_PFAULT_MMU_ENG_ID_BAR1_FN20 = 148
NV_PFAULT_MMU_ENG_ID_BAR1_FN21 = 149
NV_PFAULT_MMU_ENG_ID_BAR1_FN22 = 150
NV_PFAULT_MMU_ENG_ID_BAR1_FN23 = 151
NV_PFAULT_MMU_ENG_ID_BAR1_FN24 = 152
NV_PFAULT_MMU_ENG_ID_BAR1_FN25 = 153
NV_PFAULT_MMU_ENG_ID_BAR1_FN26 = 154
NV_PFAULT_MMU_ENG_ID_BAR1_FN27 = 155
NV_PFAULT_MMU_ENG_ID_BAR1_FN28 = 156
NV_PFAULT_MMU_ENG_ID_BAR1_FN29 = 157
NV_PFAULT_MMU_ENG_ID_BAR1_FN30 = 158
NV_PFAULT_MMU_ENG_ID_BAR1_FN31 = 159
NV_PFAULT_MMU_ENG_ID_BAR1_FN32 = 160
NV_PFAULT_MMU_ENG_ID_BAR1_FN33 = 161
NV_PFAULT_MMU_ENG_ID_BAR1_FN34 = 162
NV_PFAULT_MMU_ENG_ID_BAR1_FN35 = 163
NV_PFAULT_MMU_ENG_ID_BAR1_FN36 = 164
NV_PFAULT_MMU_ENG_ID_BAR1_FN37 = 165
NV_PFAULT_MMU_ENG_ID_BAR1_FN38 = 166
NV_PFAULT_MMU_ENG_ID_BAR1_FN39 = 167
NV_PFAULT_MMU_ENG_ID_BAR1_FN40 = 168
NV_PFAULT_MMU_ENG_ID_BAR1_FN41 = 169
NV_PFAULT_MMU_ENG_ID_BAR1_FN42 = 170
NV_PFAULT_MMU_ENG_ID_BAR1_FN43 = 171
NV_PFAULT_MMU_ENG_ID_BAR1_FN44 = 172
NV_PFAULT_MMU_ENG_ID_BAR1_FN45 = 173
NV_PFAULT_MMU_ENG_ID_BAR1_FN46 = 174
NV_PFAULT_MMU_ENG_ID_BAR1_FN47 = 175
NV_PFAULT_MMU_ENG_ID_BAR1_FN48 = 176
NV_PFAULT_MMU_ENG_ID_BAR1_FN49 = 177
NV_PFAULT_MMU_ENG_ID_BAR1_FN50 = 178
NV_PFAULT_MMU_ENG_ID_BAR1_FN51 = 179
NV_PFAULT_MMU_ENG_ID_BAR1_FN52 = 180
NV_PFAULT_MMU_ENG_ID_BAR1_FN53 = 181
NV_PFAULT_MMU_ENG_ID_BAR1_FN54 = 182
NV_PFAULT_MMU_ENG_ID_BAR1_FN55 = 183
NV_PFAULT_MMU_ENG_ID_BAR1_FN56 = 184
NV_PFAULT_MMU_ENG_ID_BAR1_FN57 = 185
NV_PFAULT_MMU_ENG_ID_BAR1_FN58 = 186
NV_PFAULT_MMU_ENG_ID_BAR1_FN59 = 187
NV_PFAULT_MMU_ENG_ID_BAR1_FN60 = 188
NV_PFAULT_MMU_ENG_ID_BAR1_FN61 = 189
NV_PFAULT_MMU_ENG_ID_BAR1_FN62 = 190
NV_PFAULT_MMU_ENG_ID_BAR1_FN63 = 191
NV_PFAULT_MMU_ENG_ID_BAR2_FN0 = 192
NV_PFAULT_MMU_ENG_ID_BAR2_FN1 = 193
NV_PFAULT_MMU_ENG_ID_BAR2_FN2 = 194
NV_PFAULT_MMU_ENG_ID_BAR2_FN3 = 195
NV_PFAULT_MMU_ENG_ID_BAR2_FN4 = 196
NV_PFAULT_MMU_ENG_ID_BAR2_FN5 = 197
NV_PFAULT_MMU_ENG_ID_BAR2_FN6 = 198
NV_PFAULT_MMU_ENG_ID_BAR2_FN7 = 199
NV_PFAULT_MMU_ENG_ID_BAR2_FN8 = 200
NV_PFAULT_MMU_ENG_ID_BAR2_FN9 = 201
NV_PFAULT_MMU_ENG_ID_BAR2_FN10 = 202
NV_PFAULT_MMU_ENG_ID_BAR2_FN11 = 203
NV_PFAULT_MMU_ENG_ID_BAR2_FN12 = 204
NV_PFAULT_MMU_ENG_ID_BAR2_FN13 = 205
NV_PFAULT_MMU_ENG_ID_BAR2_FN14 = 206
NV_PFAULT_MMU_ENG_ID_BAR2_FN15 = 207
NV_PFAULT_MMU_ENG_ID_BAR2_FN16 = 208
NV_PFAULT_MMU_ENG_ID_BAR2_FN17 = 209
NV_PFAULT_MMU_ENG_ID_BAR2_FN18 = 210
NV_PFAULT_MMU_ENG_ID_BAR2_FN19 = 211
NV_PFAULT_MMU_ENG_ID_BAR2_FN20 = 212
NV_PFAULT_MMU_ENG_ID_BAR2_FN21 = 213
NV_PFAULT_MMU_ENG_ID_BAR2_FN22 = 214
NV_PFAULT_MMU_ENG_ID_BAR2_FN23 = 215
NV_PFAULT_MMU_ENG_ID_BAR2_FN24 = 216
NV_PFAULT_MMU_ENG_ID_BAR2_FN25 = 217
NV_PFAULT_MMU_ENG_ID_BAR2_FN26 = 218
NV_PFAULT_MMU_ENG_ID_BAR2_FN27 = 219
NV_PFAULT_MMU_ENG_ID_BAR2_FN28 = 220
NV_PFAULT_MMU_ENG_ID_BAR2_FN29 = 221
NV_PFAULT_MMU_ENG_ID_BAR2_FN30 = 222
NV_PFAULT_MMU_ENG_ID_BAR2_FN31 = 223
NV_PFAULT_MMU_ENG_ID_BAR2_FN32 = 224
NV_PFAULT_MMU_ENG_ID_BAR2_FN33 = 225
NV_PFAULT_MMU_ENG_ID_BAR2_FN34 = 226
NV_PFAULT_MMU_ENG_ID_BAR2_FN35 = 227
NV_PFAULT_MMU_ENG_ID_BAR2_FN36 = 228
NV_PFAULT_MMU_ENG_ID_BAR2_FN37 = 229
NV_PFAULT_MMU_ENG_ID_BAR2_FN38 = 230
NV_PFAULT_MMU_ENG_ID_BAR2_FN39 = 231
NV_PFAULT_MMU_ENG_ID_BAR2_FN40 = 232
NV_PFAULT_MMU_ENG_ID_BAR2_FN41 = 233
NV_PFAULT_MMU_ENG_ID_BAR2_FN42 = 234
NV_PFAULT_MMU_ENG_ID_BAR2_FN43 = 235
NV_PFAULT_MMU_ENG_ID_BAR2_FN44 = 236
NV_PFAULT_MMU_ENG_ID_BAR2_FN45 = 237
NV_PFAULT_MMU_ENG_ID_BAR2_FN46 = 238
NV_PFAULT_MMU_ENG_ID_BAR2_FN47 = 239
NV_PFAULT_MMU_ENG_ID_BAR2_FN48 = 240
NV_PFAULT_MMU_ENG_ID_BAR2_FN49 = 241
NV_PFAULT_MMU_ENG_ID_BAR2_FN50 = 242
NV_PFAULT_MMU_ENG_ID_BAR2_FN51 = 243
NV_PFAULT_MMU_ENG_ID_BAR2_FN52 = 244
NV_PFAULT_MMU_ENG_ID_BAR2_FN53 = 245
NV_PFAULT_MMU_ENG_ID_BAR2_FN54 = 246
NV_PFAULT_MMU_ENG_ID_BAR2_FN55 = 247
NV_PFAULT_MMU_ENG_ID_BAR2_FN56 = 248
NV_PFAULT_MMU_ENG_ID_BAR2_FN57 = 249
NV_PFAULT_MMU_ENG_ID_BAR2_FN58 = 250
NV_PFAULT_MMU_ENG_ID_BAR2_FN59 = 251
NV_PFAULT_MMU_ENG_ID_BAR2_FN60 = 252
NV_PFAULT_MMU_ENG_ID_BAR2_FN61 = 253
NV_PFAULT_MMU_ENG_ID_BAR2_FN62 = 254
NV_PFAULT_MMU_ENG_ID_BAR2_FN63 = 255
NV_PFAULT_FAULT_TYPE_PDE = 0x00000000
NV_PFAULT_FAULT_TYPE_PDE_SIZE = 0x00000001
NV_PFAULT_FAULT_TYPE_PTE = 0x00000002
NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION = 0x00000003
NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK = 0x00000004
NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION = 0x00000005
NV_PFAULT_FAULT_TYPE_RO_VIOLATION = 0x00000006
NV_PFAULT_FAULT_TYPE_WO_VIOLATION = 0x00000007
NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION = 0x00000008
NV_PFAULT_FAULT_TYPE_WORK_CREATION = 0x00000009
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE = 0x0000000a
NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE = 0x0000000b
NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND = 0x0000000c
NV_PFAULT_FAULT_TYPE_REGION_VIOLATION = 0x0000000d
NV_PFAULT_FAULT_TYPE_POISONED = 0x0000000e
NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION = 0x0000000f
NV_PFAULT_CLIENT_GPC_T1_0 = 0x00000000
NV_PFAULT_CLIENT_GPC_T1_1 = 0x00000001
NV_PFAULT_CLIENT_GPC_T1_2 = 0x00000002
NV_PFAULT_CLIENT_GPC_T1_3 = 0x00000003
NV_PFAULT_CLIENT_GPC_T1_4 = 0x00000004
NV_PFAULT_CLIENT_GPC_T1_5 = 0x00000005
NV_PFAULT_CLIENT_GPC_T1_6 = 0x00000006
NV_PFAULT_CLIENT_GPC_T1_7 = 0x00000007
NV_PFAULT_CLIENT_GPC_PE_0 = 0x00000008
NV_PFAULT_CLIENT_GPC_PE_1 = 0x00000009
NV_PFAULT_CLIENT_GPC_PE_2 = 0x0000000A
NV_PFAULT_CLIENT_GPC_PE_3 = 0x0000000B
NV_PFAULT_CLIENT_GPC_PE_4 = 0x0000000C
NV_PFAULT_CLIENT_GPC_PE_5 = 0x0000000D
NV_PFAULT_CLIENT_GPC_PE_6 = 0x0000000E
NV_PFAULT_CLIENT_GPC_PE_7 = 0x0000000F
NV_PFAULT_CLIENT_GPC_RAST = 0x00000010
NV_PFAULT_CLIENT_GPC_GCC = 0x00000011
NV_PFAULT_CLIENT_GPC_GPCCS = 0x00000012
NV_PFAULT_CLIENT_GPC_PROP_0 = 0x00000013
NV_PFAULT_CLIENT_GPC_PROP_1 = 0x00000014
NV_PFAULT_CLIENT_GPC_PROP_2 = 0x00000015
NV_PFAULT_CLIENT_GPC_PROP_3 = 0x00000016
NV_PFAULT_CLIENT_GPC_T1_8 = 0x00000021
NV_PFAULT_CLIENT_GPC_T1_9 = 0x00000022
NV_PFAULT_CLIENT_GPC_T1_10 = 0x00000023
NV_PFAULT_CLIENT_GPC_T1_11 = 0x00000024
NV_PFAULT_CLIENT_GPC_T1_12 = 0x00000025
NV_PFAULT_CLIENT_GPC_T1_13 = 0x00000026
NV_PFAULT_CLIENT_GPC_T1_14 = 0x00000027
NV_PFAULT_CLIENT_GPC_T1_15 = 0x00000028
NV_PFAULT_CLIENT_GPC_TPCCS_0 = 0x00000029
NV_PFAULT_CLIENT_GPC_TPCCS_1 = 0x0000002A
NV_PFAULT_CLIENT_GPC_TPCCS_2 = 0x0000002B
NV_PFAULT_CLIENT_GPC_TPCCS_3 = 0x0000002C
NV_PFAULT_CLIENT_GPC_TPCCS_4 = 0x0000002D
NV_PFAULT_CLIENT_GPC_TPCCS_5 = 0x0000002E
NV_PFAULT_CLIENT_GPC_TPCCS_6 = 0x0000002F
NV_PFAULT_CLIENT_GPC_TPCCS_7 = 0x00000030
NV_PFAULT_CLIENT_GPC_PE_8 = 0x00000031
NV_PFAULT_CLIENT_GPC_PE_9 = 0x00000032
NV_PFAULT_CLIENT_GPC_TPCCS_8 = 0x00000033
NV_PFAULT_CLIENT_GPC_TPCCS_9 = 0x00000034
NV_PFAULT_CLIENT_GPC_T1_16 = 0x00000035
NV_PFAULT_CLIENT_GPC_T1_17 = 0x00000036
NV_PFAULT_CLIENT_GPC_T1_18 = 0x00000037
NV_PFAULT_CLIENT_GPC_T1_19 = 0x00000038
NV_PFAULT_CLIENT_GPC_PE_10 = 0x00000039
NV_PFAULT_CLIENT_GPC_PE_11 = 0x0000003A
NV_PFAULT_CLIENT_GPC_TPCCS_10 = 0x0000003B
NV_PFAULT_CLIENT_GPC_TPCCS_11 = 0x0000003C
NV_PFAULT_CLIENT_GPC_T1_20 = 0x0000003D
NV_PFAULT_CLIENT_GPC_T1_21 = 0x0000003E
NV_PFAULT_CLIENT_GPC_T1_22 = 0x0000003F
NV_PFAULT_CLIENT_GPC_T1_23 = 0x00000040
NV_PFAULT_CLIENT_GPC_PE_12 = 0x00000041
NV_PFAULT_CLIENT_GPC_PE_13 = 0x00000042
NV_PFAULT_CLIENT_GPC_TPCCS_12 = 0x00000043
NV_PFAULT_CLIENT_GPC_TPCCS_13 = 0x00000044
NV_PFAULT_CLIENT_GPC_T1_24 = 0x00000045
NV_PFAULT_CLIENT_GPC_T1_25 = 0x00000046
NV_PFAULT_CLIENT_GPC_T1_26 = 0x00000047
NV_PFAULT_CLIENT_GPC_T1_27 = 0x00000048
NV_PFAULT_CLIENT_GPC_PE_14 = 0x00000049
NV_PFAULT_CLIENT_GPC_PE_15 = 0x0000004A
NV_PFAULT_CLIENT_GPC_TPCCS_14 = 0x0000004B
NV_PFAULT_CLIENT_GPC_TPCCS_15 = 0x0000004C
NV_PFAULT_CLIENT_GPC_T1_28 = 0x0000004D
NV_PFAULT_CLIENT_GPC_T1_29 = 0x0000004E
NV_PFAULT_CLIENT_GPC_T1_30 = 0x0000004F
NV_PFAULT_CLIENT_GPC_T1_31 = 0x00000050
NV_PFAULT_CLIENT_GPC_PE_16 = 0x00000051
NV_PFAULT_CLIENT_GPC_PE_17 = 0x00000052
NV_PFAULT_CLIENT_GPC_TPCCS_16 = 0x00000053
NV_PFAULT_CLIENT_GPC_TPCCS_17 = 0x00000054
NV_PFAULT_CLIENT_GPC_T1_32 = 0x00000055
NV_PFAULT_CLIENT_GPC_T1_33 = 0x00000056
NV_PFAULT_CLIENT_GPC_T1_34 = 0x00000057
NV_PFAULT_CLIENT_GPC_T1_35 = 0x00000058
NV_PFAULT_CLIENT_GPC_PE_18 = 0x00000059
NV_PFAULT_CLIENT_GPC_PE_19 = 0x0000005A
NV_PFAULT_CLIENT_GPC_TPCCS_18 = 0x0000005B
NV_PFAULT_CLIENT_GPC_TPCCS_19 = 0x0000005C
NV_PFAULT_CLIENT_GPC_T1_36 = 0x0000005D
NV_PFAULT_CLIENT_GPC_T1_37 = 0x0000005E
NV_PFAULT_CLIENT_GPC_T1_38 = 0x0000005F
NV_PFAULT_CLIENT_GPC_T1_39 = 0x00000060
NV_PFAULT_CLIENT_GPC_ROP_0 = 0x00000070
NV_PFAULT_CLIENT_GPC_ROP_1 = 0x00000071
NV_PFAULT_CLIENT_GPC_ROP_2 = 0x00000072
NV_PFAULT_CLIENT_GPC_ROP_3 = 0x00000073
NV_PFAULT_CLIENT_GPC_GPM = 0x00000017
NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 = 0x00000018
NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 = 0x00000019
NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 = 0x0000001A
NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 = 0x0000001B
NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 = 0x0000001C
NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 = 0x0000001D
NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 = 0x0000001E
NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 = 0x0000001F
NV_PFAULT_CLIENT_GPC_RGG_UTLB = 0x00000020
NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 = 0x00000031
NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 = 0x00000032
NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 = 0x00000033
NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 = 0x00000034
NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 = 0x00000035
NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 = 0x00000036
NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 = 0x00000037
NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 = 0x00000038
NV_PFAULT_CLIENT_HUB_VIP = 0x00000000
NV_PFAULT_CLIENT_HUB_CE0 = 0x00000001
NV_PFAULT_CLIENT_HUB_CE1 = 0x00000002
NV_PFAULT_CLIENT_HUB_DNISO = 0x00000003
NV_PFAULT_CLIENT_HUB_DISPNISO = 0x00000003
NV_PFAULT_CLIENT_HUB_FE0 = 0x00000004
NV_PFAULT_CLIENT_HUB_FE = 0x00000004
NV_PFAULT_CLIENT_HUB_FECS0 = 0x00000005
NV_PFAULT_CLIENT_HUB_FECS = 0x00000005
NV_PFAULT_CLIENT_HUB_HOST = 0x00000006
NV_PFAULT_CLIENT_HUB_HOST_CPU = 0x00000007
NV_PFAULT_CLIENT_HUB_HOST_CPU_NB = 0x00000008
NV_PFAULT_CLIENT_HUB_ISO = 0x00000009
NV_PFAULT_CLIENT_HUB_MMU = 0x0000000A
NV_PFAULT_CLIENT_HUB_NVDEC0 = 0x0000000B
NV_PFAULT_CLIENT_HUB_NVDEC = 0x0000000B
NV_PFAULT_CLIENT_HUB_NVENC1 = 0x0000000D
NV_PFAULT_CLIENT_HUB_NISO = 0x0000000E
NV_PFAULT_CLIENT_HUB_ACTRS = 0x0000000E
NV_PFAULT_CLIENT_HUB_P2P = 0x0000000F
NV_PFAULT_CLIENT_HUB_PD = 0x00000010
NV_PFAULT_CLIENT_HUB_PERF0 = 0x00000011
NV_PFAULT_CLIENT_HUB_PERF = 0x00000011
NV_PFAULT_CLIENT_HUB_PMU = 0x00000012
NV_PFAULT_CLIENT_HUB_RASTERTWOD = 0x00000013
NV_PFAULT_CLIENT_HUB_SCC = 0x00000014
NV_PFAULT_CLIENT_HUB_SCC_NB = 0x00000015
NV_PFAULT_CLIENT_HUB_SEC = 0x00000016
NV_PFAULT_CLIENT_HUB_SSYNC = 0x00000017
NV_PFAULT_CLIENT_HUB_GRCOPY = 0x00000018
NV_PFAULT_CLIENT_HUB_CE2 = 0x00000018
NV_PFAULT_CLIENT_HUB_XV = 0x00000019
NV_PFAULT_CLIENT_HUB_MMU_NB = 0x0000001A
NV_PFAULT_CLIENT_HUB_NVENC0 = 0x0000001B
NV_PFAULT_CLIENT_HUB_NVENC = 0x0000001B
NV_PFAULT_CLIENT_HUB_DFALCON = 0x0000001C
NV_PFAULT_CLIENT_HUB_SKED0 = 0x0000001D
NV_PFAULT_CLIENT_HUB_SKED = 0x0000001D
NV_PFAULT_CLIENT_HUB_AFALCON = 0x0000001E
NV_PFAULT_CLIENT_HUB_DONT_CARE = 0x0000001F
NV_PFAULT_CLIENT_HUB_HSCE0 = 0x00000020
NV_PFAULT_CLIENT_HUB_HSCE1 = 0x00000021
NV_PFAULT_CLIENT_HUB_HSCE2 = 0x00000022
NV_PFAULT_CLIENT_HUB_HSCE3 = 0x00000023
NV_PFAULT_CLIENT_HUB_HSCE4 = 0x00000024
NV_PFAULT_CLIENT_HUB_HSCE5 = 0x00000025
NV_PFAULT_CLIENT_HUB_HSCE6 = 0x00000026
NV_PFAULT_CLIENT_HUB_HSCE7 = 0x00000027
NV_PFAULT_CLIENT_HUB_HSCE8 = 0x00000028
NV_PFAULT_CLIENT_HUB_HSCE9 = 0x00000029
NV_PFAULT_CLIENT_HUB_HSHUB = 0x0000002A
NV_PFAULT_CLIENT_HUB_PTP_X0 = 0x0000002B
NV_PFAULT_CLIENT_HUB_PTP_X1 = 0x0000002C
NV_PFAULT_CLIENT_HUB_PTP_X2 = 0x0000002D
NV_PFAULT_CLIENT_HUB_PTP_X3 = 0x0000002E
NV_PFAULT_CLIENT_HUB_PTP_X4 = 0x0000002F
NV_PFAULT_CLIENT_HUB_PTP_X5 = 0x00000030
NV_PFAULT_CLIENT_HUB_PTP_X6 = 0x00000031
NV_PFAULT_CLIENT_HUB_PTP_X7 = 0x00000032
NV_PFAULT_CLIENT_HUB_NVENC2 = 0x00000033
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 = 0x00000034
NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 = 0x00000035
NV_PFAULT_CLIENT_HUB_DWBIF = 0x00000036
NV_PFAULT_CLIENT_HUB_FBFALCON = 0x00000037
NV_PFAULT_CLIENT_HUB_CE_SHIM = 0x00000038
NV_PFAULT_CLIENT_HUB_GSP = 0x00000039
NV_PFAULT_CLIENT_HUB_NVDEC1 = 0x0000003A
NV_PFAULT_CLIENT_HUB_NVDEC2 = 0x0000003B
NV_PFAULT_CLIENT_HUB_NVJPG0 = 0x0000003C
NV_PFAULT_CLIENT_HUB_NVDEC3 = 0x0000003D
NV_PFAULT_CLIENT_HUB_NVDEC4 = 0x0000003E
NV_PFAULT_CLIENT_HUB_OFA0 = 0x0000003F
NV_PFAULT_CLIENT_HUB_HSCE10 = 0x00000040
NV_PFAULT_CLIENT_HUB_HSCE11 = 0x00000041
NV_PFAULT_CLIENT_HUB_HSCE12 = 0x00000042
NV_PFAULT_CLIENT_HUB_HSCE13 = 0x00000043
NV_PFAULT_CLIENT_HUB_HSCE14 = 0x00000044
NV_PFAULT_CLIENT_HUB_HSCE15 = 0x00000045
NV_PFAULT_CLIENT_HUB_PTP_X8 = 0x00000046
NV_PFAULT_CLIENT_HUB_PTP_X9 = 0x00000047
NV_PFAULT_CLIENT_HUB_PTP_X10 = 0x00000048
NV_PFAULT_CLIENT_HUB_PTP_X11 = 0x00000049
NV_PFAULT_CLIENT_HUB_PTP_X12 = 0x0000004A
NV_PFAULT_CLIENT_HUB_PTP_X13 = 0x0000004B
NV_PFAULT_CLIENT_HUB_PTP_X14 = 0x0000004C
NV_PFAULT_CLIENT_HUB_PTP_X15 = 0x0000004D
NV_PFAULT_CLIENT_HUB_FE1 = 0x0000004E
NV_PFAULT_CLIENT_HUB_FE2 = 0x0000004F
NV_PFAULT_CLIENT_HUB_FE3 = 0x00000050
NV_PFAULT_CLIENT_HUB_FE4 = 0x00000051
NV_PFAULT_CLIENT_HUB_FE5 = 0x00000052
NV_PFAULT_CLIENT_HUB_FE6 = 0x00000053
NV_PFAULT_CLIENT_HUB_FE7 = 0x00000054
NV_PFAULT_CLIENT_HUB_FECS1 = 0x00000055
NV_PFAULT_CLIENT_HUB_FECS2 = 0x00000056
NV_PFAULT_CLIENT_HUB_FECS3 = 0x00000057
NV_PFAULT_CLIENT_HUB_FECS4 = 0x00000058
NV_PFAULT_CLIENT_HUB_FECS5 = 0x00000059
NV_PFAULT_CLIENT_HUB_FECS6 = 0x0000005A
NV_PFAULT_CLIENT_HUB_FECS7 = 0x0000005B
NV_PFAULT_CLIENT_HUB_SKED1 = 0x0000005C
NV_PFAULT_CLIENT_HUB_SKED2 = 0x0000005D
NV_PFAULT_CLIENT_HUB_SKED3 = 0x0000005E
NV_PFAULT_CLIENT_HUB_SKED4 = 0x0000005F
NV_PFAULT_CLIENT_HUB_SKED5 = 0x00000060
NV_PFAULT_CLIENT_HUB_SKED6 = 0x00000061
NV_PFAULT_CLIENT_HUB_SKED7 = 0x00000062
NV_PFAULT_CLIENT_HUB_ESC = 0x00000063
NV_PFAULT_ACCESS_TYPE_READ = 0x00000000
NV_PFAULT_ACCESS_TYPE_WRITE = 0x00000001
NV_PFAULT_ACCESS_TYPE_ATOMIC = 0x00000002
NV_PFAULT_ACCESS_TYPE_PREFETCH = 0x00000003
NV_PFAULT_ACCESS_TYPE_VIRT_READ = 0x00000000
NV_PFAULT_ACCESS_TYPE_VIRT_WRITE = 0x00000001
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC = 0x00000002
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG = 0x00000002
NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH = 0x00000003
NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK = 0x00000004
NV_PFAULT_ACCESS_TYPE_PHYS_READ = 0x00000008
NV_PFAULT_ACCESS_TYPE_PHYS_WRITE = 0x00000009
NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC = 0x0000000a
NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH = 0x0000000b
NV_PFAULT_MMU_CLIENT_TYPE_GPC = 0x00000000
NV_PFAULT_MMU_CLIENT_TYPE_HUB = 0x00000001
NV_ESC_RM_ALLOC_MEMORY = 0x27
NV_ESC_RM_ALLOC_OBJECT = 0x28
NV_ESC_RM_FREE = 0x29
NV_ESC_RM_CONTROL = 0x2A
NV_ESC_RM_ALLOC = 0x2B
NV_ESC_RM_CONFIG_GET = 0x32
NV_ESC_RM_CONFIG_SET = 0x33
NV_ESC_RM_DUP_OBJECT = 0x34
NV_ESC_RM_SHARE = 0x35
NV_ESC_RM_CONFIG_GET_EX = 0x37
NV_ESC_RM_CONFIG_SET_EX = 0x38
NV_ESC_RM_I2C_ACCESS = 0x39
NV_ESC_RM_IDLE_CHANNELS = 0x41
NV_ESC_RM_VID_HEAP_CONTROL = 0x4A
NV_ESC_RM_ACCESS_REGISTRY = 0x4D
NV_ESC_RM_MAP_MEMORY = 0x4E
NV_ESC_RM_UNMAP_MEMORY = 0x4F
NV_ESC_RM_GET_EVENT_DATA = 0x52
NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54
NV_ESC_RM_ADD_VBLANK_CALLBACK = 0x56
NV_ESC_RM_MAP_MEMORY_DMA = 0x57
NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58
NV_ESC_RM_BIND_CONTEXT_DMA = 0x59
NV_ESC_RM_EXPORT_OBJECT_TO_FD = 0x5C
NV_ESC_RM_IMPORT_OBJECT_FROM_FD = 0x5D
NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5E
NV_ESC_RM_LOCKLESS_DIAGNOSTIC = 0x5F
NV_RM_API_VERSION_STRING_LENGTH = 64
NV_RM_API_VERSION_CMD_STRICT = 0
NV_RM_API_VERSION_CMD_RELAXED = '1'
NV_RM_API_VERSION_CMD_QUERY = '2'
NV_RM_API_VERSION_REPLY_UNRECOGNIZED = 0
NV_RM_API_VERSION_REPLY_RECOGNIZED = 1
NV_DMABUF_EXPORT_MAX_HANDLES = 128
NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = 0
NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = 1
NV_IOCTL_MAGIC = 'F'
NV_IOCTL_BASE = 200
NV_ESC_CARD_INFO = (NV_IOCTL_BASE + 0)
NV_ESC_REGISTER_FD = (NV_IOCTL_BASE + 1)
NV_ESC_ALLOC_OS_EVENT = (NV_IOCTL_BASE + 6)
NV_ESC_FREE_OS_EVENT = (NV_IOCTL_BASE + 7)
NV_ESC_STATUS_CODE = (NV_IOCTL_BASE + 9)
NV_ESC_CHECK_VERSION_STR = (NV_IOCTL_BASE + 10)
NV_ESC_IOCTL_XFER_CMD = (NV_IOCTL_BASE + 11)
NV_ESC_ATTACH_GPUS_TO_FD = (NV_IOCTL_BASE + 12)
NV_ESC_QUERY_DEVICE_INTR = (NV_IOCTL_BASE + 13)
NV_ESC_SYS_PARAMS = (NV_IOCTL_BASE + 14)
NV_ESC_EXPORT_TO_DMABUF_FD = (NV_IOCTL_BASE + 17)
NV_ESC_WAIT_OPEN_COMPLETE = (NV_IOCTL_BASE + 18)
__aligned = lambda n: __attribute__((aligned(n)))
NV_ESC_NUMA_INFO = (NV_IOCTL_BASE + 15)
NV_ESC_SET_NUMA_STATUS = (NV_IOCTL_BASE + 16)
NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64
NV_IOCTL_NUMA_STATUS_DISABLED = 0
NV_IOCTL_NUMA_STATUS_OFFLINE = 1
NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS = 2
NV_IOCTL_NUMA_STATUS_ONLINE = 3
NV_IOCTL_NUMA_STATUS_ONLINE_FAILED = 4
NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS = 5
NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED = 6
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL = 0x00000000
NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL = 0x00000001
NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL = 0x00000002
NVOS04_FLAGS_VPR_FALSE = 0x00000000
NVOS04_FLAGS_VPR_TRUE = 0x00000001
NVOS04_FLAGS_CC_SECURE_FALSE = 0x00000000
NVOS04_FLAGS_CC_SECURE_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE = 0x00000001
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT = 0x00000000
NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE = 0x00000001
NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE = 0x00000000
NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE = 0x00000001
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE = 0x00000000
NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE = 0x00000001
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE = 0x00000000
NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE = 0x00000001
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE = 0x00000000
NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE = 0x00000001
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT = 0x00000000
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE = 0x00000001
NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO = 0x00000002
NVOS04_FLAGS_MAP_CHANNEL_FALSE = 0x00000000
NVOS04_FLAGS_MAP_CHANNEL_TRUE = 0x00000001
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE = 0x00000000
NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE = 0x00000001
CC_CHAN_ALLOC_IV_SIZE_DWORD = 3
CC_CHAN_ALLOC_NONCE_SIZE_DWORD = 8
NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID = (0x906f)
FILE_DEVICE_NV = 0x00008000
NV_IOCTL_FCT_BASE = 0x00000800
NVOS_MAX_SUBDEVICES = 8
UNIFIED_NV_STATUS = 1
NVOS_STATUS = NV_STATUS
NVOS_STATUS_SUCCESS = NV_OK
NVOS_STATUS_ERROR_CARD_NOT_PRESENT = NV_ERR_CARD_NOT_PRESENT
NVOS_STATUS_ERROR_DUAL_LINK_INUSE = NV_ERR_DUAL_LINK_INUSE
NVOS_STATUS_ERROR_GENERIC = NV_ERR_GENERIC
NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER = NV_ERR_GPU_NOT_FULL_POWER
NVOS_STATUS_ERROR_ILLEGAL_ACTION = NV_ERR_ILLEGAL_ACTION
NVOS_STATUS_ERROR_IN_USE = NV_ERR_STATE_IN_USE
NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES = NV_ERR_INSUFFICIENT_RESOURCES
NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE = NV_ERR_INVALID_ACCESS_TYPE
NVOS_STATUS_ERROR_INVALID_ARGUMENT = NV_ERR_INVALID_ARGUMENT
NVOS_STATUS_ERROR_INVALID_BASE = NV_ERR_INVALID_BASE
NVOS_STATUS_ERROR_INVALID_CHANNEL = NV_ERR_INVALID_CHANNEL
NVOS_STATUS_ERROR_INVALID_CLASS = NV_ERR_INVALID_CLASS
NVOS_STATUS_ERROR_INVALID_CLIENT = NV_ERR_INVALID_CLIENT
NVOS_STATUS_ERROR_INVALID_COMMAND = NV_ERR_INVALID_COMMAND
NVOS_STATUS_ERROR_INVALID_DATA = NV_ERR_INVALID_DATA
NVOS_STATUS_ERROR_INVALID_DEVICE = NV_ERR_INVALID_DEVICE
NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER = NV_ERR_INVALID_DMA_SPECIFIER
NVOS_STATUS_ERROR_INVALID_EVENT = NV_ERR_INVALID_EVENT
NVOS_STATUS_ERROR_INVALID_FLAGS = NV_ERR_INVALID_FLAGS
NVOS_STATUS_ERROR_INVALID_FUNCTION = NV_ERR_INVALID_FUNCTION
NVOS_STATUS_ERROR_INVALID_HEAP = NV_ERR_INVALID_HEAP
NVOS_STATUS_ERROR_INVALID_INDEX = NV_ERR_INVALID_INDEX
NVOS_STATUS_ERROR_INVALID_LIMIT = NV_ERR_INVALID_LIMIT
NVOS_STATUS_ERROR_INVALID_METHOD = NV_ERR_INVALID_METHOD
NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER = NV_ERR_BUFFER_TOO_SMALL
NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR = NV_ERR_INVALID_OBJECT
NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE = NV_ERR_INVALID_OBJECT_HANDLE
NVOS_STATUS_ERROR_INVALID_OBJECT_NEW = NV_ERR_INVALID_OBJECT_NEW
NVOS_STATUS_ERROR_INVALID_OBJECT_OLD = NV_ERR_INVALID_OBJECT_OLD
NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT = NV_ERR_INVALID_OBJECT_PARENT
NVOS_STATUS_ERROR_INVALID_OFFSET = NV_ERR_INVALID_OFFSET
NVOS_STATUS_ERROR_INVALID_OWNER = NV_ERR_INVALID_OWNER
NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT = NV_ERR_INVALID_PARAM_STRUCT
NVOS_STATUS_ERROR_INVALID_PARAMETER = NV_ERR_INVALID_PARAMETER
NVOS_STATUS_ERROR_INVALID_POINTER = NV_ERR_INVALID_POINTER
NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY = NV_ERR_INVALID_REGISTRY_KEY
NVOS_STATUS_ERROR_INVALID_STATE = NV_ERR_INVALID_STATE
NVOS_STATUS_ERROR_INVALID_STRING_LENGTH = NV_ERR_INVALID_STRING_LENGTH
NVOS_STATUS_ERROR_INVALID_XLATE = NV_ERR_INVALID_XLATE
NVOS_STATUS_ERROR_IRQ_NOT_FIRING = NV_ERR_IRQ_NOT_FIRING
NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES = NV_ERR_MULTIPLE_MEMORY_TYPES
NVOS_STATUS_ERROR_NOT_SUPPORTED = NV_ERR_NOT_SUPPORTED
NVOS_STATUS_ERROR_OPERATING_SYSTEM = NV_ERR_OPERATING_SYSTEM
NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH = NV_ERR_LIB_RM_VERSION_MISMATCH
NVOS_STATUS_ERROR_PROTECTION_FAULT = NV_ERR_PROTECTION_FAULT
NVOS_STATUS_ERROR_TIMEOUT = NV_ERR_TIMEOUT
NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES = NV_ERR_TOO_MANY_PRIMARIES
NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED = NV_ERR_IRQ_EDGE_TRIGGERED
NVOS_STATUS_ERROR_INVALID_OPERATION = NV_ERR_INVALID_OPERATION
NVOS_STATUS_ERROR_NOT_COMPATIBLE = NV_ERR_NOT_COMPATIBLE
NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED = NV_WARN_MORE_PROCESSING_REQUIRED
NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS = NV_ERR_INSUFFICIENT_PERMISSIONS
NVOS_STATUS_ERROR_TIMEOUT_RETRY = NV_ERR_TIMEOUT_RETRY
NVOS_STATUS_ERROR_NOT_READY = NV_ERR_NOT_READY
NVOS_STATUS_ERROR_GPU_IS_LOST = NV_ERR_GPU_IS_LOST
NVOS_STATUS_ERROR_IN_FULLCHIP_RESET = NV_ERR_GPU_IN_FULLCHIP_RESET
NVOS_STATUS_ERROR_INVALID_LOCK_STATE = NV_ERR_INVALID_LOCK_STATE
NVOS_STATUS_ERROR_INVALID_ADDRESS = NV_ERR_INVALID_ADDRESS
NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL = NV_ERR_INVALID_IRQ_LEVEL
NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED = NV_ERR_MEMORY_TRAINING_FAILED
NVOS_STATUS_ERROR_BUSY_RETRY = NV_ERR_BUSY_RETRY
NVOS_STATUS_ERROR_INSUFFICIENT_POWER = NV_ERR_INSUFFICIENT_POWER
NVOS_STATUS_ERROR_OBJECT_NOT_FOUND = NV_ERR_OBJECT_NOT_FOUND
NVOS_STATUS_ERROR_RESOURCE_LOST = NV_ERR_RESOURCE_LOST
NVOS_STATUS_ERROR_BUFFER_TOO_SMALL = NV_ERR_BUFFER_TOO_SMALL
NVOS_STATUS_ERROR_RESET_REQUIRED = NV_ERR_RESET_REQUIRED
NVOS_STATUS_ERROR_INVALID_REQUEST = NV_ERR_INVALID_REQUEST
NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION = NV_ERR_PRIV_SEC_VIOLATION
NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE = NV_ERR_GPU_IN_DEBUG_MODE
NVOS_STATUS_ERROR_ALREADY_SIGNALLED = NV_ERR_ALREADY_SIGNALLED
NV01_FREE = (0x00000000)
NV01_ROOT = (0x0)
NV01_ROOT_NON_PRIV = (0x00000001)
NV01_ROOT_CLIENT = (0x00000041)
NV01_ALLOC_MEMORY = (0x00000002)
NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS = (0x00000000)
NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS = (0x00000001)
NVOS02_FLAGS_LOCATION_PCI = (0x00000000)
NVOS02_FLAGS_LOCATION_VIDMEM = (0x00000002)
NVOS02_FLAGS_COHERENCY_UNCACHED = (0x00000000)
NVOS02_FLAGS_COHERENCY_CACHED = (0x00000001)
NVOS02_FLAGS_COHERENCY_WRITE_COMBINE = (0x00000002)
NVOS02_FLAGS_COHERENCY_WRITE_THROUGH = (0x00000003)
NVOS02_FLAGS_COHERENCY_WRITE_PROTECT = (0x00000004)
NVOS02_FLAGS_COHERENCY_WRITE_BACK = (0x00000005)
NVOS02_FLAGS_ALLOC_NONE = (0x00000001)
NVOS02_FLAGS_GPU_CACHEABLE_NO = (0x00000000)
NVOS02_FLAGS_GPU_CACHEABLE_YES = (0x00000001)
NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP = (0x00000000)
NVOS02_FLAGS_KERNEL_MAPPING_MAP = (0x00000001)
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO = (0x00000000)
NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES = (0x00000001)
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO = (0x00000000)
NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES = (0x00000001)
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO = (0x00000000)
NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES = (0x00000001)
NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT = (0x00000000)
NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED = (0x00000001)
NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE = (0x00000001)
NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT = (0x00000000)
NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED = (0x00000001)
NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED = (0x00000002)
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = (0x00000000)
NVOS02_FLAGS_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = (0x00000001)
NVOS02_FLAGS_MAPPING_DEFAULT = (0x00000000)
NVOS02_FLAGS_MAPPING_NO_MAP = (0x00000001)
NVOS02_FLAGS_MAPPING_NEVER_MAP = (0x00000002)
NVOS03_FLAGS_ACCESS_READ_WRITE = (0x00000000)
NVOS03_FLAGS_ACCESS_READ_ONLY = (0x00000001)
NVOS03_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
NVOS03_FLAGS_PREALLOCATE_DISABLE = (0x00000000)
NVOS03_FLAGS_PREALLOCATE_ENABLE = (0x00000001)
NVOS03_FLAGS_GPU_MAPPABLE_DISABLE = (0x00000000)
NVOS03_FLAGS_GPU_MAPPABLE_ENABLE = (0x00000001)
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE = (0x00000000)
NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE = (0x00000001)
NVOS03_FLAGS_PTE_KIND_NONE = (0x00000000)
NVOS03_FLAGS_PTE_KIND_BL = (0x00000001)
NVOS03_FLAGS_PTE_KIND_PITCH = (0x00000002)
NVOS03_FLAGS_TYPE_NOTIFIER = (0x00000001)
NVOS03_FLAGS_MAPPING_NONE = (0x00000000)
NVOS03_FLAGS_MAPPING_KERNEL = (0x00000001)
NVOS03_FLAGS_CACHE_SNOOP_ENABLE = (0x00000000)
NVOS03_FLAGS_CACHE_SNOOP_DISABLE = (0x00000001)
NVOS03_FLAGS_HASH_TABLE_ENABLE = (0x00000000)
NVOS03_FLAGS_HASH_TABLE_DISABLE = (0x00000001)
NV01_ALLOC_OBJECT = (0x00000005)
NV01_EVENT_KERNEL_CALLBACK = (0x00000078)
NV01_EVENT_OS_EVENT = (0x00000079)
NV01_EVENT_WIN32_EVENT = NV01_EVENT_OS_EVENT
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007E)
NV01_EVENT_BROADCAST = (0x80000000)
NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION = (0x40000000)
NV01_EVENT_SUBDEVICE_SPECIFIC = (0x20000000)
NV01_EVENT_WITHOUT_EVENT_DATA = (0x10000000)
NV01_EVENT_NONSTALL_INTR = (0x08000000)
NV01_EVENT_CLIENT_RM = (0x04000000)
NV04_I2C_ACCESS = (0x00000013)
NVOS_I2C_ACCESS_MAX_BUFFER_SIZE = 2048
NVOS20_COMMAND_unused0001 = 0x0001
NVOS20_COMMAND_unused0002 = 0x0002
NVOS20_COMMAND_STRING_PRINT = 0x0003
NV04_ALLOC = (0x00000015)
NVOS64_FLAGS_NONE = (0x00000000)
NVOS64_FLAGS_FINN_SERIALIZED = (0x00000001)
NVOS65_PARAMETERS_VERSION_MAGIC = 0x77FEF81E
NV04_IDLE_CHANNELS = (0x0000001E)
NVOS30_FLAGS_BEHAVIOR_SPIN = (0x00000000)
NVOS30_FLAGS_BEHAVIOR_SLEEP = (0x00000001)
NVOS30_FLAGS_BEHAVIOR_QUERY = (0x00000002)
NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK = (0x00000003)
NVOS30_FLAGS_CHANNEL_LIST = (0x00000000)
NVOS30_FLAGS_CHANNEL_SINGLE = (0x00000001)
NVOS30_FLAGS_IDLE_PUSH_BUFFER = (0x00000001)
NVOS30_FLAGS_IDLE_CACHE1 = (0x00000002)
NVOS30_FLAGS_IDLE_GRAPHICS = (0x00000004)
NVOS30_FLAGS_IDLE_MPEG = (0x00000008)
NVOS30_FLAGS_IDLE_MOTION_ESTIMATION = (0x00000010)
NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR = (0x00000020)
NVOS30_FLAGS_IDLE_MSPDEC = (0x00000020)
NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR = (0x00000040)
NVOS30_FLAGS_IDLE_MSVLD = (0x00000040)
NVOS30_FLAGS_IDLE_NVDEC0 = NVOS30_FLAGS_IDLE_MSVLD
NVOS30_FLAGS_IDLE_CIPHER_DMA = (0x00000080)
NVOS30_FLAGS_IDLE_SEC = (0x00000080)
NVOS30_FLAGS_IDLE_CALLBACKS = (0x00000100)
NVOS30_FLAGS_IDLE_MSPPP = (0x00000200)
NVOS30_FLAGS_IDLE_CE0 = (0x00000400)
NVOS30_FLAGS_IDLE_CE1 = (0x00000800)
NVOS30_FLAGS_IDLE_CE2 = (0x00001000)
NVOS30_FLAGS_IDLE_CE3 = (0x00002000)
NVOS30_FLAGS_IDLE_CE4 = (0x00004000)
NVOS30_FLAGS_IDLE_CE5 = (0x00008000)
NVOS30_FLAGS_IDLE_VIC = (0x00010000)
NVOS30_FLAGS_IDLE_MSENC = (0x00020000)
NVOS30_FLAGS_IDLE_NVENC0 = NVOS30_FLAGS_IDLE_MSENC
NVOS30_FLAGS_IDLE_NVENC1 = (0x00040000)
NVOS30_FLAGS_IDLE_NVENC2 = (0x00080000)
NVOS30_FLAGS_IDLE_NVJPG = (0x00100000)
NVOS30_FLAGS_IDLE_NVDEC1 = (0x00200000)
NVOS30_FLAGS_IDLE_NVDEC2 = (0x00400000)
NVOS30_FLAGS_IDLE_ACTIVECHANNELS = (0x00800000)
NVOS30_FLAGS_IDLE_ALL_ENGINES = (NVOS30_FLAGS_IDLE_GRAPHICS | NVOS30_FLAGS_IDLE_MPEG | NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | NVOS30_FLAGS_IDLE_CIPHER_DMA  | NVOS30_FLAGS_IDLE_MSPDEC      | NVOS30_FLAGS_IDLE_NVDEC0      | NVOS30_FLAGS_IDLE_SEC         | NVOS30_FLAGS_IDLE_MSPPP       | NVOS30_FLAGS_IDLE_CE0         | NVOS30_FLAGS_IDLE_CE1         | NVOS30_FLAGS_IDLE_CE2         | NVOS30_FLAGS_IDLE_CE3         | NVOS30_FLAGS_IDLE_CE4         | NVOS30_FLAGS_IDLE_CE5         | NVOS30_FLAGS_IDLE_NVENC0      | NVOS30_FLAGS_IDLE_NVENC1      | NVOS30_FLAGS_IDLE_NVENC2      | NVOS30_FLAGS_IDLE_VIC         | NVOS30_FLAGS_IDLE_NVJPG       | NVOS30_FLAGS_IDLE_NVDEC1      | NVOS30_FLAGS_IDLE_NVDEC2)
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO = (0x00000000)
NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES = (0x00000001)
NV04_VID_HEAP_CONTROL = (0x00000020)
NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS = 0
NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY = 1
NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY = 2
NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR = 3
NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE = 4
NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR = 5
NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR = 6
NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS = 7
NVOS32_FUNCTION_ALLOC_SIZE = 2
NVOS32_FUNCTION_FREE = 3
NVOS32_FUNCTION_INFO = 5
NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT = 6
NVOS32_FUNCTION_DUMP = 11
NVOS32_FUNCTION_ALLOC_SIZE_RANGE = 14
NVOS32_FUNCTION_REACQUIRE_COMPR = 15
NVOS32_FUNCTION_RELEASE_COMPR = 16
NVOS32_FUNCTION_GET_MEM_ALIGNMENT = 18
NVOS32_FUNCTION_HW_ALLOC = 19
NVOS32_FUNCTION_HW_FREE = 20
NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR = 27
NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU = (0x00000001)
NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP = 0
NVAL_MAX_BANKS = (4)
NVAL_MAP_DIRECTION_DOWN = 0x00000000
NVAL_MAP_DIRECTION_UP = 0x00000001
NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR = 1
NVOS32_DELETE_RESOURCES_ALL = 0
NVOS32_TYPE_IMAGE = 0
NVOS32_TYPE_DEPTH = 1
NVOS32_TYPE_TEXTURE = 2
NVOS32_TYPE_VIDEO = 3
NVOS32_TYPE_FONT = 4
NVOS32_TYPE_CURSOR = 5
NVOS32_TYPE_DMA = 6
NVOS32_TYPE_INSTANCE = 7
NVOS32_TYPE_PRIMARY = 8
NVOS32_TYPE_ZCULL = 9
NVOS32_TYPE_UNUSED = 10
NVOS32_TYPE_SHADER_PROGRAM = 11
NVOS32_TYPE_OWNER_RM = 12
NVOS32_TYPE_NOTIFIER = 13
NVOS32_TYPE_RESERVED = 14
NVOS32_TYPE_PMA = 15
NVOS32_TYPE_STENCIL = 16
NVOS32_NUM_MEM_TYPES = 17
NVOS32_ATTR_NONE = 0x00000000
NVOS32_ATTR_DEPTH_UNKNOWN = 0x00000000
NVOS32_ATTR_DEPTH_8 = 0x00000001
NVOS32_ATTR_DEPTH_16 = 0x00000002
NVOS32_ATTR_DEPTH_24 = 0x00000003
NVOS32_ATTR_DEPTH_32 = 0x00000004
NVOS32_ATTR_DEPTH_64 = 0x00000005
NVOS32_ATTR_DEPTH_128 = 0x00000006
NVOS32_ATTR_COMPR_COVG_DEFAULT = 0x00000000
NVOS32_ATTR_COMPR_COVG_PROVIDED = 0x00000001
NVOS32_ATTR_AA_SAMPLES_1 = 0x00000000
NVOS32_ATTR_AA_SAMPLES_2 = 0x00000001
NVOS32_ATTR_AA_SAMPLES_4 = 0x00000002
NVOS32_ATTR_AA_SAMPLES_4_ROTATED = 0x00000003
NVOS32_ATTR_AA_SAMPLES_6 = 0x00000004
NVOS32_ATTR_AA_SAMPLES_8 = 0x00000005
NVOS32_ATTR_AA_SAMPLES_16 = 0x00000006
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 = 0x00000007
NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 = 0x00000008
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 = 0x00000009
NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 = 0x0000000A
NVOS32_ATTR_ZCULL_NONE = 0x00000000
NVOS32_ATTR_ZCULL_REQUIRED = 0x00000001
NVOS32_ATTR_ZCULL_ANY = 0x00000002
NVOS32_ATTR_ZCULL_SHARED = 0x00000003
NVOS32_ATTR_COMPR_NONE = 0x00000000
NVOS32_ATTR_COMPR_REQUIRED = 0x00000001
NVOS32_ATTR_COMPR_ANY = 0x00000002
NVOS32_ATTR_COMPR_PLC_REQUIRED = NVOS32_ATTR_COMPR_REQUIRED
NVOS32_ATTR_COMPR_PLC_ANY = NVOS32_ATTR_COMPR_ANY
NVOS32_ATTR_COMPR_DISABLE_PLC_ANY = 0x00000003
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO = 0x00000000
NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES = 0x00000001
NVOS32_ATTR_FORMAT_LOW_FIELD = 16
NVOS32_ATTR_FORMAT_HIGH_FIELD = 17
NVOS32_ATTR_FORMAT_PITCH = 0x00000000
NVOS32_ATTR_FORMAT_SWIZZLED = 0x00000001
NVOS32_ATTR_FORMAT_BLOCK_LINEAR = 0x00000002
NVOS32_ATTR_Z_TYPE_FIXED = 0x00000000
NVOS32_ATTR_Z_TYPE_FLOAT = 0x00000001
NVOS32_ATTR_ZS_PACKING_S8 = 0x00000000
NVOS32_ATTR_ZS_PACKING_Z24S8 = 0x00000000
NVOS32_ATTR_ZS_PACKING_S8Z24 = 0x00000001
NVOS32_ATTR_ZS_PACKING_Z32 = 0x00000002
NVOS32_ATTR_ZS_PACKING_Z24X8 = 0x00000003
NVOS32_ATTR_ZS_PACKING_X8Z24 = 0x00000004
NVOS32_ATTR_ZS_PACKING_Z32_X24S8 = 0x00000005
NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 = 0x00000006
NVOS32_ATTR_ZS_PACKING_Z16 = 0x00000007
NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 = 0x00000000
NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 = 0x00000001
NVOS32_ATTR_PAGE_SIZE_DEFAULT = 0x00000000
NVOS32_ATTR_PAGE_SIZE_4KB = 0x00000001
NVOS32_ATTR_PAGE_SIZE_BIG = 0x00000002
NVOS32_ATTR_PAGE_SIZE_HUGE = 0x00000003
NVOS32_ATTR_LOCATION_VIDMEM = 0x00000000
NVOS32_ATTR_LOCATION_PCI = 0x00000001
NVOS32_ATTR_LOCATION_ANY = 0x00000003
NVOS32_ATTR_PHYSICALITY_DEFAULT = 0x00000000
NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS = 0x00000001
NVOS32_ATTR_PHYSICALITY_CONTIGUOUS = 0x00000002
NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS = 0x00000003
NVOS32_ATTR_COHERENCY_UNCACHED = 0x00000000
NVOS32_ATTR_COHERENCY_CACHED = 0x00000001
NVOS32_ATTR_COHERENCY_WRITE_COMBINE = 0x00000002
NVOS32_ATTR_COHERENCY_WRITE_THROUGH = 0x00000003
NVOS32_ATTR_COHERENCY_WRITE_PROTECT = 0x00000004
NVOS32_ATTR_COHERENCY_WRITE_BACK = 0x00000005
NVOS32_ATTR2_NONE = 0x00000000
NVOS32_ATTR2_ZBC_DEFAULT = 0x00000000
NVOS32_ATTR2_ZBC_PREFER_NO_ZBC = 0x00000001
NVOS32_ATTR2_ZBC_PREFER_ZBC = 0x00000002
NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC = 0x00000003
NVOS32_ATTR2_ZBC_INVALID = 0x00000003
NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT = 0x00000000
NVOS32_ATTR2_GPU_CACHEABLE_YES = 0x00000001
NVOS32_ATTR2_GPU_CACHEABLE_NO = 0x00000002
NVOS32_ATTR2_GPU_CACHEABLE_INVALID = 0x00000003
NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT = 0x00000000
NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES = 0x00000001
NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO = 0x00000002
NVOS32_ATTR2_32BIT_POINTER_DISABLE = 0x00000000
NVOS32_ATTR2_32BIT_POINTER_ENABLE = 0x00000001
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO = 0x00000000
NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES = 0x00000001
NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT = 0x00000000
NVOS32_ATTR2_SMMU_ON_GPU_DISABLE = 0x00000001
NVOS32_ATTR2_SMMU_ON_GPU_ENABLE = 0x00000002
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE = 0x00000000
NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE = 0x00000001
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF = 0x0
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON = 0x1
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT = NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF
NVOS32_ATTR2_PRIORITY_DEFAULT = 0x0
NVOS32_ATTR2_PRIORITY_HIGH = 0x1
NVOS32_ATTR2_PRIORITY_LOW = 0x2
NVOS32_ATTR2_INTERNAL_NO = 0x0
NVOS32_ATTR2_INTERNAL_YES = 0x1
NVOS32_ATTR2_PREFER_2C_NO = 0x00000000
NVOS32_ATTR2_PREFER_2C_YES = 0x00000001
NVOS32_ATTR2_NISO_DISPLAY_NO = 0x00000000
NVOS32_ATTR2_NISO_DISPLAY_YES = 0x00000001
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO = 0x00000000
NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES = 0x00000001
NVOS32_ATTR2_ISO_NO = 0x00000000
NVOS32_ATTR2_ISO_YES = 0x00000001
NVOS32_ATTR2_BLACKLIST_ON = 0x00000000
NVOS32_ATTR2_BLACKLIST_OFF = 0x00000001
NVOS32_ATTR2_PAGE_OFFLINING_ON = 0x00000000
NVOS32_ATTR2_PAGE_OFFLINING_OFF = 0x00000001
NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT = 0x00000000
NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB = 0x00000001
NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB = 0x00000002
NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB = 0x00000003
NVOS32_ATTR2_PROTECTION_USER_READ_WRITE = 0x00000000
NVOS32_ATTR2_PROTECTION_USER_READ_ONLY = 0x00000001
NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE = 0x00000000
NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY = 0x00000001
NVOS32_ATTR2_USE_EGM_FALSE = 0x00000000
NVOS32_ATTR2_USE_EGM_TRUE = 0x00000001
NVOS32_ATTR2_MEMORY_PROTECTION_DEFAULT = 0x00000000
NVOS32_ATTR2_MEMORY_PROTECTION_PROTECTED = 0x00000001
NVOS32_ATTR2_MEMORY_PROTECTION_UNPROTECTED = 0x00000002
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO = 0x00000000
NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES = 0x00000001
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE = 0x00000000
NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE = 0x00000001
NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT = 0x00000001
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP = 0x00000002
NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN = 0x00000004
NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE = 0x00000008
NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE = 0x00000010
NVOS32_ALLOC_FLAGS_BANK_HINT = 0x00000020
NVOS32_ALLOC_FLAGS_BANK_FORCE = 0x00000040
NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT = 0x00000080
NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE = 0x00000100
NVOS32_ALLOC_FLAGS_BANK_GROW_UP = 0x00000000
NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN = 0x00000200
NVOS32_ALLOC_FLAGS_LAZY = 0x00000400
NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC = 0x00000800
NVOS32_ALLOC_FLAGS_NO_SCANOUT = 0x00001000
NVOS32_ALLOC_FLAGS_PITCH_FORCE = 0x00002000
NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00004000
NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED = 0x00008000
NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM = 0x00010000
NVOS32_ALLOC_FLAGS_USE_BEGIN_END = 0x00020000
NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED = 0x00040000
NVOS32_ALLOC_FLAGS_VIRTUAL = 0x00080000
NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX = 0x00100000
NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED = 0x00200000
NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED = 0x00400000
NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE = 0x00800000
NVOS32_ALLOC_FLAGS_PROTECTED = 0x01000000
NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP = 0x02000000
NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE = 0x02000000
NVOS32_ALLOC_FLAGS_SPARSE = 0x04000000
NVOS32_ALLOC_FLAGS_USER_READ_ONLY = 0x04000000
NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY = 0x08000000
NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED = 0x08000000
NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC = 0x10000000
NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY = 0x20000000
NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD = 0x40000000
NVOS32_ALLOC_FLAGS_WPR1 = 0x40000000
NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X = 0x80000000
NVOS32_ALLOC_FLAGS_WPR2 = 0x80000000
NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC = 0x00000001
NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB = 0x00000004
NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE = NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE
NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY = ( NVOS32_ALLOC_FLAGS_VIRTUAL                  | NVOS32_ALLOC_FLAGS_LAZY                     | NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED       | NVOS32_ALLOC_FLAGS_SPARSE                   | NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE   | NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY )
NVOS32_ALLOC_COMPR_COVG_SCALE = 10
NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT = 0x00000000
NVOS32_ALLOC_COMPR_COVG_BITS_1 = 0x00000001
NVOS32_ALLOC_COMPR_COVG_BITS_2 = 0x00000002
NVOS32_ALLOC_COMPR_COVG_BITS_4 = 0x00000003
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z = 0x00000000
NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z = 0x00000002
NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS = 0x00000003
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW = 0x00000000
NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW = 0x00000001
NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT = 0x00000000
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT = 0x00000000
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF = 0x00000000
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED = 0x00000001
NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN = 0x00000002
NVOS32_REALLOC_FLAGS_GROW_ALLOCATION = 0x00000000
NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION = 0x00000001
NVOS32_REALLOC_FLAGS_REALLOC_UP = 0x00000000
NVOS32_REALLOC_FLAGS_REALLOC_DOWN = 0x00000002
NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001
NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED = 0x000000001
NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED = 0x00000001
NVOS32_DUMP_FLAGS_TYPE_FB = 0x00000000
NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD = 0x00000001
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA = 0x00000002
NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE = 0x00000003
NVOS32_BLOCK_TYPE_FREE = 0xFFFFFFFF
NVOS32_INVALID_BLOCK_FREE_OFFSET = 0xFFFFFFFF
NVOS32_MEM_TAG_NONE = 0x00000000
NV04_MAP_MEMORY = (0x00000021)
NV04_MAP_MEMORY_FLAGS_NONE = (0x00000000)
NV04_MAP_MEMORY_FLAGS_USER = (0x00004000)
NVOS33_FLAGS_ACCESS_READ_WRITE = (0x00000000)
NVOS33_FLAGS_ACCESS_READ_ONLY = (0x00000001)
NVOS33_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
NVOS33_FLAGS_PERSISTENT_DISABLE = (0x00000000)
NVOS33_FLAGS_PERSISTENT_ENABLE = (0x00000001)
NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE = (0x00000000)
NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE = (0x00000001)
NVOS33_FLAGS_MEM_SPACE_CLIENT = (0x00000000)
NVOS33_FLAGS_MEM_SPACE_USER = (0x00000001)
NVOS33_FLAGS_MAPPING_DEFAULT = (0x00000000)
NVOS33_FLAGS_MAPPING_DIRECT = (0x00000001)
NVOS33_FLAGS_MAPPING_REFLECTED = (0x00000002)
NVOS33_FLAGS_FIFO_MAPPING_DEFAULT = (0x00000000)
NVOS33_FLAGS_FIFO_MAPPING_ENABLE = (0x00000001)
NVOS33_FLAGS_MAP_FIXED_DISABLE = (0x00000000)
NVOS33_FLAGS_MAP_FIXED_ENABLE = (0x00000001)
NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE = (0x00000000)
NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE = (0x00000001)
NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE = (0x00000000)
NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE = (0x00000001)
NVOS33_FLAGS_CACHING_TYPE_CACHED = 0
NVOS33_FLAGS_CACHING_TYPE_UNCACHED = 1
NVOS33_FLAGS_CACHING_TYPE_WRITECOMBINED = 2
NVOS33_FLAGS_CACHING_TYPE_WRITEBACK = 5
NVOS33_FLAGS_CACHING_TYPE_DEFAULT = 6
NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK = 7
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO = (0x00000000)
NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES = (0x00000001)
NV04_UNMAP_MEMORY = (0x00000022)
NV04_ACCESS_REGISTRY = (0x00000026)
NVOS38_ACCESS_TYPE_READ_DWORD = 1
NVOS38_ACCESS_TYPE_WRITE_DWORD = 2
NVOS38_ACCESS_TYPE_READ_BINARY = 6
NVOS38_ACCESS_TYPE_WRITE_BINARY = 7
NVOS38_MAX_REGISTRY_STRING_LENGTH = 256
NVOS38_MAX_REGISTRY_BINARY_LENGTH = 256
NV04_ALLOC_CONTEXT_DMA = (0x00000027)
NV04_GET_EVENT_DATA = (0x00000028)
NVSIM01_BUS_XACT = (0x0000002C)
NV04_MAP_MEMORY_DMA = (0x0000002E)
NVOS46_FLAGS_ACCESS_READ_WRITE = (0x00000000)
NVOS46_FLAGS_ACCESS_READ_ONLY = (0x00000001)
NVOS46_FLAGS_ACCESS_WRITE_ONLY = (0x00000002)
NVOS46_FLAGS_32BIT_POINTER_DISABLE = (0x00000000)
NVOS46_FLAGS_32BIT_POINTER_ENABLE = (0x00000001)
NVOS46_FLAGS_PAGE_KIND_PHYSICAL = (0x00000000)
NVOS46_FLAGS_PAGE_KIND_VIRTUAL = (0x00000001)
NVOS46_FLAGS_CACHE_SNOOP_DISABLE = (0x00000000)
NVOS46_FLAGS_CACHE_SNOOP_ENABLE = (0x00000001)
NVOS46_FLAGS_KERNEL_MAPPING_NONE = (0x00000000)
NVOS46_FLAGS_KERNEL_MAPPING_ENABLE = (0x00000001)
NVOS46_FLAGS_SHADER_ACCESS_DEFAULT = (0x00000000)
NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001)
NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002)
NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000003)
NVOS46_FLAGS_PAGE_SIZE_DEFAULT = (0x00000000)
NVOS46_FLAGS_PAGE_SIZE_4KB = (0x00000001)
NVOS46_FLAGS_PAGE_SIZE_BIG = (0x00000002)
NVOS46_FLAGS_PAGE_SIZE_BOTH = (0x00000003)
NVOS46_FLAGS_PAGE_SIZE_HUGE = (0x00000004)
NVOS46_FLAGS_PAGE_SIZE_512M = (0x00000005)
NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT = (0x00000000)
NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT = (0x00000001)
NVOS46_FLAGS_DMA_OFFSET_GROWS_UP = (0x00000000)
NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN = (0x00000001)
NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE = (0x00000000)
NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE = (0x00000001)
NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE = (0x00000000)
NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE = (0x00000001)
NVOS46_FLAGS_P2P_ENABLE_NO = (0x00000000)
NVOS46_FLAGS_P2P_ENABLE_YES = (0x00000001)
NVOS46_FLAGS_P2P_ENABLE_NONE = NVOS46_FLAGS_P2P_ENABLE_NO
NVOS46_FLAGS_P2P_ENABLE_SLI = NVOS46_FLAGS_P2P_ENABLE_YES
NVOS46_FLAGS_P2P_ENABLE_NOSLI = (0x00000002)
NVOS46_FLAGS_TLB_LOCK_DISABLE = (0x00000000)
NVOS46_FLAGS_TLB_LOCK_ENABLE = (0x00000001)
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE = (0x00000000)
NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE = (0x00000001)
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE = (0x00000000)
NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE = (0x00000001)
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000)
NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001)
NV04_UNMAP_MEMORY_DMA = (0x0000002F)
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE = (0x00000000)
NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE = (0x00000001)
NV04_BIND_CONTEXT_DMA = (0x00000031)
NV04_CONTROL = (0x00000036)
NVOS54_FLAGS_NONE = (0x00000000)
NVOS54_FLAGS_IRQL_RAISED = (0x00000001)
NVOS54_FLAGS_LOCK_BYPASS = (0x00000002)
NVOS54_FLAGS_FINN_SERIALIZED = (0x00000004)
NV04_DUP_OBJECT = (0x00000037)
NV04_DUP_HANDLE_FLAGS_NONE = (0x00000000)
NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE = (0x00000001)
NV04_UPDATE_DEVICE_MAPPING_INFO = (0x00000038)
NV04_SHARE = (0x0000003E)
NV_DEVICE_ALLOCATION_SZNAME_MAXLEN = 128
NV_DEVICE_ALLOCATION_FLAGS_NONE = (0x00000000)
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY = (0x00000001)
NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = (0x00000002)
NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = (0x00000004)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE = (0x00000008)
NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE = (0x00000010)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET = (0x00000020)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT = (0x00000100)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k = (0x00000200)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k = (0x00000400)
NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS = (0x00000800)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED = (0x00000040)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED = (0x00001000)
NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE = (0x00002000)
NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT = (0x00004000)
NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET = (0x00008000)
NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES = (0x00000000)
NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE = (0x00000001)
NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES = (0x00000002)
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR = 0x00000000
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN = 0x00000001
NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS = 0x00000002
NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 = 3
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE = 0x1
NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE = 0x0
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES = 0x00000000
NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO = 0x00000001
NV_SWRUNLIST_QOS_INTR_NONE = 0x00000000
NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE = (0x00000000)
NV_VP_ALLOCATION_FLAGS_STATIC_UCODE = (0x00000001)
NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE = (0x00000002)
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO = (0x00000000)
NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO = (0x00000001)
NV04_ADD_VBLANK_CALLBACK = (0x0000003D)
NV_VASPACE_ALLOCATION_FLAGS_NONE = (0x00000000)
NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE = BIT(0)
NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS = BIT(1)
NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT = BIT(2)
NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED = BIT(3)
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS = BIT(4)
NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED = BIT(5)
NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING = BIT(6)
NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT = BIT(7)
NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS = BIT(8)
NV_VASPACE_ALLOCATION_FLAGS_IS_FLA = BIT(9)
NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL = BIT(10)
NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE = BIT(11)
NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET = BIT(12)
NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED = BIT(13)
NV_VASPACE_ALLOCATION_INDEX_GPU_NEW = 0x00
NV_VASPACE_ALLOCATION_INDEX_GPU_HOST = 0x01
NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL = 0x02
NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE = 0x03
NV_VASPACE_ALLOCATION_INDEX_GPU_FLA = 0x04
NV_VASPACE_ALLOCATION_INDEX_GPU_MAX = 0x05
NV_VASPACE_BIG_PAGE_SIZE_64K = (64 * 1024)
NV_VASPACE_BIG_PAGE_SIZE_128K = (128 * 1024)
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC = (0x00000000)
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC = (0x00000001)
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED = (0x00000002)
NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER = (0x00000003)
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS = (0x00000001)
NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL = (0x00000000)
NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT = (0x00000002)
NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT = (0x00000003)
NVC36F_CTRL_RESERVED = (0x00)
NVC36F_CTRL_GPFIFO = (0x01)
NVC36F_CTRL_EVENT = (0x02)
NVC36F_CTRL_INTERNAL = (0x03)
NVC36F_CTRL_CMD_NULL = (0xc36f0000)
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0108)
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x8)
NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES = 0x2
NVC36F_CTRL_CMD_GPFIFO_UPDATE_FAULT_METHOD_BUFFER = (0xc36f0109)
NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_MESSAGE_ID = (0x9)
NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = (0xc36f010a)
NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_MESSAGE_ID = (0xA)
NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION = (0xc36f0205)
NVC36F_CTRL_CMD_EVENT_SET_TRIGGER = (0xc36f0206)
NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN = (0xc36f0301)
NVC36F_CTRL_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_MESSAGE_ID = (0x1)
NVCB33_CTRL_RESERVED = (0x00)
NVCB33_CTRL_CONF_COMPUTE = (0x01)
NV_CONF_COMPUTE_CTRL_CMD_NULL = (0xcb330000)
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = (0xcb330101)
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE = 0
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV = 1
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX = 2
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV_SNP = 3
NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SNP_VTOM = 4
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE = 0
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM = 1
NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC = 2
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE = 0
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM = 1
NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD = 2
NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED = 0
NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED = 1
NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED = 2
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED = 0
NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED = 1
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE = 0
NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE = 1
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = (0xcb330104)
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE = (0xcb330105)
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_VIDMEM_SIZE = (0xcb330106)
NV_CONF_COMPUTE_CTRL_CMD_GPU_SET_VIDMEM_SIZE = (0xcb330107)
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS = (0xcb330108)
NV_CONF_COMPUTE_CTRL_CMD_GET_NUM_SUPPORTED_CC_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0x8)
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE = (0xcb330109)
NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE = 0x1000
NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE = 0x1400
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS_MESSAGE_ID = (0x9)
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT = (0xcb33010a)
NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE = 0x2000
NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE = 0x1000
NV_CONF_COMPUTE_NONCE_SIZE = 0x20
NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS_MESSAGE_ID = (0xA)
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = (0xcb33010b)
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xB)
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE = (0xcb33010c)
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED = 0
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED = 1
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED = 2
NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED = 3
NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID = (0xC)
NVA06C_CTRL_RESERVED = (0x00)
NVA06C_CTRL_GPFIFO = (0x01)
NVA06C_CTRL_INTERNAL = (0x02)
NVA06C_CTRL_CMD_NULL = (0xa06c0000)
NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = (0xa06c0101)
NVA06C_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
NVA06C_CTRL_CMD_BIND = (0xa06c0102)
NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID = (0x2)
NVA06C_CTRL_CMD_SET_TIMESLICE = (0xa06c0103)
NVA06C_CTRL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x3)
NVA06C_CTRL_CMD_GET_TIMESLICE = (0xa06c0104)
NVA06C_CTRL_GET_TIMESLICE_PARAMS_MESSAGE_ID = (0x4)
NVA06C_CTRL_CMD_PREEMPT = (0xa06c0105)
NVA06C_CTRL_PREEMPT_PARAMS_MESSAGE_ID = (0x5)
NVA06C_CTRL_CMD_PREEMPT_MAX_MANUAL_TIMEOUT_US = (1000000)
NVA06C_CTRL_CMD_GET_INFO = (0xa06c0106)
NVA06C_CTRL_GET_INFO_PARAMS_MESSAGE_ID = (0x6)
NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL = (0xa06c0107)
NVA06C_CTRL_INTERLEAVE_LEVEL_LOW = (0x00000000)
NVA06C_CTRL_INTERLEAVE_LEVEL_MEDIUM = (0x00000001)
NVA06C_CTRL_INTERLEAVE_LEVEL_HIGH = (0x00000002)
NVA06C_CTRL_SET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x7)
NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL = (0xa06c0108)
NVA06C_CTRL_GET_INTERLEAVE_LEVEL_PARAMS_MESSAGE_ID = (0x8)
NVA06C_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE = (0xa06c0109)
NVA06C_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS_MESSAGE_ID = (0x9)
NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS = (0xa06c010a)
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES = (NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES)
NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_MESSAGE_ID = (0xa)
NVA06C_CTRL_CMD_MAKE_REALTIME = (0xa06c0110)
NVA06C_CTRL_MAKE_REALTIME_PARAMS_MESSAGE_ID = (0x10)
NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE = (0xa06c0201)
NVA06C_CTRL_INTERNAL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
NVA06C_CTRL_CMD_INTERNAL_SET_TIMESLICE = (0xa06c0202)
NVA06C_CTRL_INTERNAL_SET_TIMESLICE_PARAMS_MESSAGE_ID = (0x2)
GMMU_FMT_MAX_LEVELS = 6
NV90F1_CTRL_RESERVED = (0x00)
NV90F1_CTRL_VASPACE = (0x01)
NV90F1_CTRL_CMD_NULL = (0x90f10000)
NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101)
NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1)
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102)
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2)
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0
NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103)
NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3)
NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104)
NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4)
NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105)
NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5)
NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106)
NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6)
NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107)
NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7)
NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108)
NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8)
NV0000_CTRL_RESERVED = (0x00)
NV0000_CTRL_SYSTEM = (0x01)
NV0000_CTRL_GPU = (0x02)
NV0000_CTRL_GSYNC = (0x03)
NV0000_CTRL_DIAG = (0x04)
NV0000_CTRL_EVENT = (0x05)
NV0000_CTRL_NVD = (0x06)
NV0000_CTRL_SWINSTR = (0x07)
NV0000_CTRL_PROC = (0x09)
NV0000_CTRL_SYNC_GPU_BOOST = (0x0A)
NV0000_CTRL_GPUACCT = (0x0B)
NV0000_CTRL_VGPU = (0x0C)
NV0000_CTRL_CLIENT = (0x0D)
NV0000_CTRL_OS_WINDOWS = (0x3F)
NV0000_CTRL_OS_MACOS = (0x3E)
NV0000_CTRL_OS_UNIX = (0x3D)
NV0000_CTRL_CMD_NULL = (0x0)
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE = (0xd01)
NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID = 0x00000000
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM = 0x00000001
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM = 0x00000002
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM = 0x00000003
NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC = 0x00000004
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO = (0xd02)
NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_INVALID = 0x00000000
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_PARENT = 0x00000001
NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO_INDEX_CLASSID = 0x00000002
NV0000_CTRL_CMD_CLIENT_GET_ACCESS_RIGHTS = (0xd03)
NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY = (0xd04)
NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE = (0xd05)
NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_CMD_CLIENT_SHARE_OBJECT = (0xd06)
NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS_MESSAGE_ID = (0x6)
NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES = (0xd07)
NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID = (0x7)
NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL = (0xd08)
NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID = (0x8)
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_STATE = (0x480)
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x80)
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_DISABLED = (0x00000000)
NV0000_CTRL_DIAG_GET_LOCK_METER_STATE_ENABLED = (0x00000001)
NV0000_CTRL_DIAG_LOCK_METER_MAX_TABLE_ENTRIES = (0x20000)
NV0000_CTRL_CMD_DIAG_SET_LOCK_METER_STATE = (0x481)
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_PARAMS_MESSAGE_ID = (0x81)
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_DISABLE = (0x00000000)
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_ENABLE = (0x00000001)
NV0000_CTRL_DIAG_SET_LOCK_METER_STATE_RESET = (0x00000002)
NV0000_CTRL_DIAG_LOCK_METER_ENTRY_FILENAME_LENGTH = (0xc)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA = (0x00000001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_FORCED = (0x00000002)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_SEMA_COND = (0x00000003)
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_SEMA = (0x00000004)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_API = (0x00000010)
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_API = (0x00000011)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ACQUIRE_GPUS = (0x00000020)
NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS = (0x00000021)
NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA = (0x00000100)
NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL = (0x00001000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET = (0x00002000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET = (0x00002001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX = (0x00002002)
NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX = (0x00002003)
NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP = (0x00003000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM = (0x00003001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM = (0x00003002)
NV0000_CTRL_DIAG_LOCK_METER_TAG_MAPMEM_DMA = (0x00003003)
NV0000_CTRL_DIAG_LOCK_METER_TAG_UNMAPMEM_DMA = (0x00003004)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC = (0x00004000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_MEM = (0x00004001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_DUP_OBJECT = (0x00004010)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CLIENT = (0x00005000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DEVICE = (0x00005001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE = (0x00005002)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_SUBDEVICE_DIAG = (0x00005003)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP = (0x00005004)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_DISP_CMN = (0x00005005)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL = (0x00005006)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_MPEG = (0x00005007)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_CHANNEL_DISP = (0x00005008)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_MEMORY = (0x00005009)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_FBMEM = (0x0000500A)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_OBJECT = (0x0000500B)
NV0000_CTRL_DIAG_LOCK_METER_TAG_FREE_EVENT = (0x0000500C)
NV0000_CTRL_DIAG_LOCK_METER_TAG_IDLE_CHANNELS = (0x00006000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_BIND_CTXDMA = (0x00007000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ALLOC_CTXDMA = (0x00007001)
NV0000_CTRL_DIAG_LOCK_METER_TAG_ISR = (0x0000F000)
NV0000_CTRL_DIAG_LOCK_METER_TAG_DPC = (0x0000F00F)
NV0000_CTRL_CMD_DIAG_GET_LOCK_METER_ENTRIES = (0x485)
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_MAX = (0x40)
NV0000_CTRL_DIAG_GET_LOCK_METER_ENTRIES_PARAMS_MESSAGE_ID = (0x85)
NV0000_CTRL_CMD_DIAG_PROFILE_RPC = (0x488)
NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS_MESSAGE_ID = (0x88)
NV0000_CTRL_PROFILE_RPC_CMD_DISABLE = (0x00000000)
NV0000_CTRL_PROFILE_RPC_CMD_ENABLE = (0x00000001)
NV0000_CTRL_PROFILE_RPC_CMD_RESET = (0x00000002)
NV0000_CTRL_CMD_DIAG_DUMP_RPC = (0x489)
NV0000_CTRL_DIAG_RPC_MAX_ENTRIES = (100)
NV0000_CTRL_DIAG_DUMP_RPC_PARAMS_MESSAGE_ID = (0x89)
NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x501)
NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000)
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001)
NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002)
NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS = (0x502)
NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = (0x201)
NV0000_CTRL_GPU_MAX_ATTACHED_GPUS = 32
NV0000_CTRL_GPU_INVALID_ID = (0xffffffff)
NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_CMD_GPU_GET_ID_INFO = (0x202)
NV0000_CTRL_GPU_MAX_SZNAME = 128
NV0000_CTRL_NO_NUMA_NODE = (-1)
NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_SLI_STATUS_OK = (0x00000000)
NV0000_CTRL_SLI_STATUS_OS_NOT_SUPPORTED = (0x00000002)
NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED = (0x00000040)
NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT = (0x00000001)
NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = (0x205)
NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE = (0x00000001)
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE = (0x00000001)
NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE = (0x00000001)
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE = (0x00000001)
NV0000_CTRL_GPU_ID_INFO_SOC_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_SOC_TRUE = (0x00000001)
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE = (0x00000000)
NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE = (0x00000001)
NV0000_CTRL_CMD_GPU_GET_INIT_STATUS = (0x203)
NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = (0x204)
NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = (0x214)
NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID = (0x14)
NV0000_CTRL_CMD_GPU_GET_PCI_INFO = (0x21b)
NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1B)
NV0000_CTRL_CMD_GPU_ATTACH_IDS = (0x215)
NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS = (0x0000ffff)
NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID = (0x15)
NV0000_CTRL_CMD_GPU_DETACH_IDS = (0x216)
NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS = (0x0000ffff)
NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID = (0x16)
NV0000_CTRL_CMD_GPU_GET_VIDEO_LINKS = (0x219)
NV0000_CTRL_GPU_MAX_VIDEO_LINKS = 8
NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS_MESSAGE_ID = (0x19)
NV0000_CTRL_CMD_GPU_GET_SVM_SIZE = (0x240)
NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID = (0x40)
NV0000_CTRL_CMD_GPU_GET_UUID_INFO = (0x274)
NV0000_GPU_MAX_GID_LENGTH = (0x00000100)
NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID = (0x74)
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII = (0x00000000)
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY = (0x00000002)
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 = (0x00000000)
NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 = (0x00000001)
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = (0x275)
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID = (0x75)
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII = (0x00000000)
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY = (0x00000002)
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 = (0x00000000)
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 = (0x00000001)
NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE = (0x278)
NV0000_CTRL_GPU_DRAIN_STATE_DISABLED = (0x00000000)
NV0000_CTRL_GPU_DRAIN_STATE_ENABLED = (0x00000001)
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE = (0x00000001)
NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE = (0x00000002)
NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x78)
NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = (0x279)
NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID = (0x79)
NV0000_CTRL_CMD_GPU_DISCOVER = (0x27a)
NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = (0x27b)
NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID = (0x7B)
NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE = (0x00000001)
NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT = (0x281)
NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID = (0x81)
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA = 0x00000175
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN = 6
NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT = 5
NV0000_CTRL_CMD_GPU_LEGACY_CONFIG = (0x282)
NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID = (0x82)
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET = (0x00000001)
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX = (0x00000002)
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX = (0x00000003)
NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED = (0x00000004)
NV0000_CTRL_CMD_IDLE_CHANNELS = (0x283)
NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x83)
NV0000_CTRL_GPU_IMAGE_TYPE_GSP = (0x00000001)
NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG = (0x00000002)
NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE = (0x00000003)
NV0000_CTRL_CMD_PUSH_UCODE_IMAGE = (0x285)
NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID = (0x85)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_FULL = (0x00)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_OFF = (0x01)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_MIN = (0x02)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_HALF = (0x03)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_3QUARTER = (0x04)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_LINK_COUNT = (0x05)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_UNSET = (0x00)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_NODE = (0x01)
NV0000_CTRL_CMD_GPU_NVLINK_BW_MODE_SCOPE_PER_GPU = (0x02)
NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE = (0x286)
NV0000_CTRL_GPU_SET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x86)
NV0000_CTRL_CMD_GPU_GET_NVLINK_BW_MODE = (0x287)
NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS_MESSAGE_ID = (0x87)
NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = (0x288)
NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES = 256
NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID = (0x88)
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = (0x289)
NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID = (0x89)
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = (0x290)
NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID = (0x90)
NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE = (0xb01)
NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED = (0x00000000)
NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED = (0x00000001)
NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = (0xb02)
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO = (0xb03)
NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS = (0xb04)
NV0000_GPUACCT_PID_MAX_COUNT = 4000
NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA = (0xb05)
NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = (0x301)
NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_GSYNC_INVALID_ID = (0xffffffff)
NV0000_CTRL_CMD_GSYNC_GET_ID_INFO = (0x302)
NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_NVD_DUMP_COMPONENT_SYS = (0x400)
NV0000_CTRL_NVD_DUMP_COMPONENT_NVLOG = (0x800)
NV0000_CTRL_NVD_DUMP_COMPONENT_RESERVED = (0xB00)
NV0000_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x601)
NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_NVD_MAX_DUMP_SIZE = (1000000)
NV0000_CTRL_CMD_NVD_GET_DUMP = (0x602)
NV0000_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2)
NV0000_NVD_CPU_TIME_CLK_ID_DEFAULT = (0x00000000)
NV0000_NVD_CPU_TIME_CLK_ID_OSTIME = (0x00000001)
NV0000_NVD_CPU_TIME_CLK_ID_TSC = (0x00000002)
NV0000_NVD_CPU_TIME_CLK_ID_PLATFORM_API = (0x00000003)
NV0000_CTRL_CMD_NVD_GET_TIMESTAMP = (0x603)
NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO = (0x604)
NV0000_CTRL_NVD_MAX_RUNTIME_SIZES = (16)
NV0000_CTRL_NVD_SIGNATURE_SIZE = (4)
NV0000_CTRL_NVD_MAX_BUFFERS = (3840)
NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_NVD_RUNTIME_SIZE_UNUSED = (0)
NV0000_CTRL_NVD_RUNTIME_SIZE_INT = (1)
NV0000_CTRL_NVD_RUNTIME_SIZE_LONG_LONG = (2)
NV0000_CTRL_NVD_RUNTIME_SIZE_STRING = (3)
NV0000_CTRL_NVD_RUNTIME_SIZE_PTR = (4)
NV0000_CTRL_NVD_RUNTIME_SIZE_CHAR = (5)
NV0000_CTRL_NVD_RUNTIME_SIZE_FLOAT = (6)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DISABLE = (0x00000000)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_BUFFER_SIZE_DEFAULT = (0x00000004)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_NONE = (0x00000000)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32 = (0x00000001)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_64 = (0x00000002)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_TIMESTAMP_32_DIFF = (0x00000003)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_INFO_PRINTFLAGS_INITED_YES = (0x00000001)
NV0000_CTRL_CMD_NVD_GET_NVLOG_BUFFER_INFO = (0x605)
NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_PAUSE_YES = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_DISABLED_YES = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_RING = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_TYPE_NOWRAP = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_EXPANDABLE_YES = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_NONPAGED_YES = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_NONE = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_STATE = (0x00000001)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_LOCKING_FULL = (0x00000002)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_NO = (0x00000000)
NV0000_CTRL_NVD_NVLOG_BUFFER_INFO_FLAGS_OCA_YES = (0x00000001)
NV0000_CTRL_CMD_NVD_GET_NVLOG = (0x606)
NV0000_CTRL_NVLOG_MAX_BLOCK_SIZE = (4000)
NV0000_CTRL_NVD_GET_NVLOG_PARAMS_MESSAGE_ID = (0x6)
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT = (0x607)
NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES = 200
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_TEST = 0
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GRSTATUS = 1
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_GPCSTATUS = 2
NV0000_CTRL_CMD_NVD_RCERR_RPT_TYPE_MMU_FAULT_STATUS = 3
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY = 0x00000000
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_OVERFLOWED = 0x00000001
NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_MAX_PSEDO_REG = 0x0000000f
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_FIRST = 0x00000001
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_POS_LAST = 0x00000002
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID = 0x00000004
NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID = 0x00000008
TPC_REG_ATTR = lambda gpcId,tpcId: ((gpcId << 8) | (tpcId))
ROP_REG_ATTR = lambda gpcId,ropId: ((gpcId << 8) | (ropId))
SM_REG_ATTR = lambda gpcId,tpcId,smId: ((((gpcId) << 16) | ((tpcId) << 8)) | (smId))
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_PROCESS_ID = 0x00000000
NV0000_CTRL_CMD_NVD_RCERR_RPT_ANY_OWNER_ID = 0xFFFFFFFF
NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS_MESSAGE_ID = (0x7)
NV0000_CTRL_CMD_NVD_GET_DPC_ISR_TS = (0x608)
NV0000_CTRL_NVD_GET_DPC_ISR_TS_PARAMS_MESSAGE_ID = (0x8)
NV0000_CTRL_SET_SUB_PROCESS_ID_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_DISABLE_SUB_PROCESS_USERD_ISOLATION_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_SET_SUB_PROCESS_ID = (0x901)
NV0000_CTRL_CMD_DISABLE_SUB_PROCESS_USERD_ISOLATION = (0x902)
NV0000_SYNC_GPU_BOOST_MAX_GROUPS = (0x10)
NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID = 0xFFFFFFFF
NV0000_CTRL_CMD_SYNC_GPU_BOOST_INFO = (0xa01)
NV0000_SYNC_GPU_BOOST_INFO_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_CREATE = (0xa02)
NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_DESTROY = (0xa03)
NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = (0xa04)
NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = (0x1f0)
NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID = (0xF0)
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = (0x101)
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID = (0x1)
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = (0x102)
NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY = 0xF
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY = 0xA
NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL = 0x0
NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL = 0x4
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY = 0x6
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY = 0x0
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL = 0x7
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL = 0xA
NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL = 0x9
NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN = (0x00000000)
NV0000_CTRL_SYSTEM_CPU_TYPE_P5 = (0x00000001)
NV0000_CTRL_SYSTEM_CPU_TYPE_P55 = (0x00000002)
NV0000_CTRL_SYSTEM_CPU_TYPE_P6 = (0x00000003)
NV0000_CTRL_SYSTEM_CPU_TYPE_P2 = (0x00000004)
NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC = (0x00000005)
NV0000_CTRL_SYSTEM_CPU_TYPE_CELA = (0x00000006)
NV0000_CTRL_SYSTEM_CPU_TYPE_P3 = (0x00000007)
NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 = (0x00000008)
NV0000_CTRL_SYSTEM_CPU_TYPE_P4 = (0x00000009)
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 = (0x00000010)
NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H = (0x00000011)
NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM = (0x00000012)
NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM = (0x00000013)
NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR = (0x00000014)
NV0000_CTRL_SYSTEM_CPU_TYPE_K5 = (0x00000030)
NV0000_CTRL_SYSTEM_CPU_TYPE_K6 = (0x00000031)
NV0000_CTRL_SYSTEM_CPU_TYPE_K62 = (0x00000032)
NV0000_CTRL_SYSTEM_CPU_TYPE_K63 = (0x00000033)
NV0000_CTRL_SYSTEM_CPU_TYPE_K7 = (0x00000034)
NV0000_CTRL_SYSTEM_CPU_TYPE_K8 = (0x00000035)
NV0000_CTRL_SYSTEM_CPU_TYPE_K10 = (0x00000036)
NV0000_CTRL_SYSTEM_CPU_TYPE_K11 = (0x00000037)
NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN = (0x00000038)
NV0000_CTRL_SYSTEM_CPU_TYPE_C6 = (0x00000060)
NV0000_CTRL_SYSTEM_CPU_TYPE_C62 = (0x00000061)
NV0000_CTRL_SYSTEM_CPU_TYPE_GX = (0x00000070)
NV0000_CTRL_SYSTEM_CPU_TYPE_M1 = (0x00000071)
NV0000_CTRL_SYSTEM_CPU_TYPE_M2 = (0x00000072)
NV0000_CTRL_SYSTEM_CPU_TYPE_MGX = (0x00000073)
NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE = (0x00000080)
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 = (0x00000090)
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 = (0x00000091)
NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 = (0x00000092)
NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN = (0x00000093)
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN = (0xA0000000)
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 = (0xA0000009)
NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 = (0xA000000F)
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 = (0xA0001000)
NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 = (0xA0002000)
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC = (0xA00FF000)
NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC = (0xA00FF001)
NV0000_CTRL_SYSTEM_CPU_CAP_MMX = (0x00000001)
NV0000_CTRL_SYSTEM_CPU_CAP_SSE = (0x00000002)
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW = (0x00000004)
NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 = (0x00000008)
NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE = (0x00000010)
NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING = (0x00000020)
NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC = (0x00000040)
NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO = (0x00000080)
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND = (0x00000100)
NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT = (0x00000200)
NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT = (0x00000400)
NV0000_CTRL_SYSTEM_CPU_CAP_CMOV = (0x00000800)
NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH = (0x00001000)
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 = (0x00002000)
NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 = (0x00004000)
NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 = (0x00008000)
NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE = (0x00010000)
NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 = (0x00020000)
NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 = (0x00040000)
NV0000_CTRL_SYSTEM_CPU_CAP_AVX = (0x00080000)
NV0000_CTRL_SYSTEM_CPU_CAP_ERMS = (0x00100000)
NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO = (0x104)
NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH = (0x0000020)
NV0000_SYSTEM_CHIPSET_INVALID_ID = (0xffff)
NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO = (0x00000000)
NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES = (0x00000001)
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT = (0x107)
NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID = (0x7)
NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES = (0x109)
NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID = (0x9)
NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST = (0x108)
NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE = (32)
NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x8)
NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT = (0x110)
NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID = (0x10)
NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE = (0x00000002)
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID = (0x00000003)
NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK = (0x00000004)
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF = (0x00000002)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI = (0x00000003)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL = (0x00000004)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT = (0x5)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS = (0x00000001)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF = (0x00000002)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI = (0x00000003)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL = (0x00000004)
NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT = (0x5)
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE = (0x111)
NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID = (0x11)
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP = (0x000000)
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC = (0x000001)
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA = (0x000002)
NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC = (0x000003)
NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL = (0x121)
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE = 512
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET = (0x00000000)
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET = (0x00000001)
NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID = (0x21)
NV0000_CTRL_SYSTEM_HWBC_INVALID_ID = (0xFFFFFFFF)
NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO = (0x124)
NV0000_CTRL_SYSTEM_MAX_HWBCS = (0x00000080)
NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID = (0x24)
NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL = (0x122)
NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID = (0x22)
NV0000_CTRL_CMD_SYSTEM_GPS_INVALID = (0xFFFF)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT = (0x0000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC = (0x0001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC = (0x0002)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS = (0x0003)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS = (0x0004)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC = (0x0005)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC = (0x0006)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE = (0x0007)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE = (0x0008)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT = (0x0009)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT = (0x000A)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE = (0x000B)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE = (0x000C)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER = (0x0100)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER = (0x0101)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET = (0x0102)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET = (0x0103)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD = (0x0104)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD = (0x0105)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET = (0x0106)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET = (0x0107)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT = (0x0108)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST = (0x0109)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST = (0x010A)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE = (0x010B)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE = (0x010C)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO = (0x010D)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER = (0x0200)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA = (0x0201)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE = (0x0202)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG = (0x0203)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL = (0x0204)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN = (0x0205)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE = (0x0206)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS = (0x0210)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP = (0x0220)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA = (0x0221)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE = (0x0222)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE = (0x0240)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP = (0x0241)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN = (0x0242)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX = (0x0243)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION = (0x0244)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE = (0x0250)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE = (0x0251)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA = (0x0252)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA = (0x0253)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT = (0x0321)
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID = (0xFFFF)
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM = (0x0000)
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU = lambda i: (0x0100+((i)%0x100))
NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU = lambda i: (0x0200+((i)%0x100))
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID = (0x80000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS = (0x00000004)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC = (0x00000008)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC = (0x00000010)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB = (0x00000020)
NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS = (0x00000040)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT = (0x00000003)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 = (0x00000004)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 = (0x00000005)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL = (0x123)
NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX = (16)
NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x23)
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = (0x127)
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED = 1024
NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS = 8
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER = 0xffffffff
NV0000_CTRL_P2P_CAPS_INDEX_READ = 0
NV0000_CTRL_P2P_CAPS_INDEX_WRITE = 1
NV0000_CTRL_P2P_CAPS_INDEX_NVLINK = 2
NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS = 3
NV0000_CTRL_P2P_CAPS_INDEX_PROP = 4
NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK = 5
NV0000_CTRL_P2P_CAPS_INDEX_PCI = 6
NV0000_CTRL_P2P_CAPS_INDEX_C2C = 7
NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 = 8
NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0x27)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE = (0x00000001)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE = (0x00000000)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE = (0x00000001)
NV0000_P2P_CAPS_STATUS_OK = (0x00)
NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED = (0x01)
NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED = (0x02)
NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED = (0x03)
NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY = (0x04)
NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED = (0x05)
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = (0x12b)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID = (0x2B)
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = (0x13a)
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID = (0x3A)
NV0000_CTRL_CMD_SYSTEM_GPS_CTRL = (0x12a)
NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID = (0x2A)
NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000)
NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT = (0x00000002)
NV0000_CTRL_GPS_INPUT_SENSOR_INDEX = (0x00000000)
NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT = (0x00000000)
NV0000_CTRL_GPS_RESULT_MIN_LIMIT = (0x00000001)
NV0000_CTRL_GPS_RESULT_MAX_LIMIT = (0x00000002)
NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE = (0x00000003)
NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT = (0x00000003)
NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016)
NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017)
NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018)
NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019)
NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A)
NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL = (0x00000001)
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE = (0x00000000)
NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI = (0x0000001B)
NV0000_CTRL_GPS_INPUT_ACPI_CMD = (0x00000000)
NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN = (0x00000001)
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 = (0x00000000)
NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 = (0x00000001)
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000)
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001)
NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002)
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ = (0x00000000)
NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C)
NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026)
NV0000_CTRL_GPS_INPUT_TEMP_PERIOD = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027)
NV0000_CTRL_GPS_RESULT_TEMP_PERIOD = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028)
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP = (0x00000000)
NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029)
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP = (0x00000000)
NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A)
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B)
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C)
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D)
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E)
NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F)
NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001)
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045)
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046)
NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0)
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047)
NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0)
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM = (0x00000048)
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX = (0)
NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1)
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM = (0x00000049)
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX = (0)
NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX = (2)
NV0000_CTRL_GPS_PPM_INDEX_MAXPERF = (0)
NV0000_CTRL_GPS_PPM_INDEX_BALANCED = (1)
NV0000_CTRL_GPS_PPM_INDEX_QUIET = (2)
NV0000_CTRL_GPS_PPM_INDEX_INVALID = (0xFF)
NV0000_CTRL_GPS_PPM_MASK_INVALID = (0)
NV0000_CTRL_GPS_CMD_PS_STATUS_OFF = (0)
NV0000_CTRL_GPS_CMD_PS_STATUS_ON = (1)
NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS = (0x129)
GPS_MAX_COUNTERS_PER_BLOCK = 32
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID = (0x29)
NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS = (0x12c)
NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2C)
NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS = (0x12e)
NV0000_CTRL_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x2E)
GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288
NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID = (0x2D)
NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI = (0x12d)
NV0000_CTRL_SYSTEM_PARAM_TGPU = (0x00000000)
NV0000_CTRL_SYSTEM_PARAM_PDTS = (0x00000001)
NV0000_CTRL_SYSTEM_PARAM_SFAN = (0x00000002)
NV0000_CTRL_SYSTEM_PARAM_SKNT = (0x00000003)
NV0000_CTRL_SYSTEM_PARAM_CPUE = (0x00000004)
NV0000_CTRL_SYSTEM_PARAM_TMP1 = (0x00000005)
NV0000_CTRL_SYSTEM_PARAM_TMP2 = (0x00000006)
NV0000_CTRL_SYSTEM_PARAM_CTGP = (0x00000007)
NV0000_CTRL_SYSTEM_PARAM_PPMD = (0x00000008)
NV0000_CTRL_SYSTEM_PARAM_COUNT = (0x00000009)
NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD = (0x130)
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID = (0x30)
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS = (0x00000000)
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG = (0x00000001)
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS = (0x00000002)
NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY = (0x00000003)
NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS = (0x131)
NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID = (0x31)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL = (0x00000001)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ = (0x00000002)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH = (0x00000004)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF = (0x00000010)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG = (0x00000020)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS = (0x00000040)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER = (0x00000080)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP = (0x00000100)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI = (0x00000200)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR = (0x00000400)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK = (0x00000800)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL = (0x00001000)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC = (0x00002000)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM = (0x00004000)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS = (0x00008000)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE = (0x00010000)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY = (0x00020000)
NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA = (0x12f)
NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE = 64
NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x2F)
NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA = (0x132)
NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x32)
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE = 256
NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO = (0x133)
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID = (0x33)
NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS = (0x134)
NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID = (0x34)
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED = 0
NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED = 1
NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS = (0x135)
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID = (0x35)
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG = (0x00000001)
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG = (0x00000002)
NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG = (0x00000004)
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = (0x136)
NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID = (0x36)
NV0000_CTRL_VGPU_GET_VGPU_VERSION = (0x137)
NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x37)
NV0000_CTRL_VGPU_SET_VGPU_VERSION = (0x138)
NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID = (0x38)
NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID = (0x139)
NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID = (0x39)
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO = (0x13b)
NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE = 1
NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE = 32
NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT_MESSAGE_ID = (0x48)
NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID = (0x3B)
CONTROLLER_FILTER_TYPE_EMWA = 0
CONTROLLER_FILTER_TYPE_MOVING_MAX = 1
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE = 2
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE = 3
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CASE = 4
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_CASE = 5
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL_CASE = 6
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED = (0x00000000)
NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002)
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES = 1
NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO = 0
NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION = (0x00000200)
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED = (0x00000000)
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_STATIC_CONFIG_TABLES = (0x00000001)
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS = (0x00000002)
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DC_SYSTEM_POWER_LIMITS_TABLE = (0x00000008)
NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_CPU_TDP_LIMIT_CONTROL = (0x00000009)
NVPCF0100_CTRL_CONFIG_2X_BUFF_SIZE_MAX = (255)
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT = (0x13c)
NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID = (0x3C)
NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO = (0x13d)
NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID = (0x3D)
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 = (0x13e)
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID = (0x3E)
NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL = (0x13f)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID = (0x3F)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET = (0x00000000)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET = (0x00000001)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE = (0x00000000)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE = (0x00000001)
NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL = (0x140)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID = (0x40)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID = (0xFFFF)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT = (0x0000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC = (0x0001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC = (0x0002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS = (0x0003)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS = (0x0004)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC = (0x0005)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC = (0x0006)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE = (0x0007)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE = (0x0008)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT = (0x0009)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT = (0x000A)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE = (0x000B)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE = (0x000C)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER = (0x0100)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER = (0x0101)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET = (0x0102)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET = (0x0103)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD = (0x0104)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD = (0x0105)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET = (0x0106)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET = (0x0107)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT = (0x0108)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST = (0x0109)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST = (0x010A)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE = (0x010B)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE = (0x010C)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO = (0x010D)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS = (0x010E)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER = (0x0200)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA = (0x0201)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE = (0x0202)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG = (0x0203)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL = (0x0204)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN = (0x0205)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE = (0x0206)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS = (0x0210)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP = (0x0220)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA = (0x0221)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE = (0x0222)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE = (0x0240)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP = (0x0241)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN = (0x0242)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX = (0x0243)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION = (0x0244)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT = (0x0245)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE = (0x0250)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE = (0x0251)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA = (0x0252)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA = (0x0253)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK = (0x0320)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT = (0x0321)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID = (0xFFFF)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM = (0x0000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU = lambda i: (0x0100+((i)%0x100))
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU = lambda i: (0x0200+((i)%0x100))
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID = (0x80000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE = (0xFFFFFFFF)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS = (0x00000004)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC = (0x00000008)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC = (0x00000010)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB = (0x00000020)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS = (0x00000040)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING = (0x00000002)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT = (0x00000003)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 = (0x00000004)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 = (0x00000005)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM = (0x00000006)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM = (0x00000007)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF = (0x00000000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON = (0x00000001)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL = (0x141)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX = (16)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID = (0x41)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL = (0x142)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID = (0x42)
NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION = (0x00010000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT = (0x00000002)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT = (0x00000002)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE = (0x00000003)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT = (0x00000003)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA = (0x00000004)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA = (0x00000005)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA = (0x00000006)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA = (0x00000007)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA = (0x00000008)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA = (0x00000009)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000A)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA = (0x0000000B)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000C)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA = (0x0000000D)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS = (0x00000016)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS = (0x00000017)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM = (0x00000018)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM = (0x00000019)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR = (0x0000001A)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI = (0x0000001B)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ = (0x00000002)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO = (0x0000001C)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD = (0x00000026)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD = (0x00000027)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR = (0x00000028)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR = (0x00000029)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES = (0x0000002A)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES = (0x0000002B)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS = (0x0000002C)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS = (0x0000002D)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE = (0x0000002E)
NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE = (0x0000002F)
NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS = (0x00000044)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 = (0x00000001)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS = (0x00000045)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 = (0x00000000)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT = (0x00000046)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT = (0x00000047)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM = (0x00000048)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK = (1)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM = (0x00000049)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX = (2)
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF = (0)
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED = (1)
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET = (2)
NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID = (0xFF)
NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF = (0)
NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON = (1)
PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK = 32
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS = (0x146)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x46)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS = (0x147)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS_PARAMS_MESSAGE_ID = (0x47)
PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE = 288
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID = (0x43)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI = (0x143)
NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR = (0x00008000)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA = (0x144)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE = 64
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID = (0x44)
NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA = (0x145)
NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID = (0x45)
NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE = (0x3d02)
NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH = (0x00000001)
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE = (0x00000002)
NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE = (0x00000003)
NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR = (0x3d04)
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD = (0x3d05)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE = (0x00000000)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE = (0x00000001)
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD = (0x3d06)
NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID = (0x6)
NV0000_CTRL_CMD_OS_GET_GPU_INFO = (0x3d07)
NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO = (0x3d08)
NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE = 64
NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID = (0x8)
NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST = (0x3d09)
NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD = (0x3d0a)
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE = NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE
NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID = (0xA)
NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD = (0x3d0b)
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS = 512
NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID = (0xB)
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD = (0x3d0c)
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS = 128
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE = 0
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM = 1
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM = 2
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC = 3
NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC = 4
NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID = (0xC)
NV0000_CTRL_CMD_VGPU_CREATE_DEVICE = (0xc02)
NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS_MESSAGE_ID = (0x2)
NV0000_CTRL_CMD_VGPU_GET_INSTANCES = (0xc03)
NV0000_CTRL_VGPU_GET_INSTANCES_PARAMS_MESSAGE_ID = (0x3)
NV0000_CTRL_CMD_VGPU_DELETE_DEVICE = (0xc04)
NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS_MESSAGE_ID = (0x4)
NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS = (0xc05)
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID = (0x5)
NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE = (0x206)
NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID = (0x6)
NV0080_CTRL_RESERVED = (0x00)
NV0080_CTRL_BIF = (0x01)
NV0080_CTRL_GPU = (0x02)
NV0080_CTRL_CLK = (0x10)
NV0080_CTRL_GR = (0x11)
NV0080_CTRL_CIPHER = (0x12)
NV0080_CTRL_FB = (0x13)
NV0080_CTRL_HOST = (0x14)
NV0080_CTRL_VIDEO = (0x15)
NV0080_CTRL_FIFO = (0x17)
NV0080_CTRL_DMA = (0x18)
NV0080_CTRL_PERF = (0x19)
NV0080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0x99)
NV0080_CTRL_MSENC = (0x1B)
NV0080_CTRL_BSP = (0x1C)
NV0080_CTRL_RC = (0x1D)
NV0080_CTRL_OS_UNIX = (0x1E)
NV0080_CTRL_NVJPG = (0x1F)
NV0080_CTRL_INTERNAL = (0x20)
NV0080_CTRL_NVLINK = (0x21)
NV0080_CTRL_CMD_NULL = (0x800000)
NV0080_CTRL_CMD_BIF_RESET = (0x800102)
NV0080_CTRL_BIF_RESET_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET = 0x1
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR = 0x2
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL = 0x3
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE = 0x4
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE = 0x5
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX = 0x6
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER = 0x7
NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE = 0x8
NV0080_CTRL_CMD_BIF_SET_ASPM_FEATURE = (0x800104)
NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS_MESSAGE_ID = (0x4)
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_ENABLED = 0x000000001
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L0S_DISABLED = 0x000000000
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED = 0x000000001
NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED = 0x000000000
NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE = (0x800105)
NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID = (0x5)
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK = (0x800106)
NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK_PARAMS_MESSAGE_ID = (0x6)
NV0080_CTRL_CMD_BSP_GET_CAPS = (0x801c01)
NV0080_CTRL_BSP_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_BSP_CAPS_TBL_SIZE = 8
NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = (0x801c02)
NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2_MESSAGE_ID = (0x2)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_FALSE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_VALID_TRUE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_FALSE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_TRUE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ENCRYPTED_NOT_SUPPORTED = (0x00000002)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_PEER_MEMORY = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_NONE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_1 = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_2 = (0x00000002)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_COMPTAGS_4 = (0x00000004)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_FALSE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_TRUE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_GPU_CACHED_NOT_SUPPORTED = (0x00000002)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_WRITE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_READ_ONLY = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_WRITE_ONLY = (0x00000002)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_SHADER_ACCESS_NOT_SUPPORTED = (0x00000003)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_FALSE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_READ_ONLY_TRUE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_DISABLE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ATOMIC_ENABLE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_DISABLE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_ACCESS_COUNTING_ENABLE = (0x00000001)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_FALSE = (0x00000000)
NV0080_CTRL_DMA_PTE_INFO_PARAMS_FLAGS_PRIVILEGED_TRUE = (0x00000001)
NV0080_CTRL_CMD_DMA_GET_PTE_INFO = (0x801801)
NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS = 5
NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_CMD_DMA_SET_PTE_INFO = (0x80180a)
NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS = 5
NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID = (0xA)
NV0080_CTRL_CMD_DMA_FILL_PTE_MEM = (0x801802)
NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_CMD_DMA_FLUSH = (0x801805)
NV0080_CTRL_DMA_FLUSH_PARAMS_MESSAGE_ID = (0x5)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_DISABLE = (0x00000000)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_ENABLE = (0x00000001)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_DISABLE = (0x00000000)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_COMPTAG_ENABLE = (0x00000001)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_DISABLE = (0x00000000)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_FB_ENABLE = (0x00000001)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_SYSMEM = (0x00000001)
NV0080_CTRL_DMA_FLUSH_TARGET_UNIT_L2_INVALIDATE_PEERMEM = (0x00000002)
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = (0x801806)
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS = (16)
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_MESSAGE_ID = (0x6)
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS_WITH_VA_RANGE_LO = 0x1
NV0080_CTRL_CMD_DMA_GET_PDE_INFO = (0x801809)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002)
NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS = 5
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID = (0x9)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_VIDEO_MEMORY = (0x00000000)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY = (0x00000001)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY = (0x00000002)
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_FULL = 1
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_HALF = 2
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER = 3
NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH = 4
NV0080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x80180c)
NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0xC)
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_FALSE = (0x00000000)
NV0080_CTRL_DMA_INVALIDATE_TLB_ALL_TRUE = (0x00000001)
NV0080_CTRL_CMD_DMA_GET_CAPS = (0x80180d)
NV0080_CTRL_DMA_CAPS_TBL_SIZE = 8
NV0080_CTRL_DMA_GET_CAPS_PARAMS_MESSAGE_ID = (0xD)
NV0080_CTRL_CMD_DMA_SET_VA_SPACE_SIZE = (0x80180e)
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_MESSAGE_ID = (0xE)
NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_MAX = (0xFFFFFFFFFFFFFFFF)
NV0080_CTRL_CMD_DMA_UPDATE_PDE_2 = (0x80180f)
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_INVALID = (0x00000000)
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_VIDEO_MEMORY = (0x00000001)
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_COHERENT_MEMORY = (0x00000002)
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_APERTURE_SYSTEM_NON_COHERENT_MEMORY = (0x00000003)
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_SMALL = 0
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX_BIG = 1
NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE = 2
NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_MESSAGE_ID = (0xF)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_FALSE = (0x00000000)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FLUSH_PDE_CACHE_TRUE = (0x00000001)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_FALSE = (0x00000000)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_FORCE_OVERRIDE_TRUE = (0x00000001)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_FULL = (0x00000000)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_HALF = (0x00000001)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_QUARTER = (0x00000002)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_PDE_SIZE_EIGHTH = (0x00000003)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_FALSE = (0x00000000)
NV0080_CTRL_DMA_UPDATE_PDE_2_FLAGS_SPARSE_TRUE = (0x00000001)
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE = (0x801810)
NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS_MESSAGE_ID = (0x10)
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE = (0x801812)
NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_MESSAGE_ID = (0x12)
NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY = (0x801813)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x13)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_VIDMEM = (0x00000000)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_COH = (0x00000001)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_APERTURE_SYSMEM_NONCOH = (0x00000002)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_FALSE = (0x00000000)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_PRESERVE_PDES_TRUE = (0x00000001)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_FALSE = (0x00000000)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_ALL_CHANNELS_TRUE = (0x00000001)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_FALSE = (0x00000000)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_IGNORE_CHANNEL_BUSY_TRUE = (0x00000001)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_FALSE = (0x00000000)
NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_FLAGS_EXTEND_VASPACE_TRUE = (0x00000001)
NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY = (0x801814)
NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_MESSAGE_ID = (0x14)
NV0080_CTRL_CMD_FB_GET_CAPS = (0x801301)
NV0080_CTRL_FB_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_FB_CAPS_TBL_SIZE = 3
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO = (0x801306)
NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS_MESSAGE_ID = (0x6)
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN = 0
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_SYSMEM = 1
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_FBMEM = 2
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_LEGACY = 0
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO1 = 1
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_1TO4 = 2
NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_POLICY_RAWMODE = 3
NV0080_CTRL_CMD_FB_GET_CAPS_V2 = (0x801307)
NV0080_CTRL_FB_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x7)
NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY = (0x801308)
NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID = (0x8)
NV0080_CTRL_CMD_FIFO_GET_CAPS = (0x801701)
NV0080_CTRL_FIFO_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_FIFO_CAPS_TBL_SIZE = 2
NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = (0x801707)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS = (0x00000000)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VLD = (0x00000001)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_VIDEO = (0x00000002)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_MPEG = (0x00000003)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_CAPTURE = (0x00000004)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_DISPLAY = (0x00000005)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_ENCRYPTION = (0x00000006)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_POSTPROCESS = (0x00000007)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL = (0x00000008)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PM = (0x00000009)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COMPUTE_PREEMPT = (0x0000000a)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT = (0x0000000b)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL = (0x0000000c)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL = (0x0000000d)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB = (0x0000000e)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV = (0x0000000f)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH = (0x00000010)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BUNDLE_CB = (0x00000011)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL_GLOBAL = (0x00000012)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ATTRIBUTE_CB = (0x00000013)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV_CB_GLOBAL = (0x00000014)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_POOL = (0x00000015)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK = (0x00000016)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT = (0x00000017)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP = (0x00000018)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP = (0x00000019)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = (0x0000001a)
NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x7)
NV0080_CTRL_CMD_FIFO_RUNLIST_GROUP_CHANNELS = (0x801709)
NV0080_CTRL_FIFO_RUNLIST_GROUP_MAX_CHANNELS = (8)
NV0080_CTRL_CMD_FIFO_RUNLIST_DIVIDE_TIMESLICE = (0x80170b)
NV0080_CTRL_FIFO_RUNLIST_MAX_TIMESLICE_DIVISOR = (12)
NV0080_CTRL_CMD_FIFO_PREEMPT_RUNLIST = (0x80170c)
NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = (0x80170d)
NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS_MESSAGE_ID = (0xD)
NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE = (0x80170e)
NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0xE)
NV0080_CTRL_FIFO_GET_CHANNELLIST_INVALID_CHANNEL = (0xffffffff)
NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES = (0x80170f)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_MESSAGE_ID = (0xF)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEINMICROSECONDS = (0x00000000)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEINMICROSECONDS = (0x00000001)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_ENGINETIMESLICEDISABLE = (0x00000002)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PBDMATIMESLICEDISABLE = (0x00000003)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_INVALIDATE_PDB_TARGET = (0x00000004)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT = (0x00000005)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_NOOP = (0x00000007)
NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_RESETENGINECONTEXT_NOPREEMPT = (0x00000008)
NV0080_CTRL_CMD_FIFO_STOP_RUNLIST = (0x801711)
NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_MESSAGE_ID = (0x11)
NV0080_CTRL_CMD_FIFO_START_RUNLIST = (0x801712)
NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_MESSAGE_ID = (0x12)
NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 = (0x801713)
NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x13)
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS = (0x801714)
NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS_MAX_CHANNELS = 4096
NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS_MESSAGE_ID = (0x14)
NV0080_CTRL_CMD_GPU_GET_CLASSLIST = (0x800201)
NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES = (0x800280)
NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS_MESSAGE_ID = (0x80)
NV0080_CTRL_CMD_GPU_GET_VIDLINK_ORDER = (0x800281)
NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS_MESSAGE_ID = (0x81)
NV0080_CTRL_CMD_GPU_SET_DISPLAY_OWNER = (0x800282)
NV0080_CTRL_GPU_SET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x82)
NV0080_CTRL_CMD_GPU_GET_DISPLAY_OWNER = (0x800283)
NV0080_CTRL_GPU_GET_DISPLAY_OWNER_PARAMS_MESSAGE_ID = (0x83)
NV0080_CTRL_CMD_GPU_SET_VIDLINK = (0x800285)
NV0080_CTRL_GPU_SET_VIDLINK_PARAMS_MESSAGE_ID = (0x85)
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_FALSE = (0x00000000)
NV0080_CTRL_GPU_SET_VIDLINK_ENABLE_TRUE = (0x00000001)
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_GET_STATUS = 0
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERDOWN = 1
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_POWERUP = 2
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWER_ON = 0
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_DOWN = 1
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_GATED = 2
NV0080_CTRL_CMD_GPU_VIDEO_POWERGATE_STATUS_POWERING_UP = 3
NV0080_CTRL_CMD_GPU_MODIFY_SW_STATE_PERSISTENCE = (0x800287)
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_ENABLED = (0x00000000)
NV0080_CTRL_GPU_SW_STATE_PERSISTENCE_DISABLED = (0x00000001)
NV0080_CTRL_GPU_MODIFY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x87)
NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE = (0x800288)
NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS_MESSAGE_ID = (0x88)
NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE = (0x800289)
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE = (0x00000000)
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS = (0x00000001)
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX = (0x00000002)
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST = (0x00000003)
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VGPU = NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST
NV0080_CTRL_GPU_VIRTUALIZATION_MODE_HOST_VSGA = (0x00000004)
NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS_MESSAGE_ID = (0x89)
NV0080_CTRL_CMD_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028c)
NV0080_CTRL_GPU_GET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8C)
NV0080_CTRL_CMD_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE = (0x80028d)
NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS_MESSAGE_ID = (0x8D)
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_DEFAULT = 0
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_COMPUTE = 1
NV0080_CTRL_GPU_SPARSE_TEXTURE_COMPUTE_MODE_OPTIMIZE_SPARSE_TEXTURE = 2
NV0080_CTRL_CMD_GPU_GET_VGX_CAPS = (0x80028e)
NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS_MESSAGE_ID = (0x8E)
NV0080_CTRL_CMD_GPU_GET_SRIOV_CAPS = (0x800291)
NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_MESSAGE_ID = (0x91)
NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE = 100
NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = (0x800292)
NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID = (0x92)
NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE = (0x800293)
NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM_MESSAGE_ID = (0x93)
NV0080_CTRL_GPU_GET_BRAND_CAPS_QUADRO = NVBIT(0)
NV0080_CTRL_GPU_GET_BRAND_CAPS_NVS = NVBIT(1)
NV0080_CTRL_GPU_GET_BRAND_CAPS_TITAN = NVBIT(2)
NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS = (0x800294)
NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS_MESSAGE_ID = (0x94)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M = (1 << 6)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M = (1 << 7)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M = (1 << 8)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M = (1 << 9)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G = (1 << 10)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G = (1 << 11)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G = (1 << 12)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G = (1 << 13)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G = (1 << 14)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G = (1 << 15)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G = (1 << 16)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G = (1 << 17)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G = (1 << 18)
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M
NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX = NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G
NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID = 0x0
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE = (0x800296)
NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID = (0x96)
NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE = (0x800297)
NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x97)
NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE = (0x800298)
NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0x98)
NV0080_CTRL_CMD_GR_GET_CAPS = (0x801102)
NV0080_CTRL_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_GR_CAPS_TBL_SIZE = 23
NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS = (0x00000000)
NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = (0x00000001)
NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = (0x00000002)
NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = (0x00000003)
NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = (0x00000004)
NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = (0x00000005)
NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT = (0x00000006)
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = (0x00000007)
NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = (0x00000008)
NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = (0x00000009)
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = (0x0000000A)
NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = (0x0000000B)
NV0080_CTRL_GR_INFO_INDEX_SM_VERSION = (0x0000000C)
NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = (0x0000000D)
NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = (0x0000000E)
NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = (0x0000000F)
NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = (0x00000010)
NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = (0x00000011)
NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = (0x00000012)
NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = (0x00000013)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = (0x00000014)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = (0x00000015)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = (0x00000016)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = (0x00000017)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = (0x00000018)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = (0x00000019)
NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = (0x0000001A)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = (0x0000001B)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = (0x0000001C)
NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = (0x0000001D)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = (0x0000001E)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = (0x0000001F)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = (0x00000020)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = (0x00000021)
NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = (0x00000022)
NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = (0x00000023)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = (0x00000024)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = (0x00000025)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = (0x00000026)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = (0x00000027)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = (0x00000028)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = (0x00000029)
NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = (0x0000002A)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = (0x0000002B)
NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = (0x0000002C)
NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = (0x0000002D)
NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = (0x0000002E)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = (0x00000032)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = (0x00000033)
NV0080_CTRL_GR_INFO_INDEX_DUMMY = (0x00000033)
NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = (0x00000034)
NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = (0x00000035)
NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = (0x00000036)
NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = (0x00000037)
NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = (0x00000038)
NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = (0x00000039)
NV0080_CTRL_GR_INFO_INDEX_MAX = (0x00000039)
NV0080_CTRL_GR_INFO_MAX_SIZE = (0x3a)
NV0080_CTRL_CMD_GR_GET_INFO = (0x801104)
NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x4)
NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE = (0x801107)
NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x801108)
NV0080_CTRL_GR_GET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x7)
NV0080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x8)
NV0080_CTRL_CMD_GR_GET_CAPS_V2 = (0x801109)
NV0080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x9)
NV0080_CTRL_CMD_GR_GET_INFO_V2 = (0x801110)
NV0080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10)
NV0080_CTRL_CMD_HOST_GET_CAPS = (0x801401)
NV0080_CTRL_HOST_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_HOST_CAPS_TBL_SIZE = 3
NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = (0x801402)
NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE = (0x802002)
NV0080_CTRL_CMD_INTERNAL_GR_GET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE = (0x802003)
NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID = (0x3)
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_SET_CONTROL = (0x802009)
NV0080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x802004)
NV0080_CTRL_CMD_INTERNAL_PERF_SLI_GPU_BOOST_SYNC_SET_CONTROL = (0x802007)
NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS = (0x802008)
NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS = 200
NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0x08)
NV0080_CTRL_CMD_MSENC_GET_CAPS = (0x801b01)
NV0080_CTRL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_MSENC_CAPS_TBL_SIZE = 4
NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 = (0x801b02)
NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_NVJPG_CAPS_TBL_SIZE = 9
NV0080_CTRL_CMD_NVJPG_GET_CAPS_V2 = (0x801f02)
NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x2)
NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7)
NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID = (0x9)
NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = (0x801909)
NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH = (0x801e01)
NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID = (0x1)
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_SAVE_VT_STATE = (0x00000001)
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_RESTORE_VT_STATE = (0x00000002)
NV0080_CTRL_OS_UNIX_VT_SWITCH_CMD_CONSOLE_RESTORED = (0x00000003)
NV0080_CTRL_CMD_OS_UNIX_VT_GET_FB_INFO = (0x801e02)
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_RESERVED = (0x00)
NV2080_CTRL_GPU = (0x01)
NV2080_CTRL_GPU_LEGACY_NON_PRIVILEGED = (0x81)
NV2080_CTRL_FUSE = (0x02)
NV2080_CTRL_FUSE_LEGACY_NON_PRIVILEGED = (0x82)
NV2080_CTRL_EVENT = (0x03)
NV2080_CTRL_TIMER = (0x04)
NV2080_CTRL_THERMAL = (0x05)
NV2080_CTRL_THERMAL_LEGACY_PRIVILEGED = (0xc5)
NV2080_CTRL_THERMAL_LEGACY_NON_PRIVILEGED = (0x85)
NV2080_CTRL_I2C = (0x06)
NV2080_CTRL_EXTI2C = (0x07)
NV2080_CTRL_BIOS = (0x08)
NV2080_CTRL_CIPHER = (0x09)
NV2080_CTRL_INTERNAL = (0x0A)
NV2080_CTRL_CLK_LEGACY_PRIVILEGED = (0xd0)
NV2080_CTRL_CLK_LEGACY_NON_PRIVILEGED = (0x90)
NV2080_CTRL_CLK = (0x10)
NV2080_CTRL_FIFO = (0x11)
NV2080_CTRL_GR = (0x12)
NV2080_CTRL_FB = (0x13)
NV2080_CTRL_MC = (0x17)
NV2080_CTRL_BUS = (0x18)
NV2080_CTRL_PERF_LEGACY_PRIVILEGED = (0xe0)
NV2080_CTRL_PERF_LEGACY_NON_PRIVILEGED = (0xa0)
NV2080_CTRL_PERF = (0x20)
NV2080_CTRL_NVIF = (0x21)
NV2080_CTRL_RC = (0x22)
NV2080_CTRL_GPIO = (0x23)
NV2080_CTRL_GPIO_LEGACY_NON_PRIVILEGED = (0xa3)
NV2080_CTRL_NVD = (0x24)
NV2080_CTRL_DMA = (0x25)
NV2080_CTRL_PMGR = (0x26)
NV2080_CTRL_PMGR_LEGACY_PRIVILEGED = (0xe6)
NV2080_CTRL_PMGR_LEGACY_NON_PRIVILEGED = (0xa6)
NV2080_CTRL_POWER = (0x27)
NV2080_CTRL_POWER_LEGACY_NON_PRIVILEGED = (0xa7)
NV2080_CTRL_LPWR = (0x28)
NV2080_CTRL_LPWR_LEGACY_NON_PRIVILEGED = (0xa8)
NV2080_CTRL_LPWR_LEGACY_PRIVILEGED = (0xe8)
NV2080_CTRL_ACR = (0x29)
NV2080_CTRL_CE = (0x2A)
NV2080_CTRL_SPI = (0x2B)
NV2080_CTRL_NVLINK = (0x30)
NV2080_CTRL_FLCN = (0x31)
NV2080_CTRL_VOLT = (0x32)
NV2080_CTRL_VOLT_LEGACY_PRIVILEGED = (0xf2)
NV2080_CTRL_VOLT_LEGACY_NON_PRIVILEGED = (0xb2)
NV2080_CTRL_FAS = (0x33)
NV2080_CTRL_ECC = (0x34)
NV2080_CTRL_ECC_NON_PRIVILEGED = (0xb4)
NV2080_CTRL_FLA = (0x35)
NV2080_CTRL_GSP = (0x36)
NV2080_CTRL_NNE = (0x37)
NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED = (0xb7)
NV2080_CTRL_GRMGR = (0x38)
NV2080_CTRL_UCODE_FUZZER = (0x39)
NV2080_CTRL_DMABUF = (0x3A)
NV2080_CTRL_BIF = (0x3B)
NV2080_CTRL_OS_WINDOWS = (0x3F)
NV2080_CTRL_OS_MACOS = (0x3E)
NV2080_CTRL_OS_UNIX = (0x3D)
NV2080_CTRL_CMD_NULL = (0x20800000)
NV2080_CTRL_BIOS_INFO_MAX_SIZE = (0x0000000F)
NV2080_CTRL_BIOS_INFO_INDEX_REVISION = (0x00000000)
NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION = (0x00000001)
NV2080_CTRL_CMD_BIOS_GET_INFO = (0x20800802)
NV2080_CTRL_CMD_BIOS_GET_INFO_V2 = (0x20800810)
NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x10)
NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH = (0x00000100)
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII = (0x00000000)
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE = (0x00000001)
NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH = (0x00000002)
NV2080_CTRL_BIOS_NBSI_MODULE_ROOT = (0x00000000)
NV2080_CTRL_BIOS_NBSI_MODULE_RM = (0x00000001)
NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER = (0x00000002)
NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO = (0x00000003)
NV2080_CTRL_BIOS_NBSI_MODULE_CPL = (0x00000004)
NV2080_CTRL_BIOS_NBSI_MODULE_D3D = (0x00000005)
NV2080_CTRL_BIOS_NBSI_MODULE_OGL = (0x00000006)
NV2080_CTRL_BIOS_NBSI_MODULE_PMU = (0x00000007)
NV2080_CTRL_BIOS_NBSI_MODULE_MODE = (0x00000008)
NV2080_CTRL_BIOS_NBSI_NUM_MODULES = (0x00000009)
NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN = (0x80000000)
NV2080_CTRL_BIOS_GET_NBSI_SUCCESS = (0x00000000)
NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE = (0x00000001)
NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH = (0xFFFFFFFA)
NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS = (0xFFFFFFFB)
NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE = (0xFFFFFFFC)
NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE = (0xFFFFFFFD)
NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE = (0xFFFFFFFE)
NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND = (0xFFFFFFFF)
NV2080_CTRL_CMD_BIOS_GET_NBSI = (0x20800803)
NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 = (0x2080080e)
NV2080_BIOS_GET_NBSI_MAX_RET_SIZE = (0x100)
NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ = (0x20800806)
NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID = (0x6)
GLOB_TYPE_GET_NBSI_DIR = 0xfffe
GLOB_TYPE_APITEST = 0xffff
GLOB_TYPE_GET_NBSI_ACPI_RAW = 0xfffd
NV2080_CTRL_CMD_BIOS_GET_SKU_INFO = (0x20800808)
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_BIOS_GET_POST_TIME = (0x20800809)
NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_BIOS_GET_UEFI_SUPPORT = (0x2080080b)
NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_NO = (0x00000000)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_YES = (0x00000001)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_PLACEHOLDER = (0x00000002)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_PRESENCE_HIDDEN = (0x00000003)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE = (0x00000000)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE = (0x00000001)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE = (0x00000000)
NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCI_INFO = (0x20801801)
NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_BUS_INFO_INDEX_TYPE = (0x00000000)
NV2080_CTRL_BUS_INFO_INDEX_INTLINE = (0x00000001)
NV2080_CTRL_BUS_INFO_INDEX_CAPS = (0x00000002)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS = (0x00000003)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS = (0x00000004)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS = (0x00000005)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CAPS = (0x00000006)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CTRL_STATUS = (0x00000007)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CTRL_STATUS = (0x00000008)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CTRL_STATUS = (0x00000009)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_DOWNSTREAM_LINK_CTRL_STATUS = (0x0000000A)
NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS = (0x0000000B)
NV2080_CTRL_BUS_INFO_INDEX_NONCOHERENT_DMA_FLAGS = (0x0000000C)
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE = (0x0000000D)
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS = (0x0000000E)
NV2080_CTRL_BUS_INFO_INDEX_BUS_NUMBER = (0x0000000F)
NV2080_CTRL_BUS_INFO_INDEX_DEVICE_NUMBER = (0x00000010)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_ERRORS = (0x00000011)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_ERRORS = (0x00000012)
NV2080_CTRL_BUS_INFO_INDEX_INTERFACE_TYPE = (0x00000013)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN2_INFO = (0x00000014)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_AER = (0x00000015)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CAPS = (0x00000016)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_LINK_CTRL_STATUS = (0x00000017)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_ASLM_STATUS = (0x00000018)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_WIDTH_SWITCH_ERROR_COUNT = (0x00000019)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_LINK_SPEED_SWITCH_ERROR_COUNT = (0x0000001A)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_CYA_ASPM = (0x0000001B)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS = (0x0000001C)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS = (0x0000001D)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED = (0x0000001E)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS = (0x0000001F)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_LINECODE_ERRORS_CLEAR = (0x00000020)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CRC_ERRORS_CLEAR = (0x00000021)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NAKS_RECEIVED_CLEAR = (0x00000022)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FAILED_L0S_EXITS_CLEAR = (0x00000023)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS = (0x00000024)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS = (0x00000025)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS = (0x00000026)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS = (0x00000027)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CORRECTABLE_ERRORS_CLEAR = (0x00000028)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_NONFATAL_ERRORS_CLEAR = (0x00000029)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_FATAL_ERRORS_CLEAR = (0x0000002A)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_UNSUPPORTED_REQUESTS_CLEAR = (0x0000002B)
NV2080_CTRL_BUS_INFO_INDEX_DOMAIN_NUMBER = (0x0000002C)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_GEN_INFO = (0x0000002D)
NV2080_CTRL_BUS_INFO_INDEX_GPU_INTERFACE_TYPE = (0x0000002E)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_GEN_INFO = (0x0000002F)
NV2080_CTRL_BUS_INFO_INDEX_PCIE_BOARD_GEN_INFO = (0x00000030)
NV2080_CTRL_BUS_INFO_INDEX_MSI_INFO = (0x00000031)
NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI = (0x00000032)
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE = (0x00000033)
NV2080_CTRL_BUS_INFO_INDEX_MAX = NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE
NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE = (0x00000034)
NV2080_CTRL_BUS_INFO_TYPE_PCI = (0x00000001)
NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS = (0x00000003)
NV2080_CTRL_BUS_INFO_TYPE_FPCI = (0x00000004)
NV2080_CTRL_BUS_INFO_TYPE_AXI = (0x00000008)
NV2080_CTRL_BUS_INFO_CAPS_NEED_IO_FLUSH = (0x00000001)
NV2080_CTRL_BUS_INFO_CAPS_CHIP_INTEGRATED = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_2500MBPS = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_5000MBPS = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS = (0x00000005)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS = (0x00000006)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_L0S_L1 = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN1 = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN2 = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 = (0x00000005)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 = (0x00000005)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 = (0x00000005)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_DISABLED = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L1 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_ASPM_L0S_L1 = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_2500MBPS = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_5000MBPS = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS = (0x00000003)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS = (0x00000005)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS = (0x00000006)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X2 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X4 = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X8 = (0x00000008)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X12 = (0x0000000C)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X16 = (0x00000010)
NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X32 = (0x00000020)
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_COHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_CTXDMA_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_GPUGART_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_NONCOHERENT_DMA_FLAGS_COH_MODE_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_REQFLUSH_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_GPU_GART_FLAGS_UNIFIED_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST = (0x00000008)
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_ENTERED_RECOVERY = (0x00000010)
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_FALSE = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CAP_TRUE = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN1 = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_GEN2_INFO_CURR_LEVEL_GEN2 = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_TRAINING_ERR = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_DLINK_PROTO_ERR = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_POISONED_TLP = (0x00000004)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_FC_PROTO_ERR = (0x00000008)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_TIMEOUT = (0x00000010)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_CPL_ABORT = (0x00000020)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNEXP_CPL = (0x00000040)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_RCVR_OVERFLOW = (0x00000080)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_MALFORMED_TLP = (0x00000100)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_ECRC_ERROR = (0x00000200)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_UNCORR_UNSUPPORTED_REQ = (0x00000400)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RCV_ERR = (0x00010000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_TLP = (0x00020000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_BAD_DLLP = (0x00040000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_ROLLOVER = (0x00080000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_RPLY_TIMEOUT = (0x00100000)
NV2080_CTRL_BUS_INFO_PCIE_LINK_AER_CORR_ADVISORY_NONFATAL = (0x00200000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_ERROR = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_PCIE_PRESENT = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_CL_CAPABLE_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_OS_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_MISSING = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_ASLM_STATUS_BR04_PRESENT = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_VALID_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_DISABLED = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L1 = (0x00000002)
NV2080_CTRL_BUS_INFO_PCIE_GPU_CYA_ASPM_L0S_L1 = (0x00000003)
NV2080_CTRL_BUS_INFO_MSI_STATUS_DISABLED = (0x00000000)
NV2080_CTRL_BUS_INFO_MSI_STATUS_ENABLED = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_2_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_PCIPM_L1_1_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_2_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_ASPM_L1_1_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CAP_L1PM_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_2_ENABLED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_PCIPM_L1_1_ENABLED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_2_ENABLED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_YES = (0x00000001)
NV2080_CTRL_BUS_INFO_PCIE_L1_SS_CTRL1_ASPM_L1_1_ENABLED_NO = (0x00000000)
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_PCIE = (0x00000000)
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_NVLINK = (0x00000001)
NV2080_CTRL_BUS_INFO_INDEX_SYSMEM_CONNECTION_TYPE_C2C = (0x00000002)
NV2080_CTRL_CMD_BUS_GET_INFO = (0x20801802)
NV2080_CTRL_BUS_GET_INFO_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_BUS_GET_INFO_V2 = (0x20801823)
NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO = (0x20801803)
NV2080_CTRL_BUS_MAX_PCI_BARS = (8)
NV2080_CTRL_BUS_GET_PCI_BAR_INFO_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_BUS_SET_PCIE_LINK_WIDTH = (0x20801804)
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PSTATE = (0x00000001)
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_PCIE_CFG_ACCESS = (0x00000002)
NV2080_CTRL_BUS_SET_PCIE_LINK_WIDTH_ERROR_TRAINING = (0x00000004)
NV2080_CTRL_CMD_BUS_SET_PCIE_SPEED = (0x20801805)
NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_BUS_SET_PCIE_SPEED_2500MBPS = (0x00000001)
NV2080_CTRL_BUS_SET_PCIE_SPEED_5000MBPS = (0x00000002)
NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS = (0x00000003)
NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS = (0x00000004)
NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS = (0x00000005)
NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS = (0x00000006)
NV2080_CTRL_CMD_BUS_MAP_BAR2 = (0x20801809)
NV2080_CTRL_BUS_MAP_BAR2_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_BUS_UNMAP_BAR2 = (0x2080180a)
NV2080_CTRL_BUS_UNMAP_BAR2_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_BUS_VERIFY_BAR2 = (0x2080180b)
NV2080_CTRL_BUS_VERIFY_BAR2_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_CMD_BUS_SERVICE_GPU_MULTIFUNC_STATE = (0x20801812)
NV2080_CTRL_BUS_SERVICE_GPU_MULTIFUNC_STATE_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_BUS_ENABLE_GPU_MULTIFUNC_STATE = (0x00000000)
NV2080_CTRL_BUS_DISABLE_GPU_MULTIFUNC_STATE = (0x00000001)
NV2080_CTRL_BUS_GET_GPU_MULTIFUNC_STATE = (0x00000002)
NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = (0x20801813)
NV2080_CTRL_PEX_MAX_COUNTER_TYPES = 31
NV2080_CTRL_BUS_GET_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_BUS_PEX_COUNTER_TYPE = 0x00000000
NV2080_CTRL_BUS_PEX_COUNTER_RECEIVER_ERRORS = 0x00000001
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_COUNT = 0x00000002
NV2080_CTRL_BUS_PEX_COUNTER_REPLAY_ROLLOVER_COUNT = 0x00000004
NV2080_CTRL_BUS_PEX_COUNTER_BAD_DLLP_COUNT = 0x00000008
NV2080_CTRL_BUS_PEX_COUNTER_BAD_TLP_COUNT = 0x00000010
NV2080_CTRL_BUS_PEX_COUNTER_8B10B_ERRORS_COUNT = 0x00000020
NV2080_CTRL_BUS_PEX_COUNTER_SYNC_HEADER_ERRORS_COUNT = 0x00000040
NV2080_CTRL_BUS_PEX_COUNTER_LCRC_ERRORS_COUNT = 0x00000080
NV2080_CTRL_BUS_PEX_COUNTER_FAILED_L0S_EXITS_COUNT = 0x00000100
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_SENT_COUNT = 0x00000200
NV2080_CTRL_BUS_PEX_COUNTER_NAKS_RCVD_COUNT = 0x00000400
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ERRORS = 0x00000800
NV2080_CTRL_BUS_PEX_COUNTER_L1_TO_RECOVERY_COUNT = 0x00001000
NV2080_CTRL_BUS_PEX_COUNTER_L0_TO_RECOVERY_COUNT = 0x00002000
NV2080_CTRL_BUS_PEX_COUNTER_RECOVERY_COUNT = 0x00004000
NV2080_CTRL_BUS_PEX_COUNTER_CHIPSET_XMIT_L0S_ENTRY_COUNT = 0x00008000
NV2080_CTRL_BUS_PEX_COUNTER_GPU_XMIT_L0S_ENTRY_COUNT = 0x00010000
NV2080_CTRL_BUS_PEX_COUNTER_L1_ENTRY_COUNT = 0x00020000
NV2080_CTRL_BUS_PEX_COUNTER_L1P_ENTRY_COUNT = 0x00040000
NV2080_CTRL_BUS_PEX_COUNTER_DEEP_L1_ENTRY_COUNT = 0x00080000
NV2080_CTRL_BUS_PEX_COUNTER_ASLM_COUNT = 0x00100000
NV2080_CTRL_BUS_PEX_COUNTER_TOTAL_CORR_ERROR_COUNT = 0x00200000
NV2080_CTRL_BUS_PEX_COUNTER_CORR_ERROR_COUNT = 0x00400000
NV2080_CTRL_BUS_PEX_COUNTER_NON_FATAL_ERROR_COUNT = 0x00800000
NV2080_CTRL_BUS_PEX_COUNTER_FATAL_ERROR_COUNT = 0x01000000
NV2080_CTRL_BUS_PEX_COUNTER_UNSUPP_REQ_COUNT = 0x02000000
NV2080_CTRL_BUS_PEX_COUNTER_L1_1_ENTRY_COUNT = 0x04000000
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ENTRY_COUNT = 0x08000000
NV2080_CTRL_BUS_PEX_COUNTER_L1_2_ABORT_COUNT = 0x10000000
NV2080_CTRL_BUS_PEX_COUNTER_L1SS_TO_DEEP_L1_TIMEOUT_COUNT = 0x20000000
NV2080_CTRL_BUS_PEX_COUNTER_L1_SHORT_DURATION_COUNT = 0x40000000
NV2080_CTRL_CMD_BUS_CLEAR_PEX_COUNTERS = (0x20801814)
NV2080_CTRL_BUS_CLEAR_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x14)
NV2080_CTRL_CMD_BUS_FREEZE_PEX_COUNTERS = (0x20801815)
NV2080_CTRL_BUS_FREEZE_PEX_COUNTERS_PARAMS_MESSAGE_ID = (0x15)
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS = (0x20801816)
NV2080_CTRL_PEX_MAX_LANES = 16
NV2080_CTRL_CMD_BUS_GET_PEX_LANE_COUNTERS_PARAMS_MESSAGE_ID = (0x16)
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TYPE = 0x00000000
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_CODING_ERR = 0x00000001
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SYNC_HDR_ORDER_ERR = 0x00000002
NV2080_CTRL_BUS_PEX_COUNTER_LANE_OS_DATA_SEQ_ERR = 0x00000004
NV2080_CTRL_BUS_PEX_COUNTER_LANE_TSX_DATA_SEQ_ERR = 0x00000008
NV2080_CTRL_BUS_PEX_COUNTER_LANE_SKPOS_LFSR_ERR = 0x00000010
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RX_CLK_FIFO_OVERFLOW = 0x00000020
NV2080_CTRL_BUS_PEX_COUNTER_LANE_ELASTIC_FIFO_OVERFLOW = 0x00000040
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LINK_NUM_ERR = 0x00000080
NV2080_CTRL_BUS_PEX_COUNTER_LANE_RCVD_LANE_NUM_ERR = 0x00000100
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY = (0x20801817)
NV2080_CTRL_CMD_BUS_GET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x17)
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY = (0x20801818)
NV2080_CTRL_CMD_BUS_SET_PCIE_LTR_LATENCY_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_BYTES = 0x00000001
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_BYTES = 0x00000002
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0 = 0x00000004
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0 = 0x00000008
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_TX_L0S = 0x00000010
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_RX_L0S = 0x00000020
NV2080_CTRL_BUS_PEX_UTIL_COUNTER_NON_L0_L0S = 0x00000040
NV2080_CTRL_PEX_UTIL_MAX_COUNTER_TYPES = 7
NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = (0x20801819)
NV2080_CTRL_BUS_GET_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x19)
NV2080_CTRL_CMD_BUS_CLEAR_PEX_UTIL_COUNTERS = (0x20801820)
NV2080_CTRL_BUS_CLEAR_PEX_UTIL_COUNTERS_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_BUS_GET_BFD = (0x20801821)
NV2080_CTRL_BUS_GET_BFD_PARAMSARR_MESSAGE_ID = (0x21)
NV2080_CTRL_ASPM_DISABLE_FLAGS_L1_MASK_REGKEY_OVERRIDE = 0x00000000
NV2080_CTRL_ASPM_DISABLE_FLAGS_OS_RM_MAKES_POLICY_DECISIONS = 0x00000001
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_BEHIND_BRIDGE = 0x00000002
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_UNSUPPORTED = 0x00000003
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED = 0x00000004
NV2080_CTRL_ASPM_DISABLE_FLAGS_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY = 0x00000005
NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_DISABLED = 0x00000006
NV2080_CTRL_ASPM_DISABLE_FLAGS_CL_ASPM_L1_CHIPSET_ENABLED_MOBILE_ONLY = 0x00000007
NV2080_CTRL_ASPM_DISABLE_FLAGS_BIF_ENABLE_ASPM_DT_L1 = 0x00000008
NV2080_CTRL_ASPM_DISABLE_FLAGS_MAX_FLAGS = 9
NV2080_CTRL_CMD_BUS_GET_ASPM_DISABLE_FLAGS = (0x20801822)
NV2080_CTRL_BUS_GET_ASPM_DISABLE_FLAGS_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS = (0x20801824)
NV2080_CTRL_CMD_BUS_CONTROL_PUBLIC_ASPM_BITS_PARAMS_MESSAGE_ID = (0x24)
NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK = (0x20801825)
NV2080_CTRL_BUS_MAX_NUM_GPUS = 32
NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_MESSAGE_ID = (0x25)
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS = (0x20801826)
NV2080_CTRL_CMD_BUS_SET_EOM_PARAMETERS_PARAMS_MESSAGE_ID = (0x26)
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE = (0x20801827)
NV2080_CTRL_CMD_BUS_GET_UPHY_DLN_CFG_SPACE_PARAMS_MESSAGE_ID = (0x27)
NV2080_CTRL_CMD_BUS_GET_EOM_STATUS = (0x20801828)
NV2080_CTRL_BUS_MAX_NUM_LANES = 32
NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = (0x20801829)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x29)
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM = 0x0
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU = 0x1
NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P = 0x2
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_SWAP_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_CAS_128_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = (0x2080182a)
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IADD = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMIN = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IMAX = 2
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_INC = 3
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_DEC = 4
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IAND = 5
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IOR = 6
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_IXOR = 7
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_EXCH = 8
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_CAS = 9
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FADD = 10
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMIN = 11
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_FMAX = 12
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT = 13
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID = (0x2A)
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_VECTOR_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_32_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_64_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIZE_128_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SIGNED_NO = 0
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_YES = 1
NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_UNSIGNED_NO = 0
NV2080_CTRL_CMD_BUS_GET_C2C_INFO = (0x2080182b)
NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID = (0x2B)
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU = 1
NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU = 2
NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS = (0x2080182c)
NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS_MESSAGE_ID = (0x2C)
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING = (0x2080182e)
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID = 0
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK = 1
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE = 2
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 = 3
NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C = 4
NV2080_SET_P2P_MAPPING_UUID_LEN = 16
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2E)
NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING = (0x2080182f)
NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID = (0x2F)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = (0x20801830)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID = (0x30)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO = (0x00000000)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES = (0x00000001)
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO = (0x00000000)
NV2080_CTRL_CMD_CE_GET_CAPS = (0x20802a01)
NV2080_CTRL_CE_CAPS_TBL_SIZE = 2
NV2080_CTRL_CE_GET_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_CE_GET_CAPS_V2 = (0x20802a03)
NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = (0x20802a02)
NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG = (0x20802a04)
NV2080_CTRL_MAX_PCES = 32
NV2080_CTRL_MAX_GRCES = 4
NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS = (0x20802a05)
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE = 0xf
NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB = (0x20802a06)
NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID = (0x6)
NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS = (0x20802a07)
NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE = (0x20802a08)
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK = (0x20802a09)
NV2080_CTRL_CE_MAX_HSHUBS = 32
NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_CE_GET_ALL_CAPS = (0x20802a0a)
NV2080_CTRL_MAX_CES = 64
NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID = (0xa)
NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS = (0x20802a0b)
NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID = (0xb)
NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO = (0x20802a0c)
NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID = (0xc)
NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 = (0x20802a0d)
NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID = (0xd)
NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 = (0x20802a0e)
NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID = (0xe)
NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE = (0x20802a0f)
NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID = (0xf)
NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK = (0x20802a11)
NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID = (0x11)
NV2080_CTRL_CMD_CE_IS_DECOMP_LCE_ENABLED = (0x20802a12)
NV2080_CTRL_CE_IS_DECOMP_LCE_ENABLED_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_CMD_DMA_INVALIDATE_TLB = (0x20802502)
NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_GRAPHICS_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VIDEO_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_DISPLAY_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_CAPTURE_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_IFB_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MV_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_MPEG_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_VLD_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_ENCRYPTION_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_PERFMON_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_POSTPROCESS_TRUE = (0x00000001)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_FALSE = (0x00000000)
NV2080_CTRL_DMA_INVALIDATE_TLB_ENGINE_BAR_TRUE = (0x00000001)
NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE = (0x000000000)
NV2080_CTRL_DMA_INFO_INDEX_MAX = NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
NV2080_CTRL_CMD_DMA_GET_INFO = (0x20802503)
NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES = (256)
NV2080_CTRL_DMA_GET_INFO_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD = (0x20803a01)
NV2080_CTRL_DMABUF_MAX_HANDLES = 128
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT = (0x00000000)
NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE = (0x00000001)
NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS = (0x20803400)
NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID = (0x0)
NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS = (0x20803401)
NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = (0x20800301)
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE = (0x00000000)
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE = (0x00000001)
NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT = (0x00000002)
NV2080_EVENT_DSTATE_XUSB_D0 = (0x00000000)
NV2080_EVENT_DSTATE_XUSB_D3 = (0x00000003)
NV2080_EVENT_DSTATE_XUSB_INVALID = (0xFFFFFFFF)
NV2080_EVENT_DSTATE_PPC_D0 = (0x00000000)
NV2080_EVENT_DSTATE_PPC_D3 = (0x00000003)
NV2080_EVENT_DSTATE_PPC_INVALID = (0xFFFFFFFF)
NV2080_CTRL_CMD_EVENT_SET_TRIGGER = (0x20800302)
NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES = (0x20800303)
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID = (0x3)
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED = 0
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_PENDING = 1
NV2080_EVENT_MEMORY_NOTIFIES_STATUS_ERROR = 2
NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY = (0x20800304)
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_EVENT_SET_GUEST_MSI = (0x20800305)
NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION = (0x20800306)
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS_MESSAGE_ID = (0x6)
NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO = (0x20800308)
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF = (0x20800309)
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF = (0x2080030a)
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT = (0x00000000)
NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE = (0x00000001)
NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE = (0x00000002)
NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT = (0x00000003)
NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT = (0x00000004)
NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE = (0x00000005)
NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT = (0x00000006)
NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE = (0x00000007)
NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE = (0x00000008)
NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE = (0x00000009)
NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE = (0x0000000A)
NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH = (0x0000000B)
NV2080_CTRL_FB_INFO_INDEX_RAM_CFG = (0x0000000C)
NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE = (0x0000000D)
NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT = (0x0000000E)
NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT = (0x0000000F)
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB = (0x0000000F)
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB = (0x0000000F)
NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB = (0x0000000F)
NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW = (0x0000000F)
NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB = (0x00000010)
NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB = (0x00000011)
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB = (0x00000012)
NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB = (0x00000013)
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK = (0x00000014)
NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE = (0x00000015)
NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE = (0x00000016)
NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION = (0x00000017)
NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN = (0x00000018)
NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT = (0x00000019)
NV2080_CTRL_FB_INFO_INDEX_FBP_MASK = (0x0000001A)
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE = (0x0000001B)
NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID = (0x0000001C)
NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE = (0x0000001D)
NV2080_CTRL_FB_INFO_INDEX_HEAP_START = (0x0000001E)
NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE = (0x0000001F)
NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE = (0x00000020)
NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T = (0x00000021)
NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT = (0x00000022)
NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT = (0x00000023)
NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE = (0x00000024)
NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE = (0x00000025)
NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE = (0x00000026)
NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE = (0x00000027)
NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED = (0x00000028)
NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE = (0x00000029)
NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT = (0x0000002A)
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK = (0x0000002B)
NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED = (0x0000002C)
NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED = (0x0000002D)
NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED = (0x0000002E)
NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED = (0x0000002F)
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE = (0x00000030)
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT = (0x00000031)
NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB = (0x00000032)
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB = (0x00000033)
NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB = (0x00000034)
NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE = (0x00000035)
NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB = (0x00000036)
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 = (0x00000037)
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 = (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 = (0x00000038)
NV2080_CTRL_FB_INFO_MAX_LIST_SIZE = (0x00000039)
NV2080_CTRL_FB_INFO_INDEX_MAX = (0x38)
NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN = (0x00000000)
NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM = (0x00000001)
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 = (0x00000002)
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 = (0x00000003)
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 = (0x00000004)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 = (0x00000005)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 = (0x00000006)
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 = (0x00000007)
NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 = NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 = (0x00000008)
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 = (0x00000009)
NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 = (0x0000000C)
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 = (0x0000000D)
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 = (0x0000000E)
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 = (0x0000000F)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X = (0x00000010)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 = (0x00000011)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X = (0x00000012)
NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 = (0x00000013)
NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 = (0x00000014)
NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 = (0x00000015)
NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED = (0x00000000)
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED = (0x00000001)
NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED = (0x00000002)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG = (0x00000001)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA = (0x00000002)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA = (0x00000003)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON = (0x00000004)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA = (0x00000005)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX = (0x00000006)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL = (0x00000007)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND = (0x00000008)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT = (0x00000009)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON = (0x0000000F)
NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN = (0xFFFFFFFF)
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED = (0x00000000)
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED = (0x00000001)
NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED = (0x00000002)
NV2080_CTRL_CMD_FB_GET_INFO = (0x20801301)
NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_FB_GET_INFO_V2 = (0x20801303)
NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET = (0x20801310)
NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID = (0x10)
NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED = (0x2080130c)
NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE = (0x00000000)
NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET = (0x00000001)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL = (0x2080130d)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO = (0x00000000)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES = (0x00000001)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO = (0x00000000)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES = (0x00000001)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO = (0x00000000)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES = (0x00000001)
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = (0x2080130e)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES = 500
NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY = (0x00000000)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY = (0x00000001)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY = (0x00000002)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO = (0x00000000)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES = (0x00000001)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO = (0x00000000)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES = (0x00000001)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY = (0x00000000)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE = (0x00000001)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO = (0x00000000)
NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES = (0x00000001)
NV2080_CTRL_CMD_FB_IS_KIND = (0x20801313)
NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED = (0x00000000)
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE = (0x00000001)
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 = (0x00000002)
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 = (0x00000003)
NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 = (0x00000004)
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC = (0x00000005)
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 = (0x00000006)
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 = (0x00000007)
NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 = (0x00000008)
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = (0x20801315)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID = (0x15)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED = (0x00000000)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED = (0x00000001)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH = (0x00000000)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK = (0x00000001)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED = (0x00000000)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED = (0x00000001)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL = (0x00000000)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING = (0x00000001)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED = (0x00000002)
NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE = (0x00000003)
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = (0x20801320)
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES = 17
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES = 16
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_FB_OFFLINE_PAGES = (0x20801321)
NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES = (0x00000040)
NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS = (0xffffffffffffffff)
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K = (0x00000000)
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K = (0x00000001)
NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K = (0x00000002)
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE = (0x00000002)
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE = (0x00000004)
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK = (0x00000000)
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT = (0x00000001)
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED = (0x00000002)
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL = (0x00000003)
NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR = (0x00000004)
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE
NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DBE = NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE
NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID = (0x21)
NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = (0x20801322)
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE = 0
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE = 1
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE = 0
NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE = 1
NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION = (0x20801325)
NV2080_CTRL_CMD_FB_ACR_CLIENT_ID = 2
NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID = (0x25)
NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES = (0x20801326)
NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x26)
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO = (0x20801327)
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID = (0x27)
NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP = (0x20801328)
NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT = (0x20801329)
NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS = (0x2080132a)
NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS = (0x2080132b)
NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB = (0x2080132c)
NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB = (0x2080132d)
NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 = (0x20801335)
NV2080_CTRL_CMD_FB_GET_AMAP_CONF = (0x20801336)
NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID = (0x36)
NV2080_CTRL_CMD_FB_CBC_OP = (0x20801337)
NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID = (0x37)
NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION = (0x20801338)
NV2080_MAX_CTAGS_FOR_CBC_EVICTION = 0x7F
NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID = (0x38)
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE = (0x20801339)
NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID = (0x39)
NV2080_CTRL_CMD_FB_FREE_TILE = (0x2080133a)
NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID = (0x3A)
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION = (0x2080133b)
NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID = (0x3B)
NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES = (0x2080133c)
NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x3C)
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO = (0x2080133d)
NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID = (0x3D)
NV2080_CTRL_CMD_FB_SET_RRD = (0x2080133e)
NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID = (0x3E)
NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE = (0xff)
NV2080_CTRL_CMD_FB_SET_READ_LIMIT = (0x2080133f)
NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID = (0x3F)
NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT = (0x20801340)
NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE = NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE
NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID = (0x40)
NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING = (0x20801341)
NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID = (0x41)
NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT = (0x20801342)
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS = (4)
NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID = (0x42)
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR = (0x20801343)
NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x43)
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE = 0
NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE = 1
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD = (0x00000002)
NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD = (0x00000003)
NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS = (0x00000200)
NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS = (0x20801344)
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE = NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE = 0
NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE = 1
NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID = (0x44)
NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE = 24
NV2080_CTRL_FB_FS_INFO_INVALID_QUERY = 0x0
NV2080_CTRL_FB_FS_INFO_FBP_MASK = 0x1
NV2080_CTRL_FB_FS_INFO_LTC_MASK = 0x2
NV2080_CTRL_FB_FS_INFO_LTS_MASK = 0x3
NV2080_CTRL_FB_FS_INFO_FBPA_MASK = 0x4
NV2080_CTRL_FB_FS_INFO_ROP_MASK = 0x5
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK = 0x6
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK = 0x7
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK = 0x8
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK = 0x9
NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK = 0xA
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK = 0xB
NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP = 0xC
NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK = 0xD
NV2080_CTRL_FB_FS_INFO_PAC_MASK = 0xE
NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK = 0xF
NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK = 0x10
NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK = 0x11
NV2080_CTRL_FB_FS_INFO_MAX_QUERIES = 120
NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID = (0x46)
NV2080_CTRL_CMD_FB_GET_FS_INFO = (0x20801346)
NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS = (0x0)
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW = (0x1)
NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS = (0x2)
NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW = (0x3)
NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS = (0x4)
NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID = (0x47)
NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM = (0x20801347)
NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES = (0x20801348)
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES = 512
NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES = 64
NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID = (0x48)
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID = (0x00000000)
NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE = (0x00000001)
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO = (0x20801349)
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM = 0
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM = 1
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE = 0
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE = 1
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE = 0
NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE = 1
NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID = (0x49)
NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS = (0x20801350)
NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID = (0x50)
NV2080_CTRL_CMD_FB_GET_NUMA_INFO = (0x20801351)
NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES = 64
NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID = (0x51)
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = (0x20801352)
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED = (0x00000001)
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED = (0x00000002)
NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID = (0x52)
NV2080_CTRL_CMD_GMMU_COMMIT_TLB_INVALIDATE = (0x20801353)
NV2080_CTRL_GMMU_COMMIT_TLB_INVALIDATE_PARAMS_MESSAGE_ID = (0x53)
NV2080_CTRL_CMD_FB_STATS_MAX_OWNER = 200
NV2080_CTRL_CMD_FB_STATS_GET = (0x2080132a)
NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID = (0x2A)
NV2080_CTRL_CMD_FB_GET_STATIC_BAR1_INFO = (0x20801354)
NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS_MESSAGE_ID = (0x54)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = (0x20801355)
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED = (0x00000000)
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED = (0x00000001)
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID = (0x55)
NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION = (0x20801356)
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE = (0x00000000)
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE = (0x00000001)
NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID = (0x56)
NV2080_CTRL_CMD_FB_GET_STATUS = (0x20801357)
NV2080_CTRL_FB_STATUS_FAILED = (0x00000000)
NV2080_CTRL_FB_STATUS_READY = (0x00000001)
NV2080_CTRL_FB_STATUS_PENDING = (0x00000002)
NV2080_CTRL_FB_STATUS_NOT_APPLICABLE = (0x00000003)
NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID = (0x57)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = (0x20801358)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED = (0x00000000)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED = (0x00000001)
NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID = (0x58)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = (0x20801359)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED = (0x00000000)
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED = (0x00000001)
NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID = (0x59)
NV2080_CTRL_CMD_SET_GPFIFO = (0x20801102)
NV2080_CTRL_CMD_SET_GPFIFO_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_FIFO_BIND_ENGINES_MAX_CHANNELS = (16)
NV2080_CTRL_FIFO_BIND_ENGINES_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_FIFO_BIND_ENGINES = (0x20801103)
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES = (0x20801104)
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_FALSE = (0x00000000)
NV2080_CTRL_CMD_SET_OPERATIONAL_PROPERTIES_FLAGS_ERROR_ON_STUCK_SEMAPHORE_TRUE = (0x00000001)
NV2080_CTRL_CMD_FIFO_GET_PHYSICAL_CHANNEL_COUNT = (0x20801108)
NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL = (0x000000000)
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS = (0x000000001)
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNELS_PER_GROUP = (0x000000002)
NV2080_CTRL_FIFO_INFO_INDEX_MAX_SUBCONTEXT_PER_GROUP = (0x000000003)
NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET = (0x000000004)
NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE = (0x000000005)
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE = (0x000000006)
NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED = (0x000000007)
NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE = (0x000000008)
NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE = (0x000000009)
NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT = (0x00000000a)
NV2080_CTRL_FIFO_INFO_INDEX_MAX = NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT = (12)
NV2080_CTRL_CMD_FIFO_GET_INFO = (0x20801109)
NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES = (256)
NV2080_CTRL_FIFO_GET_INFO_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_FIFO_CHANNEL_PREEMPTIVE_REMOVAL = (0x2080110a)
NV2080_CTRL_FIFO_CHANNEL_PREEMPTIVE_REMOVAL_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS = (0x2080110b)
NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = (64)
NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_FIFO_DISABLE_CHANNEL_FALSE = (0x00000000)
NV2080_CTRL_FIFO_DISABLE_CHANNEL_TRUE = (0x00000001)
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_FALSE = (0x00000000)
NV2080_CTRL_FIFO_ONLY_DISABLE_SCHEDULING_TRUE = (0x00000001)
NV2080_CTRL_FIFO_GET_CHANNEL_MEM_INFO_MAX_COUNT = 0x2
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO = (0x2080110c)
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_INVALID = 0x00000000
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_VIDMEM = 0x00000001
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_COH = 0x00000002
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_APERTURE_SYSMEM_NCOH = 0x00000003
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION = (0x2080110d)
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_VIDMEM = 0x00000000
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_APERTURE_SYSMEM = 0x00000001
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_CACHED = 0x00000000
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_UNCACHED = 0X00000001
NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED = 0X00000002
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN = 0
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER = 1
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT = 2
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE = 3
NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE = 4
NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT = 3
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT = 0
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE = 1
NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE = 2
NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG = (0x2080110e)
NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT = 32
NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS = 8
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES = 200
NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE = (0x20801112)
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES = 256
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES = 32
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES = 16
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA = 2
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN = 16
NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT = (0x20801113)
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_ENGINE = 0x00000001
NV2080_CTRL_FIFO_CLEAR_FAULTED_BIT_FAULT_TYPE_PBDMA = 0x00000002
NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY = (0x20801115)
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_DEFAULT = 0x0
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED = 0x1
NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM = 0x2
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_FALSE = (0x00000000)
NV2080_CTRL_CMD_FIFO_RUNLIST_SET_SCHED_POLICY_FLAGS_RESTORE_TRUE = (0x00000001)
NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS_MESSAGE_ID = (0x15)
NV2080_CTRL_CMD_FIFO_UPDATE_CHANNEL_INFO = (0x20801116)
NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS_MESSAGE_ID = (0x16)
NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS = (0x20801117)
NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS_MESSAGE_ID = (0x17)
NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB = (0x20801118)
NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS = (0x20801119)
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS = 4096
NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID = (0x19)
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION = (0x2080111a)
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES = (64)
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0x1A)
NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 = (0x2080111b)
NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID = (0x1B)
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE = (0x20801120)
NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE = (0x20801121)
NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID = (0x21)
NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS = (0x20801122)
NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG = 128
NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO = (0x20801123)
NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID = (0x20801124)
NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID = (0x24)
NV2080_CTRL_CMD_FLA_RANGE = (0x20803501)
NV2080_CTRL_FLA_RANGE_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_NONE = 0x00000000
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_INITIALIZE = NVBIT(0)
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_DESTROY = NVBIT(1)
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE = NVBIT(2)
NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_DESTROY = NVBIT(3)
NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK = (0x20803502)
NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_FLA_GET_RANGE = (0x20803503)
NV2080_CTRL_FLA_GET_RANGE_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS = (0x20803504)
NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_MESSAGE_ID = (0x4)
FALCON_ID_PMU = (NV2080_ENGINE_TYPE_PMU)
FALCON_ID_DPU = (NV2080_ENGINE_TYPE_DPU)
FALCON_ID_SEC2 = (NV2080_ENGINE_TYPE_SEC2)
FALCON_ID_FBFLCN = (NV2080_ENGINE_TYPE_FBFLCN)
NV2080_CTRL_CMD_FLCN_GET_DMEM_USAGE = (0x20803101)
NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE = 0x00
NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END = 0x01
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN = 0x02
NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END = 0x03
NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK = 0x04
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN = 0x05
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END = 0x06
NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY = 0x07
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT = 0x08
NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 = 0x09
NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END = 0x0A
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN = 0x0B
NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END = 0x0C
NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY = 0x0D
NV2080_CTRL_FLCN_NVOS_INST_INVALID_TASK_ID = 0xFF
NV2080_CTRL_CMD_FLCN_GET_ENGINE_ARCH = (0x20803118)
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT = 0x0
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON = 0x1
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV = 0x2
NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB = 0x3
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_EXTENT = (27)
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTID_DRF_BASE = (20)
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_EXTENT = (28)
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_EVENTIDCOMPACT_DRF_BASE = (24)
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_YIELD = 0x0
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_INT0 = 0x1
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_TIMER_TICK = 0x2
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_QUEUE_BLOCK = 0x3
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_CTXSW_END_REASON_DMA_SUSPENDED = 0x4
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE = 0xF0
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_RM_QUEUE_LATENCY_SHIFT = 10
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_RESERVED = 0x000000
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_SPECIAL_EVENT_ID_CB_ENQUEUE_FAIL = 0x000001
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_LATENCY_SHIFT = 6
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_INVALID = 0x000
NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_GENERIC_ID_VF_SWITCH_TOTAL = 0x001
NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT = 0
NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON = 1
NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT = 2
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_DISABLED = 0
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IDLE_FLUSH_ENABLED = 1
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_DISABLED = 0
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_FULL_FLUSH_ENABLED = 1
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_DISABLED = 0
NV2080_CTRL_FLCN_USTREAMER_QUEUE_POLICY_IMMEDIATE_FLUSH_ENABLED = 1
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES_COMPACT = (0x20)
NV2080_CTRL_FLCN_USTREAMER_NUM_EVT_TYPES = (0x120)
NV2080_CTRL_FLCN_USTREAMER_MASK_SIZE_BYTES = (0x24)
NV2080_CTRL_CMD_FLCN_USTREAMER_QUEUE_INFO = (0x20803120)
NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET = (0x20803122)
NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET = (0x20803123)
NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO = (0x20803124)
NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x24)
NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = (0x20803125)
NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x25)
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION = (0x20802300)
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID = (0x00)
NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT = (0x20802301)
NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID = (0x01)
NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT = (0x20802302)
NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID = (0x02)
NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION = (0x20802303)
NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID = (0x03)
NV_GRID_LICENSE_INFO_MAX_LENGTH = (128)
NV_GRID_LICENSE_FEATURE_VPC_EDITION = "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
NV_GRID_LICENSE_FEATURE_VAPPS_EDITION = "GRID-Virtual-Apps,3.0"
NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION = "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
NV_GRID_LICENSE_FEATURE_GAMING_EDITION = "GRID-vGaming,8.0"
NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION = "NVIDIA-vComputeServer,9.0"
NV_GRID_LICENSED_PRODUCT_VWS = "NVIDIA RTX Virtual Workstation"
NV_GRID_LICENSED_PRODUCT_GAMING = "NVIDIA Cloud Gaming"
NV_GRID_LICENSED_PRODUCT_VPC = "NVIDIA Virtual PC"
NV_GRID_LICENSED_PRODUCT_VAPPS = "NVIDIA Virtual Applications"
NV_GRID_LICENSED_PRODUCT_COMPUTE = "NVIDIA Virtual Compute Server"
NV2080_CTRL_GPU_INFO_INDEX_ECID_LO32 = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_ECID_HI32 = (0x00000002)
NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT = (0x00000004)
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 = (0x00000012)
NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 = (0x00000013)
NV2080_CTRL_GPU_INFO_INDEX_ECID_EXTENDED = (0x0000001b)
NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS = (0x0000001f)
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD = (0x00000022)
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE = (0x00000025)
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED = (0x00000027)
NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED = (0x00000028)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT = (0x00000029)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE = (0x0000002a)
NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM = (0x0000002b)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION = (0x0000002c)
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY = (0x0000002d)
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM = (0x0000002f)
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY = (0x00000030)
NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE = (0x00000031)
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED = (0x00000033)
NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED = (0x00000034)
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED = (0x00000035)
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY = (0x00000036)
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY = (0x00000037)
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY = (0x0000003a)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY = (0x0000003b)
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU = (0x0000003c)
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY = (0x0000003d)
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED = (0x0000003f)
NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE = (0x00000041)
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE = (0x00000000)
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P = (0x00000001)
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V = (0x00000002)
NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV = (0x00000003)
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED = (0x00000000)
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED = (0x00000001)
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED = (0x00000002)
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING = (0x00000003)
NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING = (0x00000004)
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED = (0x00000000)
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED = (0x00000001)
NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED = (0x00000002)
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES = (0x00000001)
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO = (0x00000000)
NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES = (0x00000001)
NV2080_CTRL_CMD_GPU_GET_INFO = (0x20800101)
NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_GPU_GET_INFO_V2 = (0x20800102)
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_GPU_GET_NAME_STRING = (0x20800110)
NV2080_GPU_MAX_NAME_STRING_LENGTH = (0x0000040)
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII = (0x00000000)
NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE = (0x00000001)
NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID = (0x10)
NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = (0x20800111)
NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID = (0x11)
NV2080_CTRL_CMD_GPU_SET_POWER = (0x20800112)
NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 = (0x00000000)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 = (0x00000001)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 = (0x00000002)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 = (0x00000003)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 = (0x00000004)
NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 = (0x00000007)
NV2080_CTRL_CMD_GPU_GET_SDM = (0x20800118)
NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_CMD_GPU_SET_SDM = (0x20800120)
NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = (0x20800119)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID = (0x19)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE = (0x00000000)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL = (0x00000001)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL = (0x00000002)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL = (0x00000003)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL = (0x00000004)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU = (0x00000005)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER = (0x00000006)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA = (0x00000007)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL = (0x00000008)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL = (0x00000009)
NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN = (0xFFFFFFFF)
NV2080_CTRL_GPU_REG_OP_READ_32 = (0x00000000)
NV2080_CTRL_GPU_REG_OP_WRITE_32 = (0x00000001)
NV2080_CTRL_GPU_REG_OP_READ_64 = (0x00000002)
NV2080_CTRL_GPU_REG_OP_WRITE_64 = (0x00000003)
NV2080_CTRL_GPU_REG_OP_READ_08 = (0x00000004)
NV2080_CTRL_GPU_REG_OP_WRITE_08 = (0x00000005)
NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL = (0x00000000)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX = (0x00000001)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC = (0x00000002)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM = (0x00000004)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP = (0x00000008)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP = (0x00000010)
NV2080_CTRL_GPU_REG_OP_TYPE_FB = (0x00000020)
NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD = (0x00000040)
NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE = (0x00000080)
NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS = (0x00)
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP = (0x01)
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE = (0x02)
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET = (0x04)
NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP = (0x08)
NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK = (0x10)
NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS = (0x20)
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = (0x20800122)
NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_GPU_GET_ENGINES = (0x20800123)
NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 = (0x20800170)
NV2080_GPU_MAX_ENGINES_LIST_SIZE = 0x54
NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID = (0x70)
NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST = (0x20800124)
NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID = (0x24)
NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO = (0x20800125)
NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID = (0x25)
NV2080_CTRL_CMD_GPU_QUERY_MODE = (0x20800128)
NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE = (0x00000000)
NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE = (0x00000001)
NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE = (0x00000002)
NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN = 0
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM = 1
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH = 2
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB = 3
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL = 4
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB = 5
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL = 6
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL = 7
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK = 8
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT = 9
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP = 10
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP = 11
NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP = 12
NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES = 16
NV2080_CTRL_CMD_GPU_PROMOTE_CTX = (0x2080012b)
NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID = (0x2B)
NV2080_CTRL_CMD_GPU_EVICT_CTX = (0x2080012c)
NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID = (0x2C)
NV2080_CTRL_CMD_GPU_INITIALIZE_CTX = (0x2080012d)
NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID = (0x2D)
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM = (0x00000000)
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS = (0x00000001)
NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS = (0x00000002)
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES = (0x00000000)
NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO = (0x00000001)
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO = (0x00000000)
NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES = (0x00000001)
NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR = (0x2080012e)
NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = (0x2080012f)
NV2080_CTRL_GPU_ECC_UNIT_GSP = (0x0000001D)
NV2080_CTRL_GPU_ECC_UNIT_COUNT = (0x00000024)
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED = (0x00000000)
NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW = (0x00000001)
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE = 0
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE = 1
NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE = 2
NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID = (0x2F)
NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES = (0x20800130)
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE = (0x00000000)
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE = (0x00000001)
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED = (0x00000002)
NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS = (0x00000003)
NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x30)
NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = (0x20800131)
NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID = (0x31)
NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = (0x20800133)
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED = (0x00000000)
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED = (0x00000001)
NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x33)
NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION = (0x20800134)
NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE = (0x00000000)
NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE = (0x00000001)
NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID = (0x34)
NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS = (0x20800136)
NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE = (0x00000000)
NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE = (0x00000001)
NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE = (0x00000002)
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE = 0
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE = 1
NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID = (0x36)
NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO = (0x20800137)
NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID = (0x37)
NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO = (0x20800138)
NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID = (0x38)
NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO = (0x20800139)
NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x39)
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = (0x2080013f)
NV2080_GPU_MAX_MARKETING_NAME_LENGTH = (0x00000018)
NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH = (0x00000010)
NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH = (0x00000014)
NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH = (0x00000006)
NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH = (0x00000014)
NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID = (0x3F)
NV2080_CTRL_CMD_GPU_GET_ID = (0x20800142)
NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID = (0x42)
NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE = (0x20800143)
NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x43)
NV2080_CTRL_GPU_DEBUG_MODE_ENABLED = (0x00000001)
NV2080_CTRL_GPU_DEBUG_MODE_DISABLED = (0x00000002)
NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE = (0x20800144)
NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID = (0x44)
NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = (0x20800147)
NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS = (0x00000020)
NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID = (0x47)
NV2080_CTRL_CMD_GPU_GET_GID_INFO = (0x2080014a)
NV2080_GPU_MAX_GID_LENGTH = (0x000000100)
NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH = (0x000000010)
NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID = (0x4A)
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII = (0x00000000)
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY = (0x00000002)
NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 = (0x00000000)
NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = (0x2080014b)
NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN = 3
NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID = (0x4B)
NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO = (0x2080014c)
NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID = (0x4C)
NV2080_CTRL_CMD_GPU_GET_IP_VERSION = (0x2080014d)
NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4D)
NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY = (0x00000001)
NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC = (0x00000002)
NV2080_CTRL_GPU_GET_IP_VERSION_PMGR = (0x00000003)
NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU = (0x00000004)
NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON = (0x00000005)
NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS = 0
NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS = 1
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT = (0x20800153)
NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID = (0x53)
NV2080_CTRL_CMD_GPU_GET_ILLUM = (0x20800154)
NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID = (0x54)
NV2080_CTRL_CMD_GPU_SET_ILLUM = (0x20800155)
NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0x55)
NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = (0x20800156)
NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN = 16
NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID = (0x56)
NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT = (0x20800157)
NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO = (0x2080015a)
NV2080_CTRL_MAX_PHYSICAL_BRIDGE = (100)
NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID = (0x5A)
NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU = (0x2080015b)
NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID = (0x5B)
NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS = (0x2080015f)
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID = (0x5F)
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING = (0x00000000)
NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE = (0x00000001)
NV2080_CTRL_CMD_GPU_GET_VPR_CAPS = (0x20800160)
NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID = (0x60)
NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR = (0x20800167)
NV2080_CTRL_CMD_GPU_GET_PES_INFO = (0x20800168)
NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT = 10
NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID = (0x68)
NV2080_CTRL_CMD_GPU_GET_OEM_INFO = (0x20800169)
NV2080_GPU_MAX_OEM_INFO_LENGTH = (0x000001F8)
NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID = (0x69)
NV2080_CTRL_CMD_GPU_GET_VPR_INFO = (0x2080016b)
NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID = (0x6B)
NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY = (0x2080016c)
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x6C)
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS = (0x2080016d)
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x6D)
NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES = 0x200
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x6E)
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO = (0x2080016e)
NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x6F)
NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR = (0x2080016f)
NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID = (0x72)
NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT = (0x20800172)
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID = (0x73)
NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS = (0x20800173)
NV_GI_UUID_LEN = 16
NV2080_CTRL_GPU_PARTITION_ID_INVALID = 0xFFFFFFFF
NV2080_CTRL_GPU_MAX_PARTITIONS = 0x00000008
NV2080_CTRL_GPU_MAX_PARTITION_IDS = 0x00000009
NV2080_CTRL_GPU_MAX_SMC_IDS = 0x00000008
NV2080_CTRL_GPU_MAX_GPC_PER_SMC = 0x0000000c
NV2080_CTRL_GPU_MAX_CE_PER_SMC = 0x00000008
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL = 0x00000000
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF = 0x00000001
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER = 0x00000002
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH = 0x00000003
NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE = 4
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL = 0x00000000
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF = 0x00000001
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF = 0x00000002
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER = 0x00000003
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER = 0x00000004
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH = 0x00000005
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_06 = 0x00000006
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 = 0x00000007
NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE = 8
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL = 0x00000001
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF = 0x00000002
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF = 0x00000003
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER = 0x00000004
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH = 0x00000005
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 = 0x00000006
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 = 0x00000007
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE = 0x00000000
NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE = 8
NV2080_CTRL_GPU_PARTITION_MAX_TYPES = 40
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE = 0
NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE = 1
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE = 0
NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE = 1
NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID = (0x74)
NV2080_CTRL_CMD_GPU_SET_PARTITIONS = (0x20800174)
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID = (0x75)
NV2080_CTRL_CMD_GPU_GET_PARTITIONS = (0x20800175)
NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION = (0x20800176)
NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID = (0x76)
NV2080_CTRL_GPU_FAULT_PACKET_SIZE = 32
NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT = (0x20800177)
NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID = (0x77)
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU = (0x20800178)
NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID = (0x78)
NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE = (0x20800179)
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID = (0x79)
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL = (0xFFFFFFFF)
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR = (0xFFFFFFFB)
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID = (0xFFFFFFFF)
NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR = (0xFFFFFFFB)
NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID = (0x2080017a)
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID = (0x7A)
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL = (0xFFFFFFFF)
NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR = (0xFFFFFFFB)
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS = (0x2080017b)
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID = (0x7B)
NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED = 0x00000001
NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED = 0x00000002
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT = 0x00000004
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE = 0x00000008
NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT = 0x00000010
NV2080_GPU_NVFBC_MAX_SESSION_COUNT = 256
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID = (0x7C)
NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO = (0x2080017c)
NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID = (0xe6)
NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX = (0x208001e6)
NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE = (0x2080017e)
NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID = (0x7E)
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB = 0x02000000
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB = 0x04000000
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB = 0x08000000
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB = 0x10000000
NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB = 0x20000000
NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY = (0x20800181)
NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID = (0x81)
NV2080_CTRL_CMD_GPU_GET_CACHED_INFO = (0x20800182)
NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID = (0x82)
NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE = (0x20800183)
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY = 0
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF = 1
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG = 2
NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0x83)
NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID = (0x85)
NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS = (0x20800185)
NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE = (0x20800188)
NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID = (0x88)
NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID = (0x8A)
NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC = (0x2080018a)
NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID = (0x8B)
NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS = (0x2080018b)
NV2080_CTRL_CMD_GPU_GET_PIDS = (0x2080018d)
NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT = 950
NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID = (0x8D)
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS = (0x00000000)
NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST = (0x00000001)
NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE = (0x00000000)
NV2080_CTRL_GPU_PID_INFO_INDEX_MAX = NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE
NV2080_CTRL_CMD_GPU_GET_PID_INFO = (0x2080018e)
NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT = 200
NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID = (0x8E)
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT = (0x20800192)
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID = 0
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 = 1
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 = 2
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL = 3
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE = 4
NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID = (0x92)
NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE = 0
NV2080_CTRL_GPU_COMPUTE_POLICY_MAX = 1
NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x94)
NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = (0x20800195)
NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX = 32
NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID = (0x95)
NV2080_CTRL_CMD_GPU_GET_GFID = (0x20800196)
NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID = (0x96)
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY = (0x20800197)
NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID = (0x97)
NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST = (0x20800198)
NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID = (0x98)
NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR = (0x20800199)
NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID = (0x99)
NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES = (0x2080019b)
NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS = 0xC8
NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID = (0x9B)
NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING = (0x2080019c)
NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID = (0x9C)
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS = (0x2080019d)
NV2080_CTRL_REG_OPS_ARRAY_MAX = 100
NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID = (0x9D)
NV2080_GET_P2P_CAPS_UUID_LEN = 16
NV2080_CTRL_CMD_GET_P2P_CAPS = (0x208001a0)
NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xA0)
NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xA2)
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES = (0x208001a2)
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED = 0
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED = 1
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS = 2
NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE = 3
NV2080_GPU_FABRIC_CLUSTER_UUID_LEN = 16
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED = 0
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE = 1
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE = 2
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED = 0
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE = 1
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE = 2
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED = 0
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE = 1
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE = 2
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED = 0
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE = 1
NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE = 2
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xA3)
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = (0x208001a3)
NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = (0x208001a4)
GPU_PART_NUMBER_FMT = "%4X-%s-%X%X"
NV2080_MAX_CHIP_SKU_LENGTH = 0x00000004
NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID = (0xA4)
NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP = (0x208001a5)
NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID = (0xA5)
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS = (0x208001a6)
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP = (0x208001a7)
NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU = (0x208001a8)
NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX = 50
NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID = (0xA6)
NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID = (0xA7)
NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID = (0xA8)
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET = (0x208001a9)
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET = (0x208001aa)
NV2080_CTRL_CMD_GPU_GET_RESET_STATUS = (0x208001ab)
NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAB)
NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ac)
NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET = (0x208001ad)
NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS = (0x208001ae)
NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID = (0xAE)
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID = (0xAF)
NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 = (0x208001af)
NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS = 0x40
NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO = (0x208001b0)
NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID = (0xB0)
NV2080_CTRL_CMD_GPU_GET_VF_CAPS = (0x208001b1)
NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID = (0xB1)
NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = (0x208001b2)
NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID = (0xB2)
NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID = (0xe4)
NV2080_CTRL_GPU_GET_FIPS_STATUS = (0x208001e4)
NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU = 0x2
NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU = 0xC
NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC = (0x18)
NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT = (0x1a)
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID = (0xB3)
NV2080_CTRL_GPU_GET_RAFTS_FS_MASK = (0x208001b3)
NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY = (0x208001e5)
NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID = (0xe5)
NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK = (0x208001e7)
NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0xe7)
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PWR_MONITOR_STATUS = 0x00000001
NV2080_CTRL_GPUMON_SAMPLE_TYPE_PERFMON_UTIL = 0x00000002
NV2080_GPUMON_PID_INVALID = ((NvU32)(~0))
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_NONE = 0x0
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_ENGID = 0x1
NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL = 0x2
NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS = NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 = NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK = NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT = NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE = NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR = NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT = NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT = NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
NV2080_CTRL_GR_INFO_INDEX_SM_VERSION = NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP = NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES = NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY = NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM = NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED = NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT = NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC = NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT = NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES
NV2080_CTRL_GR_INFO_INDEX_DUMMY = NV0080_CTRL_GR_INFO_INDEX_DUMMY
NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES = NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES = NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS = NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG = NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET
NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET = NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET
NV2080_CTRL_GR_INFO_INDEX_MAX = NV0080_CTRL_GR_INFO_INDEX_MAX
NV2080_CTRL_GR_INFO_MAX_SIZE = NV0080_CTRL_GR_INFO_MAX_SIZE
NV2080_CTRL_GR_INFO_SM_VERSION_NONE = (0x00000000)
NV2080_CTRL_GR_INFO_SM_VERSION_1_05 = (0x00000105)
NV2080_CTRL_GR_INFO_SM_VERSION_1_1 = (0x00000110)
NV2080_CTRL_GR_INFO_SM_VERSION_1_2 = (0x00000120)
NV2080_CTRL_GR_INFO_SM_VERSION_1_3 = (0x00000130)
NV2080_CTRL_GR_INFO_SM_VERSION_1_4 = (0x00000140)
NV2080_CTRL_GR_INFO_SM_VERSION_1_5 = (0x00000150)
NV2080_CTRL_GR_INFO_SM_VERSION_2_0 = (0x00000200)
NV2080_CTRL_GR_INFO_SM_VERSION_2_1 = (0x00000210)
NV2080_CTRL_GR_INFO_SM_VERSION_2_2 = (0x00000220)
NV2080_CTRL_GR_INFO_SM_VERSION_3_0 = (0x00000300)
NV2080_CTRL_GR_INFO_SM_VERSION_3_1 = (0x00000310)
NV2080_CTRL_GR_INFO_SM_VERSION_3_2 = (0x00000320)
NV2080_CTRL_GR_INFO_SM_VERSION_3_3 = (0x00000330)
NV2080_CTRL_GR_INFO_SM_VERSION_3_5 = (0x00000350)
NV2080_CTRL_GR_INFO_SM_VERSION_3_6 = (0x00000360)
NV2080_CTRL_GR_INFO_SM_VERSION_3_8 = (0x00000380)
NV2080_CTRL_GR_INFO_SM_VERSION_3_9 = (0x00000390)
NV2080_CTRL_GR_INFO_SM_VERSION_4_0 = (0x00000400)
NV2080_CTRL_GR_INFO_SM_VERSION_5_0 = (0x00000500)
NV2080_CTRL_GR_INFO_SM_VERSION_5_02 = (0x00000502)
NV2080_CTRL_GR_INFO_SM_VERSION_5_03 = (0x00000503)
NV2080_CTRL_GR_INFO_SM_VERSION_6_0 = (0x00000600)
NV2080_CTRL_GR_INFO_SM_VERSION_6_01 = (0x00000601)
NV2080_CTRL_GR_INFO_SM_VERSION_6_02 = (0x00000602)
NV2080_CTRL_GR_INFO_SM_VERSION_7_0 = (0x00000700)
NV2080_CTRL_GR_INFO_SM_VERSION_7_01 = (0x00000701)
NV2080_CTRL_GR_INFO_SM_VERSION_7_02 = (0x00000702)
NV2080_CTRL_GR_INFO_SM_VERSION_7_03 = (0x00000703)
NV2080_CTRL_GR_INFO_SM_VERSION_7_05 = (0x00000705)
NV2080_CTRL_GR_INFO_SM_VERSION_8_02 = (0x00000802)
NV2080_CTRL_GR_INFO_SM_VERSION_8_06 = (0x00000806)
NV2080_CTRL_GR_INFO_SM_VERSION_8_07 = (0x00000807)
NV2080_CTRL_GR_INFO_SM_VERSION_8_08 = (0x00000808)
NV2080_CTRL_GR_INFO_SM_VERSION_8_09 = (0x00000809)
NV2080_CTRL_GR_INFO_SM_VERSION_9_00 = (0x00000900)
NV2080_CTRL_GR_INFO_SM_VERSION_10_00 = (0x00000A00)
NV2080_CTRL_GR_INFO_SM_VERSION_10_01 = (0x00000A01)
NV2080_CTRL_GR_INFO_SM_VERSION_10_04 = (0x00000A04)
NV2080_CTRL_GR_INFO_SM_VERSION_5_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
NV2080_CTRL_GR_INFO_SM_VERSION_5_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
NV2080_CTRL_GR_INFO_SM_VERSION_6_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
NV2080_CTRL_GR_INFO_SM_VERSION_6_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
NV2080_CTRL_GR_INFO_SM_VERSION_7_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
NV2080_CTRL_GR_INFO_SM_VERSION_7_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
NV2080_CTRL_GR_INFO_SM_VERSION_7_3 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
NV2080_CTRL_GR_INFO_SM_VERSION_7_5 = (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
NV2080_CTRL_GR_INFO_SM_VERSION_8_2 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
NV2080_CTRL_GR_INFO_SM_VERSION_8_6 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
NV2080_CTRL_GR_INFO_SM_VERSION_8_7 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
NV2080_CTRL_GR_INFO_SM_VERSION_8_8 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
NV2080_CTRL_GR_INFO_SM_VERSION_8_9 = (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
NV2080_CTRL_GR_INFO_SM_VERSION_9_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
NV2080_CTRL_GR_INFO_SM_VERSION_10_0 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
NV2080_CTRL_GR_INFO_SM_VERSION_10_1 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
NV2080_CTRL_GR_INFO_SM_VERSION_10_4 = (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE = 0x0
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE = 0x1
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE = 0x0
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE = 0x1
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE = 0x0
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE = 0x1
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE = 0x0
NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE = 0x1
NV2080_CTRL_CMD_GR_GET_INFO = (0x20801201)
NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE = (0x20801205)
NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_CTXSW_ZCULL_MODE_GLOBAL = (0x00000000)
NV2080_CTRL_CTXSW_ZCULL_MODE_NO_CTXSW = (0x00000001)
NV2080_CTRL_CTXSW_ZCULL_MODE_SEPARATE_BUFFER = (0x00000002)
NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = (0x20801206)
NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x6)
NV2080_CTRL_CMD_GR_CTXSW_PM_MODE = (0x20801207)
NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW = (0x00000000)
NV2080_CTRL_CTXSW_PM_MODE_CTXSW = (0x00000001)
NV2080_CTRL_CTXSW_PM_MODE_STREAM_OUT_CTXSW = (0x00000002)
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = (0x20801208)
NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_GR_CTXSW_PM_BIND = (0x20801209)
NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND = (0x2080123a)
NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0x3A)
NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES = 128
NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP = (0x2080120a)
NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE = (0x2080120e)
NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CTXSW_SMPC_MODE_NO_CTXSW = (0x00000000)
NV2080_CTRL_CTXSW_SMPC_MODE_CTXSW = (0x00000001)
NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = (0x2080120f)
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT = 240
NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID = (0xF)
NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = (0x20801210)
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID = (0x10)
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_IGNORE = (0x00000000)
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_CILP_SET = (0x00000001)
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_IGNORE = (0x00000000)
NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_FLAGS_GFXP_SET = (0x00000001)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI = (0x00000000)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP = (0x00000001)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP_POOL = (0x00000002)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_WFI = (0x00000000)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CTA = (0x00000001)
NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_COMPUTE_CILP = (0x00000002)
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND = (0x20801211)
NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID = (0x11)
NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE = (0x20801212)
NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_PC_SAMPLING_MODE_DISABLED = (0x00000000)
NV2080_CTRL_PC_SAMPLING_MODE_ENABLED = (0x00000001)
NV2080_CTRL_CMD_GR_GET_ROP_INFO = (0x20801213)
NV2080_CTRL_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_CMD_GR_GET_CTXSW_STATS = (0x20801215)
NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID = (0x15)
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_FALSE = (0x00000000)
NV2080_CTRL_GR_GET_CTXSW_STATS_FLAGS_RESET_TRUE = (0x00000001)
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = (0x20801218)
NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT = 64
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_INFO = (0x20801219)
NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_MESSAGE_ID = (0x19)
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN = 0
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM = 1
NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM = 2
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = (0x2080121b)
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT = 512
NV2080_CTRL_GR_DISABLED_SM_VGPC_ID = 0xFF
NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x1B)
NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL = (0x2080121c)
NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID = (0x1C)
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT = 10
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT = 10
NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA = (0x2080121d)
NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID = (0x1D)
NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE = (0x2080121e)
NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS_MESSAGE_ID = (0x1E)
NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE = (0x2080121f)
NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID = (0x1F)
NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE = (0x20801220)
NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS = 64
NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS = (0x20801221)
NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID = (0x21)
NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS = (0x20801222)
NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_GR_GET_CAPS_V2 = (0x20801227)
NV2080_CTRL_GR_GET_CAPS_V2_PARAMS_MESSAGE_ID = (0x27)
NV2080_CTRL_CMD_GR_GET_INFO_V2 = (0x20801228)
NV2080_CTRL_GR_GET_INFO_V2_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_CMD_GR_GET_GPC_MASK = (0x2080122a)
NV2080_CTRL_GR_GET_GPC_MASK_PARAMS_MESSAGE_ID = (0x2A)
NV2080_CTRL_CMD_GR_GET_TPC_MASK = (0x2080122b)
NV2080_CTRL_GR_GET_TPC_MASK_PARAMS_MESSAGE_ID = (0x2B)
NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = (0x2080122c)
NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID = (0x2C)
NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES = (0x2080122d)
NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID = (0x2D)
NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER = (0x20801230)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA0_REDUCED_SPEED_1_64 = (0x6)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA16_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_DP_REDUCED_SPEED = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FMLA32_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_FFMA_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA1_REDUCED_SPEED_1_64 = (0x6)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA2_REDUCED_SPEED_1_64 = (0x6)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA3_REDUCED_SPEED_1_64 = (0x6)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_FULL_SPEED = (0x0)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_2 = (0x1)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_4 = (0x2)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_8 = (0x3)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_16 = (0x4)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_32 = (0x5)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_IMLA4_REDUCED_SPEED_1_64 = (0x6)
NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x30)
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID = (0x20801231)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS_MESSAGE_ID = (0x31)
NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK = (0x20801232)
NV2080_CTRL_GR_GET_PHYS_GPC_MASK_PARAMS_MESSAGE_ID = (0x32)
NV2080_CTRL_CMD_GR_GET_PPC_MASK = (0x20801233)
NV2080_CTRL_GR_GET_PPC_MASK_PARAMS_MESSAGE_ID = (0x33)
NV2080_CTRL_CMD_GR_GET_NUM_TPCS_FOR_GPC = (0x20801234)
NV2080_CTRL_GR_GET_NUM_TPCS_FOR_GPC_PARAMS_MESSAGE_ID = (0x34)
NV2080_CTRL_CMD_GR_GET_CTXSW_MODES = (0x20801235)
NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x35)
NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP = (0x20801236)
NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID = (0x36)
NV2080_CTRL_CMD_GR_GET_ZCULL_MASK = (0x20801237)
NV2080_CTRL_GR_GET_ZCULL_MASK_PARAMS_MESSAGE_ID = (0x37)
NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID_V2 = (0x20801238)
NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS_MESSAGE_ID = (0x38)
NV2080_CTRL_CMD_GR_GET_GFX_GPC_AND_TPC_INFO = (0x20801239)
NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS_MESSAGE_ID = (0x39)
NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK = (0x2080123b)
NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID = (0x3b)
NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO = (0x20803801)
NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES = 96
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_MAX_SIZE = 32
NV2080_CTRL_GRMGR_MAX_SMC_IDS = 8
NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_INVALID = 0
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT = 1
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP = 2
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK = 3
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK = 4
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP = 5
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK = 6
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS = 7
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK = 8
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID = 9
NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK = 10
NV2080_CTRL_CMD_GSP_GET_FEATURES = (0x20803601)
NV2080_GSP_MAX_BUILD_VERSION_LENGTH = (0x0000040)
NV2080_CTRL_GSP_GET_FEATURES_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE = (0x00000000)
NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE = (0x00000001)
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE = (0x00000000)
NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE = (0x00000001)
NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS = (0x20803602)
NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS = (0x20803603)
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS = (0x20803604)
NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX = 64
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK = (0x20804101)
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE = (0x20804102)
NV2080_CTRL_I2C_VERSION_0 = 0x00
NV2080_CTRL_I2C_MAX_ENTRIES = 256
NV2080_CTRL_I2C_MAX_REG_LEN = 8
NV2080_CTRL_I2C_MAX_ADDR_ENTRIES = 20
NV2080_CTRL_I2C_FLAGS_NONSTD_SI1930UC = (0x00000001)
NV2080_CTRL_I2C_FLAGS_PRIVILEGE = (0x00000002)
NV2080_CTRL_I2C_FLAGS_DATA_ENCRYPTED = (0x00000004)
NV2080_CTRL_I2C_FLAGS_PX3540 = (0x00000010)
NV2080_CTRL_I2C_FLAGS_ADDR_AUTO_INC_NOT_SUPPORTED = (0x00000008)
NV2080_CTRL_I2C_READ_BUFFER_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_I2C_READ_BUFFER = (0x20800601)
NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_I2C_WRITE_BUFFER = (0x20800602)
NV2080_CTRL_CMD_I2C_READ_REG = (0x20800603)
NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_I2C_WRITE_REG = (0x20800604)
NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_I2C_ACCESS = (0x20800610)
NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID = (0x10)
NV2080_CTRL_I2C_ACCESS_CMD_ACQUIRE = 0x1
NV2080_CTRL_I2C_ACCESS_CMD_RELEASE = 0x2
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BYTE = 0x3
NV2080_CTRL_I2C_ACCESS_CMD_READ_BYTE = 0x4
NV2080_CTRL_I2C_ACCESS_CMD_NULL = 0x5
NV2080_CTRL_I2C_ACCESS_CMD_RESET = 0x6
NV2080_CTRL_I2C_ACCESS_CMD_TEST_PORT = 0x11
NV2080_CTRL_I2C_ACCESS_CMD_SET_FAST_MODE = 0x12
NV2080_CTRL_I2C_ACCESS_CMD_SET_NORMAL_MODE = 0x13
NV2080_CTRL_I2C_ACCESS_CMD_WRITE_BUFFER = 0x14
NV2080_CTRL_I2C_ACCESS_CMD_READ_BUFFER = 0x15
NV2080_CTRL_I2C_ACCESS_CMD_START = 0x17
NV2080_CTRL_I2C_ACCESS_CMD_STOP = 0x18
NV2080_CTRL_I2C_ACCESS_CMD_SET_SLOW_MODE = 0x20
NV2080_CTRL_I2C_ACCESS_FLAG_START = 0x1
NV2080_CTRL_I2C_ACCESS_FLAG_STOP = 0x2
NV2080_CTRL_I2C_ACCESS_FLAG_ACK = 0x4
NV2080_CTRL_I2C_ACCESS_FLAG_RAB = 0x8
NV2080_CTRL_I2C_ACCESS_FLAG_ADDR_10BITS = 0x10
NV2080_CTRL_I2C_ACCESS_FLAG_PRIVILEGE = 0x20
NV2080_CTRL_I2C_ACCESS_FLAG_DATA_ENCRYPTED = 0x40
NV2080_CTRL_I2C_ACCESS_FLAG_RESTART = 0x80
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33_33PCT = 0x100
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_33PCT = 0x200
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_10PCT = 0x400
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3_33PCT = 0x800
NV2080_CTRL_I2C_ACCESS_FLAG_SLOW_MODE_3PCT = 0x1000
NV2080_CTRL_I2C_ACCESS_PORT_DYNAMIC = 0x0
NV2080_CTRL_I2C_ACCESS_PORT_PRIMARY = 0x1
NV2080_CTRL_I2C_ACCESS_PORT_SECONDARY = 0x2
NV2080_CTRL_I2C_ACCESS_PORT_TERTIARY = 0x3
NV2080_CTRL_I2C_ACCESS_PORT_QUARTIARY = 0x4
NV2080_CTRL_I2C_ACCESS_PORT_1 = 0x1
NV2080_CTRL_I2C_ACCESS_PORT_2 = 0x2
NV2080_CTRL_I2C_ACCESS_PORT_3 = 0x3
NV2080_CTRL_I2C_ACCESS_PORT_4 = 0x4
NV2080_CTRL_I2C_ACCESS_PORT_5 = 0x5
NV2080_CTRL_I2C_ACCESS_PORT_6 = 0x6
NV2080_CTRL_I2C_ACCESS_PORT_7 = 0x7
NV2080_CTRL_I2C_ACCESS_PORT_8 = 0x8
NV2080_CTRL_I2C_ACCESS_PORT_9 = 0x9
NV2080_CTRL_I2C_ACCESS_PORT_10 = 0x10
NV2080_CTRL_I2C_ACCESS_NUM_PORTS = NV2080_CTRL_I2C_ACCESS_PORT_10
NV2080_CTRL_I2C_ACCESS_STATUS_SUCCESS = 0x0
NV2080_CTRL_I2C_ACCESS_STATUS_ERROR = 0x1
NV2080_CTRL_I2C_ACCESS_STATUS_PROTOCOL_ERROR = 0x2
NV2080_CTRL_I2C_ACCESS_STATUS_DEVICE_BUSY = 0x3
NV2080_CTRL_I2C_ACCESS_STATUS_NACK_AFTER_SEND = 0x4
NV2080_CTRL_I2C_ACCESS_STATUS_DP2TMDS_DONGLE_MISSING = 0x5
NV2080_CTRL_CMD_I2C_ENABLE_MONITOR_3D_MODE = (0x20800620)
NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01)
NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG = (0x20800a1c)
NV2080_CTRL_CMD_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER = (0x20800a1d)
NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES = 64
NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1D)
NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER = (0x20800a1e)
NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID = (0x1E)
NV2080_CTRL_INTERNAL_GR_MAX_ENGINES = 8
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID = (0x20)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS = (0x20800a1f)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID = (0x1F)
NV2080_CTRL_INTERNAL_GR_MAX_SM = 240
NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER = (0x20800a22)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID = (0x22)
NV2080_CTRL_CMD_INTERNAL_MAX_BSPS = 8
NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS = 8
NV2080_CTRL_INTERNAL_GR_MAX_GPC = 12
NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT = 10
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x27)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS = (0x20800a26)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID = (0x26)
NV2080_CTRL_KGR_MAX_BUFFER_PTES = 128
NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES = (0x20800a28)
NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID = (0x2B)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO = (0x20800a2a)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID = (0x2A)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2D)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO = (0x20800a2c)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID = (0x2C)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2F)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO = (0x20800a2e)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID = (0x2E)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x31)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS = (0x20800a30)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID = (0x30)
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT = 0x1a
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x33)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO = (0x20800a32)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID = (0x32)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x35)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER = (0x20800a34)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID = (0x34)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_CHIP_INFO = (0x20800a36)
NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX = 16
NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS_MESSAGE_ID = (0x36)
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE = (0x20800a37)
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE = (0x20800a38)
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x37)
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID = (0x38)
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET = (0x20800a39)
NV2080_CTRL_CMD_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET = (0x20800a3a)
NV2080_CTRL_CMD_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET = (0x20800a3b)
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x39)
NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID = (0x3A)
NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID = (0x3B)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE = (0x20800a3d)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3C)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID = (0x3D)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3E)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES = (0x20800a3f)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID = (0x3F)
NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES = 512
NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE = (0x20800a40)
NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID = (0x40)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP = (0x20800a41)
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_COMPRESSED_SIZE = 4096
NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES = 4096
NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS_MESSAGE_ID = (0x41)
NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x43)
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a44)
NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID = (0x44)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE = (0x20800a43)
NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x45)
NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR = (0x20800a46)
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID = (0x46)
NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x47)
NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES = (0x20800a48)
NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID = (0x48)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM = (0x20800a49)
NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID = (0x49)
NV2080_CTRL_CMD_INTERNAL_RECOVER_ALL_COMPUTE_CONTEXTS = (0x20800a4a)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION = (0x20800a4b)
NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS_MESSAGE_ID = (0x4B)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE = (0x20800a4c)
NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS_MESSAGE_ID = (0x4C)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR = (0x20800a4d)
NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS_MESSAGE_ID = (0x4D)
NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES = 60
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x4F)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM = (0x20800a51)
NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS_MESSAGE_ID = (0x51)
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE = 4
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x52)
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS = 2
NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_ID = 64
NV2080_CTRL_CMD_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS = (0x20800a53)
NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS_MESSAGE_ID = (0x53)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_SET_IMP_INIT_INFO = (0x20800a54)
NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS_MESSAGE_ID = (0x54)
NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO = (0x20800a55)
NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID = (0x55)
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE = (0x00000000)
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM = (0x00000001)
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 = (0x00000002)
NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 = (0x00000003)
NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR = (0x20800a70)
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL = (0x20800a71)
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS_MESSAGE_ID = (0x71)
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE = (0x20800a72)
NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS_MESSAGE_ID = (0x72)
NV2080_CTRL_CMD_INTERNAL_BUS_DESTROY_P2P_MAILBOX = (0x20800a73)
NV2080_CTRL_INTERNAL_BUS_DESTROY_P2P_MAILBOX_PARAMS_MESSAGE_ID = (0x73)
NV2080_CTRL_CMD_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING = (0x20800a74)
NV2080_CTRL_INTERNAL_BUS_CREATE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x74)
NV2080_CTRL_CMD_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING = (0x20800a75)
NV2080_CTRL_INTERNAL_BUS_REMOVE_C2C_PEER_MAPPING_PARAMS_MESSAGE_ID = (0x75)
NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES = (0x20800a57)
NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES = 128
NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS_MESSAGE_ID = (0x57)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER = (0x20800a58)
NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID = (0x58)
NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO = (0x20800a59)
NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x59)
NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES = (0x20800a5a)
NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID = (0x5A)
NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE = (0x20800a5b)
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS_MESSAGE_ID = (0x5B)
NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE = (0x20800a5c)
NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE = 128
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID = (0x5C)
NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_GR = (0x00000000)
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK = (0x20800a98)
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS_MESSAGE_ID = (0x98)
NV2080_CTRL_CMD_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET = (0x20800a99)
NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS_MESSAGE_ID = (0x99)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES = (0x20800a5d)
NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS_MESSAGE_ID = (0x5D)
NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a60)
NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID = 15
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x60)
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS = (0x20800a61)
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS_MESSAGE_ID = (0x61)
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES = (0x20800a63)
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID = (0x63)
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES = (0x20800a65)
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID = (0x65)
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES = (0x20800a66)
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID = (0x66)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a68)
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x68)
NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG = (0x20800a67)
NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID = (0x67)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE = (0x20800a6b)
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE = 8
NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID = (0x6B)
NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT = (0x20800a6a)
NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE = (0x20800a7a)
NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR = (0x20800a7c)
NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE = (0x20800a81)
NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x81)
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X = (0x20800a9a)
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID = (0x9A)
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_PSTATE = 0
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK = 1
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_LAST = NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_GPCCLK
NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM = (0x2)
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_CONTROL = (0x20800a7e)
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID = (0x7E)
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS = (0x20800a7f)
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_MESSAGE_ID = (0x7F)
NV2080_CTRL_CMD_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO = (0x20800a80)
NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_GET_INFO_PARAMS_MESSAGE_ID = (0x80)
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER = (0x20800a9b)
NV2080_CTRL_INTERNAL_GMMU_FAULT_BUFFER_MAX_PAGES = 256
NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9B)
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER = (0x20800a9c)
NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE = (0x00000000)
NV2080_CTRL_FAULT_BUFFER_REPLAYABLE = (0x00000001)
NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9d)
NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES = 3000
NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9D)
NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER = (0x20800a9e)
NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID = (0x9E)
NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER = (0x20800a9f)
NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID = (0x9F)
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X = (0x20800aa0)
NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID = (0xA0)
NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_CLEAR_3X = (0x20800aa1)
NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X_MESSAGE_ID = (0xA1)
NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO = (0x20800aa2)
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES = 8
NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS = 12
NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID = (0xA2)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE = (0x20800aa3)
NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID = (0xA3)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE = (0x20800aa4)
NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA4)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES = (0x20800aa5)
NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA5)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES = (0x20800aa6)
NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID = (0xA6)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED = (0x20800a69)
NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID = (0x69)
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa7)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE = (0x20800aa8)
NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE = (0x20800aa9)
NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE = (0x20800aaa)
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE = 4
NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA7)
NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA8)
NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xA9)
NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID = (0xAA)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT = (0x20800a6c)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS_MESSAGE_ID = (0x6c)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL = (0x00000001)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_FIRST = (0x00000002)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_LAST = (0x00000004)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_NORMAL = (0x00000008)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN = (0x00000010)
NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL = (0x00000020)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_FLUSH_L2_ALL_RAMS_AND_CACHES = (0x20800a6d)
NV2080_CTRL_CMD_INTERNAL_BIF_GET_STATIC_INFO = (0x20800aac)
NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xac)
NV2080_CTRL_CMD_INTERNAL_HSHUB_PEER_CONN_CONFIG = (0x20800a88)
NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS_MESSAGE_ID = (0x88)
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS = (0x20800a8a)
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_TABLE_SIZE = 32
NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS_MESSAGE_ID = (0x8a)
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_NUM_UNITS = (0x20800a8b)
NV2080_CTRL_INTERNAL_HSHUB_GET_NUM_UNITS_PARAMS_MESSAGE_ID = (0x8b)
NV2080_CTRL_CMD_INTERNAL_HSHUB_NEXT_HSHUB_ID = (0x20800a8c)
NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS_MESSAGE_ID = (0x8c)
NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG = (0x20800a8d)
NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID = (0x8d)
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR = (0x20800aad)
NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS_MESSAGE_ID = (0xae)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR = (0x20800aae)
NV2080_CTRL_CMD_INTERNAL_BIF_GET_ASPM_L1_FLAGS = (0x20800ab0)
NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS_MESSAGE_ID = (0xb0)
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT = (0x20800ab1)
NV2080_CTRL_CMD_INTERNAL_PERF_CF_CONTROLLERS_MAX_ACTIVE_VGPU_VM_COUNT_MAX_VALUE = 32
NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS_MESSAGE_ID = (0xB1)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_DISABLE_NVLINK_PEERS = (0x20800a6e)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE = (0x20800a6f)
NV2080_CTRL_INTERNAL_MEMSYS_PROGRAM_RAW_COMPRESSION_MODE_PARAMS_MESSAGE_ID = (0x6f)
NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO = (0x20800ab2)
NV2080_CTRL_CMD_INTERNAL_CCU_MAP = (0x20800ab3)
NV2080_CTRL_INTERNAL_CCU_DEV_SHRBUF_COUNT_MAX = 1
NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS_MESSAGE_ID = (0xB3)
NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP = (0x20800ab4)
NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID = (0xB4)
NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS = (0x20800ab5)
NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB5)
NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS = (0x20800ab6)
NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB6)
NV2080_CTRL_CMD_INTERNAL_GET_PCIE_P2P_CAPS = (0x20800ab8)
NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS_MESSAGE_ID = (0xB8)
NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO = (0x20800ab9)
NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID = (0xB9)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE = (0x20800a76)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x76)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE = (0x20800a77)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID = (0x77)
NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBB)
NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES = (0x20800aba)
NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID = (0xBA)
NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE = (0x20800abd)
NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID = (0xBD)
NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT = (0x20800abe)
NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID = (0xBE)
NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS = (0x20800abf)
NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID = (0xBF)
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS = (0x20800ac0)
NV2080_MAX_NUM_HEADS = 4
NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID = (0xC0)
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC = (0x20800ac1)
NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID = (0xC1)
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES = (0x20800ac4)
NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID = (0xC4)
NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID = (0x20800ac9)
NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID = (0xC9)
NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC = (0x20800aca)
NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID = (0xCA)
NV2080_CTRL_CMD_INTERNAL_FBSR_INIT = (0x20800ac2)
NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID = (0xC2)
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING = (0x20800ac3)
NV2080_CTRL_CMD_INTERNAL_FIFO_TOGGLE_ACTIVE_CHANNEL_SCHEDULING_PARAMS_MESSAGE_ID = (0xC3)
NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB = (0x20800ac5)
NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID = (0xC5)
NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD = (0x20800ac6)
NV2080_CTRL_ACPI_DSM_READ_SIZE = (0x1000)
NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID = (0xC6)
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC7)
NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL = (0x20800ac7)
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID = (0xC8)
NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL = (0x20800ac8)
NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE = (0x20800acb)
NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID = (0xCB)
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR = 0x00
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM = 0x01
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI = 0x02
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD = 0x00
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT = 0x01
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR = 0x02
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET = 0x03
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC = (0x20800acc)
NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID = (0xCC)
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC = (0x20800acd)
NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID = (0xCD)
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS = 0x00
NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS = 0x01
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE = (0x20800ace)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCE)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE = (0x20800acf)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID = (0xCF)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT = (0x20800ad0)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID = (0xD0)
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT = (0x20800ad1)
NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID = (0xD1)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE = (0x20800ad2)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID = (0xD2)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 = (0x20800ad3)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID = (0xD3)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO = (0x20800ad4)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID = (0xD4)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING = (0x20800ad5)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID = (0xD5)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE = (0x20800ad6)
NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID = (0xD6)
NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE = (0x2080a7d7)
NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID = (0xD7)
NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT = (0x20800a7b)
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS = (0x20800ad8)
NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID = (0xD8)
NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS = (0x20800adb)
NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID = (0xDB)
NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS = (0x20800adc)
NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID = (0xDC)
NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE = (0x20800add)
NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL = (0x20800ade)
NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID = (0xDE)
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA = (0x20800adf)
MAX_EDID_SIZE_FROM_SBIOS = 512
NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID = (0xDF)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED = (0x20800af0)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET = (0x20800af1)
NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET = (0x20800af2)
NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF4)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO = (0x208001f4)
NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF5)
NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE = (0x208001f5)
NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE = (0x208001f6)
NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE = (0x208001f7)
NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID = (0xF8)
NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE = (0x208001f8)
NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE = (0x208001f9)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO = (0x20800af3)
NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0xF3)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS = (0x20800ae1)
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE = 3
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL = 0
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER = 1
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER = 2
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT = 3
NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT = 6
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS_MESSAGE_ID = (0xE1)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS = (0x20800ae2)
NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS_MESSAGE_ID = (0xE2)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ROTATE_KEYS = (0x20800ae5)
NV2080_CTRL_INTERNAL_CONF_COMPUTE_ROTATE_KEYS_PARAMS_MESSAGE_ID = (0xE5)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION = (0x20800ae6)
NV2080_CTRL_INTERNAL_CONF_COMPUTE_RC_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID = (0xE6)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE = (0x20800ae7)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID = (0xE7)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY = (0x20800ae8)
NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID = (0xE8)
NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID = (0x20800aef)
NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID = (0xEF)
NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP = (0x20800afa)
CC_AES_256_GCM_AUTH_TAG_SIZE_BYTES = (0x10)
NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID = (0xFA)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG = (0x20800afb)
NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFB)
NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG = (0x20800afc)
NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID = (0xFC)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO = (0x20800afd)
NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID = (0xFD)
NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID = (0xFE)
NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA = (0x20800afe)
NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID = (0xFF)
NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL = (0x20800aff)
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_PARAMS_MESSAGE_ID = (0xE3)
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_OLDEST = 0x00
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_START_KEEP_NEWEST = 0x01
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE_FLAG_STOP = 0x02
NV2080_CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE = (0x208001e3)
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID = (0xAF)
NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES = (0x20800aaf)
NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND = (0x20800ae4)
NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID = (0xE4)
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID = (0xE9)
NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER = (0x20800ae9)
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY = (0x20800aea)
NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID = (0xEA)
NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID = (0xEB)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP = (0x20800aeb)
NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID = (0xEC)
NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM = (0x20800aec)
NV2080_CTRL_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR_PARAMS_MESSAGE_ID = (0xED)
NV2080_CTRL_CMD_INTERNAL_GSYNC_APPLY_STEREO_PIN_ALWAYS_HI_WAR = (0x20800aed)
NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM = (0x20800a79)
NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID = (0x79)
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS_MESSAGE_ID = (0x14)
NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE = (0x20800a14)
NV2080_CTRL_INTERNAL_GPU_GET_PF_BAR1_SPA_PARAMS_MESSAGE_ID = (0xEE)
NV2080_CTRL_CMD_INTERNAL_GPU_GET_PF_BAR1_SPA = (0x20800aee)
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_NVLINK_PEER = (0x20800a21)
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x21)
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_OFF = 0x00
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_HS = 0x01
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAFE = 0x02
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAULT = 0x03
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RECOVERY = 0x04
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_FAIL = 0x05
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DETECT = 0x06
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESET = 0x07
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ENABLE_PM = 0x08
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_PM = 0x09
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SLEEP = 0x0A
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_SAVE_STATE = 0x0B
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_RESTORE_STATE = 0x0C
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_PRE_HS = 0x0E
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_ERR_DETECT = 0x0F
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_DISABLE = 0x10
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_LANE_SHUTDOWN = 0x11
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_TRAFFIC_SETUP = 0x12
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE1 = 0x13
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITNEGOTIATE = 0x14
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITNEGOTIATE = 0x15
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITOPTIMIZE = 0x16
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_POST_INITOPTIMIZE = 0x17
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_DISABLE_HEARTBEAT = 0x18
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_CONTAIN = 0x19
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITTL = 0x1A
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INITPHASE5 = 0x1B
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ALI = 0x1C
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_ACTIVE_PENDING = 0x1D
NV2080_INTERNAL_NVLINK_CORE_LINK_STATE_INVALID = 0xFF
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_HS = 0x00
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SINGLE_LANE = 0x04
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_LOW_POWER = 0x04
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_TRAIN = 0x05
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_SAFE = 0x06
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_OFF = 0x07
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE = 0x08
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_COMMON_MODE_DISABLE = 0x09
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_DATA_READY = 0x0A
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_EQ = 0x0B
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_PRBS_EN = 0x0C
NV2080_NVLINK_CORE_SUBLINK_STATE_TX_POST_HS = 0x0D
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_HS = 0x00
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SINGLE_LANE = 0x04
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_LOW_POWER = 0x04
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_TRAIN = 0x05
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_SAFE = 0x06
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_OFF = 0x07
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_RXCAL = 0x08
NV2080_NVLINK_CORE_SUBLINK_STATE_RX_INIT_TERM = 0x09
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_NUM = 6
NV2080_CTRL_INTERNAL_NVLINK_MAX_SEED_BUFFER_SIZE = (0x7)
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE = 0x00
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_DL_LINK_MODE = 0x01
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TL_LINK_MODE = 0x02
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TL_LINK_MODE = 0x03
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_TX_SUBLINK_MODE = 0x04
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_TX_SUBLINK_MODE = 0x05
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_MODE = 0x06
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_MODE = 0x07
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_RX_SUBLINK_DETECT = 0x08
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_SET_RX_SUBLINK_DETECT = 0x09
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_WRITE_DISCOVERY_TOKEN = 0x0A
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_READ_DISCOVERY_TOKEN = 0x0B
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_TRAINING_COMPLETE = 0x0C
NV2080_CTRL_INTERNAL_NVLINK_CALLBACK_TYPE_GET_UPHY_LOAD = 0x0D
NV2080_CTRL_INTERNAL_NVLINK_CORE_CALLBACK_PARAMS_MESSAGE_ID = (0x24)
NV2080_CTRL_CMD_INTERNAL_NVLINK_CORE_CALLBACK = (0x20800a24)
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID_PARAMS_MESSAGE_ID = (0x25)
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_REMOTE_LOCAL_SID = (0x20800a25)
NV2080_CTRL_INTERNAL_NVLINK_GET_ALI_ENABLED_PARAMS_MESSAGE_ID = (0x29)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_ALI_ENABLED = (0x20800a29)
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_PROGRAM = 0x0
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_TYPE_RESET = 0x1
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS_MESSAGE_ID = (0x42)
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_HSHUB_MUX = (0x20800a42)
NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x4E)
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER = (0x20800a4e)
NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x50)
NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER = (0x20800a50)
NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID = (0x20800a56)
NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE = (81)
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID = (0x56)
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM = 0x1
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER = 0x2
NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID = (0x5F)
NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING = (0x20800a5f)
NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID = (0x62)
NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE = (0x20800a62)
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET = (0x00000000)
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE = (0x00000001)
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE = (0x00000002)
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID = (0x64)
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY = (0x20800a64)
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID = (0x78)
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG = (0x20800a78)
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID = (0x7D)
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK = (0x20800a7d)
NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID = (0x82)
NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION = (0x20800a82)
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID = (0x83)
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY = (0x20800a83)
NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x84)
NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI = (0x20800a84)
NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE = 64
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID = (0x85)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET = (0x20800a85)
NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID = (0x86)
NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI = (0x20800a86)
NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x87)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO = (0x20800a87)
NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW = 6
NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x8E)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO = (0x20800a8e)
NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID = (0x8F)
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED = (0x20800a8f)
NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID = (0x90)
NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED = (0x20800a90)
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT = (0x00000000)
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT = (0x00000001)
NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE = (0x00000002)
NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID = (0x91)
NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS = (0x20800a91)
NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID = (0x92)
NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS = (0x20800a92)
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID = (0x93)
NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO = (0x20800a93)
NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID = (0x94)
NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM = (0x20800a94)
NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID = (0x95)
NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS = (0x20800a95)
NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID = (0x96)
NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS = (0x20800a96)
NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97)
NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97)
NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB)
NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab)
NV2080_CTRL_CMD_LPWR_DIFR_CTRL = (0x20802801)
NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE = (0x00000001)
NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE = (0x00000002)
NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS = (0x00000003)
NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_LPWR_DIFR_SUPPORTED = (0x00000001)
NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED = (0x00000002)
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE = (0x20802802)
NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS = (0x00000001)
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED = (0x00000002)
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE = (0x00000003)
NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR = (0x00000004)
NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_MC_GET_ARCH_INFO = (0x20801701)
NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X = (0xE0000023)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_TU100 = (0x00000160)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 = (0x00000170)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GH100 = (0x00000180)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 = (0x00000190)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 = (0x000001A0)
NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 = (0x000001B0)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234 = (0x00000004)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_T234D = (0x00000005)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU100 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU102 = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU104 = (0x00000004)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU106 = (0x00000006)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU116 = (0x00000008)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_TU117 = (0x00000007)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA102 = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA103 = (0x00000003)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA104 = (0x00000004)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA106 = (0x00000006)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA107 = (0x00000007)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA10B = (0x0000000B)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GH100_SOC = (0x00000001)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD100 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD000 = (0x00000001)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD101 = (0x00000001)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD102 = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD103 = (0x00000003)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD104 = (0x00000004)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD106 = (0x00000006)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD107 = (0x00000007)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_AD10B = (0x0000000B)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 = (0x00000003)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 = (0x00000004)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 = (0x00000005)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 = (0x00000006)
NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 = (0x00000007)
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION = (0x00000000)
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_P = (0x00000001)
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_Q = (0x00000002)
NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_R = (0x00000003)
NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS = (0x20801702)
NV2080_CTRL_MC_ENGINE_ID_GRAPHICS = 0x00000001
NV2080_CTRL_MC_ENGINE_ID_ALL = 0xFFFFFFFF
NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_MC_GET_MANUFACTURER = (0x20801703)
NV2080_CTRL_MC_GET_MANUFACTURER_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP = (0x2080170c)
NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS = (0x2080170d)
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES = 256
NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE = (0x2080170e)
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX = 32
NV2080_INTR_TYPE_NULL = (0x00000000)
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT = (0x00000001)
NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR = (0x00000002)
NV2080_INTR_TYPE_INFO_FAULT = (0x00000003)
NV2080_INTR_TYPE_REPLAYABLE_FAULT = (0x00000004)
NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR = (0x00000005)
NV2080_INTR_TYPE_ACCESS_CNTR = (0x00000006)
NV2080_INTR_TYPE_TMR = (0x00000007)
NV2080_INTR_TYPE_CPU_DOORBELL = (0x00000008)
NV2080_INTR_TYPE_GR0_FECS_LOG = (0x00000009)
NV2080_INTR_TYPE_GR1_FECS_LOG = (0x0000000A)
NV2080_INTR_TYPE_GR2_FECS_LOG = (0x0000000B)
NV2080_INTR_TYPE_GR3_FECS_LOG = (0x0000000C)
NV2080_INTR_TYPE_GR4_FECS_LOG = (0x0000000D)
NV2080_INTR_TYPE_GR5_FECS_LOG = (0x0000000E)
NV2080_INTR_TYPE_GR6_FECS_LOG = (0x0000000F)
NV2080_INTR_TYPE_GR7_FECS_LOG = (0x00000010)
NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CMD_NVD_GET_DUMP_SIZE = (0x20802401)
NV2080_CTRL_NVD_GET_DUMP_SIZE_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_NVD_GET_DUMP = (0x20802402)
NV2080_CTRL_NVD_GET_DUMP_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_NVD_GET_NOCAT_JOURNAL = (0x20802409)
NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER = 1024
NV2080_NOCAT_JOURNAL_MAX_STR_LEN = 65
NV2080_NOCAT_JOURNAL_MAX_JOURNAL_RECORDS = 10
NV2080_NOCAT_JOURNAL_MAX_ASSERT_RECORDS = 32
NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN = 0
NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK = 1
NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE = 2
NV2080_NOCAT_JOURNAL_REC_TYPE_TDR = 3
NV2080_NOCAT_JOURNAL_REC_TYPE_RC = 4
NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT = 5
NV2080_NOCAT_JOURNAL_REC_TYPE_ANY = 6
NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT = (0x7)
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX = 0
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX = 1
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX = 2
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX = 3
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX = 4
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX = 5
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX = 6
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX = 7
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX = 8
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX = 9
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX = 10
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX = 11
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX = 12
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX = 13
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX = 14
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX = 15
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX = 16
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX = 17
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX = 18
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX = 19
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX = 20
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX = 21
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX = 22
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX = 23
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX = 24
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX = 25
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX = 26
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX = 27
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX = 28
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX = 29
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX = 30
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX = 31
NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT = (0x20)
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES = 1
NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO = 0
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES = 1
NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO = 0
NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA = (0x2080240b)
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY = 0
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON = 1
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG = 2
NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG = 3
NV2080_CTRL_NOCAT_TDR_TYPE_NONE = 0
NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY = 1
NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP = 2
NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET = 3
NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET = 4
NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL = 5
NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET = 6
NV2080_CTRL_NOCAT_TDR_TYPE_TEST = 7
NV2080_CTRL_NOCAT_TAG_CLEAR_YES = 1
NV2080_CTRL_NOCAT_TAG_CLEAR_NO = 0
NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD = (0x2080240c)
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES = 1
NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO = 0
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES = 1
NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO = 0
NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_NVLINK_CAPS_TBL_SIZE = 2
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID = (0x00000000)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 = (0x00000002)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 = (0x00000004)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 = (0x00000005)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 = (0x00000006)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 = (0x00000007)
NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 = (0x00000008)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID = (0x00000000)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 = (0x00000002)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 = (0x00000004)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0 = (0x00000005)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 = (0x00000006)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 = (0x00000007)
NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 = (0x00000008)
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = (0x20803001)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE = (0x00000000)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI = (0x00000001)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID = (0x00000002)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE = (0x00000000)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU = (0x00000001)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU = (0x00000002)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH = (0x00000003)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA = (0x00000004)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE = (0x000000FF)
NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID = (0xFFFFFFFF)
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE = (0x00000000)
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE = (0x00000001)
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE = (0x00000000)
NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INIT = (0x00000000)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG = (0x00000002)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE = (0x00000003)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_FAULT = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_SLEEP = (0x00000005)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY = (0x00000006)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_AC = (0x00000008)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY_RX = (0x0000000a)
NV2080_CTRL_NVLINK_STATUS_LINK_STATE_INVALID = (0xFFFFFFFF)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 = (0x00000000)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING = (0x00000005)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE = (0x00000006)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF = (0x00000007)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TEST = (0x00000008)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT = (0x0000000e)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 = (0x00000000)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING = (0x00000005)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE = (0x00000006)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF = (0x00000007)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TEST = (0x00000008)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT = (0x0000000e)
NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_PHY_NVHS = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_PHY_GRS = (0x00000002)
NV2080_CTRL_NVLINK_STATUS_PHY_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 = (0x00000002)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0 = (0x00000005)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 = (0x00000006)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 = (0x00000007)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 = (0x00000008)
NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 = (0x00000002)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 = (0x00000004)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0 = (0x00000005)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 = (0x00000006)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 = (0x00000007)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 = (0x00000008)
NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE = (0x00000000)
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK = (0x00000001)
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT = (0x00000002)
NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE = (0x00000000)
NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID = (0x000000FF)
NV2080_CTRL_NVLINK_MAX_LINKS = 32
NV2080_CTRL_NVLINK_MAX_ARR_SIZE = 64
NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID = (0x00)
NV2080_CTRL_NVLINK_REFCLK_TYPE_NVHS = (0x01)
NV2080_CTRL_NVLINK_REFCLK_TYPE_PEX = (0x02)
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = (0x20803002)
NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT = lambda intr,i: (((1 << i) & (intr)) >> i)
NV2080_CTRL_NVLINK_GET_TL_INTEN_BIT = lambda intr,i: NV2080_CTRL_NVLINK_GET_TL_ERRLOG_BIT(intr, i)
NV2080_CTRL_NVLINK_TL_ERRLOG_TRUE = (0x00000001)
NV2080_CTRL_NVLINK_TL_ERRLOG_FALSE = (0x00000000)
NV2080_CTRL_NVLINK_TL_INTEN_TRUE = (0x00000001)
NV2080_CTRL_NVLINK_TL_INTEN_FALSE = (0x00000000)
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLDATAPARITYEN = 0
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXDLCTRLPARITYEN = 1
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPROTOCOLEN = 2
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXOVERFLOWEN = 3
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMDATAPARITYEN = 4
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRAMHDRPARITYEN = 5
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXRESPEN = 6
NV2080_CTRL_NVLINK_TL_INTEN_IDX_RXPOISONEN = 7
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMDATAPARITYEN = 8
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXRAMHDRPARITYEN = 9
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLFLOWPARITYEN = 10
NV2080_CTRL_NVLINK_TL_INTEN_IDX_DLHDRPARITYEN = 12
NV2080_CTRL_NVLINK_TL_INTEN_IDX_TXCREDITEN = 13
NV2080_CTRL_NVLINK_TL_INTEN_IDX_MAX = 14
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLDATAPARITYERR = 0
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXDLCTRLPARITYERR = 1
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPROTOCOLERR = 2
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXOVERFLOWERR = 3
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMDATAPARITYERR = 4
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRAMHDRPARITYERR = 5
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXRESPERR = 6
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_RXPOISONERR = 7
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMDATAPARITYERR = 8
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXRAMHDRPARITYERR = 9
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLFLOWPARITYERR = 10
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_DLHDRPARITYERR = 12
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_TXCREDITERR = 13
NV2080_CTRL_NVLINK_TL_ERRLOG_IDX_MAX = 14
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_HS = (0x00000000)
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SINGLE_LANE = (0x00000004)
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN = (0x00000005)
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_SAFE = (0x00000006)
NV2080_CTRL_NVLINK_SL0_SLSM_STATUS_TX_PRIMARY_STATE_OFF = (0x00000007)
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_HS = (0x00000000)
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SINGLE_LANE = (0x00000004)
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN = (0x00000005)
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE = (0x00000006)
NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF = (0x00000007)
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT = (0x0)
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS = (0x1)
NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS = (0x2)
NV2080_CTRL_NVLINK_MAX_IOCTRLS = 3
NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO = (0x20803003)
NV2080_CTRL_NVLINK_COUNTER_INVALID = 0x00000000
NV2080_CTRL_NVLINK_COUNTER_TL_TX0 = 0x00000001
NV2080_CTRL_NVLINK_COUNTER_TL_TX1 = 0x00000002
NV2080_CTRL_NVLINK_COUNTER_TL_RX0 = 0x00000004
NV2080_CTRL_NVLINK_COUNTER_TL_RX1 = 0x00000008
NV2080_CTRL_NVLINK_LP_COUNTERS_DL = 0x00000010
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L = lambda i: (1 << (i + 8))
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE__SIZE = 4
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L0 = 0x00000100
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L1 = 0x00000200
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L2 = 0x00000400
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_ECC_LANE_L3 = 0x00000800
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT = 0x00010000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L = lambda i: (1 << (i + 17))
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE = 8
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 = 0x00020000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 = 0x00040000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 = 0x00080000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 = 0x00100000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 = 0x00200000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 = 0x00400000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 = 0x00800000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 = 0x01000000
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY = 0x02000000
NV2080_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY = 0x04000000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_REPLAY = 0x08000000
NV2080_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED = 0x10000000
NV2080_CTRL_NVLINK_COUNTER_MAX_TYPES = 32
NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS = (0x20803004)
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS = (0x20803005)
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX0 = 0
NV2080_CTRL_NVLINK_COUNTER_TP_TL_TX1 = 1
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX0 = 2
NV2080_CTRL_NVLINK_COUNTER_TP_TL_RX1 = 3
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_SIZE = 4
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L0 = 4
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L1 = 5
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L2 = 6
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_ECC_LANE_L3 = 7
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_SIZE = 8
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L0 = 8
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L1 = 9
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L2 = 10
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L3 = 11
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L4 = 12
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L5 = 13
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L6 = 14
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_LANE_L7 = 15
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_RECOVERY = 16
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_TX_ERR_REPLAY = 17
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_REPLAY = 18
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_MASKED = 19
NV2080_CTRL_NVLINK_COUNTER_ERR_DL_RX_ERR_CRC_FLIT = 20
NV2080_CTRL_NVLINK_COUNTER_LP_DL = 21
NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER = NV2080_CTRL_NVLINK_COUNTER_LP_DL
NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS = 22
NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES = 23
NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS = 24
NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES = 25
NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER = 26
NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER = 27
NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER = 28
NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS = 29
NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS = 30
NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS = 31
NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR = 32
NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR = 33
NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR = 34
NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS = 35
NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS = 36
NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME = 37
NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS = 38
NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS = 39
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS = 40
NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS = 41
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 = 42
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 = 43
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL = 44
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 = 45
NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 = 46
NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS = 47
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 = 48
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 = 49
NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL = 50
NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS = 51
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS = 52
NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER = 53
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS = 54
NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER = 55
NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS = 56
NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS = 57
NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR = 58
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS = 59
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS = 60
NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS = 61
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS = 62
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS = 63
NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS = 64
NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS = 65
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD = 66
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR = 67
NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH = 68
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD = 69
NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR = 70
NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 = 71
NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 = 72
NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 = 73
NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 = 74
NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 = 75
NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 = 76
NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 = 77
NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 = 78
NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 = 79
NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 = 80
NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 = 81
NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 = 82
NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 = 83
NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 = 84
NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 = 85
NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 = 86
NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA = 87
NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA = 88
NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW = 89
NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW = 90
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY = 91
NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE = 92
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT = 93
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL = 94
NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE = 95
NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME = 96
NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME = 97
NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME = 98
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME = 99
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME = 100
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME = 101
NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME = 102
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME = 103
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME = 104
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME = 105
NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME = 106
NV2080_CTRL_NVLINK_COUNTERS_MAX = 107
NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS = 2
NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ = 28
NV2080_CTRL_NVLINK_COUNTER_V2_GROUP = lambda i: ((i) / 64)
NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x50)
NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 = (0x20803050)
NV2080_CTRL_NVLINK_CLEAR_COUNTERS_V2_PARAMS_MESSAGE_ID = (0x51)
NV2080_CTRL_CMD_NVLINK_CLEAR_COUNTERS_V2 = (0x20803051)
NV2080_CTRL_CMD_NVLINK_INJECT_ERROR = (0x20803006)
NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID = (0x6)
NV2080_CTRL_NVLINK_UNIT_DL = 0x01
NV2080_CTRL_NVLINK_UNIT_TL = 0x02
NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 = 0x03
NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 = 0x04
NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 = 0x05
NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 = 0x06
NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 = 0x07
NV2080_CTRL_NVLINK_UNIT_MINION = 0x08
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER = 0x00000001
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER = 0x00000002
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN = 0x00000001
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN = 0x00000001
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN = 0x00000001
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN = 0x00000001
NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x81)
NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT = (0x20803081)
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST = 0x00000001
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR = 0x00000002
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT = 0x00000000
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT = 0x00000001
NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID = (0x82)
NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT = (0x20803082)
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES = (0x20803007)
NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CMD_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE = (0x20803008)
NV2080_CTRL_NVLINK_GET_LINK_LAST_ERROR_REMOTE_TYPE_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_NVLINK_GET_LINK_FATAL_ERROR_COUNTS = (0x20803009)
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_DATA_PARITY = 0
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_DL_CTRL_PARITY = 1
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_PROTOCOL = 2
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_OVERFLOW = 3
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_DATA_PARITY = 4
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RAM_HDR_PARITY = 5
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_RESP = 6
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_RX_POISON = 7
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_DATA_PARITY = 8
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_RAM_HDR_PARITY = 9
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_TX_CREDIT = 10
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_FLOW_CTRL_PARITY = 11
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TL_DL_HDR_PARITY = 12
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_RECOVERY_LONG = 13
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_RAM = 14
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_INTERFACE = 15
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_TX_FAULT_SUBLINK_CHANGE = 16
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_SUBLINK_CHANGE = 17
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_RX_FAULT_DL_PROTOCOL = 18
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT = 19
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_DATA_PARITY = 0
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_CTRL_PARITY = 1
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_DATA_PARITY = 4
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RAM_HDR_PARITY = 5
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_POISONED_PKT_RCVD = 7
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_DATA_PARITY = 8
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RAM_HDR_PARITY = 9
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_FLOW_CONTROL_PARITY = 11
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DL_HDR_PARITY = 20
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_AE_FLIT_RCVD = 21
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_BE_FLIT_RCVD = 22
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_ADDR_ALIGN = 23
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_PKT_LEN = 24
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CMD_ENC = 25
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_DAT_LEN_ENC = 26
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_ADDR_TYPE = 27
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_RSP_STATUS = 28
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_PKT_STATUS = 29
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_REQ = 30
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RSVD_CACHE_ATTR_ENC_IN_PROBE_RESP = 31
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_ATOMIC_REQ_MAX_SIZE = 32
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_GT_RMW_REQ_MAX_SIZE = 33
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DAT_LEN_LT_ATR_RESP_MIN_SIZE = 34
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_PO_FOR_CACHE_ATTR = 35
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COMPRESSED_RESP = 36
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_TARGET = 37
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_RESP_STATUS_UNSUPPORTED_REQUEST = 38
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_HDR_OVERFLOW = 39
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_DATA_OVERFLOW = 40
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_STOMPED_PKT_RCVD = 41
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_CORRECTABLE_INTERNAL = 42
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_VC_OVERFLOW = 43
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NVLINK_CREDIT_RELEASE = 44
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_UNSUPPORTED_NCISOC_CREDIT_RELEASE = 45
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_HDR_CREDIT_OVERFLOW = 46
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_CREDIT_OVERFLOW = 47
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DL_REPLAY_CREDIT_OVERFLOW = 48
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_UNSUPPORTED_VC_OVERFLOW = 49
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_STOMPED_PKT_SENT = 50
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_DATA_POISONED_PKT_SENT = 51
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_TARGET = 52
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_RESP_STATUS_UNSUPPORTED_REQUEST = 53
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_DATA_PARITY = 54
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_RX_RAM_HDR_PARITY = 55
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_DATA_PARITY = 56
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_MIF_TX_RAM_HDR_PARITY = 57
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_RX_INVALID_COLLAPSED_RESPONSE = 58
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_HDR_ECC_DBE = 59
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_TLC_TX_NCISOC_PARITY = 60
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_UP = 61
NV2080_CTRL_NVLINK_FATAL_ERROR_TYPE_DL_LTSSM_FAULT_DOWN = 62
NV2080_CTRL_NVLINK_NUM_FATAL_ERROR_TYPES = 63
NV2080_CTRL_NVLINK_IS_FATAL_ERROR_COUNT_VALID = lambda count,supportedCounts: ( not  not ((supportedCounts) & NVBIT64(count)))
NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_NVLINK_GET_LINK_NONFATAL_ERROR_RATES = (0x2080300a)
NV2080_CTRL_NVLINK_NONFATAL_ERROR_RATE_ENTRIES = 5
NV2080_CTRL_NVLINK_GET_LINK_NONFATAL_ERROR_RATES_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_NVLINK_SET_ERROR_INJECTION_MODE = (0x2080300b)
NV2080_CTRL_NVLINK_SET_ERROR_INJECTION_MODE_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_CMD_NVLINK_SETUP_EOM = (0x2080300c)
NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_NVLINK_SET_POWER_STATE = (0x2080300d)
NV2080_CTRL_NVLINK_SET_POWER_STATE_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_NVLINK_POWER_STATE_L0 = (0x00)
NV2080_CTRL_NVLINK_POWER_STATE_L1 = (0x01)
NV2080_CTRL_NVLINK_POWER_STATE_L2 = (0x02)
NV2080_CTRL_NVLINK_POWER_STATE_L3 = (0x03)
NV2080_CTRL_CMD_NVLINK_GET_POWER_STATE = (0x2080300e)
NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CMD_NVLINK_INJECT_TLC_ERROR = (0x2080300f)
NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS_MESSAGE_ID = (0xF)
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES = (0x20803011)
NV2080_CTRL_NVLINK_MAX_LANES = 4
NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS_MESSAGE_ID = (0x11)
NV2080_CTRL_CMD_NVLINK_SET_NVLINK_PEER = (0x20803012)
NV2080_CTRL_NVLINK_SET_NVLINK_PEER_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_CMD_NVLINK_READ_UPHY_PAD_LANE_REG = (0x20803013)
NV2080_CTRL_NVLINK_READ_UPHY_PAD_LANE_REG_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS_MESSAGE_ID = (0x14)
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_ECC_ERRORS = (0x20803014)
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_TX = 0
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_DATA_RX = 1
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_TX = 2
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_RAW_RX = 3
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_TYPE_MAX = 4
NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID = (0x15)
NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS = (0x20803015)
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE = (0x20803016)
NV2080_CTRL_CMD_NVLINK_LOCK_LINK_POWER_STATE_PARAMS_MESSAGE_ID = (0x16)
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS = 0
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH = 1
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER = 2
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER = 3
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT = 4
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP = 5
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME = 6
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME = 7
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME = 8
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME = 9
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME = 10
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME = 11
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME = 12
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME = 13
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME = 14
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME = 15
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS = 16
NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID = (0x18)
NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS = (0x20803018)
NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS = (0x20803052)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_DEFAULT = (0x00000000)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEA = (0x00000001)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDR = (0x00000002)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_NEDW = (0x00000003)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_REMOTE = (0x00000004)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PHY_LOCAL = (0x00000005)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_EXT_LOCAL = (0x00000006)
NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID = (0x23)
NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE = (0x20803023)
NV2080_CTRL_NVLINK_MAX_LINK_COUNT = 32
NV2080_CTRL_NVLINK_GET_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x28)
NV2080_CTRL_CMD_NVLINK_GET_REFRESH_COUNTERS = (0x20803028)
NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID = (0x29)
NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS = (0x20803029)
NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS_MESSAGE_ID = (0x38)
NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR = (0x20803038)
NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID = (0x39)
NV2080_CTRL_CMD_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO = (0x20803039)
NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS = (0x2080303a)
NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS_MESSAGE_ID = (0x3b)
NV2080_CTRL_CMD_NVLINK_PROCESS_INIT_DISABLED_LINKS = (0x2080303b)
NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID = (0x3c)
NV2080_CTRL_CMD_NVLINK_EOM_CONTROL = (0x2080303c)
NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE = 5120
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID = (0x3d)
NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE = (0x2080303d)
NV2080_CTRL_NVLINK_L1_THRESHOLD_VALUE_DEFAULT = (0xFFFFFFFF)
NV2080_CTRL_NVLINK_SET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3e)
NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD = (0x2080303e)
NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS_MESSAGE_ID = (0x3f)
NV2080_CTRL_CMD_NVLINK_GET_L1_THRESHOLD = (0x2080303f)
NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID = (0x40)
NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA = (0x20803040)
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID = (0x41)
NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED = (0x20803041)
NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID = (0x42)
NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK = (0x20803042)
NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID = (0x43)
NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP = (0x20803043)
NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE = 64
NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID = (0x44)
NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS = (0x20803044)
NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID = (0x45)
NV2080_CTRL_CMD_NVLINK_CYCLE_LINK = (0x20803045)
NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID = (0x46)
NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG = (0x20803046)
NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH = 496
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS = (0x20803047)
NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID = (0x47)
NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY = (0x20803048)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC = (0x20803053)
NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID = (0x53)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM = (0x20803054)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID = (0x54)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC = (0x20803055)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID = (0x55)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM = (0x20803056)
NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID = (0x56)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR = (0x2080305c)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID = (0x5c)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE = (0x2080305e)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID = (0x5e)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE = (0x2080305f)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID = (0x5f)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP = (0x20803061)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID = (0x61)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU = (0x20803062)
NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID = (0x62)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP = (0x20803064)
NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID = (0x64)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT = (0x20803065)
NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID = (0x65)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR = (0x20803066)
NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID = (0x66)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT = (0x20803068)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID = (0x68)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT = (0x20803069)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID = (0x69)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR = (0x2080306a)
NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID = (0x6a)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS = (0x2080306b)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID = (0x6b)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR = (0x2080306c)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID = (0x6c)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP = (0x2080306d)
NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID = (0x6d)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID = (0x2080306e)
NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID = (0x6e)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT = (0x2080306f)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID = (0x6f)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS = (0x20803070)
NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID = (0x70)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG = (0x20803071)
NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID = (0x71)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS = (0x20803072)
NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID = (0x72)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR = (0x20803073)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID = (0x73)
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS = (0x20803074)
NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID = (0x74)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD = (0x20803075)
NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID = (0x75)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP = (0x20803076)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID = (0x76)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF = (0x20803077)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID = (0x77)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL = (0x20803078)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID = (0x78)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM = (0x20803079)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID = (0x79)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE = (0x2080307a)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID = (0x7a)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM = (0x2080307b)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID = (0x7b)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR = (0x2080307c)
NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID = (0x7c)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR = (0x2080307d)
NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID = (0x7d)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS = (0x2080307e)
NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID = (0x7e)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC = (0x2080307f)
NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID = (0x7f)
NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB = (0x20803080)
NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID = (0x80)
NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = (0x20803083)
NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID = (0x83)
NV2080_CTRL_NVLINK_BLACKWELL_MAX_LINKS = 18
NV2080_CTRL_CMD_NVLINK_READ_UPHY_CLN = (0x20803084)
NV2080_CTRL_NVLINK_READ_UPHY_CLN_REG_PARAMS_MESSAGE_ID = (0x84)
NV2080_CTRL_NVLINK_SUPPORTED_MAX_BW_MODE_COUNT = 23
NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_BW_MODE = (0x20803085)
NV2080_CTRL_NVLINK_GET_SUPPORTED_BW_MODE_PARAMS_MESSAGE_ID = (0x85)
NV2080_CTRL_CMD_NVLINK_SET_BW_MODE = (0x20803086)
NV2080_CTRL_NVLINK_SET_BW_MODE_PARAMS_MESSAGE_ID = (0x86)
NV2080_CTRL_CMD_NVLINK_GET_BW_MODE = (0x20803087)
NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS_MESSAGE_ID = (0x87)
NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO = (0x20803088)
NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID = (0x88)
NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR = (0x20803089)
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID = (0x89)
NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY = (0x2080308a)
NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE = (0x2080308e)
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8E)
NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE = (0x2080308f)
NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID = (0x8F)
NV_SUBPROC_NAME_MAX_LENGTH = 100
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR = (0x00000000)
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL = (0x00000001)
NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_TO_MAX = (0x00000002)
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_NO = (0x00000000)
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_YES = (0x00000001)
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO = (0x00000000)
NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES = (0x00000001)
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT = (0x00000000)
NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH = (0x00000001)
NV2080_CTRL_PERF_BOOST_DURATION_MAX = 3600
NV2080_CTRL_PERF_BOOST_DURATION_INFINITE = 0xffffffff
NV2080_CTRL_CMD_PERF_BOOST = (0x2080200a)
NV2080_CTRL_PERF_BOOST_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_PERF_RESERVE_PERFMON_HW = (0x20802093)
NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS_MESSAGE_ID = (0x93)
NV2080_CTRL_PERF_POWER_SOURCE_AC = (0x00000000)
NV2080_CTRL_PERF_POWER_SOURCE_BATTERY = (0x00000001)
NV2080_CTRL_CMD_PERF_SET_POWERSTATE = (0x2080205b)
NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5B)
NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE = (0x20802092)
NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID = (0x92)
NV2080_CTRL_PERF_AUX_POWER_STATE_P0 = (0x00000000)
NV2080_CTRL_PERF_AUX_POWER_STATE_P1 = (0x00000001)
NV2080_CTRL_PERF_AUX_POWER_STATE_P2 = (0x00000002)
NV2080_CTRL_PERF_AUX_POWER_STATE_P3 = (0x00000003)
NV2080_CTRL_PERF_AUX_POWER_STATE_P4 = (0x00000004)
NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT = (0x00000005)
NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_MESSAGE_ID = (0x6D)
NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL = (0x2080206e)
NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID = (0x6E)
NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL = (0x2080206f)
NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID = (0x6F)
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM_MESSAGE_ID = (0x83)
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL = 72
NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 = (0x20802096)
NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_MESSAGE_ID = (0x96)
NV2080_CTRL_CMD_PERF_GPU_IS_IDLE = (0x20802089)
NV2080_CTRL_PERF_GPU_IS_IDLE_PARAMS_MESSAGE_ID = (0x89)
NV2080_CTRL_PERF_GPU_IS_IDLE_TRUE = (0x00000001)
NV2080_CTRL_PERF_GPU_IS_IDLE_FALSE = (0x00000002)
NV2080_CTRL_CMD_PERF_AGGRESSIVE_PSTATE_NOTIFY = (0x2080208f)
NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS_MESSAGE_ID = (0x8F)
NV2080_CTRL_PERF_CLK_MAX_DOMAINS = 32
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO = (0x20802002)
NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 = (0x2080200b)
NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT = (0x00000000)
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK = (0x00000001)
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE = (0x00000000)
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP = (0x00000001)
NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF = (0x00000002)
NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE = (0x20802087)
NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID = (0x87)
NV2080_CTRL_CMD_PERF_GET_POWERSTATE = (0x2080205a)
NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID = (0x5A)
NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT = (0x2080205d)
NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID = (0x5D)
NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK = (0x0000ffff)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START = (0x00000001)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP = (0x00000002)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP = NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START = (0x00000003)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP = (0x00000004)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START = (0x00000005)
NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP = (0x00000006)
NV2080_CTRL_PERF_VIDEOEVENT_OFA_START = (0x00000007)
NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP = (0x00000008)
NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE = (0x00010000)
NV2080_CTRL_PERF_PSTATES_UNDEFINED = (0x00000000)
NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED = (0x00000000)
NV2080_CTRL_PERF_PSTATES_MIN = (0x00000001)
NV2080_CTRL_PERF_PSTATES_P0 = (0x00000001)
NV2080_CTRL_PERF_PSTATES_P1 = (0x00000002)
NV2080_CTRL_PERF_PSTATES_P2 = (0x00000004)
NV2080_CTRL_PERF_PSTATES_P3 = (0x00000008)
NV2080_CTRL_PERF_PSTATES_P4 = (0x00000010)
NV2080_CTRL_PERF_PSTATES_P5 = (0x00000020)
NV2080_CTRL_PERF_PSTATES_P6 = (0x00000040)
NV2080_CTRL_PERF_PSTATES_P7 = (0x00000080)
NV2080_CTRL_PERF_PSTATES_P8 = (0x00000100)
NV2080_CTRL_PERF_PSTATES_P9 = (0x00000200)
NV2080_CTRL_PERF_PSTATES_P10 = (0x00000400)
NV2080_CTRL_PERF_PSTATES_P11 = (0x00000800)
NV2080_CTRL_PERF_PSTATES_P12 = (0x00001000)
NV2080_CTRL_PERF_PSTATES_P13 = (0x00002000)
NV2080_CTRL_PERF_PSTATES_P14 = (0x00004000)
NV2080_CTRL_PERF_PSTATES_P15 = (0x00008000)
NV2080_CTRL_PERF_PSTATES_MAX = NV2080_CTRL_PERF_PSTATES_P15
NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY = (0x10000)
NV2080_CTRL_PERF_PSTATES_ALL = (0xffff)
NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE = (0x20802068)
NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID = (0x68)
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED = 0
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED = 1
NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE = 2
NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO = (0x20802609)
NV2080_CTRL_CMD_GC6_ENTRY = (0x2080270d)
NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_GC6_EXIT = (0x2080270e)
NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM = (0x20802204)
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_CMD_RC_GET_ERROR_COUNT = (0x20802205)
NV2080_CTRL_RC_ERROR_PARAMS_BUFFER_SIZE = (0x2000)
NV2080_CTRL_CMD_RC_GET_ERROR = (0x20802206)
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS_MESSAGE_ID = (0x13)
NV2080_CTRL_CMD_RC_GET_ERROR_V2 = (0x20802213)
NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY = (0x20802207)
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO = (0x20802209)
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_NONE = (0x00000000)
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_DISABLED = (0x00000001)
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_RUNNING = (0x00000002)
NV2080_CTRL_RC_GET_WATCHDOG_INFO_FLAGS_INITIALIZED = (0x00000004)
NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG = (0x2080220a)
NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG = (0x2080220b)
NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS = (0x2080220c)
NV2080_CTRL_CMD_SET_RC_RECOVERY = (0x2080220d)
NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_GET_RC_RECOVERY = (0x2080220e)
NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID = (0xE)
NV2080_CTRL_CMD_RC_RECOVERY_DISABLED = (0x00000000)
NV2080_CTRL_CMD_RC_RECOVERY_ENABLED = (0x00000001)
NV2080_CTRL_CMD_TDR_SET_TIMEOUT_STATE = (0x2080220f)
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_PARAMS_MESSAGE_ID = (0xF)
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_BEGIN = (0x00000000)
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_CMD_GPU_RESET_END = (0x00000001)
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_SUCCESS = (0x00000000)
NV2080_CTRL_TDR_SET_TIMEOUT_STATE_STATUS_FAIL = (0x00000001)
NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG = (0x20802210)
NV2080_CTRL_CMD_SET_RC_INFO = (0x20802211)
NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID = (0x11)
NV2080_CTRL_CMD_GET_RC_INFO = (0x20802212)
NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID = (0x12)
NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE = (0x00000000)
NV2080_CTRL_CMD_RC_INFO_MODE_ENABLE = (0x00000001)
NV2080_CTRL_CMD_RC_INFO_BREAK_DISABLE = (0x00000000)
NV2080_CTRL_CMD_RC_INFO_BREAK_ENABLE = (0x00000001)
RM_GSP_SPDM_CMD_ID_CC_INIT = (0x1)
RM_GSP_SPDM_CMD_ID_CC_DEINIT = (0x2)
RM_GSP_SPDM_CMD_ID_CC_CTRL = (0x3)
RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA = (0x4)
RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL = (0x5)
RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST = (0x6)
RM_GSP_SPDM_CMD_ID_INVALID_COMMAND = (0xFF)
SPDM_SESSION_ESTABLISHMENT_TRANSCRIPT_BUFFER_SIZE = 0x2400
RSVD7_SIZE = 16
RSVD8_SIZE = 2
CE_FIPS_SELF_TEST_DATA_SIZE = 16
CE_FIPS_SELF_TEST_AUTH_TAG_SIZE = 16
CE_FIPS_SELF_TEST_IV_SIZE = 12
RM_GSP_SPDM_MSG_ID_CC_INIT = (0x1)
RM_GSP_SPDM_MSG_ID_CC_DEINIT = (0x2)
RM_GSP_SPDM_MSG_ID_CC_CTRL = (0x3)
RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA = (0x4)
RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL = (0x5)
RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST = (0x6)
RM_GSP_SPDM_MSG_ID_INVALID_COMMAND = (0xFF)
NV2080_CTRL_INTERNAL_SPDM_PARTITION = (0x20800ad9)
NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID = (0xD9)
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT = (0x20800ada)
NV2080_CTRL_INTERNAL_SPDM_RETRIEVE_TRANSCRIPT_PARAMS_MESSAGE_ID = (0xDA)
NV2080_CTRL_CMD_TIMER_SCHEDULE = (0x20800401)
NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_ABS = (0x00000000)
NV2080_CTRL_TIMER_SCHEDULE_FLAGS_TIME_REL = (0x00000001)
NV2080_CTRL_CMD_TIMER_CANCEL = (0x20800402)
NV2080_CTRL_CMD_TIMER_GET_TIME = (0x20800403)
NV2080_CTRL_TIMER_GET_TIME_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_TIMER_GET_REGISTER_OFFSET = (0x20800404)
NV2080_CTRL_TIMER_GET_REGISTER_OFFSET_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = (0x20800406)
NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES = 16
NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS_MESSAGE_ID = (0x6)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_OSTIME = (0x00000001)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_TSC = (0x00000002)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PLATFORM_API = (0x00000003)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_GSP_OS = (0x00000004)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_CPU = (0x00000000)
NV2080_TIMER_GPU_CPU_TIME_CPU_CLK_ID_PROCESSOR_GSP = (0x00000001)
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = (0x20800407)
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT = (0x20803d01)
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_INC = (0x00000001)
NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_DEC = (0x00000002)
NV2080_CTRL_CMD_OS_UNIX_ALLOW_DISALLOW_GCOFF = (0x20803d02)
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_ALLOW = (0x00000001)
NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_DISALLOW = (0x00000002)
NV2080_CTRL_CMD_OS_UNIX_AUDIO_DYNAMIC_POWER = (0x20803d03)
NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_OS_UNIX_INSTALL_PROFILER_HOOKS = (0x20803d04)
NV2080_CTRL_OS_UNIX_INSTALL_PROFILER_HOOKS_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_OS_UNIX_FLUSH_SNAPSHOT_BUFFER = (0x20803d05)
NV2080_CTRL_CMD_OS_UNIX_STOP_PROFILER = (0x20803d06)
NV2080_CTRL_CMD_OS_UNIX_VIDMEM_PERSISTENCE_STATUS = (0x20803d07)
NV2080_CTRL_OS_UNIX_VIDMEM_PERSISTENCE_STATUS_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CMD_OS_UNIX_UPDATE_TGP_STATUS = (0x20803d08)
NV2080_CTRL_OS_UNIX_UPDATE_TGP_STATUS_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK = (0x20804001)
NV2080_CTRL_MAX_VMMU_SEGMENTS = 384
NV2080_GPU_MAX_ENGINES = 0x54
NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x1)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK = (0x20804002)
NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID = (0x2)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE = (0x20804003)
NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID = (0x3)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU = (0x20804004)
NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID = (0x4)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO = (0x20804005)
NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID = (0x5)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE = (0x20804006)
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID = (0x6)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY = (0x20804007)
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID = (0x7)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP = (0x20804008)
NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID = (0x8)
NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN = 8
NV2080_CTRL_MAX_GPC_COUNT = 32
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING = (0x20804009)
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID = (0x9)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT = (0x2080400a)
NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID = (0xA)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG = (0x2080400b)
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID = (0xB)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES = (0x2080400c)
NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID = (0xC)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_FRAME_RATE_LIMITER_STATUS = (0x2080400d)
NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS_MESSAGE_ID = (0xD)
NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE = (0x2080400e)
NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID = (0xE)
NV83DE_CTRL_RESERVED = (0x00)
NV83DE_CTRL_GR = (0x01)
NV83DE_CTRL_FIFO = (0x02)
NV83DE_CTRL_DEBUG = (0x03)
NV83DE_CTRL_INTERNAL = (0x04)
NV83DE_CTRL_CMD_NULL = (0x83de0000)
NV83DE_CTRL_CMD_SM_DEBUG_MODE_ENABLE = (0x83de0301)
NV83DE_CTRL_CMD_SM_DEBUG_MODE_DISABLE = (0x83de0302)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG = (0x83de0307)
NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x7)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_ENABLE = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG_DISABLE = (0x00000002)
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_DEBUG_REQUESTS = (0x00000003)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG = (0x83de0308)
NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_MESSAGE_ID = (0x8)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_ENABLED = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG_DISABLED = (0x00000002)
NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK = (0x83de0309)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_MESSAGE_ID = (0x9)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL = (0x00000001)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP = (0x00000002)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP = (0x00000004)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT = (0x00000008)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP = (0x00000010)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED = (0x00000020)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_NONE = (0x00000000)
NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_ALL = (0x0000FFFF)
NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE = (0x83de030b)
NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xB)
NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES = (0x83de030c)
NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL = 100
NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0xC)
NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE = (0x83de030f)
NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_MESSAGE_ID = (0xF)
NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES = (0x83de0310)
NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_MESSAGE_ID = (0x10)
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_PARAMS_DEFINED = 1
NV83DE_CTRL_CMD_DEBUG_SUSPEND_ALL_CONTEXTS_FOR_CLIENT_HAS_RESIDENT_CHANNEL = 1
NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE = (0x83de0313)
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_MESSAGE_ID = (0x13)
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_SINGLE_SM = (0x00000001)
NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_BROADCSAT = (0x00000002)
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING = (0x83de0314)
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PARAMS_MESSAGE_ID = (0x14)
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_NONPAUSING = (0x00000001)
NV83DE_CTRL_DEBUG_SET_SINGLE_STEP_INTERRUPT_HANDLING_PAUSING = (0x00000002)
NV83DE_CTRL_CMD_DEBUG_READ_MEMORY = (0x83de0315)
NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS_MESSAGE_ID = (0x15)
NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY = (0x83de0316)
NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS_MESSAGE_ID = (0x16)
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT = (0x83de0317)
NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_MESSAGE_ID = (0x17)
NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT = (0x83de0318)
NV83DE_CTRL_CMD_DEBUG_GET_HANDLES = (0x83de0319)
NV83DE_CTRL_CMD_READ_SURFACE = (0x83de031a)
NV83DE_CTRL_CMD_WRITE_SURFACE = (0x83de031b)
MAX_ACCESS_OPS = 64
NV83DE_CTRL_CMD_GET_MAPPINGS = (0x83de031c)
MAX_GET_MAPPINGS_OPS = 64
NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS = (0x83de031d)
NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS = 100
NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_MESSAGE_ID = (0x1D)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG = (0x83de031f)
NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x1F)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_DISABLE = (0x00000000)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG_ENABLE = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG = (0x83de0320)
NV83DE_CTRL_DEBUG_GET_MODE_ERRBAR_DEBUG_PARAMS_MESSAGE_ID = (0x20)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_DISABLED = (0x00000000)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_ERRBAR_DEBUG_ENABLED = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP = (0x83de0321)
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_MESSAGE_ID = (0x21)
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_STOP_TRIGGER = (0x83de0322)
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_STOP_TRIGGER_PARAMS_MESSAGE_ID = (0x22)
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_RUN_TRIGGER = (0x83de0323)
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_RUN_TRIGGER_PARAMS_MESSAGE_ID = (0x23)
NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT = (0x83de0324)
NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SKIP_IDLE_WARP_DETECT_PARAMS_MESSAGE_ID = (0x24)
NV83DE_CTRL_CMD_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS = (0x83de0325)
NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS_MESSAGE_ID = (0x25)
NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY = (0x83de0326)
NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY = (0x83de0327)
MAX_ACCESS_MEMORY_OPS = 150
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES = 4
NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO = (0x83de0328)
NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID = (0x28)
NV83DE_CTRL_CMD_DEBUG_SET_DROP_DEFERRED_RC = (0x83de0329)
NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS_MESSAGE_ID = (0x29)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG = (0x83de032a)
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2A)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE = (0x00000002)
NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS = (0x00000003)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG = (0x83de032b)
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID = (0x2B)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED = (0x00000001)
NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED = (0x00000002)
NV_STATUS_LEVEL_OK = 0
NV_STATUS_LEVEL_WARN = 1
NV_STATUS_LEVEL_ERR = 3
NV01_ROOT = (0x00000000)
NV1_ROOT = (0x00000000)
NV01_NULL_OBJECT = (0x00000000)
NV1_NULL_OBJECT = (0x00000000)
NV01_ROOT_NON_PRIV = (0x00000001)
NV1_ROOT_NON_PRIV = (0x00000001)
NV01_ROOT_CLIENT = (0x00000041)
FABRIC_MANAGER_SESSION = (0x0000000f)
NV0020_GPU_MANAGEMENT = (0x00000020)
NV01_DEVICE_0 = (0x00000080)
NV20_SUBDEVICE_0 = (0x00002080)
NV2081_BINAPI = (0x00002081)
NV2082_BINAPI_PRIVILEGED = (0x00002082)
NV20_SUBDEVICE_DIAG = (0x0000208f)
NV01_CONTEXT_DMA = (0x00000002)
NV01_MEMORY_SYSTEM = (0x0000003e)
NV1_MEMORY_SYSTEM = (0x0000003e)
NV01_MEMORY_LOCAL_PRIVILEGED = (0x0000003f)
NV1_MEMORY_LOCAL_PRIVILEGED = (0x0000003f)
NV01_MEMORY_PRIVILEGED = (0x0000003f)
NV1_MEMORY_PRIVILEGED = (0x0000003f)
NV01_MEMORY_LOCAL_USER = (0x00000040)
NV1_MEMORY_LOCAL_USER = (0x00000040)
NV01_MEMORY_USER = (0x00000040)
NV1_MEMORY_USER = (0x00000040)
NV_MEMORY_EXTENDED_USER = (0x00000042)
NV01_MEMORY_VIRTUAL = (0x00000070)
NV01_MEMORY_SYSTEM_DYNAMIC = (0x00000070)
NV1_MEMORY_SYSTEM_DYNAMIC = (0x00000070)
NV_MEMORY_MAPPER = (0x000000fe)
NV01_MEMORY_LOCAL_PHYSICAL = (0x000000c2)
NV01_MEMORY_SYNCPOINT = (0x000000c3)
NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = (0x00000071)
NV01_MEMORY_DEVICELESS = (0x000090ce)
NV01_MEMORY_FRAMEBUFFER_CONSOLE = (0x00000076)
NV01_MEMORY_HW_RESOURCES = (0x000000b1)
NV01_MEMORY_LIST_SYSTEM = (0x00000081)
NV01_MEMORY_LIST_FBMEM = (0x00000082)
NV01_MEMORY_LIST_OBJECT = (0x00000083)
NV_IMEX_SESSION = (0x000000f1)
NV01_MEMORY_FLA = (0x000000f3)
NV_MEMORY_EXPORT = (0x000000e0)
NV_CE_UTILS = (0x00000050)
NV_MEMORY_FABRIC = (0x000000f8)
NV_MEMORY_FABRIC_IMPORT_V2 = (0x000000f9)
NV_MEMORY_FABRIC_IMPORTED_REF = (0x000000fb)
FABRIC_VASPACE_A = (0x000000fc)
NV_MEMORY_MULTICAST_FABRIC = (0x000000fd)
IO_VASPACE_A = (0x000000f2)
NV01_NULL = (0x00000030)
NV1_NULL = (0x00000030)
NV01_EVENT = (0x00000005)
NV1_EVENT = (0x00000005)
NV01_EVENT_KERNEL_CALLBACK = (0x00000078)
NV1_EVENT_KERNEL_CALLBACK = (0x00000078)
NV01_EVENT_OS_EVENT = (0x00000079)
NV1_EVENT_OS_EVENT = (0x00000079)
NV01_EVENT_WIN32_EVENT = (0x00000079)
NV1_EVENT_WIN32_EVENT = (0x00000079)
NV01_EVENT_KERNEL_CALLBACK_EX = (0x0000007e)
NV1_EVENT_KERNEL_CALLBACK_EX = (0x0000007e)
NV01_TIMER = (0x00000004)
NV1_TIMER = (0x00000004)
KERNEL_GRAPHICS_CONTEXT = (0x00000090)
LOCK_STRESS_OBJECT = (0x00000100)
NV50_CHANNEL_GPFIFO = (0x0000506f)
GF100_CHANNEL_GPFIFO = (0x0000906f)
KEPLER_CHANNEL_GPFIFO_A = (0x0000a06f)
UVM_CHANNEL_RETAINER = (0x0000c574)
KEPLER_CHANNEL_GPFIFO_B = (0x0000a16f)
MAXWELL_CHANNEL_GPFIFO_A = (0x0000b06f)
PASCAL_CHANNEL_GPFIFO_A = (0x0000c06f)
VOLTA_CHANNEL_GPFIFO_A = (0x0000c36f)
TURING_CHANNEL_GPFIFO_A = (0x0000c46f)
AMPERE_CHANNEL_GPFIFO_A = (0x0000c56f)
HOPPER_CHANNEL_GPFIFO_A = (0x0000c86f)
BLACKWELL_CHANNEL_GPFIFO_A = (0x0000c96f)
BLACKWELL_CHANNEL_GPFIFO_B = (0x0000ca6f)
NV04_SOFTWARE_TEST = (0x0000007d)
NV4_SOFTWARE_TEST = (0x0000007d)
NV30_GSYNC = (0x000030f1)
VOLTA_USERMODE_A = (0x0000c361)
TURING_USERMODE_A = (0x0000c461)
AMPERE_USERMODE_A = (0x0000c561)
HOPPER_USERMODE_A = (0x0000c661)
BLACKWELL_USERMODE_A = (0x0000c761)
NVC371_DISP_SF_USER = (0x0000c371)
NVC372_DISPLAY_SW = (0x0000c372)
NVC573_DISP_CAPABILITIES = (0x0000c573)
NVC673_DISP_CAPABILITIES = (0x0000c673)
NVC773_DISP_CAPABILITIES = (0x0000c773)
NVC973_DISP_CAPABILITIES = (0x0000c973)
NVCA73_DISP_CAPABILITIES = (0x0000ca73)
NV04_DISPLAY_COMMON = (0x00000073)
NV50_DEFERRED_API_CLASS = (0x00005080)
MPS_COMPUTE = (0x0000900e)
NVC570_DISPLAY = (0x0000c570)
NVC57A_CURSOR_IMM_CHANNEL_PIO = (0x0000c57a)
NVC57B_WINDOW_IMM_CHANNEL_DMA = (0x0000c57b)
NVC57D_CORE_CHANNEL_DMA = (0x0000c57d)
NVC57E_WINDOW_CHANNEL_DMA = (0x0000c57e)
NVC670_DISPLAY = (0x0000c670)
NVC671_DISP_SF_USER = (0x0000c671)
NVC67A_CURSOR_IMM_CHANNEL_PIO = (0x0000c67a)
NVC67B_WINDOW_IMM_CHANNEL_DMA = (0x0000c67b)
NVC67D_CORE_CHANNEL_DMA = (0x0000c67d)
NVC67E_WINDOW_CHANNEL_DMA = (0x0000c67e)
NVC77F_ANY_CHANNEL_DMA = (0x0000c77f)
NVC770_DISPLAY = (0x0000c770)
NVC771_DISP_SF_USER = (0x0000c771)
NVC77D_CORE_CHANNEL_DMA = (0x0000c77d)
NVC970_DISPLAY = (0x0000c970)
NVC971_DISP_SF_USER = (0x0000c971)
NVC97A_CURSOR_IMM_CHANNEL_PIO = (0x0000c97a)
NVC97B_WINDOW_IMM_CHANNEL_DMA = (0x0000c97b)
NVC97D_CORE_CHANNEL_DMA = (0x0000c97d)
NVC97E_WINDOW_CHANNEL_DMA = (0x0000c97e)
NVCA70_DISPLAY = (0x0000ca70)
NVCA71_DISP_SF_USER = (0x0000ca71)
NVCA7A_CURSOR_IMM_CHANNEL_PIO = (0x0000ca7a)
NVCA7B_WINDOW_IMM_CHANNEL_DMA = (0x0000ca7b)
NVCA7D_CORE_CHANNEL_DMA = (0x0000ca7d)
NVCA7E_WINDOW_CHANNEL_DMA = (0x0000ca7e)
NV9010_VBLANK_CALLBACK = (0x00009010)
GF100_PROFILER = (0x000090cc)
MAXWELL_PROFILER = (0x0000b0cc)
MAXWELL_PROFILER_CONTEXT = (0x0000b1cc)
MAXWELL_PROFILER_DEVICE = (0x0000b2cc)
GF100_SUBDEVICE_MASTER = (0x000090e6)
GF100_SUBDEVICE_INFOROM = (0x000090e7)
GF100_ZBC_CLEAR = (0x00009096)
GF100_DISP_SW = (0x00009072)
GF100_TIMED_SEMAPHORE_SW = (0x00009074)
G84_PERFBUFFER = (0x0000844c)
NV50_MEMORY_VIRTUAL = (0x000050a0)
NV50_P2P = (0x0000503b)
NV50_THIRD_PARTY_P2P = (0x0000503c)
FERMI_TWOD_A = (0x0000902d)
FERMI_VASPACE_A = (0x000090f1)
HOPPER_SEC2_WORK_LAUNCH_A = (0x0000cba2)
GF100_HDACODEC = (0x000090ec)
NVB8B0_VIDEO_DECODER = (0x0000b8b0)
NVC4B0_VIDEO_DECODER = (0x0000c4b0)
NVC6B0_VIDEO_DECODER = (0x0000c6b0)
NVC7B0_VIDEO_DECODER = (0x0000c7b0)
NVC9B0_VIDEO_DECODER = (0x0000c9b0)
NVCDB0_VIDEO_DECODER = (0x0000cdb0)
NVCFB0_VIDEO_DECODER = (0x0000cfb0)
NVC4B7_VIDEO_ENCODER = (0x0000c4b7)
NVB4B7_VIDEO_ENCODER = (0x0000b4b7)
NVC7B7_VIDEO_ENCODER = (0x0000c7b7)
NVC9B7_VIDEO_ENCODER = (0x0000c9b7)
NVCFB7_VIDEO_ENCODER = (0x0000cfb7)
NVB8D1_VIDEO_NVJPG = (0x0000b8d1)
NVC4D1_VIDEO_NVJPG = (0x0000c4d1)
NVC9D1_VIDEO_NVJPG = (0x0000c9d1)
NVCDD1_VIDEO_NVJPG = (0x0000cdd1)
NVCFD1_VIDEO_NVJPG = (0x0000cfd1)
NVB8FA_VIDEO_OFA = (0x0000b8fa)
NVC6FA_VIDEO_OFA = (0x0000c6fa)
NVC7FA_VIDEO_OFA = (0x0000c7fa)
NVC9FA_VIDEO_OFA = (0x0000c9fa)
NVCDFA_VIDEO_OFA = (0x0000cdfa)
NVCFFA_VIDEO_OFA = (0x0000cffa)
KEPLER_INLINE_TO_MEMORY_B = (0x0000a140)
FERMI_CONTEXT_SHARE_A = (0x00009067)
KEPLER_CHANNEL_GROUP_A = (0x0000a06c)
PASCAL_DMA_COPY_A = (0x0000c0b5)
TURING_DMA_COPY_A = (0x0000c5b5)
AMPERE_DMA_COPY_A = (0x0000c6b5)
AMPERE_DMA_COPY_B = (0x0000c7b5)
HOPPER_DMA_COPY_A = (0x0000c8b5)
BLACKWELL_DMA_COPY_A = (0x0000c9b5)
BLACKWELL_DMA_COPY_B = (0x0000cab5)
MAXWELL_DMA_COPY_A = (0x0000b0b5)
ACCESS_COUNTER_NOTIFY_BUFFER = (0x0000c365)
MMU_FAULT_BUFFER = (0x0000c369)
MMU_VIDMEM_ACCESS_BIT_BUFFER = (0x0000c763)
TURING_A = (0x0000c597)
TURING_COMPUTE_A = (0x0000c5c0)
AMPERE_A = (0x0000c697)
AMPERE_COMPUTE_A = (0x0000c6c0)
AMPERE_B = (0x0000c797)
AMPERE_COMPUTE_B = (0x0000c7c0)
ADA_A = (0x0000c997)
ADA_COMPUTE_A = (0x0000c9c0)
AMPERE_SMC_PARTITION_REF = (0x0000c637)
AMPERE_SMC_EXEC_PARTITION_REF = (0x0000c638)
AMPERE_SMC_CONFIG_SESSION = (0x0000c639)
NV0092_RG_LINE_CALLBACK = (0x00000092)
AMPERE_SMC_MONITOR_SESSION = (0x0000c640)
HOPPER_A = (0x0000cb97)
HOPPER_COMPUTE_A = (0x0000cbc0)
BLACKWELL_A = (0x0000cd97)
BLACKWELL_COMPUTE_A = (0x0000cdc0)
BLACKWELL_B = (0x0000ce97)
BLACKWELL_COMPUTE_B = (0x0000cec0)
BLACKWELL_INLINE_TO_MEMORY_A = (0x0000cd40)
NV40_DEBUG_BUFFER = (0x000000db)
RM_USER_SHARED_DATA = (0x000000de)
GT200_DEBUGGER = (0x000083de)
NV40_I2C = (0x0000402c)
KEPLER_DEVICE_VGPU = (0x0000a080)
NVA081_VGPU_CONFIG = (0x0000a081)
NVA084_KERNEL_HOST_VGPU_DEVICE = (0x0000a084)
NV0060_SYNC_GPU_BOOST = (0x00000060)
GP100_UVM_SW = (0x0000c076)
NVENC_SW_SESSION = (0x0000a0bc)
NV_EVENT_BUFFER = (0x000090cd)
NVFBC_SW_SESSION = (0x0000a0bd)
NV_CONFIDENTIAL_COMPUTE = (0x0000cb33)
NV_COUNTER_COLLECTION_UNIT = (0x0000cbca)
NV_SEMAPHORE_SURFACE = (0x000000da)