diff --git a/.github/workflows/autogen.yml b/.github/workflows/autogen.yml index 3e2c73ea4b..c812588d14 100644 --- a/.github/workflows/autogen.yml +++ b/.github/workflows/autogen.yml @@ -116,11 +116,9 @@ jobs: - name: Verify Qualcomm autogen run: | mv tinygrad/runtime/autogen/kgsl.py /tmp/kgsl.py.bak - mv tinygrad/runtime/autogen/adreno.py /tmp/adreno.py.bak mv tinygrad/runtime/autogen/qcom_dsp.py /tmp/qcom_dsp.py.bak - python3 -c "from tinygrad.runtime.autogen import kgsl, adreno, qcom_dsp" + python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp" diff /tmp/kgsl.py.bak tinygrad/runtime/autogen/kgsl.py - diff /tmp/adreno.py.bak tinygrad/runtime/autogen/adreno.py diff /tmp/qcom_dsp.py.bak tinygrad/runtime/autogen/qcom_dsp.py - name: Verify libusb autogen run: | diff --git a/tinygrad/runtime/autogen/__init__.py b/tinygrad/runtime/autogen/__init__.py index 9f96b12f8c..3eadb25987 100644 --- a/tinygrad/runtime/autogen/__init__.py +++ b/tinygrad/runtime/autogen/__init__.py @@ -99,7 +99,6 @@ def __getattr__(nm): "sienna_cichlid_ip_offset"]], args=["-I/opt/rocm/include", "-x", "c++"]) case "kgsl": return load("kgsl", [], [root/"extra/qcom_gpu_driver/msm_kgsl.h"], args=["-D__user="]) - case "adreno": return load("adreno", [], [root/"extra/qcom_gpu_driver/a6xx.xml.h"]) case "qcom_dsp": return load("qcom_dsp", [], [root/f"extra/dsp/include/{s}.h" for s in ["ion", "msm_ion", "adsprpc_shared", "remote_default", "apps_std"]]) case "sqtt": return load("sqtt", [], [root/"extra/sqtt/sqtt.h"]) @@ -114,17 +113,16 @@ def __getattr__(nm): *[f"{{}}/src/nouveau/{s}.h" for s in ["headers/nv_device_info", "compiler/nak"]], *[f"{{}}/src/gallium/auxiliary/gallivm/lp_bld{s}.h" for s in ["", "_passmgr", "_misc", "_type", "_init", "_nir", "_struct", "_jit_types", "_flow", "_const"]], - "{}/src/compiler/glsl_types.h", "{}/src/util/blob.h", "{}/src/util/ralloc.h", "{}/gen/builtin_types.h"], args=lambda:[ + "{}/src/compiler/glsl_types.h", "{}/src/util/blob.h", "{}/src/util/ralloc.h", "{}/gen/builtin_types.h", "{}/gen/a6xx.xml.h", + "{}/gen/adreno_pm4.xml.h", "{}/gen/a6xx_enums.xml.h", "{}/gen/a6xx_descriptors.xml.h"], args=lambda:[ "-DHAVE_ENDIAN_H", "-DHAVE_STRUCT_TIMESPEC", "-DHAVE_PTHREAD", "-DHAVE_FUNC_ATTRIBUTE_PACKED", "-I{}/src", "-I{}/include", "-I{}/gen", "-I{}/src/compiler/nir", "-I{}/src/gallium/auxiliary", "-I{}/src/gallium/include", f"-I{system('llvm-config-20 --includedir')}"], - preprocess=lambda path: subprocess.run("""mkdir -p gen/util/format -python3 src/util/format/u_format_table.py src/util/format/u_format.yaml --enums > gen/util/format/u_format_gen.h -python3 src/compiler/nir/nir_opcodes_h.py > gen/nir_opcodes.h -python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen -python3 src/compiler/nir/nir_intrinsics_indices_h.py --outdir gen -python3 src/compiler/nir/nir_builder_opcodes_h.py > gen/nir_builder_opcodes.h -python3 src/compiler/nir/nir_intrinsics_h.py --outdir gen -python3 src/compiler/builtin_types_h.py gen/builtin_types.h""", cwd=path, shell=True, check=True), + preprocess=lambda path: subprocess.run("\n".join(["mkdir -p gen/util/format", "python3 src/compiler/builtin_types_h.py gen/builtin_types.h", + "python3 src/util/format/u_format_table.py src/util/format/u_format.yaml --enums > gen/util/format/u_format_gen.h", + *["python3 src/freedreno/registers/gen_header.py --rnn src/freedreno/registers/ --xml " + + f"src/freedreno/registers/adreno/{s}.xml c-defines > gen/{s}.xml.h" for s in ["a6xx", "adreno_pm4", "a6xx_enums", "a6xx_descriptors"]], + *[f"python3 src/compiler/{s}_h.py > gen/{s.split('/')[-1]}.h" for s in ["nir/nir_opcodes", "nir/nir_builder_opcodes"]], + *[f"python3 src/compiler/nir/nir_{s}_h.py --outdir gen" for s in ["intrinsics", "intrinsics_indices"]]]), cwd=path, shell=True, check=True), tarball="https://gitlab.freedesktop.org/mesa/mesa/-/archive/mesa-25.2.4/mesa-25.2.4.tar.gz", prolog=["import gzip, base64", "from tinygrad.helpers import OSX"], epilog=lambda path: [system(f"{root}/extra/mesa/lvp_nir_options.sh {path}")]) case "libclang": @@ -135,4 +133,4 @@ python3 src/compiler/builtin_types_h.py gen/builtin_types.h""", cwd=path, shell= return load("metal", ["find_library('Metal')"],[f"{macossdk}/System/Library/Frameworks/Metal.framework/Headers/MTL{s}.h" for s in ["ComputeCommandEncoder", "ComputePipeline", "CommandQueue", "Device", "IndirectCommandBuffer", "Resource", "CommandEncoder"]], args=["-xobjective-c","-isysroot",macossdk], types={"dispatch_data_t":"objc.id_"}) - case _: raise AttributeError(f"no such autogen: {nm}") \ No newline at end of file + case _: raise AttributeError(f"no such autogen: {nm}") diff --git a/tinygrad/runtime/autogen/adreno.py b/tinygrad/runtime/autogen/adreno.py deleted file mode 100644 index f34f825c35..0000000000 --- a/tinygrad/runtime/autogen/adreno.py +++ /dev/null @@ -1,7807 +0,0 @@ -# mypy: ignore-errors -import ctypes -from tinygrad.helpers import unwrap -from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR -enum_vgt_event_type = CEnum(ctypes.c_uint32) -VS_DEALLOC = enum_vgt_event_type.define('VS_DEALLOC', 0) -PS_DEALLOC = enum_vgt_event_type.define('PS_DEALLOC', 1) -VS_DONE_TS = enum_vgt_event_type.define('VS_DONE_TS', 2) -PS_DONE_TS = enum_vgt_event_type.define('PS_DONE_TS', 3) -CACHE_FLUSH_TS = enum_vgt_event_type.define('CACHE_FLUSH_TS', 4) -CONTEXT_DONE = enum_vgt_event_type.define('CONTEXT_DONE', 5) -CACHE_FLUSH = enum_vgt_event_type.define('CACHE_FLUSH', 6) -VIZQUERY_START = enum_vgt_event_type.define('VIZQUERY_START', 7) -HLSQ_FLUSH = enum_vgt_event_type.define('HLSQ_FLUSH', 7) -VIZQUERY_END = enum_vgt_event_type.define('VIZQUERY_END', 8) -SC_WAIT_WC = enum_vgt_event_type.define('SC_WAIT_WC', 9) -WRITE_PRIMITIVE_COUNTS = enum_vgt_event_type.define('WRITE_PRIMITIVE_COUNTS', 9) -START_PRIMITIVE_CTRS = enum_vgt_event_type.define('START_PRIMITIVE_CTRS', 11) -STOP_PRIMITIVE_CTRS = enum_vgt_event_type.define('STOP_PRIMITIVE_CTRS', 12) -RST_PIX_CNT = enum_vgt_event_type.define('RST_PIX_CNT', 13) -RST_VTX_CNT = enum_vgt_event_type.define('RST_VTX_CNT', 14) -TILE_FLUSH = enum_vgt_event_type.define('TILE_FLUSH', 15) -STAT_EVENT = enum_vgt_event_type.define('STAT_EVENT', 16) -CACHE_FLUSH_AND_INV_TS_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) -ZPASS_DONE = enum_vgt_event_type.define('ZPASS_DONE', 21) -CACHE_FLUSH_AND_INV_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_EVENT', 22) -RB_DONE_TS = enum_vgt_event_type.define('RB_DONE_TS', 22) -PERFCOUNTER_START = enum_vgt_event_type.define('PERFCOUNTER_START', 23) -PERFCOUNTER_STOP = enum_vgt_event_type.define('PERFCOUNTER_STOP', 24) -VS_FETCH_DONE = enum_vgt_event_type.define('VS_FETCH_DONE', 27) -FACENESS_FLUSH = enum_vgt_event_type.define('FACENESS_FLUSH', 28) -WT_DONE_TS = enum_vgt_event_type.define('WT_DONE_TS', 8) -START_FRAGMENT_CTRS = enum_vgt_event_type.define('START_FRAGMENT_CTRS', 13) -STOP_FRAGMENT_CTRS = enum_vgt_event_type.define('STOP_FRAGMENT_CTRS', 14) -START_COMPUTE_CTRS = enum_vgt_event_type.define('START_COMPUTE_CTRS', 15) -STOP_COMPUTE_CTRS = enum_vgt_event_type.define('STOP_COMPUTE_CTRS', 16) -FLUSH_SO_0 = enum_vgt_event_type.define('FLUSH_SO_0', 17) -FLUSH_SO_1 = enum_vgt_event_type.define('FLUSH_SO_1', 18) -FLUSH_SO_2 = enum_vgt_event_type.define('FLUSH_SO_2', 19) -FLUSH_SO_3 = enum_vgt_event_type.define('FLUSH_SO_3', 20) -PC_CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('PC_CCU_INVALIDATE_DEPTH', 24) -PC_CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('PC_CCU_INVALIDATE_COLOR', 25) -PC_CCU_RESOLVE_TS = enum_vgt_event_type.define('PC_CCU_RESOLVE_TS', 26) -PC_CCU_FLUSH_DEPTH_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_DEPTH_TS', 28) -PC_CCU_FLUSH_COLOR_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_COLOR_TS', 29) -BLIT = enum_vgt_event_type.define('BLIT', 30) -LRZ_FLIP_BUFFER = enum_vgt_event_type.define('LRZ_FLIP_BUFFER', 36) -LRZ_CLEAR = enum_vgt_event_type.define('LRZ_CLEAR', 37) -LRZ_FLUSH = enum_vgt_event_type.define('LRZ_FLUSH', 38) -BLIT_OP_FILL_2D = enum_vgt_event_type.define('BLIT_OP_FILL_2D', 39) -BLIT_OP_COPY_2D = enum_vgt_event_type.define('BLIT_OP_COPY_2D', 40) -UNK_40 = enum_vgt_event_type.define('UNK_40', 40) -BLIT_OP_SCALE_2D = enum_vgt_event_type.define('BLIT_OP_SCALE_2D', 42) -CONTEXT_DONE_2D = enum_vgt_event_type.define('CONTEXT_DONE_2D', 43) -UNK_2C = enum_vgt_event_type.define('UNK_2C', 44) -UNK_2D = enum_vgt_event_type.define('UNK_2D', 45) -CACHE_INVALIDATE = enum_vgt_event_type.define('CACHE_INVALIDATE', 49) -LABEL = enum_vgt_event_type.define('LABEL', 63) -DUMMY_EVENT = enum_vgt_event_type.define('DUMMY_EVENT', 1) -CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('CCU_INVALIDATE_DEPTH', 24) -CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('CCU_INVALIDATE_COLOR', 25) -CCU_RESOLVE_CLEAN = enum_vgt_event_type.define('CCU_RESOLVE_CLEAN', 26) -CCU_FLUSH_DEPTH = enum_vgt_event_type.define('CCU_FLUSH_DEPTH', 28) -CCU_FLUSH_COLOR = enum_vgt_event_type.define('CCU_FLUSH_COLOR', 29) -CCU_RESOLVE = enum_vgt_event_type.define('CCU_RESOLVE', 30) -CCU_END_RESOLVE_GROUP = enum_vgt_event_type.define('CCU_END_RESOLVE_GROUP', 31) -CCU_CLEAN_DEPTH = enum_vgt_event_type.define('CCU_CLEAN_DEPTH', 32) -CCU_CLEAN_COLOR = enum_vgt_event_type.define('CCU_CLEAN_COLOR', 33) -CACHE_RESET = enum_vgt_event_type.define('CACHE_RESET', 48) -CACHE_CLEAN = enum_vgt_event_type.define('CACHE_CLEAN', 49) -CACHE_FLUSH7 = enum_vgt_event_type.define('CACHE_FLUSH7', 50) -CACHE_INVALIDATE7 = enum_vgt_event_type.define('CACHE_INVALIDATE7', 51) - -enum_pc_di_primtype = CEnum(ctypes.c_uint32) -DI_PT_NONE = enum_pc_di_primtype.define('DI_PT_NONE', 0) -DI_PT_POINTLIST_PSIZE = enum_pc_di_primtype.define('DI_PT_POINTLIST_PSIZE', 1) -DI_PT_LINELIST = enum_pc_di_primtype.define('DI_PT_LINELIST', 2) -DI_PT_LINESTRIP = enum_pc_di_primtype.define('DI_PT_LINESTRIP', 3) -DI_PT_TRILIST = enum_pc_di_primtype.define('DI_PT_TRILIST', 4) -DI_PT_TRIFAN = enum_pc_di_primtype.define('DI_PT_TRIFAN', 5) -DI_PT_TRISTRIP = enum_pc_di_primtype.define('DI_PT_TRISTRIP', 6) -DI_PT_LINELOOP = enum_pc_di_primtype.define('DI_PT_LINELOOP', 7) -DI_PT_RECTLIST = enum_pc_di_primtype.define('DI_PT_RECTLIST', 8) -DI_PT_POINTLIST = enum_pc_di_primtype.define('DI_PT_POINTLIST', 9) -DI_PT_LINE_ADJ = enum_pc_di_primtype.define('DI_PT_LINE_ADJ', 10) -DI_PT_LINESTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_LINESTRIP_ADJ', 11) -DI_PT_TRI_ADJ = enum_pc_di_primtype.define('DI_PT_TRI_ADJ', 12) -DI_PT_TRISTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_TRISTRIP_ADJ', 13) -DI_PT_PATCHES0 = enum_pc_di_primtype.define('DI_PT_PATCHES0', 31) -DI_PT_PATCHES1 = enum_pc_di_primtype.define('DI_PT_PATCHES1', 32) -DI_PT_PATCHES2 = enum_pc_di_primtype.define('DI_PT_PATCHES2', 33) -DI_PT_PATCHES3 = enum_pc_di_primtype.define('DI_PT_PATCHES3', 34) -DI_PT_PATCHES4 = enum_pc_di_primtype.define('DI_PT_PATCHES4', 35) -DI_PT_PATCHES5 = enum_pc_di_primtype.define('DI_PT_PATCHES5', 36) -DI_PT_PATCHES6 = enum_pc_di_primtype.define('DI_PT_PATCHES6', 37) -DI_PT_PATCHES7 = enum_pc_di_primtype.define('DI_PT_PATCHES7', 38) -DI_PT_PATCHES8 = enum_pc_di_primtype.define('DI_PT_PATCHES8', 39) -DI_PT_PATCHES9 = enum_pc_di_primtype.define('DI_PT_PATCHES9', 40) -DI_PT_PATCHES10 = enum_pc_di_primtype.define('DI_PT_PATCHES10', 41) -DI_PT_PATCHES11 = enum_pc_di_primtype.define('DI_PT_PATCHES11', 42) -DI_PT_PATCHES12 = enum_pc_di_primtype.define('DI_PT_PATCHES12', 43) -DI_PT_PATCHES13 = enum_pc_di_primtype.define('DI_PT_PATCHES13', 44) -DI_PT_PATCHES14 = enum_pc_di_primtype.define('DI_PT_PATCHES14', 45) -DI_PT_PATCHES15 = enum_pc_di_primtype.define('DI_PT_PATCHES15', 46) -DI_PT_PATCHES16 = enum_pc_di_primtype.define('DI_PT_PATCHES16', 47) -DI_PT_PATCHES17 = enum_pc_di_primtype.define('DI_PT_PATCHES17', 48) -DI_PT_PATCHES18 = enum_pc_di_primtype.define('DI_PT_PATCHES18', 49) -DI_PT_PATCHES19 = enum_pc_di_primtype.define('DI_PT_PATCHES19', 50) -DI_PT_PATCHES20 = enum_pc_di_primtype.define('DI_PT_PATCHES20', 51) -DI_PT_PATCHES21 = enum_pc_di_primtype.define('DI_PT_PATCHES21', 52) -DI_PT_PATCHES22 = enum_pc_di_primtype.define('DI_PT_PATCHES22', 53) -DI_PT_PATCHES23 = enum_pc_di_primtype.define('DI_PT_PATCHES23', 54) -DI_PT_PATCHES24 = enum_pc_di_primtype.define('DI_PT_PATCHES24', 55) -DI_PT_PATCHES25 = enum_pc_di_primtype.define('DI_PT_PATCHES25', 56) -DI_PT_PATCHES26 = enum_pc_di_primtype.define('DI_PT_PATCHES26', 57) -DI_PT_PATCHES27 = enum_pc_di_primtype.define('DI_PT_PATCHES27', 58) -DI_PT_PATCHES28 = enum_pc_di_primtype.define('DI_PT_PATCHES28', 59) -DI_PT_PATCHES29 = enum_pc_di_primtype.define('DI_PT_PATCHES29', 60) -DI_PT_PATCHES30 = enum_pc_di_primtype.define('DI_PT_PATCHES30', 61) -DI_PT_PATCHES31 = enum_pc_di_primtype.define('DI_PT_PATCHES31', 62) - -enum_pc_di_src_sel = CEnum(ctypes.c_uint32) -DI_SRC_SEL_DMA = enum_pc_di_src_sel.define('DI_SRC_SEL_DMA', 0) -DI_SRC_SEL_IMMEDIATE = enum_pc_di_src_sel.define('DI_SRC_SEL_IMMEDIATE', 1) -DI_SRC_SEL_AUTO_INDEX = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_INDEX', 2) -DI_SRC_SEL_AUTO_XFB = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_XFB', 3) - -enum_pc_di_face_cull_sel = CEnum(ctypes.c_uint32) -DI_FACE_CULL_NONE = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_NONE', 0) -DI_FACE_CULL_FETCH = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_FETCH', 1) -DI_FACE_BACKFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_BACKFACE_CULL', 2) -DI_FACE_FRONTFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_FRONTFACE_CULL', 3) - -enum_pc_di_index_size = CEnum(ctypes.c_uint32) -INDEX_SIZE_IGN = enum_pc_di_index_size.define('INDEX_SIZE_IGN', 0) -INDEX_SIZE_16_BIT = enum_pc_di_index_size.define('INDEX_SIZE_16_BIT', 0) -INDEX_SIZE_32_BIT = enum_pc_di_index_size.define('INDEX_SIZE_32_BIT', 1) -INDEX_SIZE_8_BIT = enum_pc_di_index_size.define('INDEX_SIZE_8_BIT', 2) -INDEX_SIZE_INVALID = enum_pc_di_index_size.define('INDEX_SIZE_INVALID', 0) - -enum_pc_di_vis_cull_mode = CEnum(ctypes.c_uint32) -IGNORE_VISIBILITY = enum_pc_di_vis_cull_mode.define('IGNORE_VISIBILITY', 0) -USE_VISIBILITY = enum_pc_di_vis_cull_mode.define('USE_VISIBILITY', 1) - -enum_adreno_pm4_packet_type = CEnum(ctypes.c_uint32) -CP_TYPE0_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE0_PKT', 0) -CP_TYPE1_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE1_PKT', 1073741824) -CP_TYPE2_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE2_PKT', 2147483648) -CP_TYPE3_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE3_PKT', 3221225472) -CP_TYPE4_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE4_PKT', 1073741824) -CP_TYPE7_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE7_PKT', 1879048192) - -enum_adreno_pm4_type3_packets = CEnum(ctypes.c_uint32) -CP_ME_INIT = enum_adreno_pm4_type3_packets.define('CP_ME_INIT', 72) -CP_NOP = enum_adreno_pm4_type3_packets.define('CP_NOP', 16) -CP_PREEMPT_ENABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE', 28) -CP_PREEMPT_TOKEN = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_TOKEN', 30) -CP_INDIRECT_BUFFER = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER', 63) -CP_INDIRECT_BUFFER_CHAIN = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_CHAIN', 87) -CP_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFD', 55) -CP_WAIT_FOR_IDLE = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_IDLE', 38) -CP_WAIT_REG_MEM = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_MEM', 60) -CP_WAIT_REG_EQ = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_EQ', 82) -CP_WAIT_REG_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_GTE', 83) -CP_WAIT_UNTIL_READ = enum_adreno_pm4_type3_packets.define('CP_WAIT_UNTIL_READ', 92) -CP_WAIT_IB_PFD_COMPLETE = enum_adreno_pm4_type3_packets.define('CP_WAIT_IB_PFD_COMPLETE', 93) -CP_REG_RMW = enum_adreno_pm4_type3_packets.define('CP_REG_RMW', 33) -CP_SET_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA', 47) -CP_SET_BIN_DATA5 = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5', 47) -CP_REG_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM', 62) -CP_MEM_WRITE = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE', 61) -CP_MEM_WRITE_CNTR = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE_CNTR', 79) -CP_COND_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_EXEC', 68) -CP_COND_WRITE = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE', 69) -CP_COND_WRITE5 = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE5', 69) -CP_EVENT_WRITE = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE', 70) -CP_EVENT_WRITE7 = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE7', 70) -CP_EVENT_WRITE_SHD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_SHD', 88) -CP_EVENT_WRITE_CFL = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_CFL', 89) -CP_EVENT_WRITE_ZPD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_ZPD', 91) -CP_RUN_OPENCL = enum_adreno_pm4_type3_packets.define('CP_RUN_OPENCL', 49) -CP_DRAW_INDX = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX', 34) -CP_DRAW_INDX_2 = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2', 54) -CP_DRAW_INDX_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_BIN', 52) -CP_DRAW_INDX_2_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2_BIN', 53) -CP_VIZ_QUERY = enum_adreno_pm4_type3_packets.define('CP_VIZ_QUERY', 35) -CP_SET_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_STATE', 37) -CP_SET_CONSTANT = enum_adreno_pm4_type3_packets.define('CP_SET_CONSTANT', 45) -CP_IM_LOAD = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD', 39) -CP_IM_LOAD_IMMEDIATE = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD_IMMEDIATE', 43) -CP_LOAD_CONSTANT_CONTEXT = enum_adreno_pm4_type3_packets.define('CP_LOAD_CONSTANT_CONTEXT', 46) -CP_INVALIDATE_STATE = enum_adreno_pm4_type3_packets.define('CP_INVALIDATE_STATE', 59) -CP_SET_SHADER_BASES = enum_adreno_pm4_type3_packets.define('CP_SET_SHADER_BASES', 74) -CP_SET_BIN_MASK = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_MASK', 80) -CP_SET_BIN_SELECT = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_SELECT', 81) -CP_CONTEXT_UPDATE = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_UPDATE', 94) -CP_INTERRUPT = enum_adreno_pm4_type3_packets.define('CP_INTERRUPT', 64) -CP_IM_STORE = enum_adreno_pm4_type3_packets.define('CP_IM_STORE', 44) -CP_SET_DRAW_INIT_FLAGS = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_INIT_FLAGS', 75) -CP_SET_PROTECTED_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_PROTECTED_MODE', 95) -CP_BOOTSTRAP_UCODE = enum_adreno_pm4_type3_packets.define('CP_BOOTSTRAP_UCODE', 111) -CP_LOAD_STATE = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE', 48) -CP_LOAD_STATE4 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE4', 48) -CP_COND_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFE', 58) -CP_COND_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFD', 50) -CP_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFE', 63) -CP_SET_BIN = enum_adreno_pm4_type3_packets.define('CP_SET_BIN', 76) -CP_TEST_TWO_MEMS = enum_adreno_pm4_type3_packets.define('CP_TEST_TWO_MEMS', 113) -CP_REG_WR_NO_CTXT = enum_adreno_pm4_type3_packets.define('CP_REG_WR_NO_CTXT', 120) -CP_RECORD_PFP_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_RECORD_PFP_TIMESTAMP', 17) -CP_SET_SECURE_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_SECURE_MODE', 102) -CP_WAIT_FOR_ME = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_ME', 19) -CP_SET_DRAW_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_STATE', 67) -CP_DRAW_INDX_OFFSET = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_OFFSET', 56) -CP_DRAW_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT', 40) -CP_DRAW_INDX_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_INDIRECT', 41) -CP_DRAW_INDIRECT_MULTI = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT_MULTI', 42) -CP_DRAW_AUTO = enum_adreno_pm4_type3_packets.define('CP_DRAW_AUTO', 36) -CP_DRAW_PRED_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_GLOBAL', 25) -CP_DRAW_PRED_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_LOCAL', 26) -CP_DRAW_PRED_SET = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_SET', 78) -CP_WIDE_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_WIDE_REG_WRITE', 116) -CP_SCRATCH_TO_REG = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_TO_REG', 77) -CP_REG_TO_SCRATCH = enum_adreno_pm4_type3_packets.define('CP_REG_TO_SCRATCH', 74) -CP_WAIT_MEM_WRITES = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_WRITES', 18) -CP_COND_REG_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_REG_EXEC', 71) -CP_MEM_TO_REG = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_REG', 66) -CP_EXEC_CS_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS_INDIRECT', 65) -CP_EXEC_CS = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS', 51) -CP_PERFCOUNTER_ACTION = enum_adreno_pm4_type3_packets.define('CP_PERFCOUNTER_ACTION', 80) -CP_SMMU_TABLE_UPDATE = enum_adreno_pm4_type3_packets.define('CP_SMMU_TABLE_UPDATE', 83) -CP_SET_MARKER = enum_adreno_pm4_type3_packets.define('CP_SET_MARKER', 101) -CP_SET_PSEUDO_REG = enum_adreno_pm4_type3_packets.define('CP_SET_PSEUDO_REG', 86) -CP_CONTEXT_REG_BUNCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH', 92) -CP_YIELD_ENABLE = enum_adreno_pm4_type3_packets.define('CP_YIELD_ENABLE', 28) -CP_SKIP_IB2_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_GLOBAL', 29) -CP_SKIP_IB2_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_LOCAL', 35) -CP_SET_SUBDRAW_SIZE = enum_adreno_pm4_type3_packets.define('CP_SET_SUBDRAW_SIZE', 53) -CP_WHERE_AM_I = enum_adreno_pm4_type3_packets.define('CP_WHERE_AM_I', 98) -CP_SET_VISIBILITY_OVERRIDE = enum_adreno_pm4_type3_packets.define('CP_SET_VISIBILITY_OVERRIDE', 100) -CP_PREEMPT_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_GLOBAL', 105) -CP_PREEMPT_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_LOCAL', 106) -CP_CONTEXT_SWITCH_YIELD = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH_YIELD', 107) -CP_SET_RENDER_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_RENDER_MODE', 108) -CP_COMPUTE_CHECKPOINT = enum_adreno_pm4_type3_packets.define('CP_COMPUTE_CHECKPOINT', 110) -CP_MEM_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_MEM', 115) -CP_BLIT = enum_adreno_pm4_type3_packets.define('CP_BLIT', 44) -CP_REG_TEST = enum_adreno_pm4_type3_packets.define('CP_REG_TEST', 57) -CP_SET_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_MODE', 99) -CP_LOAD_STATE6_GEOM = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_GEOM', 50) -CP_LOAD_STATE6_FRAG = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_FRAG', 52) -CP_LOAD_STATE6 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6', 54) -IN_IB_PREFETCH_END = enum_adreno_pm4_type3_packets.define('IN_IB_PREFETCH_END', 23) -IN_SUBBLK_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_SUBBLK_PREFETCH', 31) -IN_INSTR_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_PREFETCH', 32) -IN_INSTR_MATCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_MATCH', 71) -IN_CONST_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_CONST_PREFETCH', 73) -IN_INCR_UPDT_STATE = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_STATE', 85) -IN_INCR_UPDT_CONST = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_CONST', 86) -IN_INCR_UPDT_INSTR = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_INSTR', 87) -PKT4 = enum_adreno_pm4_type3_packets.define('PKT4', 4) -IN_IB_END = enum_adreno_pm4_type3_packets.define('IN_IB_END', 10) -IN_GMU_INTERRUPT = enum_adreno_pm4_type3_packets.define('IN_GMU_INTERRUPT', 11) -IN_PREEMPT = enum_adreno_pm4_type3_packets.define('IN_PREEMPT', 15) -CP_SCRATCH_WRITE = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_WRITE', 76) -CP_REG_TO_MEM_OFFSET_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_MEM', 116) -CP_REG_TO_MEM_OFFSET_REG = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_REG', 114) -CP_WAIT_MEM_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_GTE', 20) -CP_WAIT_TWO_REGS = enum_adreno_pm4_type3_packets.define('CP_WAIT_TWO_REGS', 112) -CP_MEMCPY = enum_adreno_pm4_type3_packets.define('CP_MEMCPY', 117) -CP_SET_BIN_DATA5_OFFSET = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5_OFFSET', 46) -CP_SET_UNK_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_UNK_BIN_DATA', 45) -CP_CONTEXT_SWITCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH', 84) -CP_SET_CTXSWITCH_IB = enum_adreno_pm4_type3_packets.define('CP_SET_CTXSWITCH_IB', 85) -CP_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_REG_WRITE', 109) -CP_START_BIN = enum_adreno_pm4_type3_packets.define('CP_START_BIN', 80) -CP_END_BIN = enum_adreno_pm4_type3_packets.define('CP_END_BIN', 81) -CP_PREEMPT_DISABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_DISABLE', 108) -CP_WAIT_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_WAIT_TIMESTAMP', 20) -CP_GLOBAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_GLOBAL_TIMESTAMP', 21) -CP_LOCAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_LOCAL_TIMESTAMP', 22) -CP_THREAD_CONTROL = enum_adreno_pm4_type3_packets.define('CP_THREAD_CONTROL', 23) -CP_RESOURCE_LIST = enum_adreno_pm4_type3_packets.define('CP_RESOURCE_LIST', 24) -CP_BV_BR_COUNT_OPS = enum_adreno_pm4_type3_packets.define('CP_BV_BR_COUNT_OPS', 27) -CP_MODIFY_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_MODIFY_TIMESTAMP', 28) -CP_CONTEXT_REG_BUNCH2 = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH2', 93) -CP_MEM_TO_SCRATCH_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_SCRATCH_MEM', 73) -CP_FIXED_STRIDE_DRAW_TABLE = enum_adreno_pm4_type3_packets.define('CP_FIXED_STRIDE_DRAW_TABLE', 127) -CP_RESET_CONTEXT_STATE = enum_adreno_pm4_type3_packets.define('CP_RESET_CONTEXT_STATE', 31) -CP_CCHE_INVALIDATE = enum_adreno_pm4_type3_packets.define('CP_CCHE_INVALIDATE', 58) - -enum_adreno_state_block = CEnum(ctypes.c_uint32) -SB_VERT_TEX = enum_adreno_state_block.define('SB_VERT_TEX', 0) -SB_VERT_MIPADDR = enum_adreno_state_block.define('SB_VERT_MIPADDR', 1) -SB_FRAG_TEX = enum_adreno_state_block.define('SB_FRAG_TEX', 2) -SB_FRAG_MIPADDR = enum_adreno_state_block.define('SB_FRAG_MIPADDR', 3) -SB_VERT_SHADER = enum_adreno_state_block.define('SB_VERT_SHADER', 4) -SB_GEOM_SHADER = enum_adreno_state_block.define('SB_GEOM_SHADER', 5) -SB_FRAG_SHADER = enum_adreno_state_block.define('SB_FRAG_SHADER', 6) -SB_COMPUTE_SHADER = enum_adreno_state_block.define('SB_COMPUTE_SHADER', 7) - -enum_adreno_state_type = CEnum(ctypes.c_uint32) -ST_SHADER = enum_adreno_state_type.define('ST_SHADER', 0) -ST_CONSTANTS = enum_adreno_state_type.define('ST_CONSTANTS', 1) - -enum_adreno_state_src = CEnum(ctypes.c_uint32) -SS_DIRECT = enum_adreno_state_src.define('SS_DIRECT', 0) -SS_INVALID_ALL_IC = enum_adreno_state_src.define('SS_INVALID_ALL_IC', 2) -SS_INVALID_PART_IC = enum_adreno_state_src.define('SS_INVALID_PART_IC', 3) -SS_INDIRECT = enum_adreno_state_src.define('SS_INDIRECT', 4) -SS_INDIRECT_TCM = enum_adreno_state_src.define('SS_INDIRECT_TCM', 5) -SS_INDIRECT_STM = enum_adreno_state_src.define('SS_INDIRECT_STM', 6) - -enum_a4xx_state_block = CEnum(ctypes.c_uint32) -SB4_VS_TEX = enum_a4xx_state_block.define('SB4_VS_TEX', 0) -SB4_HS_TEX = enum_a4xx_state_block.define('SB4_HS_TEX', 1) -SB4_DS_TEX = enum_a4xx_state_block.define('SB4_DS_TEX', 2) -SB4_GS_TEX = enum_a4xx_state_block.define('SB4_GS_TEX', 3) -SB4_FS_TEX = enum_a4xx_state_block.define('SB4_FS_TEX', 4) -SB4_CS_TEX = enum_a4xx_state_block.define('SB4_CS_TEX', 5) -SB4_VS_SHADER = enum_a4xx_state_block.define('SB4_VS_SHADER', 8) -SB4_HS_SHADER = enum_a4xx_state_block.define('SB4_HS_SHADER', 9) -SB4_DS_SHADER = enum_a4xx_state_block.define('SB4_DS_SHADER', 10) -SB4_GS_SHADER = enum_a4xx_state_block.define('SB4_GS_SHADER', 11) -SB4_FS_SHADER = enum_a4xx_state_block.define('SB4_FS_SHADER', 12) -SB4_CS_SHADER = enum_a4xx_state_block.define('SB4_CS_SHADER', 13) -SB4_SSBO = enum_a4xx_state_block.define('SB4_SSBO', 14) -SB4_CS_SSBO = enum_a4xx_state_block.define('SB4_CS_SSBO', 15) - -enum_a4xx_state_type = CEnum(ctypes.c_uint32) -ST4_SHADER = enum_a4xx_state_type.define('ST4_SHADER', 0) -ST4_CONSTANTS = enum_a4xx_state_type.define('ST4_CONSTANTS', 1) -ST4_UBO = enum_a4xx_state_type.define('ST4_UBO', 2) - -enum_a4xx_state_src = CEnum(ctypes.c_uint32) -SS4_DIRECT = enum_a4xx_state_src.define('SS4_DIRECT', 0) -SS4_INDIRECT = enum_a4xx_state_src.define('SS4_INDIRECT', 2) - -enum_a6xx_state_block = CEnum(ctypes.c_uint32) -SB6_VS_TEX = enum_a6xx_state_block.define('SB6_VS_TEX', 0) -SB6_HS_TEX = enum_a6xx_state_block.define('SB6_HS_TEX', 1) -SB6_DS_TEX = enum_a6xx_state_block.define('SB6_DS_TEX', 2) -SB6_GS_TEX = enum_a6xx_state_block.define('SB6_GS_TEX', 3) -SB6_FS_TEX = enum_a6xx_state_block.define('SB6_FS_TEX', 4) -SB6_CS_TEX = enum_a6xx_state_block.define('SB6_CS_TEX', 5) -SB6_VS_SHADER = enum_a6xx_state_block.define('SB6_VS_SHADER', 8) -SB6_HS_SHADER = enum_a6xx_state_block.define('SB6_HS_SHADER', 9) -SB6_DS_SHADER = enum_a6xx_state_block.define('SB6_DS_SHADER', 10) -SB6_GS_SHADER = enum_a6xx_state_block.define('SB6_GS_SHADER', 11) -SB6_FS_SHADER = enum_a6xx_state_block.define('SB6_FS_SHADER', 12) -SB6_CS_SHADER = enum_a6xx_state_block.define('SB6_CS_SHADER', 13) -SB6_IBO = enum_a6xx_state_block.define('SB6_IBO', 14) -SB6_CS_IBO = enum_a6xx_state_block.define('SB6_CS_IBO', 15) - -enum_a6xx_state_type = CEnum(ctypes.c_uint32) -ST6_SHADER = enum_a6xx_state_type.define('ST6_SHADER', 0) -ST6_CONSTANTS = enum_a6xx_state_type.define('ST6_CONSTANTS', 1) -ST6_UBO = enum_a6xx_state_type.define('ST6_UBO', 2) -ST6_IBO = enum_a6xx_state_type.define('ST6_IBO', 3) - -enum_a6xx_state_src = CEnum(ctypes.c_uint32) -SS6_DIRECT = enum_a6xx_state_src.define('SS6_DIRECT', 0) -SS6_BINDLESS = enum_a6xx_state_src.define('SS6_BINDLESS', 1) -SS6_INDIRECT = enum_a6xx_state_src.define('SS6_INDIRECT', 2) -SS6_UBO = enum_a6xx_state_src.define('SS6_UBO', 3) - -enum_a4xx_index_size = CEnum(ctypes.c_uint32) -INDEX4_SIZE_8_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_8_BIT', 0) -INDEX4_SIZE_16_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_16_BIT', 1) -INDEX4_SIZE_32_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_32_BIT', 2) - -enum_a6xx_patch_type = CEnum(ctypes.c_uint32) -TESS_QUADS = enum_a6xx_patch_type.define('TESS_QUADS', 0) -TESS_TRIANGLES = enum_a6xx_patch_type.define('TESS_TRIANGLES', 1) -TESS_ISOLINES = enum_a6xx_patch_type.define('TESS_ISOLINES', 2) - -enum_a6xx_draw_indirect_opcode = CEnum(ctypes.c_uint32) -INDIRECT_OP_NORMAL = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_NORMAL', 2) -INDIRECT_OP_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDEXED', 4) -INDIRECT_OP_INDIRECT_COUNT = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT', 6) -INDIRECT_OP_INDIRECT_COUNT_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT_INDEXED', 7) - -enum_cp_draw_pred_src = CEnum(ctypes.c_uint32) -PRED_SRC_MEM = enum_cp_draw_pred_src.define('PRED_SRC_MEM', 5) - -enum_cp_draw_pred_test = CEnum(ctypes.c_uint32) -NE_0_PASS = enum_cp_draw_pred_test.define('NE_0_PASS', 0) -EQ_0_PASS = enum_cp_draw_pred_test.define('EQ_0_PASS', 1) - -enum_cp_cond_function = CEnum(ctypes.c_uint32) -WRITE_ALWAYS = enum_cp_cond_function.define('WRITE_ALWAYS', 0) -WRITE_LT = enum_cp_cond_function.define('WRITE_LT', 1) -WRITE_LE = enum_cp_cond_function.define('WRITE_LE', 2) -WRITE_EQ = enum_cp_cond_function.define('WRITE_EQ', 3) -WRITE_NE = enum_cp_cond_function.define('WRITE_NE', 4) -WRITE_GE = enum_cp_cond_function.define('WRITE_GE', 5) -WRITE_GT = enum_cp_cond_function.define('WRITE_GT', 6) - -enum_poll_memory_type = CEnum(ctypes.c_uint32) -POLL_REGISTER = enum_poll_memory_type.define('POLL_REGISTER', 0) -POLL_MEMORY = enum_poll_memory_type.define('POLL_MEMORY', 1) -POLL_SCRATCH = enum_poll_memory_type.define('POLL_SCRATCH', 2) -POLL_ON_CHIP = enum_poll_memory_type.define('POLL_ON_CHIP', 3) - -enum_render_mode_cmd = CEnum(ctypes.c_uint32) -BYPASS = enum_render_mode_cmd.define('BYPASS', 1) -BINNING = enum_render_mode_cmd.define('BINNING', 2) -GMEM = enum_render_mode_cmd.define('GMEM', 3) -BLIT2D = enum_render_mode_cmd.define('BLIT2D', 5) -BLIT2DSCALE = enum_render_mode_cmd.define('BLIT2DSCALE', 7) -END2D = enum_render_mode_cmd.define('END2D', 8) - -enum_event_write_src = CEnum(ctypes.c_uint32) -EV_WRITE_USER_32B = enum_event_write_src.define('EV_WRITE_USER_32B', 0) -EV_WRITE_USER_64B = enum_event_write_src.define('EV_WRITE_USER_64B', 1) -EV_WRITE_TIMESTAMP_SUM = enum_event_write_src.define('EV_WRITE_TIMESTAMP_SUM', 2) -EV_WRITE_ALWAYSON = enum_event_write_src.define('EV_WRITE_ALWAYSON', 3) -EV_WRITE_REGS_CONTENT = enum_event_write_src.define('EV_WRITE_REGS_CONTENT', 4) - -enum_event_write_dst = CEnum(ctypes.c_uint32) -EV_DST_RAM = enum_event_write_dst.define('EV_DST_RAM', 0) -EV_DST_ONCHIP = enum_event_write_dst.define('EV_DST_ONCHIP', 1) - -enum_cp_blit_cmd = CEnum(ctypes.c_uint32) -BLIT_OP_FILL = enum_cp_blit_cmd.define('BLIT_OP_FILL', 0) -BLIT_OP_COPY = enum_cp_blit_cmd.define('BLIT_OP_COPY', 1) -BLIT_OP_SCALE = enum_cp_blit_cmd.define('BLIT_OP_SCALE', 3) - -enum_a6xx_marker = CEnum(ctypes.c_uint32) -RM6_BYPASS = enum_a6xx_marker.define('RM6_BYPASS', 1) -RM6_BINNING = enum_a6xx_marker.define('RM6_BINNING', 2) -RM6_GMEM = enum_a6xx_marker.define('RM6_GMEM', 4) -RM6_ENDVIS = enum_a6xx_marker.define('RM6_ENDVIS', 5) -RM6_RESOLVE = enum_a6xx_marker.define('RM6_RESOLVE', 6) -RM6_YIELD = enum_a6xx_marker.define('RM6_YIELD', 7) -RM6_COMPUTE = enum_a6xx_marker.define('RM6_COMPUTE', 8) -RM6_BLIT2DSCALE = enum_a6xx_marker.define('RM6_BLIT2DSCALE', 12) -RM6_IB1LIST_START = enum_a6xx_marker.define('RM6_IB1LIST_START', 13) -RM6_IB1LIST_END = enum_a6xx_marker.define('RM6_IB1LIST_END', 14) -RM6_IFPC_ENABLE = enum_a6xx_marker.define('RM6_IFPC_ENABLE', 256) -RM6_IFPC_DISABLE = enum_a6xx_marker.define('RM6_IFPC_DISABLE', 257) - -enum_pseudo_reg = CEnum(ctypes.c_uint32) -SMMU_INFO = enum_pseudo_reg.define('SMMU_INFO', 0) -NON_SECURE_SAVE_ADDR = enum_pseudo_reg.define('NON_SECURE_SAVE_ADDR', 1) -SECURE_SAVE_ADDR = enum_pseudo_reg.define('SECURE_SAVE_ADDR', 2) -NON_PRIV_SAVE_ADDR = enum_pseudo_reg.define('NON_PRIV_SAVE_ADDR', 3) -COUNTER = enum_pseudo_reg.define('COUNTER', 4) -DRAW_STRM_ADDRESS = enum_pseudo_reg.define('DRAW_STRM_ADDRESS', 8) -DRAW_STRM_SIZE_ADDRESS = enum_pseudo_reg.define('DRAW_STRM_SIZE_ADDRESS', 9) -PRIM_STRM_ADDRESS = enum_pseudo_reg.define('PRIM_STRM_ADDRESS', 10) -UNK_STRM_ADDRESS = enum_pseudo_reg.define('UNK_STRM_ADDRESS', 11) -UNK_STRM_SIZE_ADDRESS = enum_pseudo_reg.define('UNK_STRM_SIZE_ADDRESS', 12) -BINDLESS_BASE_0_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_0_ADDR', 16) -BINDLESS_BASE_1_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_1_ADDR', 17) -BINDLESS_BASE_2_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_2_ADDR', 18) -BINDLESS_BASE_3_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_3_ADDR', 19) -BINDLESS_BASE_4_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_4_ADDR', 20) -BINDLESS_BASE_5_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_5_ADDR', 21) -BINDLESS_BASE_6_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_6_ADDR', 22) - -enum_source_type = CEnum(ctypes.c_uint32) -SOURCE_REG = enum_source_type.define('SOURCE_REG', 0) -SOURCE_SCRATCH_MEM = enum_source_type.define('SOURCE_SCRATCH_MEM', 1) - -enum_compare_mode = CEnum(ctypes.c_uint32) -PRED_TEST = enum_compare_mode.define('PRED_TEST', 1) -REG_COMPARE = enum_compare_mode.define('REG_COMPARE', 2) -RENDER_MODE = enum_compare_mode.define('RENDER_MODE', 3) -REG_COMPARE_IMM = enum_compare_mode.define('REG_COMPARE_IMM', 4) -THREAD_MODE = enum_compare_mode.define('THREAD_MODE', 5) - -enum_ctxswitch_ib = CEnum(ctypes.c_uint32) -RESTORE_IB = enum_ctxswitch_ib.define('RESTORE_IB', 0) -YIELD_RESTORE_IB = enum_ctxswitch_ib.define('YIELD_RESTORE_IB', 1) -SAVE_IB = enum_ctxswitch_ib.define('SAVE_IB', 2) -RB_SAVE_IB = enum_ctxswitch_ib.define('RB_SAVE_IB', 3) - -enum_reg_tracker = CEnum(ctypes.c_uint32) -TRACK_CNTL_REG = enum_reg_tracker.define('TRACK_CNTL_REG', 1) -TRACK_RENDER_CNTL = enum_reg_tracker.define('TRACK_RENDER_CNTL', 2) -UNK_EVENT_WRITE = enum_reg_tracker.define('UNK_EVENT_WRITE', 4) -TRACK_LRZ = enum_reg_tracker.define('TRACK_LRZ', 8) - -enum_ts_wait_value_src = CEnum(ctypes.c_uint32) -TS_WAIT_GE_32B = enum_ts_wait_value_src.define('TS_WAIT_GE_32B', 0) -TS_WAIT_GE_64B = enum_ts_wait_value_src.define('TS_WAIT_GE_64B', 1) -TS_WAIT_GE_TIMESTAMP_SUM = enum_ts_wait_value_src.define('TS_WAIT_GE_TIMESTAMP_SUM', 2) - -enum_ts_wait_type = CEnum(ctypes.c_uint32) -TS_WAIT_RAM = enum_ts_wait_type.define('TS_WAIT_RAM', 0) -TS_WAIT_ONCHIP = enum_ts_wait_type.define('TS_WAIT_ONCHIP', 1) - -enum_pipe_count_op = CEnum(ctypes.c_uint32) -PIPE_CLEAR_BV_BR = enum_pipe_count_op.define('PIPE_CLEAR_BV_BR', 1) -PIPE_SET_BR_OFFSET = enum_pipe_count_op.define('PIPE_SET_BR_OFFSET', 2) -PIPE_BR_WAIT_FOR_BV = enum_pipe_count_op.define('PIPE_BR_WAIT_FOR_BV', 3) -PIPE_BV_WAIT_FOR_BR = enum_pipe_count_op.define('PIPE_BV_WAIT_FOR_BR', 4) - -enum_timestamp_op = CEnum(ctypes.c_uint32) -MODIFY_TIMESTAMP_CLEAR = enum_timestamp_op.define('MODIFY_TIMESTAMP_CLEAR', 0) -MODIFY_TIMESTAMP_ADD_GLOBAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_GLOBAL', 1) -MODIFY_TIMESTAMP_ADD_LOCAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_LOCAL', 2) - -enum_cp_thread = CEnum(ctypes.c_uint32) -CP_SET_THREAD_BR = enum_cp_thread.define('CP_SET_THREAD_BR', 1) -CP_SET_THREAD_BV = enum_cp_thread.define('CP_SET_THREAD_BV', 2) -CP_SET_THREAD_BOTH = enum_cp_thread.define('CP_SET_THREAD_BOTH', 3) - -enum_chip = CEnum(ctypes.c_uint32) -A2XX = enum_chip.define('A2XX', 2) -A3XX = enum_chip.define('A3XX', 3) -A4XX = enum_chip.define('A4XX', 4) -A5XX = enum_chip.define('A5XX', 5) -A6XX = enum_chip.define('A6XX', 6) -A7XX = enum_chip.define('A7XX', 7) - -enum_adreno_pa_su_sc_draw = CEnum(ctypes.c_uint32) -PC_DRAW_POINTS = enum_adreno_pa_su_sc_draw.define('PC_DRAW_POINTS', 0) -PC_DRAW_LINES = enum_adreno_pa_su_sc_draw.define('PC_DRAW_LINES', 1) -PC_DRAW_TRIANGLES = enum_adreno_pa_su_sc_draw.define('PC_DRAW_TRIANGLES', 2) - -enum_adreno_compare_func = CEnum(ctypes.c_uint32) -FUNC_NEVER = enum_adreno_compare_func.define('FUNC_NEVER', 0) -FUNC_LESS = enum_adreno_compare_func.define('FUNC_LESS', 1) -FUNC_EQUAL = enum_adreno_compare_func.define('FUNC_EQUAL', 2) -FUNC_LEQUAL = enum_adreno_compare_func.define('FUNC_LEQUAL', 3) -FUNC_GREATER = enum_adreno_compare_func.define('FUNC_GREATER', 4) -FUNC_NOTEQUAL = enum_adreno_compare_func.define('FUNC_NOTEQUAL', 5) -FUNC_GEQUAL = enum_adreno_compare_func.define('FUNC_GEQUAL', 6) -FUNC_ALWAYS = enum_adreno_compare_func.define('FUNC_ALWAYS', 7) - -enum_adreno_stencil_op = CEnum(ctypes.c_uint32) -STENCIL_KEEP = enum_adreno_stencil_op.define('STENCIL_KEEP', 0) -STENCIL_ZERO = enum_adreno_stencil_op.define('STENCIL_ZERO', 1) -STENCIL_REPLACE = enum_adreno_stencil_op.define('STENCIL_REPLACE', 2) -STENCIL_INCR_CLAMP = enum_adreno_stencil_op.define('STENCIL_INCR_CLAMP', 3) -STENCIL_DECR_CLAMP = enum_adreno_stencil_op.define('STENCIL_DECR_CLAMP', 4) -STENCIL_INVERT = enum_adreno_stencil_op.define('STENCIL_INVERT', 5) -STENCIL_INCR_WRAP = enum_adreno_stencil_op.define('STENCIL_INCR_WRAP', 6) -STENCIL_DECR_WRAP = enum_adreno_stencil_op.define('STENCIL_DECR_WRAP', 7) - -enum_adreno_rb_blend_factor = CEnum(ctypes.c_uint32) -FACTOR_ZERO = enum_adreno_rb_blend_factor.define('FACTOR_ZERO', 0) -FACTOR_ONE = enum_adreno_rb_blend_factor.define('FACTOR_ONE', 1) -FACTOR_SRC_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_SRC_COLOR', 4) -FACTOR_ONE_MINUS_SRC_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC_COLOR', 5) -FACTOR_SRC_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_SRC_ALPHA', 6) -FACTOR_ONE_MINUS_SRC_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC_ALPHA', 7) -FACTOR_DST_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_DST_COLOR', 8) -FACTOR_ONE_MINUS_DST_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_DST_COLOR', 9) -FACTOR_DST_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_DST_ALPHA', 10) -FACTOR_ONE_MINUS_DST_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_DST_ALPHA', 11) -FACTOR_CONSTANT_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_CONSTANT_COLOR', 12) -FACTOR_ONE_MINUS_CONSTANT_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_CONSTANT_COLOR', 13) -FACTOR_CONSTANT_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_CONSTANT_ALPHA', 14) -FACTOR_ONE_MINUS_CONSTANT_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_CONSTANT_ALPHA', 15) -FACTOR_SRC_ALPHA_SATURATE = enum_adreno_rb_blend_factor.define('FACTOR_SRC_ALPHA_SATURATE', 16) -FACTOR_SRC1_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_SRC1_COLOR', 20) -FACTOR_ONE_MINUS_SRC1_COLOR = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC1_COLOR', 21) -FACTOR_SRC1_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_SRC1_ALPHA', 22) -FACTOR_ONE_MINUS_SRC1_ALPHA = enum_adreno_rb_blend_factor.define('FACTOR_ONE_MINUS_SRC1_ALPHA', 23) - -enum_adreno_rb_surface_endian = CEnum(ctypes.c_uint32) -ENDIAN_NONE = enum_adreno_rb_surface_endian.define('ENDIAN_NONE', 0) -ENDIAN_8IN16 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN16', 1) -ENDIAN_8IN32 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN32', 2) -ENDIAN_16IN32 = enum_adreno_rb_surface_endian.define('ENDIAN_16IN32', 3) -ENDIAN_8IN64 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN64', 4) -ENDIAN_8IN128 = enum_adreno_rb_surface_endian.define('ENDIAN_8IN128', 5) - -enum_adreno_rb_dither_mode = CEnum(ctypes.c_uint32) -DITHER_DISABLE = enum_adreno_rb_dither_mode.define('DITHER_DISABLE', 0) -DITHER_ALWAYS = enum_adreno_rb_dither_mode.define('DITHER_ALWAYS', 1) -DITHER_IF_ALPHA_OFF = enum_adreno_rb_dither_mode.define('DITHER_IF_ALPHA_OFF', 2) - -enum_adreno_rb_depth_format = CEnum(ctypes.c_uint32) -DEPTHX_16 = enum_adreno_rb_depth_format.define('DEPTHX_16', 0) -DEPTHX_24_8 = enum_adreno_rb_depth_format.define('DEPTHX_24_8', 1) -DEPTHX_32 = enum_adreno_rb_depth_format.define('DEPTHX_32', 2) - -enum_adreno_rb_copy_control_mode = CEnum(ctypes.c_uint32) -RB_COPY_RESOLVE = enum_adreno_rb_copy_control_mode.define('RB_COPY_RESOLVE', 1) -RB_COPY_CLEAR = enum_adreno_rb_copy_control_mode.define('RB_COPY_CLEAR', 2) -RB_COPY_DEPTH_STENCIL = enum_adreno_rb_copy_control_mode.define('RB_COPY_DEPTH_STENCIL', 5) - -enum_a3xx_rop_code = CEnum(ctypes.c_uint32) -ROP_CLEAR = enum_a3xx_rop_code.define('ROP_CLEAR', 0) -ROP_NOR = enum_a3xx_rop_code.define('ROP_NOR', 1) -ROP_AND_INVERTED = enum_a3xx_rop_code.define('ROP_AND_INVERTED', 2) -ROP_COPY_INVERTED = enum_a3xx_rop_code.define('ROP_COPY_INVERTED', 3) -ROP_AND_REVERSE = enum_a3xx_rop_code.define('ROP_AND_REVERSE', 4) -ROP_INVERT = enum_a3xx_rop_code.define('ROP_INVERT', 5) -ROP_XOR = enum_a3xx_rop_code.define('ROP_XOR', 6) -ROP_NAND = enum_a3xx_rop_code.define('ROP_NAND', 7) -ROP_AND = enum_a3xx_rop_code.define('ROP_AND', 8) -ROP_EQUIV = enum_a3xx_rop_code.define('ROP_EQUIV', 9) -ROP_NOOP = enum_a3xx_rop_code.define('ROP_NOOP', 10) -ROP_OR_INVERTED = enum_a3xx_rop_code.define('ROP_OR_INVERTED', 11) -ROP_COPY = enum_a3xx_rop_code.define('ROP_COPY', 12) -ROP_OR_REVERSE = enum_a3xx_rop_code.define('ROP_OR_REVERSE', 13) -ROP_OR = enum_a3xx_rop_code.define('ROP_OR', 14) -ROP_SET = enum_a3xx_rop_code.define('ROP_SET', 15) - -enum_a3xx_render_mode = CEnum(ctypes.c_uint32) -RB_RENDERING_PASS = enum_a3xx_render_mode.define('RB_RENDERING_PASS', 0) -RB_TILING_PASS = enum_a3xx_render_mode.define('RB_TILING_PASS', 1) -RB_RESOLVE_PASS = enum_a3xx_render_mode.define('RB_RESOLVE_PASS', 2) -RB_COMPUTE_PASS = enum_a3xx_render_mode.define('RB_COMPUTE_PASS', 3) - -enum_a3xx_msaa_samples = CEnum(ctypes.c_uint32) -MSAA_ONE = enum_a3xx_msaa_samples.define('MSAA_ONE', 0) -MSAA_TWO = enum_a3xx_msaa_samples.define('MSAA_TWO', 1) -MSAA_FOUR = enum_a3xx_msaa_samples.define('MSAA_FOUR', 2) -MSAA_EIGHT = enum_a3xx_msaa_samples.define('MSAA_EIGHT', 3) - -enum_a3xx_threadmode = CEnum(ctypes.c_uint32) -MULTI = enum_a3xx_threadmode.define('MULTI', 0) -SINGLE = enum_a3xx_threadmode.define('SINGLE', 1) - -enum_a3xx_instrbuffermode = CEnum(ctypes.c_uint32) -CACHE = enum_a3xx_instrbuffermode.define('CACHE', 0) -BUFFER = enum_a3xx_instrbuffermode.define('BUFFER', 1) - -enum_a3xx_threadsize = CEnum(ctypes.c_uint32) -TWO_QUADS = enum_a3xx_threadsize.define('TWO_QUADS', 0) -FOUR_QUADS = enum_a3xx_threadsize.define('FOUR_QUADS', 1) - -enum_a3xx_color_swap = CEnum(ctypes.c_uint32) -WZYX = enum_a3xx_color_swap.define('WZYX', 0) -WXYZ = enum_a3xx_color_swap.define('WXYZ', 1) -ZYXW = enum_a3xx_color_swap.define('ZYXW', 2) -XYZW = enum_a3xx_color_swap.define('XYZW', 3) - -enum_a3xx_rb_blend_opcode = CEnum(ctypes.c_uint32) -BLEND_DST_PLUS_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_DST_PLUS_SRC', 0) -BLEND_SRC_MINUS_DST = enum_a3xx_rb_blend_opcode.define('BLEND_SRC_MINUS_DST', 1) -BLEND_DST_MINUS_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_DST_MINUS_SRC', 2) -BLEND_MIN_DST_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_MIN_DST_SRC', 3) -BLEND_MAX_DST_SRC = enum_a3xx_rb_blend_opcode.define('BLEND_MAX_DST_SRC', 4) - -enum_a4xx_tess_spacing = CEnum(ctypes.c_uint32) -EQUAL_SPACING = enum_a4xx_tess_spacing.define('EQUAL_SPACING', 0) -ODD_SPACING = enum_a4xx_tess_spacing.define('ODD_SPACING', 2) -EVEN_SPACING = enum_a4xx_tess_spacing.define('EVEN_SPACING', 3) - -enum_a5xx_address_mode = CEnum(ctypes.c_uint32) -ADDR_32B = enum_a5xx_address_mode.define('ADDR_32B', 0) -ADDR_64B = enum_a5xx_address_mode.define('ADDR_64B', 1) - -enum_a5xx_line_mode = CEnum(ctypes.c_uint32) -BRESENHAM = enum_a5xx_line_mode.define('BRESENHAM', 0) -RECTANGULAR = enum_a5xx_line_mode.define('RECTANGULAR', 1) - -enum_a6xx_tex_prefetch_cmd = CEnum(ctypes.c_uint32) -TEX_PREFETCH_UNK0 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK0', 0) -TEX_PREFETCH_SAM = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_SAM', 1) -TEX_PREFETCH_GATHER4R = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4R', 2) -TEX_PREFETCH_GATHER4G = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4G', 3) -TEX_PREFETCH_GATHER4B = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4B', 4) -TEX_PREFETCH_GATHER4A = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_GATHER4A', 5) -TEX_PREFETCH_UNK6 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK6', 6) -TEX_PREFETCH_UNK7 = enum_a6xx_tex_prefetch_cmd.define('TEX_PREFETCH_UNK7', 7) - -enum_a6xx_tile_mode = CEnum(ctypes.c_uint32) -TILE6_LINEAR = enum_a6xx_tile_mode.define('TILE6_LINEAR', 0) -TILE6_2 = enum_a6xx_tile_mode.define('TILE6_2', 2) -TILE6_3 = enum_a6xx_tile_mode.define('TILE6_3', 3) - -enum_a6xx_format = CEnum(ctypes.c_uint32) -FMT6_A8_UNORM = enum_a6xx_format.define('FMT6_A8_UNORM', 2) -FMT6_8_UNORM = enum_a6xx_format.define('FMT6_8_UNORM', 3) -FMT6_8_SNORM = enum_a6xx_format.define('FMT6_8_SNORM', 4) -FMT6_8_UINT = enum_a6xx_format.define('FMT6_8_UINT', 5) -FMT6_8_SINT = enum_a6xx_format.define('FMT6_8_SINT', 6) -FMT6_4_4_4_4_UNORM = enum_a6xx_format.define('FMT6_4_4_4_4_UNORM', 8) -FMT6_5_5_5_1_UNORM = enum_a6xx_format.define('FMT6_5_5_5_1_UNORM', 10) -FMT6_1_5_5_5_UNORM = enum_a6xx_format.define('FMT6_1_5_5_5_UNORM', 12) -FMT6_5_6_5_UNORM = enum_a6xx_format.define('FMT6_5_6_5_UNORM', 14) -FMT6_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_UNORM', 15) -FMT6_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_SNORM', 16) -FMT6_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_UINT', 17) -FMT6_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_SINT', 18) -FMT6_L8_A8_UNORM = enum_a6xx_format.define('FMT6_L8_A8_UNORM', 19) -FMT6_16_UNORM = enum_a6xx_format.define('FMT6_16_UNORM', 21) -FMT6_16_SNORM = enum_a6xx_format.define('FMT6_16_SNORM', 22) -FMT6_16_FLOAT = enum_a6xx_format.define('FMT6_16_FLOAT', 23) -FMT6_16_UINT = enum_a6xx_format.define('FMT6_16_UINT', 24) -FMT6_16_SINT = enum_a6xx_format.define('FMT6_16_SINT', 25) -FMT6_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_UNORM', 33) -FMT6_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_SNORM', 34) -FMT6_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_UINT', 35) -FMT6_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_SINT', 36) -FMT6_8_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_8_UNORM', 48) -FMT6_8_8_8_X8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_X8_UNORM', 49) -FMT6_8_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_8_SNORM', 50) -FMT6_8_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_8_UINT', 51) -FMT6_8_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_8_SINT', 52) -FMT6_9_9_9_E5_FLOAT = enum_a6xx_format.define('FMT6_9_9_9_E5_FLOAT', 53) -FMT6_10_10_10_2_UNORM = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM', 54) -FMT6_10_10_10_2_UNORM_DEST = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM_DEST', 55) -FMT6_10_10_10_2_SNORM = enum_a6xx_format.define('FMT6_10_10_10_2_SNORM', 57) -FMT6_10_10_10_2_UINT = enum_a6xx_format.define('FMT6_10_10_10_2_UINT', 58) -FMT6_10_10_10_2_SINT = enum_a6xx_format.define('FMT6_10_10_10_2_SINT', 59) -FMT6_11_11_10_FLOAT = enum_a6xx_format.define('FMT6_11_11_10_FLOAT', 66) -FMT6_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_UNORM', 67) -FMT6_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_SNORM', 68) -FMT6_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_FLOAT', 69) -FMT6_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_UINT', 70) -FMT6_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_SINT', 71) -FMT6_32_UNORM = enum_a6xx_format.define('FMT6_32_UNORM', 72) -FMT6_32_SNORM = enum_a6xx_format.define('FMT6_32_SNORM', 73) -FMT6_32_FLOAT = enum_a6xx_format.define('FMT6_32_FLOAT', 74) -FMT6_32_UINT = enum_a6xx_format.define('FMT6_32_UINT', 75) -FMT6_32_SINT = enum_a6xx_format.define('FMT6_32_SINT', 76) -FMT6_32_FIXED = enum_a6xx_format.define('FMT6_32_FIXED', 77) -FMT6_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_UNORM', 88) -FMT6_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_SNORM', 89) -FMT6_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_FLOAT', 90) -FMT6_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_UINT', 91) -FMT6_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_SINT', 92) -FMT6_16_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_16_UNORM', 96) -FMT6_16_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_16_SNORM', 97) -FMT6_16_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_16_FLOAT', 98) -FMT6_16_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_16_UINT', 99) -FMT6_16_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_16_SINT', 100) -FMT6_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_UNORM', 101) -FMT6_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_SNORM', 102) -FMT6_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_FLOAT', 103) -FMT6_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_UINT', 104) -FMT6_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_SINT', 105) -FMT6_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_FIXED', 106) -FMT6_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_UNORM', 112) -FMT6_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_SNORM', 113) -FMT6_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_UINT', 114) -FMT6_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_SINT', 115) -FMT6_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_FLOAT', 116) -FMT6_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_FIXED', 117) -FMT6_32_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_32_UNORM', 128) -FMT6_32_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_32_SNORM', 129) -FMT6_32_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_32_FLOAT', 130) -FMT6_32_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_32_UINT', 131) -FMT6_32_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_32_SINT', 132) -FMT6_32_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_32_FIXED', 133) -FMT6_G8R8B8R8_422_UNORM = enum_a6xx_format.define('FMT6_G8R8B8R8_422_UNORM', 140) -FMT6_R8G8R8B8_422_UNORM = enum_a6xx_format.define('FMT6_R8G8R8B8_422_UNORM', 141) -FMT6_R8_G8B8_2PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8B8_2PLANE_420_UNORM', 142) -FMT6_NV21 = enum_a6xx_format.define('FMT6_NV21', 143) -FMT6_R8_G8_B8_3PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8_B8_3PLANE_420_UNORM', 144) -FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 145) -FMT6_NV12_Y = enum_a6xx_format.define('FMT6_NV12_Y', 148) -FMT6_NV12_UV = enum_a6xx_format.define('FMT6_NV12_UV', 149) -FMT6_NV12_VU = enum_a6xx_format.define('FMT6_NV12_VU', 150) -FMT6_NV12_4R = enum_a6xx_format.define('FMT6_NV12_4R', 151) -FMT6_NV12_4R_Y = enum_a6xx_format.define('FMT6_NV12_4R_Y', 152) -FMT6_NV12_4R_UV = enum_a6xx_format.define('FMT6_NV12_4R_UV', 153) -FMT6_P010 = enum_a6xx_format.define('FMT6_P010', 154) -FMT6_P010_Y = enum_a6xx_format.define('FMT6_P010_Y', 155) -FMT6_P010_UV = enum_a6xx_format.define('FMT6_P010_UV', 156) -FMT6_TP10 = enum_a6xx_format.define('FMT6_TP10', 157) -FMT6_TP10_Y = enum_a6xx_format.define('FMT6_TP10_Y', 158) -FMT6_TP10_UV = enum_a6xx_format.define('FMT6_TP10_UV', 159) -FMT6_Z24_UNORM_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT', 160) -FMT6_ETC2_RG11_UNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_UNORM', 171) -FMT6_ETC2_RG11_SNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_SNORM', 172) -FMT6_ETC2_R11_UNORM = enum_a6xx_format.define('FMT6_ETC2_R11_UNORM', 173) -FMT6_ETC2_R11_SNORM = enum_a6xx_format.define('FMT6_ETC2_R11_SNORM', 174) -FMT6_ETC1 = enum_a6xx_format.define('FMT6_ETC1', 175) -FMT6_ETC2_RGB8 = enum_a6xx_format.define('FMT6_ETC2_RGB8', 176) -FMT6_ETC2_RGBA8 = enum_a6xx_format.define('FMT6_ETC2_RGBA8', 177) -FMT6_ETC2_RGB8A1 = enum_a6xx_format.define('FMT6_ETC2_RGB8A1', 178) -FMT6_DXT1 = enum_a6xx_format.define('FMT6_DXT1', 179) -FMT6_DXT3 = enum_a6xx_format.define('FMT6_DXT3', 180) -FMT6_DXT5 = enum_a6xx_format.define('FMT6_DXT5', 181) -FMT6_RGTC1_UNORM = enum_a6xx_format.define('FMT6_RGTC1_UNORM', 183) -FMT6_RGTC1_SNORM = enum_a6xx_format.define('FMT6_RGTC1_SNORM', 184) -FMT6_RGTC2_UNORM = enum_a6xx_format.define('FMT6_RGTC2_UNORM', 187) -FMT6_RGTC2_SNORM = enum_a6xx_format.define('FMT6_RGTC2_SNORM', 188) -FMT6_BPTC_UFLOAT = enum_a6xx_format.define('FMT6_BPTC_UFLOAT', 190) -FMT6_BPTC_FLOAT = enum_a6xx_format.define('FMT6_BPTC_FLOAT', 191) -FMT6_BPTC = enum_a6xx_format.define('FMT6_BPTC', 192) -FMT6_ASTC_4x4 = enum_a6xx_format.define('FMT6_ASTC_4x4', 193) -FMT6_ASTC_5x4 = enum_a6xx_format.define('FMT6_ASTC_5x4', 194) -FMT6_ASTC_5x5 = enum_a6xx_format.define('FMT6_ASTC_5x5', 195) -FMT6_ASTC_6x5 = enum_a6xx_format.define('FMT6_ASTC_6x5', 196) -FMT6_ASTC_6x6 = enum_a6xx_format.define('FMT6_ASTC_6x6', 197) -FMT6_ASTC_8x5 = enum_a6xx_format.define('FMT6_ASTC_8x5', 198) -FMT6_ASTC_8x6 = enum_a6xx_format.define('FMT6_ASTC_8x6', 199) -FMT6_ASTC_8x8 = enum_a6xx_format.define('FMT6_ASTC_8x8', 200) -FMT6_ASTC_10x5 = enum_a6xx_format.define('FMT6_ASTC_10x5', 201) -FMT6_ASTC_10x6 = enum_a6xx_format.define('FMT6_ASTC_10x6', 202) -FMT6_ASTC_10x8 = enum_a6xx_format.define('FMT6_ASTC_10x8', 203) -FMT6_ASTC_10x10 = enum_a6xx_format.define('FMT6_ASTC_10x10', 204) -FMT6_ASTC_12x10 = enum_a6xx_format.define('FMT6_ASTC_12x10', 205) -FMT6_ASTC_12x12 = enum_a6xx_format.define('FMT6_ASTC_12x12', 206) -FMT6_Z24_UINT_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UINT_S8_UINT', 234) -FMT6_NONE = enum_a6xx_format.define('FMT6_NONE', 255) - -enum_a6xx_polygon_mode = CEnum(ctypes.c_uint32) -POLYMODE6_POINTS = enum_a6xx_polygon_mode.define('POLYMODE6_POINTS', 1) -POLYMODE6_LINES = enum_a6xx_polygon_mode.define('POLYMODE6_LINES', 2) -POLYMODE6_TRIANGLES = enum_a6xx_polygon_mode.define('POLYMODE6_TRIANGLES', 3) - -enum_a6xx_depth_format = CEnum(ctypes.c_uint32) -DEPTH6_NONE = enum_a6xx_depth_format.define('DEPTH6_NONE', 0) -DEPTH6_16 = enum_a6xx_depth_format.define('DEPTH6_16', 1) -DEPTH6_24_8 = enum_a6xx_depth_format.define('DEPTH6_24_8', 2) -DEPTH6_32 = enum_a6xx_depth_format.define('DEPTH6_32', 4) - -enum_a6xx_shader_id = CEnum(ctypes.c_uint32) -A6XX_TP0_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_TMO_DATA', 9) -A6XX_TP0_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_SMO_DATA', 10) -A6XX_TP0_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP0_MIPMAP_BASE_DATA', 11) -A6XX_TP1_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_TMO_DATA', 25) -A6XX_TP1_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_SMO_DATA', 26) -A6XX_TP1_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP1_MIPMAP_BASE_DATA', 27) -A6XX_SP_INST_DATA = enum_a6xx_shader_id.define('A6XX_SP_INST_DATA', 41) -A6XX_SP_LB_0_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_0_DATA', 42) -A6XX_SP_LB_1_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_1_DATA', 43) -A6XX_SP_LB_2_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_2_DATA', 44) -A6XX_SP_LB_3_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_3_DATA', 45) -A6XX_SP_LB_4_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_4_DATA', 46) -A6XX_SP_LB_5_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_5_DATA', 47) -A6XX_SP_CB_BINDLESS_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_DATA', 48) -A6XX_SP_CB_LEGACY_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_LEGACY_DATA', 49) -A6XX_SP_UAV_DATA = enum_a6xx_shader_id.define('A6XX_SP_UAV_DATA', 50) -A6XX_SP_INST_TAG = enum_a6xx_shader_id.define('A6XX_SP_INST_TAG', 51) -A6XX_SP_CB_BINDLESS_TAG = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_TAG', 52) -A6XX_SP_TMO_UMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_TMO_UMO_TAG', 53) -A6XX_SP_SMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_SMO_TAG', 54) -A6XX_SP_STATE_DATA = enum_a6xx_shader_id.define('A6XX_SP_STATE_DATA', 55) -A6XX_HLSQ_CHUNK_CVS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM', 73) -A6XX_HLSQ_CHUNK_CPS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM', 74) -A6XX_HLSQ_CHUNK_CVS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM_TAG', 75) -A6XX_HLSQ_CHUNK_CPS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM_TAG', 76) -A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', 77) -A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 78) -A6XX_HLSQ_CVS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM', 80) -A6XX_HLSQ_CPS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM', 81) -A6XX_HLSQ_INST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM', 82) -A6XX_HLSQ_GFX_CVS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM', 83) -A6XX_HLSQ_GFX_CPS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM', 84) -A6XX_HLSQ_CVS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM_TAG', 85) -A6XX_HLSQ_CPS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM_TAG', 86) -A6XX_HLSQ_INST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_TAG', 87) -A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', 88) -A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', 89) -A6XX_HLSQ_PWR_REST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_RAM', 90) -A6XX_HLSQ_PWR_REST_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_TAG', 91) -A6XX_HLSQ_DATAPATH_META = enum_a6xx_shader_id.define('A6XX_HLSQ_DATAPATH_META', 96) -A6XX_HLSQ_FRONTEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_FRONTEND_META', 97) -A6XX_HLSQ_INDIRECT_META = enum_a6xx_shader_id.define('A6XX_HLSQ_INDIRECT_META', 98) -A6XX_HLSQ_BACKEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_BACKEND_META', 99) -A6XX_SP_LB_6_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_6_DATA', 112) -A6XX_SP_LB_7_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_7_DATA', 113) -A6XX_HLSQ_INST_RAM_1 = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_1', 115) - -enum_a7xx_statetype_id = CEnum(ctypes.c_uint32) -A7XX_TP0_NCTX_REG = enum_a7xx_statetype_id.define('A7XX_TP0_NCTX_REG', 0) -A7XX_TP0_CTX0_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX0_3D_CVS_REG', 1) -A7XX_TP0_CTX0_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX0_3D_CPS_REG', 2) -A7XX_TP0_CTX1_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX1_3D_CVS_REG', 3) -A7XX_TP0_CTX1_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX1_3D_CPS_REG', 4) -A7XX_TP0_CTX2_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX2_3D_CPS_REG', 5) -A7XX_TP0_CTX3_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_TP0_CTX3_3D_CPS_REG', 6) -A7XX_TP0_TMO_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_TMO_DATA', 9) -A7XX_TP0_SMO_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_SMO_DATA', 10) -A7XX_TP0_MIPMAP_BASE_DATA = enum_a7xx_statetype_id.define('A7XX_TP0_MIPMAP_BASE_DATA', 11) -A7XX_SP_NCTX_REG = enum_a7xx_statetype_id.define('A7XX_SP_NCTX_REG', 32) -A7XX_SP_CTX0_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX0_3D_CVS_REG', 33) -A7XX_SP_CTX0_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX0_3D_CPS_REG', 34) -A7XX_SP_CTX1_3D_CVS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX1_3D_CVS_REG', 35) -A7XX_SP_CTX1_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX1_3D_CPS_REG', 36) -A7XX_SP_CTX2_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX2_3D_CPS_REG', 37) -A7XX_SP_CTX3_3D_CPS_REG = enum_a7xx_statetype_id.define('A7XX_SP_CTX3_3D_CPS_REG', 38) -A7XX_SP_INST_DATA = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA', 39) -A7XX_SP_INST_DATA_1 = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA_1', 40) -A7XX_SP_LB_0_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_0_DATA', 41) -A7XX_SP_LB_1_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_1_DATA', 42) -A7XX_SP_LB_2_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_2_DATA', 43) -A7XX_SP_LB_3_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_3_DATA', 44) -A7XX_SP_LB_4_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_4_DATA', 45) -A7XX_SP_LB_5_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_5_DATA', 46) -A7XX_SP_LB_6_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_6_DATA', 47) -A7XX_SP_LB_7_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_7_DATA', 48) -A7XX_SP_CB_RAM = enum_a7xx_statetype_id.define('A7XX_SP_CB_RAM', 49) -A7XX_SP_LB_13_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_13_DATA', 50) -A7XX_SP_LB_14_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_14_DATA', 51) -A7XX_SP_INST_TAG = enum_a7xx_statetype_id.define('A7XX_SP_INST_TAG', 52) -A7XX_SP_INST_DATA_2 = enum_a7xx_statetype_id.define('A7XX_SP_INST_DATA_2', 53) -A7XX_SP_TMO_TAG = enum_a7xx_statetype_id.define('A7XX_SP_TMO_TAG', 54) -A7XX_SP_SMO_TAG = enum_a7xx_statetype_id.define('A7XX_SP_SMO_TAG', 55) -A7XX_SP_STATE_DATA = enum_a7xx_statetype_id.define('A7XX_SP_STATE_DATA', 56) -A7XX_SP_HWAVE_RAM = enum_a7xx_statetype_id.define('A7XX_SP_HWAVE_RAM', 57) -A7XX_SP_L0_INST_BUF = enum_a7xx_statetype_id.define('A7XX_SP_L0_INST_BUF', 58) -A7XX_SP_LB_8_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_8_DATA', 59) -A7XX_SP_LB_9_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_9_DATA', 60) -A7XX_SP_LB_10_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_10_DATA', 61) -A7XX_SP_LB_11_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_11_DATA', 62) -A7XX_SP_LB_12_DATA = enum_a7xx_statetype_id.define('A7XX_SP_LB_12_DATA', 63) -A7XX_HLSQ_DATAPATH_DSTR_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_DATAPATH_DSTR_META', 64) -A7XX_HLSQ_L2STC_TAG_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_L2STC_TAG_RAM', 67) -A7XX_HLSQ_L2STC_INFO_CMD = enum_a7xx_statetype_id.define('A7XX_HLSQ_L2STC_INFO_CMD', 68) -A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', 69) -A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', 70) -A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM', 71) -A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM', 72) -A7XX_HLSQ_CHUNK_CVS_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CVS_RAM', 73) -A7XX_HLSQ_CHUNK_CPS_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CPS_RAM', 74) -A7XX_HLSQ_CHUNK_CVS_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CVS_RAM_TAG', 75) -A7XX_HLSQ_CHUNK_CPS_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CHUNK_CPS_RAM_TAG', 76) -A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_ICB_CVS_CB_BASE_TAG', 77) -A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', 78) -A7XX_HLSQ_CVS_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_MISC_RAM', 79) -A7XX_HLSQ_CPS_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM', 80) -A7XX_HLSQ_CPS_MISC_RAM_1 = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM_1', 81) -A7XX_HLSQ_INST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM', 82) -A7XX_HLSQ_GFX_CVS_CONST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_CONST_RAM', 83) -A7XX_HLSQ_GFX_CPS_CONST_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_CONST_RAM', 84) -A7XX_HLSQ_CVS_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CVS_MISC_RAM_TAG', 85) -A7XX_HLSQ_CPS_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_CPS_MISC_RAM_TAG', 86) -A7XX_HLSQ_INST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_TAG', 87) -A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG', 88) -A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG', 89) -A7XX_HLSQ_GFX_LOCAL_MISC_RAM = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_LOCAL_MISC_RAM', 90) -A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = enum_a7xx_statetype_id.define('A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG', 91) -A7XX_HLSQ_INST_RAM_1 = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_1', 92) -A7XX_HLSQ_STPROC_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_STPROC_META', 93) -A7XX_HLSQ_BV_BE_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_BV_BE_META', 94) -A7XX_HLSQ_INST_RAM_2 = enum_a7xx_statetype_id.define('A7XX_HLSQ_INST_RAM_2', 95) -A7XX_HLSQ_DATAPATH_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_DATAPATH_META', 96) -A7XX_HLSQ_FRONTEND_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_FRONTEND_META', 97) -A7XX_HLSQ_INDIRECT_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_INDIRECT_META', 98) -A7XX_HLSQ_BACKEND_META = enum_a7xx_statetype_id.define('A7XX_HLSQ_BACKEND_META', 99) - -enum_a6xx_debugbus_id = CEnum(ctypes.c_uint32) -A6XX_DBGBUS_CP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CP', 1) -A6XX_DBGBUS_RBBM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBBM', 2) -A6XX_DBGBUS_VBIF = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VBIF', 3) -A6XX_DBGBUS_HLSQ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ', 4) -A6XX_DBGBUS_UCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE', 5) -A6XX_DBGBUS_DPM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DPM', 6) -A6XX_DBGBUS_TESS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TESS', 7) -A6XX_DBGBUS_PC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_PC', 8) -A6XX_DBGBUS_VFDP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFDP', 9) -A6XX_DBGBUS_VPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VPC', 10) -A6XX_DBGBUS_TSE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TSE', 11) -A6XX_DBGBUS_RAS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RAS', 12) -A6XX_DBGBUS_VSC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VSC', 13) -A6XX_DBGBUS_COM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_COM', 14) -A6XX_DBGBUS_LRZ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LRZ', 16) -A6XX_DBGBUS_A2D = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_A2D', 17) -A6XX_DBGBUS_CCUFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCUFCHE', 18) -A6XX_DBGBUS_GMU_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_CX', 19) -A6XX_DBGBUS_RBP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBP', 20) -A6XX_DBGBUS_DCS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DCS', 21) -A6XX_DBGBUS_DBGC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DBGC', 22) -A6XX_DBGBUS_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CX', 23) -A6XX_DBGBUS_GMU_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_GX', 24) -A6XX_DBGBUS_TPFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPFCHE', 25) -A6XX_DBGBUS_GBIF_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GBIF_GX', 26) -A6XX_DBGBUS_GPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GPC', 29) -A6XX_DBGBUS_LARC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LARC', 30) -A6XX_DBGBUS_HLSQ_SPTP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ_SPTP', 31) -A6XX_DBGBUS_RB_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_0', 32) -A6XX_DBGBUS_RB_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_1', 33) -A6XX_DBGBUS_RB_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_2', 34) -A6XX_DBGBUS_UCHE_WRAPPER = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE_WRAPPER', 36) -A6XX_DBGBUS_CCU_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_0', 40) -A6XX_DBGBUS_CCU_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_1', 41) -A6XX_DBGBUS_CCU_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_2', 42) -A6XX_DBGBUS_VFD_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_0', 56) -A6XX_DBGBUS_VFD_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_1', 57) -A6XX_DBGBUS_VFD_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_2', 58) -A6XX_DBGBUS_VFD_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_3', 59) -A6XX_DBGBUS_VFD_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_4', 60) -A6XX_DBGBUS_VFD_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_5', 61) -A6XX_DBGBUS_SP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_0', 64) -A6XX_DBGBUS_SP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_1', 65) -A6XX_DBGBUS_SP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_2', 66) -A6XX_DBGBUS_TPL1_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_0', 72) -A6XX_DBGBUS_TPL1_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_1', 73) -A6XX_DBGBUS_TPL1_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_2', 74) -A6XX_DBGBUS_TPL1_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_3', 75) -A6XX_DBGBUS_TPL1_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_4', 76) -A6XX_DBGBUS_TPL1_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_5', 77) -A6XX_DBGBUS_SPTP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_0', 88) -A6XX_DBGBUS_SPTP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_1', 89) -A6XX_DBGBUS_SPTP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_2', 90) -A6XX_DBGBUS_SPTP_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_3', 91) -A6XX_DBGBUS_SPTP_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_4', 92) -A6XX_DBGBUS_SPTP_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_5', 93) - -enum_a7xx_state_location = CEnum(ctypes.c_uint32) -A7XX_HLSQ_STATE = enum_a7xx_state_location.define('A7XX_HLSQ_STATE', 0) -A7XX_HLSQ_DP = enum_a7xx_state_location.define('A7XX_HLSQ_DP', 1) -A7XX_SP_TOP = enum_a7xx_state_location.define('A7XX_SP_TOP', 2) -A7XX_USPTP = enum_a7xx_state_location.define('A7XX_USPTP', 3) -A7XX_HLSQ_DP_STR = enum_a7xx_state_location.define('A7XX_HLSQ_DP_STR', 4) - -enum_a7xx_pipe = CEnum(ctypes.c_uint32) -A7XX_PIPE_NONE = enum_a7xx_pipe.define('A7XX_PIPE_NONE', 0) -A7XX_PIPE_BR = enum_a7xx_pipe.define('A7XX_PIPE_BR', 1) -A7XX_PIPE_BV = enum_a7xx_pipe.define('A7XX_PIPE_BV', 2) -A7XX_PIPE_LPAC = enum_a7xx_pipe.define('A7XX_PIPE_LPAC', 3) - -enum_a7xx_cluster = CEnum(ctypes.c_uint32) -A7XX_CLUSTER_NONE = enum_a7xx_cluster.define('A7XX_CLUSTER_NONE', 0) -A7XX_CLUSTER_FE = enum_a7xx_cluster.define('A7XX_CLUSTER_FE', 1) -A7XX_CLUSTER_SP_VS = enum_a7xx_cluster.define('A7XX_CLUSTER_SP_VS', 2) -A7XX_CLUSTER_PC_VS = enum_a7xx_cluster.define('A7XX_CLUSTER_PC_VS', 3) -A7XX_CLUSTER_GRAS = enum_a7xx_cluster.define('A7XX_CLUSTER_GRAS', 4) -A7XX_CLUSTER_SP_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_SP_PS', 5) -A7XX_CLUSTER_VPC_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_VPC_PS', 6) -A7XX_CLUSTER_PS = enum_a7xx_cluster.define('A7XX_CLUSTER_PS', 7) - -enum_a7xx_debugbus_id = CEnum(ctypes.c_uint32) -A7XX_DBGBUS_CP_0_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CP_0_0', 1) -A7XX_DBGBUS_CP_0_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CP_0_1', 2) -A7XX_DBGBUS_RBBM = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RBBM', 3) -A7XX_DBGBUS_GBIF_GX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GBIF_GX', 5) -A7XX_DBGBUS_GBIF_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GBIF_CX', 6) -A7XX_DBGBUS_HLSQ = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ', 7) -A7XX_DBGBUS_UCHE_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_0', 9) -A7XX_DBGBUS_UCHE_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_1', 10) -A7XX_DBGBUS_TESS_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TESS_BR', 13) -A7XX_DBGBUS_TESS_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TESS_BV', 14) -A7XX_DBGBUS_PC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_PC_BR', 17) -A7XX_DBGBUS_PC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_PC_BV', 18) -A7XX_DBGBUS_VFDP_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFDP_BR', 21) -A7XX_DBGBUS_VFDP_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFDP_BV', 22) -A7XX_DBGBUS_VPC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_BR', 25) -A7XX_DBGBUS_VPC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_BV', 26) -A7XX_DBGBUS_TSE_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TSE_BR', 29) -A7XX_DBGBUS_TSE_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TSE_BV', 30) -A7XX_DBGBUS_RAS_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RAS_BR', 33) -A7XX_DBGBUS_RAS_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RAS_BV', 34) -A7XX_DBGBUS_VSC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VSC', 37) -A7XX_DBGBUS_COM_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_COM_0', 39) -A7XX_DBGBUS_LRZ_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LRZ_BR', 43) -A7XX_DBGBUS_LRZ_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LRZ_BV', 44) -A7XX_DBGBUS_UFC_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_0', 47) -A7XX_DBGBUS_UFC_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_1', 48) -A7XX_DBGBUS_GMU_GX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GMU_GX', 55) -A7XX_DBGBUS_DBGC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_DBGC', 59) -A7XX_DBGBUS_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CX', 60) -A7XX_DBGBUS_GMU_CX = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GMU_CX', 61) -A7XX_DBGBUS_GPC_BR = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GPC_BR', 62) -A7XX_DBGBUS_GPC_BV = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_GPC_BV', 63) -A7XX_DBGBUS_LARC = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_LARC', 66) -A7XX_DBGBUS_HLSQ_SPTP = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_SPTP', 68) -A7XX_DBGBUS_RB_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_0', 70) -A7XX_DBGBUS_RB_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_1', 71) -A7XX_DBGBUS_RB_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_2', 72) -A7XX_DBGBUS_RB_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_3', 73) -A7XX_DBGBUS_RB_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_4', 74) -A7XX_DBGBUS_RB_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_RB_5', 75) -A7XX_DBGBUS_UCHE_WRAPPER = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UCHE_WRAPPER', 102) -A7XX_DBGBUS_CCU_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_0', 106) -A7XX_DBGBUS_CCU_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_1', 107) -A7XX_DBGBUS_CCU_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_2', 108) -A7XX_DBGBUS_CCU_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_3', 109) -A7XX_DBGBUS_CCU_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_4', 110) -A7XX_DBGBUS_CCU_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCU_5', 111) -A7XX_DBGBUS_VFD_BR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_0', 138) -A7XX_DBGBUS_VFD_BR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_1', 139) -A7XX_DBGBUS_VFD_BR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_2', 140) -A7XX_DBGBUS_VFD_BR_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_3', 141) -A7XX_DBGBUS_VFD_BR_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_4', 142) -A7XX_DBGBUS_VFD_BR_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_5', 143) -A7XX_DBGBUS_VFD_BR_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_6', 144) -A7XX_DBGBUS_VFD_BR_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BR_7', 145) -A7XX_DBGBUS_VFD_BV_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_0', 202) -A7XX_DBGBUS_VFD_BV_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_1', 203) -A7XX_DBGBUS_VFD_BV_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_2', 204) -A7XX_DBGBUS_VFD_BV_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VFD_BV_3', 205) -A7XX_DBGBUS_USP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_0', 234) -A7XX_DBGBUS_USP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_1', 235) -A7XX_DBGBUS_USP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_2', 236) -A7XX_DBGBUS_USP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_3', 237) -A7XX_DBGBUS_USP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_4', 238) -A7XX_DBGBUS_USP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USP_5', 239) -A7XX_DBGBUS_TP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_0', 266) -A7XX_DBGBUS_TP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_1', 267) -A7XX_DBGBUS_TP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_2', 268) -A7XX_DBGBUS_TP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_3', 269) -A7XX_DBGBUS_TP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_4', 270) -A7XX_DBGBUS_TP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_5', 271) -A7XX_DBGBUS_TP_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_6', 272) -A7XX_DBGBUS_TP_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_7', 273) -A7XX_DBGBUS_TP_8 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_8', 274) -A7XX_DBGBUS_TP_9 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_9', 275) -A7XX_DBGBUS_TP_10 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_10', 276) -A7XX_DBGBUS_TP_11 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_TP_11', 277) -A7XX_DBGBUS_USPTP_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_0', 330) -A7XX_DBGBUS_USPTP_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_1', 331) -A7XX_DBGBUS_USPTP_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_2', 332) -A7XX_DBGBUS_USPTP_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_3', 333) -A7XX_DBGBUS_USPTP_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_4', 334) -A7XX_DBGBUS_USPTP_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_5', 335) -A7XX_DBGBUS_USPTP_6 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_6', 336) -A7XX_DBGBUS_USPTP_7 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_7', 337) -A7XX_DBGBUS_USPTP_8 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_8', 338) -A7XX_DBGBUS_USPTP_9 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_9', 339) -A7XX_DBGBUS_USPTP_10 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_10', 340) -A7XX_DBGBUS_USPTP_11 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_USPTP_11', 341) -A7XX_DBGBUS_CCHE_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_0', 396) -A7XX_DBGBUS_CCHE_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_1', 397) -A7XX_DBGBUS_CCHE_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CCHE_2', 398) -A7XX_DBGBUS_VPC_DSTR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_0', 408) -A7XX_DBGBUS_VPC_DSTR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_1', 409) -A7XX_DBGBUS_VPC_DSTR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_VPC_DSTR_2', 410) -A7XX_DBGBUS_HLSQ_DP_STR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_0', 411) -A7XX_DBGBUS_HLSQ_DP_STR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_1', 412) -A7XX_DBGBUS_HLSQ_DP_STR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_2', 413) -A7XX_DBGBUS_HLSQ_DP_STR_3 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_3', 414) -A7XX_DBGBUS_HLSQ_DP_STR_4 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_4', 415) -A7XX_DBGBUS_HLSQ_DP_STR_5 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_HLSQ_DP_STR_5', 416) -A7XX_DBGBUS_UFC_DSTR_0 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_0', 443) -A7XX_DBGBUS_UFC_DSTR_1 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_1', 444) -A7XX_DBGBUS_UFC_DSTR_2 = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_UFC_DSTR_2', 445) -A7XX_DBGBUS_CGC_SUBCORE = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CGC_SUBCORE', 446) -A7XX_DBGBUS_CGC_CORE = enum_a7xx_debugbus_id.define('A7XX_DBGBUS_CGC_CORE', 447) - -enum_a6xx_cp_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_CP_ALWAYS_COUNT = enum_a6xx_cp_perfcounter_select.define('PERF_CP_ALWAYS_COUNT', 0) -PERF_CP_BUSY_GFX_CORE_IDLE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_BUSY_GFX_CORE_IDLE', 1) -PERF_CP_BUSY_CYCLES = enum_a6xx_cp_perfcounter_select.define('PERF_CP_BUSY_CYCLES', 2) -PERF_CP_NUM_PREEMPTIONS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_NUM_PREEMPTIONS', 3) -PERF_CP_PREEMPTION_REACTION_DELAY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_REACTION_DELAY', 4) -PERF_CP_PREEMPTION_SWITCH_OUT_TIME = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_SWITCH_OUT_TIME', 5) -PERF_CP_PREEMPTION_SWITCH_IN_TIME = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREEMPTION_SWITCH_IN_TIME', 6) -PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 7) -PERF_CP_PREDICATED_DRAWS_KILLED = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PREDICATED_DRAWS_KILLED', 8) -PERF_CP_MODE_SWITCH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MODE_SWITCH', 9) -PERF_CP_ZPASS_DONE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_ZPASS_DONE', 10) -PERF_CP_CONTEXT_DONE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CONTEXT_DONE', 11) -PERF_CP_CACHE_FLUSH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CACHE_FLUSH', 12) -PERF_CP_LONG_PREEMPTIONS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_LONG_PREEMPTIONS', 13) -PERF_CP_SQE_I_CACHE_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_I_CACHE_STARVE', 14) -PERF_CP_SQE_IDLE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_IDLE', 15) -PERF_CP_SQE_PM4_STARVE_RB_IB = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_STARVE_RB_IB', 16) -PERF_CP_SQE_PM4_STARVE_SDS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_STARVE_SDS', 17) -PERF_CP_SQE_MRB_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_MRB_STARVE', 18) -PERF_CP_SQE_RRB_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_RRB_STARVE', 19) -PERF_CP_SQE_VSD_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_VSD_STARVE', 20) -PERF_CP_VSD_DECODE_STARVE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VSD_DECODE_STARVE', 21) -PERF_CP_SQE_PIPE_OUT_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PIPE_OUT_STALL', 22) -PERF_CP_SQE_SYNC_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SYNC_STALL', 23) -PERF_CP_SQE_PM4_WFI_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_PM4_WFI_STALL', 24) -PERF_CP_SQE_SYS_WFI_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SYS_WFI_STALL', 25) -PERF_CP_SQE_T4_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_T4_EXEC', 26) -PERF_CP_SQE_LOAD_STATE_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_LOAD_STATE_EXEC', 27) -PERF_CP_SQE_SAVE_SDS_STATE = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_SAVE_SDS_STATE', 28) -PERF_CP_SQE_DRAW_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_DRAW_EXEC', 29) -PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 30) -PERF_CP_SQE_EXEC_PROFILED = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_EXEC_PROFILED', 31) -PERF_CP_MEMORY_POOL_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_EMPTY', 32) -PERF_CP_MEMORY_POOL_SYNC_STALL = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_SYNC_STALL', 33) -PERF_CP_MEMORY_POOL_ABOVE_THRESH = enum_a6xx_cp_perfcounter_select.define('PERF_CP_MEMORY_POOL_ABOVE_THRESH', 34) -PERF_CP_AHB_WR_STALL_PRE_DRAWS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_WR_STALL_PRE_DRAWS', 35) -PERF_CP_AHB_STALL_SQE_GMU = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_GMU', 36) -PERF_CP_AHB_STALL_SQE_WR_OTHER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_WR_OTHER', 37) -PERF_CP_AHB_STALL_SQE_RD_OTHER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_AHB_STALL_SQE_RD_OTHER', 38) -PERF_CP_CLUSTER0_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER0_EMPTY', 39) -PERF_CP_CLUSTER1_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER1_EMPTY', 40) -PERF_CP_CLUSTER2_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER2_EMPTY', 41) -PERF_CP_CLUSTER3_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER3_EMPTY', 42) -PERF_CP_CLUSTER4_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER4_EMPTY', 43) -PERF_CP_CLUSTER5_EMPTY = enum_a6xx_cp_perfcounter_select.define('PERF_CP_CLUSTER5_EMPTY', 44) -PERF_CP_PM4_DATA = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PM4_DATA', 45) -PERF_CP_PM4_HEADERS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_PM4_HEADERS', 46) -PERF_CP_VBIF_READ_BEATS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VBIF_READ_BEATS', 47) -PERF_CP_VBIF_WRITE_BEATS = enum_a6xx_cp_perfcounter_select.define('PERF_CP_VBIF_WRITE_BEATS', 48) -PERF_CP_SQE_INSTR_COUNTER = enum_a6xx_cp_perfcounter_select.define('PERF_CP_SQE_INSTR_COUNTER', 49) - -enum_a6xx_rbbm_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_RBBM_ALWAYS_COUNT = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_ALWAYS_COUNT', 0) -PERF_RBBM_ALWAYS_ON = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_ALWAYS_ON', 1) -PERF_RBBM_TSE_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_TSE_BUSY', 2) -PERF_RBBM_RAS_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_RAS_BUSY', 3) -PERF_RBBM_PC_DCALL_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_PC_DCALL_BUSY', 4) -PERF_RBBM_PC_VSD_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_PC_VSD_BUSY', 5) -PERF_RBBM_STATUS_MASKED = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_STATUS_MASKED', 6) -PERF_RBBM_COM_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_COM_BUSY', 7) -PERF_RBBM_DCOM_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_DCOM_BUSY', 8) -PERF_RBBM_VBIF_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_VBIF_BUSY', 9) -PERF_RBBM_VSC_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_VSC_BUSY', 10) -PERF_RBBM_TESS_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_TESS_BUSY', 11) -PERF_RBBM_UCHE_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_UCHE_BUSY', 12) -PERF_RBBM_HLSQ_BUSY = enum_a6xx_rbbm_perfcounter_select.define('PERF_RBBM_HLSQ_BUSY', 13) - -enum_a6xx_pc_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_PC_BUSY_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_BUSY_CYCLES', 0) -PERF_PC_WORKING_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_WORKING_CYCLES', 1) -PERF_PC_STALL_CYCLES_VFD = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VFD', 2) -PERF_PC_STALL_CYCLES_TSE = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TSE', 3) -PERF_PC_STALL_CYCLES_VPC = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VPC', 4) -PERF_PC_STALL_CYCLES_UCHE = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_UCHE', 5) -PERF_PC_STALL_CYCLES_TESS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TESS', 6) -PERF_PC_STALL_CYCLES_TSE_ONLY = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_TSE_ONLY', 7) -PERF_PC_STALL_CYCLES_VPC_ONLY = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STALL_CYCLES_VPC_ONLY', 8) -PERF_PC_PASS1_TF_STALL_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_PASS1_TF_STALL_CYCLES', 9) -PERF_PC_STARVE_CYCLES_FOR_INDEX = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_INDEX', 10) -PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR', 11) -PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM', 12) -PERF_PC_STARVE_CYCLES_FOR_POSITION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_FOR_POSITION', 13) -PERF_PC_STARVE_CYCLES_DI = enum_a6xx_pc_perfcounter_select.define('PERF_PC_STARVE_CYCLES_DI', 14) -PERF_PC_VIS_STREAMS_LOADED = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VIS_STREAMS_LOADED', 15) -PERF_PC_INSTANCES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_INSTANCES', 16) -PERF_PC_VPC_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VPC_PRIMITIVES', 17) -PERF_PC_DEAD_PRIM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DEAD_PRIM', 18) -PERF_PC_LIVE_PRIM = enum_a6xx_pc_perfcounter_select.define('PERF_PC_LIVE_PRIM', 19) -PERF_PC_VERTEX_HITS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VERTEX_HITS', 20) -PERF_PC_IA_VERTICES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_IA_VERTICES', 21) -PERF_PC_IA_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_IA_PRIMITIVES', 22) -PERF_PC_GS_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_GS_PRIMITIVES', 23) -PERF_PC_HS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_HS_INVOCATIONS', 24) -PERF_PC_DS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DS_INVOCATIONS', 25) -PERF_PC_VS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VS_INVOCATIONS', 26) -PERF_PC_GS_INVOCATIONS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_GS_INVOCATIONS', 27) -PERF_PC_DS_PRIMITIVES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_DS_PRIMITIVES', 28) -PERF_PC_VPC_POS_DATA_TRANSACTION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_VPC_POS_DATA_TRANSACTION', 29) -PERF_PC_3D_DRAWCALLS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_3D_DRAWCALLS', 30) -PERF_PC_2D_DRAWCALLS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_2D_DRAWCALLS', 31) -PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS', 32) -PERF_TESS_BUSY_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_BUSY_CYCLES', 33) -PERF_TESS_WORKING_CYCLES = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_WORKING_CYCLES', 34) -PERF_TESS_STALL_CYCLES_PC = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_STALL_CYCLES_PC', 35) -PERF_TESS_STARVE_CYCLES_PC = enum_a6xx_pc_perfcounter_select.define('PERF_TESS_STARVE_CYCLES_PC', 36) -PERF_PC_TSE_TRANSACTION = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TSE_TRANSACTION', 37) -PERF_PC_TSE_VERTEX = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TSE_VERTEX', 38) -PERF_PC_TESS_PC_UV_TRANS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_PC_UV_TRANS', 39) -PERF_PC_TESS_PC_UV_PATCHES = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_PC_UV_PATCHES', 40) -PERF_PC_TESS_FACTOR_TRANS = enum_a6xx_pc_perfcounter_select.define('PERF_PC_TESS_FACTOR_TRANS', 41) - -enum_a6xx_vfd_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_VFD_BUSY_CYCLES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_BUSY_CYCLES', 0) -PERF_VFD_STALL_CYCLES_UCHE = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_UCHE', 1) -PERF_VFD_STALL_CYCLES_VPC_ALLOC = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_VPC_ALLOC', 2) -PERF_VFD_STALL_CYCLES_SP_INFO = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_SP_INFO', 3) -PERF_VFD_STALL_CYCLES_SP_ATTR = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STALL_CYCLES_SP_ATTR', 4) -PERF_VFD_STARVE_CYCLES_UCHE = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_STARVE_CYCLES_UCHE', 5) -PERF_VFD_RBUFFER_FULL = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_RBUFFER_FULL', 6) -PERF_VFD_ATTR_INFO_FIFO_FULL = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_ATTR_INFO_FIFO_FULL', 7) -PERF_VFD_DECODED_ATTRIBUTE_BYTES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_DECODED_ATTRIBUTE_BYTES', 8) -PERF_VFD_NUM_ATTRIBUTES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_NUM_ATTRIBUTES', 9) -PERF_VFD_UPPER_SHADER_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_UPPER_SHADER_FIBERS', 10) -PERF_VFD_LOWER_SHADER_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_LOWER_SHADER_FIBERS', 11) -PERF_VFD_MODE_0_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_0_FIBERS', 12) -PERF_VFD_MODE_1_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_1_FIBERS', 13) -PERF_VFD_MODE_2_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_2_FIBERS', 14) -PERF_VFD_MODE_3_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_3_FIBERS', 15) -PERF_VFD_MODE_4_FIBERS = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_MODE_4_FIBERS', 16) -PERF_VFD_TOTAL_VERTICES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFD_TOTAL_VERTICES', 17) -PERF_VFDP_STALL_CYCLES_VFD = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD', 18) -PERF_VFDP_STALL_CYCLES_VFD_INDEX = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD_INDEX', 19) -PERF_VFDP_STALL_CYCLES_VFD_PROG = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STALL_CYCLES_VFD_PROG', 20) -PERF_VFDP_STARVE_CYCLES_PC = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_STARVE_CYCLES_PC', 21) -PERF_VFDP_VS_STAGE_WAVES = enum_a6xx_vfd_perfcounter_select.define('PERF_VFDP_VS_STAGE_WAVES', 22) - -enum_a6xx_hlsq_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_HLSQ_BUSY_CYCLES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_BUSY_CYCLES', 0) -PERF_HLSQ_STALL_CYCLES_UCHE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_UCHE', 1) -PERF_HLSQ_STALL_CYCLES_SP_STATE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_SP_STATE', 2) -PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', 3) -PERF_HLSQ_UCHE_LATENCY_CYCLES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_UCHE_LATENCY_CYCLES', 4) -PERF_HLSQ_UCHE_LATENCY_COUNT = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_UCHE_LATENCY_COUNT', 5) -PERF_HLSQ_FS_STAGE_1X_WAVES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_STAGE_1X_WAVES', 6) -PERF_HLSQ_FS_STAGE_2X_WAVES = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_STAGE_2X_WAVES', 7) -PERF_HLSQ_QUADS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_QUADS', 8) -PERF_HLSQ_CS_INVOCATIONS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_CS_INVOCATIONS', 9) -PERF_HLSQ_COMPUTE_DRAWCALLS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_COMPUTE_DRAWCALLS', 10) -PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', 11) -PERF_HLSQ_DUAL_FS_PROG_ACTIVE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 12) -PERF_HLSQ_DUAL_VS_PROG_ACTIVE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DUAL_VS_PROG_ACTIVE', 13) -PERF_HLSQ_FS_BATCH_COUNT_ZERO = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_FS_BATCH_COUNT_ZERO', 14) -PERF_HLSQ_VS_BATCH_COUNT_ZERO = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_VS_BATCH_COUNT_ZERO', 15) -PERF_HLSQ_WAVE_PENDING_NO_QUAD = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_WAVE_PENDING_NO_QUAD', 16) -PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', 17) -PERF_HLSQ_STALL_CYCLES_VPC = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_STALL_CYCLES_VPC', 18) -PERF_HLSQ_PIXELS = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_PIXELS', 19) -PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = enum_a6xx_hlsq_perfcounter_select.define('PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC', 20) - -enum_a6xx_vpc_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_VPC_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_BUSY_CYCLES', 0) -PERF_VPC_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_WORKING_CYCLES', 1) -PERF_VPC_STALL_CYCLES_UCHE = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_UCHE', 2) -PERF_VPC_STALL_CYCLES_VFD_WACK = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_VFD_WACK', 3) -PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC', 4) -PERF_VPC_STALL_CYCLES_PC = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_PC', 5) -PERF_VPC_STALL_CYCLES_SP_LM = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_SP_LM', 6) -PERF_VPC_STARVE_CYCLES_SP = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_SP', 7) -PERF_VPC_STARVE_CYCLES_LRZ = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_LRZ', 8) -PERF_VPC_PC_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PC_PRIMITIVES', 9) -PERF_VPC_SP_COMPONENTS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_SP_COMPONENTS', 10) -PERF_VPC_STALL_CYCLES_VPCRAM_POS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STALL_CYCLES_VPCRAM_POS', 11) -PERF_VPC_LRZ_ASSIGN_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LRZ_ASSIGN_PRIMITIVES', 12) -PERF_VPC_RB_VISIBLE_PRIMITIVES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_RB_VISIBLE_PRIMITIVES', 13) -PERF_VPC_LM_TRANSACTION = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LM_TRANSACTION', 14) -PERF_VPC_STREAMOUT_TRANSACTION = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STREAMOUT_TRANSACTION', 15) -PERF_VPC_VS_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VS_BUSY_CYCLES', 16) -PERF_VPC_PS_BUSY_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PS_BUSY_CYCLES', 17) -PERF_VPC_VS_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VS_WORKING_CYCLES', 18) -PERF_VPC_PS_WORKING_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_PS_WORKING_CYCLES', 19) -PERF_VPC_STARVE_CYCLES_RB = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_STARVE_CYCLES_RB', 20) -PERF_VPC_NUM_VPCRAM_READ_POS = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_READ_POS', 21) -PERF_VPC_WIT_FULL_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_WIT_FULL_CYCLES', 22) -PERF_VPC_VPCRAM_FULL_CYCLES = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_VPCRAM_FULL_CYCLES', 23) -PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', 24) -PERF_VPC_NUM_VPCRAM_WRITE = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_WRITE', 25) -PERF_VPC_NUM_VPCRAM_READ_SO = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_VPCRAM_READ_SO', 26) -PERF_VPC_NUM_ATTR_REQ_LM = enum_a6xx_vpc_perfcounter_select.define('PERF_VPC_NUM_ATTR_REQ_LM', 27) - -enum_a6xx_tse_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_TSE_BUSY_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_BUSY_CYCLES', 0) -PERF_TSE_CLIPPING_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIPPING_CYCLES', 1) -PERF_TSE_STALL_CYCLES_RAS = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_RAS', 2) -PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE', 3) -PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', 4) -PERF_TSE_STARVE_CYCLES_PC = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_STARVE_CYCLES_PC', 5) -PERF_TSE_INPUT_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_INPUT_PRIM', 6) -PERF_TSE_INPUT_NULL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_INPUT_NULL_PRIM', 7) -PERF_TSE_TRIVAL_REJ_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_TRIVAL_REJ_PRIM', 8) -PERF_TSE_CLIPPED_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIPPED_PRIM', 9) -PERF_TSE_ZERO_AREA_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_ZERO_AREA_PRIM', 10) -PERF_TSE_FACENESS_CULLED_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_FACENESS_CULLED_PRIM', 11) -PERF_TSE_ZERO_PIXEL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_ZERO_PIXEL_PRIM', 12) -PERF_TSE_OUTPUT_NULL_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_OUTPUT_NULL_PRIM', 13) -PERF_TSE_OUTPUT_VISIBLE_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_OUTPUT_VISIBLE_PRIM', 14) -PERF_TSE_CINVOCATION = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CINVOCATION', 15) -PERF_TSE_CPRIMITIVES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CPRIMITIVES', 16) -PERF_TSE_2D_INPUT_PRIM = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_2D_INPUT_PRIM', 17) -PERF_TSE_2D_ALIVE_CYCLES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_2D_ALIVE_CYCLES', 18) -PERF_TSE_CLIP_PLANES = enum_a6xx_tse_perfcounter_select.define('PERF_TSE_CLIP_PLANES', 19) - -enum_a6xx_ras_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_RAS_BUSY_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_BUSY_CYCLES', 0) -PERF_RAS_SUPERTILE_ACTIVE_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPERTILE_ACTIVE_CYCLES', 1) -PERF_RAS_STALL_CYCLES_LRZ = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_STALL_CYCLES_LRZ', 2) -PERF_RAS_STARVE_CYCLES_TSE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_STARVE_CYCLES_TSE', 3) -PERF_RAS_SUPER_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPER_TILES', 4) -PERF_RAS_8X4_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_8X4_TILES', 5) -PERF_RAS_MASKGEN_ACTIVE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_MASKGEN_ACTIVE', 6) -PERF_RAS_FULLY_COVERED_SUPER_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_FULLY_COVERED_SUPER_TILES', 7) -PERF_RAS_FULLY_COVERED_8X4_TILES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_FULLY_COVERED_8X4_TILES', 8) -PERF_RAS_PRIM_KILLED_INVISILBE = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_PRIM_KILLED_INVISILBE', 9) -PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 10) -PERF_RAS_LRZ_INTF_WORKING_CYCLES = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_LRZ_INTF_WORKING_CYCLES', 11) -PERF_RAS_BLOCKS = enum_a6xx_ras_perfcounter_select.define('PERF_RAS_BLOCKS', 12) - -enum_a6xx_uche_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_UCHE_BUSY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BUSY_CYCLES', 0) -PERF_UCHE_STALL_CYCLES_ARBITER = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_STALL_CYCLES_ARBITER', 1) -PERF_UCHE_VBIF_LATENCY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_LATENCY_CYCLES', 2) -PERF_UCHE_VBIF_LATENCY_SAMPLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_LATENCY_SAMPLES', 3) -PERF_UCHE_VBIF_READ_BEATS_TP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_TP', 4) -PERF_UCHE_VBIF_READ_BEATS_VFD = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_VFD', 5) -PERF_UCHE_VBIF_READ_BEATS_HLSQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_HLSQ', 6) -PERF_UCHE_VBIF_READ_BEATS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_LRZ', 7) -PERF_UCHE_VBIF_READ_BEATS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_SP', 8) -PERF_UCHE_READ_REQUESTS_TP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_TP', 9) -PERF_UCHE_READ_REQUESTS_VFD = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_VFD', 10) -PERF_UCHE_READ_REQUESTS_HLSQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_HLSQ', 11) -PERF_UCHE_READ_REQUESTS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_LRZ', 12) -PERF_UCHE_READ_REQUESTS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_SP', 13) -PERF_UCHE_WRITE_REQUESTS_LRZ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_LRZ', 14) -PERF_UCHE_WRITE_REQUESTS_SP = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_SP', 15) -PERF_UCHE_WRITE_REQUESTS_VPC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_VPC', 16) -PERF_UCHE_WRITE_REQUESTS_VSC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_WRITE_REQUESTS_VSC', 17) -PERF_UCHE_EVICTS = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_EVICTS', 18) -PERF_UCHE_BANK_REQ0 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ0', 19) -PERF_UCHE_BANK_REQ1 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ1', 20) -PERF_UCHE_BANK_REQ2 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ2', 21) -PERF_UCHE_BANK_REQ3 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ3', 22) -PERF_UCHE_BANK_REQ4 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ4', 23) -PERF_UCHE_BANK_REQ5 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ5', 24) -PERF_UCHE_BANK_REQ6 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ6', 25) -PERF_UCHE_BANK_REQ7 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_BANK_REQ7', 26) -PERF_UCHE_VBIF_READ_BEATS_CH0 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_CH0', 27) -PERF_UCHE_VBIF_READ_BEATS_CH1 = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_CH1', 28) -PERF_UCHE_GMEM_READ_BEATS = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_GMEM_READ_BEATS', 29) -PERF_UCHE_TPH_REF_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_REF_FULL', 30) -PERF_UCHE_TPH_VICTIM_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_VICTIM_FULL', 31) -PERF_UCHE_TPH_EXT_FULL = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_TPH_EXT_FULL', 32) -PERF_UCHE_VBIF_STALL_WRITE_DATA = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_STALL_WRITE_DATA', 33) -PERF_UCHE_DCMP_LATENCY_SAMPLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_DCMP_LATENCY_SAMPLES', 34) -PERF_UCHE_DCMP_LATENCY_CYCLES = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_DCMP_LATENCY_CYCLES', 35) -PERF_UCHE_VBIF_READ_BEATS_PC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_VBIF_READ_BEATS_PC', 36) -PERF_UCHE_READ_REQUESTS_PC = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_READ_REQUESTS_PC', 37) -PERF_UCHE_RAM_READ_REQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_RAM_READ_REQ', 38) -PERF_UCHE_RAM_WRITE_REQ = enum_a6xx_uche_perfcounter_select.define('PERF_UCHE_RAM_WRITE_REQ', 39) - -enum_a6xx_tp_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_TP_BUSY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_BUSY_CYCLES', 0) -PERF_TP_STALL_CYCLES_UCHE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STALL_CYCLES_UCHE', 1) -PERF_TP_LATENCY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_LATENCY_CYCLES', 2) -PERF_TP_LATENCY_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_LATENCY_TRANS', 3) -PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUEST_SAMPLES', 4) -PERF_TP_FLAG_CACHE_REQUEST_LATENCY = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUEST_LATENCY', 5) -PERF_TP_L1_CACHELINE_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_CACHELINE_REQUESTS', 6) -PERF_TP_L1_CACHELINE_MISSES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_CACHELINE_MISSES', 7) -PERF_TP_SP_TP_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_SP_TP_TRANS', 8) -PERF_TP_TP_SP_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_TP_SP_TRANS', 9) -PERF_TP_OUTPUT_PIXELS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS', 10) -PERF_TP_FILTER_WORKLOAD_16BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FILTER_WORKLOAD_16BIT', 11) -PERF_TP_FILTER_WORKLOAD_32BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FILTER_WORKLOAD_32BIT', 12) -PERF_TP_QUADS_RECEIVED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_RECEIVED', 13) -PERF_TP_QUADS_OFFSET = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_OFFSET', 14) -PERF_TP_QUADS_SHADOW = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_SHADOW', 15) -PERF_TP_QUADS_ARRAY = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_ARRAY', 16) -PERF_TP_QUADS_GRADIENT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_GRADIENT', 17) -PERF_TP_QUADS_1D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_1D', 18) -PERF_TP_QUADS_2D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_2D', 19) -PERF_TP_QUADS_BUFFER = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_BUFFER', 20) -PERF_TP_QUADS_3D = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_3D', 21) -PERF_TP_QUADS_CUBE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_CUBE', 22) -PERF_TP_DIVERGENT_QUADS_RECEIVED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_DIVERGENT_QUADS_RECEIVED', 23) -PERF_TP_PRT_NON_RESIDENT_EVENTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_PRT_NON_RESIDENT_EVENTS', 24) -PERF_TP_OUTPUT_PIXELS_POINT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_POINT', 25) -PERF_TP_OUTPUT_PIXELS_BILINEAR = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_BILINEAR', 26) -PERF_TP_OUTPUT_PIXELS_MIP = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_MIP', 27) -PERF_TP_OUTPUT_PIXELS_ANISO = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_ANISO', 28) -PERF_TP_OUTPUT_PIXELS_ZERO_LOD = enum_a6xx_tp_perfcounter_select.define('PERF_TP_OUTPUT_PIXELS_ZERO_LOD', 29) -PERF_TP_FLAG_CACHE_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_REQUESTS', 30) -PERF_TP_FLAG_CACHE_MISSES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_MISSES', 31) -PERF_TP_L1_5_L2_REQUESTS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_REQUESTS', 32) -PERF_TP_2D_OUTPUT_PIXELS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS', 33) -PERF_TP_2D_OUTPUT_PIXELS_POINT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS_POINT', 34) -PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', 35) -PERF_TP_2D_FILTER_WORKLOAD_16BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_FILTER_WORKLOAD_16BIT', 36) -PERF_TP_2D_FILTER_WORKLOAD_32BIT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_2D_FILTER_WORKLOAD_32BIT', 37) -PERF_TP_TPA2TPC_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_TPA2TPC_TRANS', 38) -PERF_TP_L1_MISSES_ASTC_1TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_1TILE', 39) -PERF_TP_L1_MISSES_ASTC_2TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_2TILE', 40) -PERF_TP_L1_MISSES_ASTC_4TILE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_MISSES_ASTC_4TILE', 41) -PERF_TP_L1_5_L2_COMPRESS_REQS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_COMPRESS_REQS', 42) -PERF_TP_L1_5_L2_COMPRESS_MISS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_L2_COMPRESS_MISS', 43) -PERF_TP_L1_BANK_CONFLICT = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_BANK_CONFLICT', 44) -PERF_TP_L1_5_MISS_LATENCY_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_MISS_LATENCY_CYCLES', 45) -PERF_TP_L1_5_MISS_LATENCY_TRANS = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_MISS_LATENCY_TRANS', 46) -PERF_TP_QUADS_CONSTANT_MULTIPLIED = enum_a6xx_tp_perfcounter_select.define('PERF_TP_QUADS_CONSTANT_MULTIPLIED', 47) -PERF_TP_FRONTEND_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FRONTEND_WORKING_CYCLES', 48) -PERF_TP_L1_TAG_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_TAG_WORKING_CYCLES', 49) -PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', 50) -PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', 51) -PERF_TP_BACKEND_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_BACKEND_WORKING_CYCLES', 52) -PERF_TP_FLAG_CACHE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_FLAG_CACHE_WORKING_CYCLES', 53) -PERF_TP_L1_5_CACHE_WORKING_CYCLES = enum_a6xx_tp_perfcounter_select.define('PERF_TP_L1_5_CACHE_WORKING_CYCLES', 54) -PERF_TP_STARVE_CYCLES_SP = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STARVE_CYCLES_SP', 55) -PERF_TP_STARVE_CYCLES_UCHE = enum_a6xx_tp_perfcounter_select.define('PERF_TP_STARVE_CYCLES_UCHE', 56) - -enum_a6xx_sp_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_SP_BUSY_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_BUSY_CYCLES', 0) -PERF_SP_ALU_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ALU_WORKING_CYCLES', 1) -PERF_SP_EFU_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EFU_WORKING_CYCLES', 2) -PERF_SP_STALL_CYCLES_VPC = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_VPC', 3) -PERF_SP_STALL_CYCLES_TP = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_TP', 4) -PERF_SP_STALL_CYCLES_UCHE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_UCHE', 5) -PERF_SP_STALL_CYCLES_RB = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STALL_CYCLES_RB', 6) -PERF_SP_NON_EXECUTION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_NON_EXECUTION_CYCLES', 7) -PERF_SP_WAVE_CONTEXTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CONTEXTS', 8) -PERF_SP_WAVE_CONTEXT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CONTEXT_CYCLES', 9) -PERF_SP_FS_STAGE_WAVE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_WAVE_CYCLES', 10) -PERF_SP_FS_STAGE_WAVE_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_WAVE_SAMPLES', 11) -PERF_SP_VS_STAGE_WAVE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_WAVE_CYCLES', 12) -PERF_SP_VS_STAGE_WAVE_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_WAVE_SAMPLES', 13) -PERF_SP_FS_STAGE_DURATION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_DURATION_CYCLES', 14) -PERF_SP_VS_STAGE_DURATION_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_DURATION_CYCLES', 15) -PERF_SP_WAVE_CTRL_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_CTRL_CYCLES', 16) -PERF_SP_WAVE_LOAD_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_LOAD_CYCLES', 17) -PERF_SP_WAVE_EMIT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_EMIT_CYCLES', 18) -PERF_SP_WAVE_NOP_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_NOP_CYCLES', 19) -PERF_SP_WAVE_WAIT_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_WAIT_CYCLES', 20) -PERF_SP_WAVE_FETCH_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_FETCH_CYCLES', 21) -PERF_SP_WAVE_IDLE_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_IDLE_CYCLES', 22) -PERF_SP_WAVE_END_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_END_CYCLES', 23) -PERF_SP_WAVE_LONG_SYNC_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_LONG_SYNC_CYCLES', 24) -PERF_SP_WAVE_SHORT_SYNC_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_SHORT_SYNC_CYCLES', 25) -PERF_SP_WAVE_JOIN_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WAVE_JOIN_CYCLES', 26) -PERF_SP_LM_LOAD_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_LOAD_INSTRUCTIONS', 27) -PERF_SP_LM_STORE_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_STORE_INSTRUCTIONS', 28) -PERF_SP_LM_ATOMICS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_ATOMICS', 29) -PERF_SP_GM_LOAD_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_INSTRUCTIONS', 30) -PERF_SP_GM_STORE_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_STORE_INSTRUCTIONS', 31) -PERF_SP_GM_ATOMICS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_ATOMICS', 32) -PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', 33) -PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', 34) -PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', 35) -PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', 36) -PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', 37) -PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', 38) -PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', 39) -PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', 40) -PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', 41) -PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', 42) -PERF_SP_VS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_INSTRUCTIONS', 43) -PERF_SP_FS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_INSTRUCTIONS', 44) -PERF_SP_ADDR_LOCK_COUNT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ADDR_LOCK_COUNT', 45) -PERF_SP_UCHE_READ_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_UCHE_READ_TRANS', 46) -PERF_SP_UCHE_WRITE_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_UCHE_WRITE_TRANS', 47) -PERF_SP_EXPORT_VPC_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXPORT_VPC_TRANS', 48) -PERF_SP_EXPORT_RB_TRANS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXPORT_RB_TRANS', 49) -PERF_SP_PIXELS_KILLED = enum_a6xx_sp_perfcounter_select.define('PERF_SP_PIXELS_KILLED', 50) -PERF_SP_ICL1_REQUESTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ICL1_REQUESTS', 51) -PERF_SP_ICL1_MISSES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ICL1_MISSES', 52) -PERF_SP_HS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_HS_INSTRUCTIONS', 53) -PERF_SP_DS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_DS_INSTRUCTIONS', 54) -PERF_SP_GS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GS_INSTRUCTIONS', 55) -PERF_SP_CS_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_CS_INSTRUCTIONS', 56) -PERF_SP_GPR_READ = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ', 57) -PERF_SP_GPR_WRITE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_WRITE', 58) -PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', 59) -PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', 60) -PERF_SP_LM_BANK_CONFLICTS = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_BANK_CONFLICTS', 61) -PERF_SP_TEX_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_TEX_CONTROL_WORKING_CYCLES', 62) -PERF_SP_LOAD_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LOAD_CONTROL_WORKING_CYCLES', 63) -PERF_SP_FLOW_CONTROL_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_FLOW_CONTROL_WORKING_CYCLES', 64) -PERF_SP_LM_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LM_WORKING_CYCLES', 65) -PERF_SP_DISPATCHER_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_DISPATCHER_WORKING_CYCLES', 66) -PERF_SP_SEQUENCER_WORKING_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_SEQUENCER_WORKING_CYCLES', 67) -PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = enum_a6xx_sp_perfcounter_select.define('PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', 68) -PERF_SP_STARVE_CYCLES_HLSQ = enum_a6xx_sp_perfcounter_select.define('PERF_SP_STARVE_CYCLES_HLSQ', 69) -PERF_SP_NON_EXECUTION_LS_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_NON_EXECUTION_LS_CYCLES', 70) -PERF_SP_WORKING_EU = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU', 71) -PERF_SP_ANY_EU_WORKING = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING', 72) -PERF_SP_WORKING_EU_FS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_FS_STAGE', 73) -PERF_SP_ANY_EU_WORKING_FS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_FS_STAGE', 74) -PERF_SP_WORKING_EU_VS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_VS_STAGE', 75) -PERF_SP_ANY_EU_WORKING_VS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_VS_STAGE', 76) -PERF_SP_WORKING_EU_CS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_WORKING_EU_CS_STAGE', 77) -PERF_SP_ANY_EU_WORKING_CS_STAGE = enum_a6xx_sp_perfcounter_select.define('PERF_SP_ANY_EU_WORKING_CS_STAGE', 78) -PERF_SP_GPR_READ_PREFETCH = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ_PREFETCH', 79) -PERF_SP_GPR_READ_CONFLICT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_READ_CONFLICT', 80) -PERF_SP_GPR_WRITE_CONFLICT = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GPR_WRITE_CONFLICT', 81) -PERF_SP_GM_LOAD_LATENCY_CYCLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_LATENCY_CYCLES', 82) -PERF_SP_GM_LOAD_LATENCY_SAMPLES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_GM_LOAD_LATENCY_SAMPLES', 83) -PERF_SP_EXECUTABLE_WAVES = enum_a6xx_sp_perfcounter_select.define('PERF_SP_EXECUTABLE_WAVES', 84) - -enum_a6xx_rb_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_RB_BUSY_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BUSY_CYCLES', 0) -PERF_RB_STALL_CYCLES_HLSQ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_HLSQ', 1) -PERF_RB_STALL_CYCLES_FIFO0_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO0_FULL', 2) -PERF_RB_STALL_CYCLES_FIFO1_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO1_FULL', 3) -PERF_RB_STALL_CYCLES_FIFO2_FULL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_FIFO2_FULL', 4) -PERF_RB_STARVE_CYCLES_SP = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_SP', 5) -PERF_RB_STARVE_CYCLES_LRZ_TILE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_LRZ_TILE', 6) -PERF_RB_STARVE_CYCLES_CCU = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_CCU', 7) -PERF_RB_STARVE_CYCLES_Z_PLANE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_Z_PLANE', 8) -PERF_RB_STARVE_CYCLES_BARY_PLANE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STARVE_CYCLES_BARY_PLANE', 9) -PERF_RB_Z_WORKLOAD = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_WORKLOAD', 10) -PERF_RB_HLSQ_ACTIVE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_HLSQ_ACTIVE', 11) -PERF_RB_Z_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_READ', 12) -PERF_RB_Z_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_WRITE', 13) -PERF_RB_C_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_C_READ', 14) -PERF_RB_C_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_C_WRITE', 15) -PERF_RB_TOTAL_PASS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_TOTAL_PASS', 16) -PERF_RB_Z_PASS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_PASS', 17) -PERF_RB_Z_FAIL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_Z_FAIL', 18) -PERF_RB_S_FAIL = enum_a6xx_rb_perfcounter_select.define('PERF_RB_S_FAIL', 19) -PERF_RB_BLENDED_FXP_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FXP_COMPONENTS', 20) -PERF_RB_BLENDED_FP16_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FP16_COMPONENTS', 21) -PERF_RB_PS_INVOCATIONS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_PS_INVOCATIONS', 22) -PERF_RB_2D_ALIVE_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_ALIVE_CYCLES', 23) -PERF_RB_2D_STALL_CYCLES_A2D = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STALL_CYCLES_A2D', 24) -PERF_RB_2D_STARVE_CYCLES_SRC = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_SRC', 25) -PERF_RB_2D_STARVE_CYCLES_SP = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_SP', 26) -PERF_RB_2D_STARVE_CYCLES_DST = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_STARVE_CYCLES_DST', 27) -PERF_RB_2D_VALID_PIXELS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_VALID_PIXELS', 28) -PERF_RB_3D_PIXELS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_3D_PIXELS', 29) -PERF_RB_BLENDER_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDER_WORKING_CYCLES', 30) -PERF_RB_ZPROC_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_ZPROC_WORKING_CYCLES', 31) -PERF_RB_CPROC_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_CPROC_WORKING_CYCLES', 32) -PERF_RB_SAMPLER_WORKING_CYCLES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_SAMPLER_WORKING_CYCLES', 33) -PERF_RB_STALL_CYCLES_CCU_COLOR_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_COLOR_READ', 34) -PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', 35) -PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', 36) -PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', 37) -PERF_RB_STALL_CYCLES_VPC = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_VPC', 38) -PERF_RB_2D_INPUT_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_INPUT_TRANS', 39) -PERF_RB_2D_OUTPUT_RB_DST_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_OUTPUT_RB_DST_TRANS', 40) -PERF_RB_2D_OUTPUT_RB_SRC_TRANS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_2D_OUTPUT_RB_SRC_TRANS', 41) -PERF_RB_BLENDED_FP32_COMPONENTS = enum_a6xx_rb_perfcounter_select.define('PERF_RB_BLENDED_FP32_COMPONENTS', 42) -PERF_RB_COLOR_PIX_TILES = enum_a6xx_rb_perfcounter_select.define('PERF_RB_COLOR_PIX_TILES', 43) -PERF_RB_STALL_CYCLES_CCU = enum_a6xx_rb_perfcounter_select.define('PERF_RB_STALL_CYCLES_CCU', 44) -PERF_RB_EARLY_Z_ARB3_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_EARLY_Z_ARB3_GRANT', 45) -PERF_RB_LATE_Z_ARB3_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_LATE_Z_ARB3_GRANT', 46) -PERF_RB_EARLY_Z_SKIP_GRANT = enum_a6xx_rb_perfcounter_select.define('PERF_RB_EARLY_Z_SKIP_GRANT', 47) - -enum_a6xx_vsc_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_VSC_BUSY_CYCLES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_BUSY_CYCLES', 0) -PERF_VSC_WORKING_CYCLES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_WORKING_CYCLES', 1) -PERF_VSC_STALL_CYCLES_UCHE = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_STALL_CYCLES_UCHE', 2) -PERF_VSC_EOT_NUM = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_EOT_NUM', 3) -PERF_VSC_INPUT_TILES = enum_a6xx_vsc_perfcounter_select.define('PERF_VSC_INPUT_TILES', 4) - -enum_a6xx_ccu_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_CCU_BUSY_CYCLES = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_BUSY_CYCLES', 0) -PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', 1) -PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', 2) -PERF_CCU_STARVE_CYCLES_FLAG_RETURN = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_STARVE_CYCLES_FLAG_RETURN', 3) -PERF_CCU_DEPTH_BLOCKS = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_BLOCKS', 4) -PERF_CCU_COLOR_BLOCKS = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_BLOCKS', 5) -PERF_CCU_DEPTH_BLOCK_HIT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_BLOCK_HIT', 6) -PERF_CCU_COLOR_BLOCK_HIT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_BLOCK_HIT', 7) -PERF_CCU_PARTIAL_BLOCK_READ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_PARTIAL_BLOCK_READ', 8) -PERF_CCU_GMEM_READ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_GMEM_READ', 9) -PERF_CCU_GMEM_WRITE = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_GMEM_WRITE', 10) -PERF_CCU_DEPTH_READ_FLAG0_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG0_COUNT', 11) -PERF_CCU_DEPTH_READ_FLAG1_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG1_COUNT', 12) -PERF_CCU_DEPTH_READ_FLAG2_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG2_COUNT', 13) -PERF_CCU_DEPTH_READ_FLAG3_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG3_COUNT', 14) -PERF_CCU_DEPTH_READ_FLAG4_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG4_COUNT', 15) -PERF_CCU_DEPTH_READ_FLAG5_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG5_COUNT', 16) -PERF_CCU_DEPTH_READ_FLAG6_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG6_COUNT', 17) -PERF_CCU_DEPTH_READ_FLAG8_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_DEPTH_READ_FLAG8_COUNT', 18) -PERF_CCU_COLOR_READ_FLAG0_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG0_COUNT', 19) -PERF_CCU_COLOR_READ_FLAG1_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG1_COUNT', 20) -PERF_CCU_COLOR_READ_FLAG2_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG2_COUNT', 21) -PERF_CCU_COLOR_READ_FLAG3_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG3_COUNT', 22) -PERF_CCU_COLOR_READ_FLAG4_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG4_COUNT', 23) -PERF_CCU_COLOR_READ_FLAG5_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG5_COUNT', 24) -PERF_CCU_COLOR_READ_FLAG6_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG6_COUNT', 25) -PERF_CCU_COLOR_READ_FLAG8_COUNT = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_COLOR_READ_FLAG8_COUNT', 26) -PERF_CCU_2D_RD_REQ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_2D_RD_REQ', 27) -PERF_CCU_2D_WR_REQ = enum_a6xx_ccu_perfcounter_select.define('PERF_CCU_2D_WR_REQ', 28) - -enum_a6xx_lrz_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_LRZ_BUSY_CYCLES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_BUSY_CYCLES', 0) -PERF_LRZ_STARVE_CYCLES_RAS = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STARVE_CYCLES_RAS', 1) -PERF_LRZ_STALL_CYCLES_RB = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB', 2) -PERF_LRZ_STALL_CYCLES_VSC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VSC', 3) -PERF_LRZ_STALL_CYCLES_VPC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VPC', 4) -PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', 5) -PERF_LRZ_STALL_CYCLES_UCHE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_UCHE', 6) -PERF_LRZ_LRZ_READ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_LRZ_READ', 7) -PERF_LRZ_LRZ_WRITE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_LRZ_WRITE', 8) -PERF_LRZ_READ_LATENCY = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_READ_LATENCY', 9) -PERF_LRZ_MERGE_CACHE_UPDATING = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_MERGE_CACHE_UPDATING', 10) -PERF_LRZ_PRIM_KILLED_BY_MASKGEN = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PRIM_KILLED_BY_MASKGEN', 11) -PERF_LRZ_PRIM_KILLED_BY_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PRIM_KILLED_BY_LRZ', 12) -PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 13) -PERF_LRZ_FULL_8X8_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FULL_8X8_TILES', 14) -PERF_LRZ_PARTIAL_8X8_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PARTIAL_8X8_TILES', 15) -PERF_LRZ_TILE_KILLED = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_TILE_KILLED', 16) -PERF_LRZ_TOTAL_PIXEL = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_TOTAL_PIXEL', 17) -PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', 18) -PERF_LRZ_FULLY_COVERED_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FULLY_COVERED_TILES', 19) -PERF_LRZ_PARTIAL_COVERED_TILES = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_PARTIAL_COVERED_TILES', 20) -PERF_LRZ_FEEDBACK_ACCEPT = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_ACCEPT', 21) -PERF_LRZ_FEEDBACK_DISCARD = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_DISCARD', 22) -PERF_LRZ_FEEDBACK_STALL = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_FEEDBACK_STALL', 23) -PERF_LRZ_STALL_CYCLES_RB_ZPLANE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 24) -PERF_LRZ_STALL_CYCLES_RB_BPLANE = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_RB_BPLANE', 25) -PERF_LRZ_STALL_CYCLES_VC = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_STALL_CYCLES_VC', 26) -PERF_LRZ_RAS_MASK_TRANS = enum_a6xx_lrz_perfcounter_select.define('PERF_LRZ_RAS_MASK_TRANS', 27) - -enum_a6xx_cmp_perfcounter_select = CEnum(ctypes.c_uint32) -PERF_CMPDECMP_STALL_CYCLES_ARB = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_STALL_CYCLES_ARB', 0) -PERF_CMPDECMP_VBIF_LATENCY_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_LATENCY_CYCLES', 1) -PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', 2) -PERF_CMPDECMP_VBIF_READ_DATA_CCU = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_CCU', 3) -PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', 4) -PERF_CMPDECMP_VBIF_READ_REQUEST = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_REQUEST', 5) -PERF_CMPDECMP_VBIF_WRITE_REQUEST = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_REQUEST', 6) -PERF_CMPDECMP_VBIF_READ_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA', 7) -PERF_CMPDECMP_VBIF_WRITE_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA', 8) -PERF_CMPDECMP_FLAG_FETCH_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_FLAG_FETCH_CYCLES', 9) -PERF_CMPDECMP_FLAG_FETCH_SAMPLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_FLAG_FETCH_SAMPLES', 10) -PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', 11) -PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', 12) -PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', 13) -PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', 14) -PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', 15) -PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', 16) -PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', 17) -PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', 18) -PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', 19) -PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', 20) -PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', 21) -PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', 22) -PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', 23) -PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', 24) -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ', 25) -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR', 26) -PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN', 27) -PERF_CMPDECMP_2D_RD_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_RD_DATA', 28) -PERF_CMPDECMP_2D_WR_DATA = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_WR_DATA', 29) -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', 30) -PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', 31) -PERF_CMPDECMP_2D_OUTPUT_TRANS = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_OUTPUT_TRANS', 32) -PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', 33) -PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', 34) -PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', 35) -PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', 36) -PERF_CMPDECMP_2D_BUSY_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_BUSY_CYCLES', 37) -PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES', 38) -PERF_CMPDECMP_2D_PIXELS = enum_a6xx_cmp_perfcounter_select.define('PERF_CMPDECMP_2D_PIXELS', 39) - -enum_a6xx_2d_ifmt = CEnum(ctypes.c_uint32) -R2D_UNORM8 = enum_a6xx_2d_ifmt.define('R2D_UNORM8', 16) -R2D_INT32 = enum_a6xx_2d_ifmt.define('R2D_INT32', 7) -R2D_INT16 = enum_a6xx_2d_ifmt.define('R2D_INT16', 6) -R2D_INT8 = enum_a6xx_2d_ifmt.define('R2D_INT8', 5) -R2D_FLOAT32 = enum_a6xx_2d_ifmt.define('R2D_FLOAT32', 4) -R2D_FLOAT16 = enum_a6xx_2d_ifmt.define('R2D_FLOAT16', 3) -R2D_UNORM8_SRGB = enum_a6xx_2d_ifmt.define('R2D_UNORM8_SRGB', 1) -R2D_RAW = enum_a6xx_2d_ifmt.define('R2D_RAW', 0) - -enum_a6xx_ztest_mode = CEnum(ctypes.c_uint32) -A6XX_EARLY_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_Z', 0) -A6XX_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_LATE_Z', 1) -A6XX_EARLY_LRZ_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_LRZ_LATE_Z', 2) -A6XX_INVALID_ZTEST = enum_a6xx_ztest_mode.define('A6XX_INVALID_ZTEST', 3) - -enum_a6xx_tess_spacing = CEnum(ctypes.c_uint32) -TESS_EQUAL = enum_a6xx_tess_spacing.define('TESS_EQUAL', 0) -TESS_FRACTIONAL_ODD = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_ODD', 2) -TESS_FRACTIONAL_EVEN = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_EVEN', 3) - -enum_a6xx_tess_output = CEnum(ctypes.c_uint32) -TESS_POINTS = enum_a6xx_tess_output.define('TESS_POINTS', 0) -TESS_LINES = enum_a6xx_tess_output.define('TESS_LINES', 1) -TESS_CW_TRIS = enum_a6xx_tess_output.define('TESS_CW_TRIS', 2) -TESS_CCW_TRIS = enum_a6xx_tess_output.define('TESS_CCW_TRIS', 3) - -enum_a7xx_cp_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_CP_NEVER_COUNT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_NEVER_COUNT', 0) -A7XX_PERF_CP_ALWAYS_COUNT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ALWAYS_COUNT', 1) -A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_BUSY_GFX_CORE_IDLE', 2) -A7XX_PERF_CP_BUSY_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_BUSY_CYCLES', 3) -A7XX_PERF_CP_NUM_PREEMPTIONS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_NUM_PREEMPTIONS', 4) -A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_REACTION_DELAY', 5) -A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME', 6) -A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME', 7) -A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 8) -A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PREDICATED_DRAWS_KILLED', 9) -A7XX_PERF_CP_MODE_SWITCH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MODE_SWITCH', 10) -A7XX_PERF_CP_ZPASS_DONE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ZPASS_DONE', 11) -A7XX_PERF_CP_CONTEXT_DONE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CONTEXT_DONE', 12) -A7XX_PERF_CP_CACHE_FLUSH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CACHE_FLUSH', 13) -A7XX_PERF_CP_LONG_PREEMPTIONS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_LONG_PREEMPTIONS', 14) -A7XX_PERF_CP_SQE_I_CACHE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_I_CACHE_STARVE', 15) -A7XX_PERF_CP_SQE_IDLE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_IDLE', 16) -A7XX_PERF_CP_SQE_PM4_STARVE_RB = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_RB', 17) -A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB1', 18) -A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB2', 19) -A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_IB3', 20) -A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_FSDT', 21) -A7XX_PERF_CP_SQE_PM4_STARVE_SDS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_STARVE_SDS', 22) -A7XX_PERF_CP_SQE_MRB_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MRB_STARVE', 23) -A7XX_PERF_CP_SQE_RRB_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_RRB_STARVE', 24) -A7XX_PERF_CP_SQE_VSD_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_VSD_STARVE', 25) -A7XX_PERF_CP_VSD_DECODE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VSD_DECODE_STARVE', 26) -A7XX_PERF_CP_SQE_PIPE_OUT_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PIPE_OUT_STALL', 27) -A7XX_PERF_CP_SQE_SYNC_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SYNC_STALL', 28) -A7XX_PERF_CP_SQE_PM4_WFI_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_PM4_WFI_STALL', 29) -A7XX_PERF_CP_SQE_SYS_WFI_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SYS_WFI_STALL', 30) -A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', 31) -A7XX_PERF_CP_OUTPUT_BLOCKED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_OUTPUT_BLOCKED', 32) -A7XX_PERF_CP_SQE_T4_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_T4_EXEC', 33) -A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_LOAD_STATE_EXEC', 34) -A7XX_PERF_CP_SQE_SAVE_SDS_STATE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_SAVE_SDS_STATE', 35) -A7XX_PERF_CP_SQE_DRAW_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_DRAW_EXEC', 36) -A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 37) -A7XX_PERF_CP_SQE_EXEC_PROFILED = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_EXEC_PROFILED', 38) -A7XX_PERF_CP_MEMORY_POOL_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_EMPTY', 39) -A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', 40) -A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH', 41) -A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH', 42) -A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS', 43) -A7XX_PERF_CP_AHB_STALL_SQE_GMU = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_GMU', 44) -A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER', 45) -A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER', 46) -A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_U_EMPTY', 47) -A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_S_EMPTY', 48) -A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY', 49) -A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY', 50) -A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY', 51) -A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_GRAS_EMPTY', 52) -A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY', 53) -A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY', 54) -A7XX_PERF_CP_CLUSTER_PS_EMPTY = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_PS_EMPTY', 55) -A7XX_PERF_CP_PM4_DATA = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PM4_DATA', 56) -A7XX_PERF_CP_PM4_HEADERS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_PM4_HEADERS', 57) -A7XX_PERF_CP_VBIF_READ_BEATS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VBIF_READ_BEATS', 58) -A7XX_PERF_CP_VBIF_WRITE_BEATS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_VBIF_WRITE_BEATS', 59) -A7XX_PERF_CP_SQE_INSTR_COUNTER = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_INSTR_COUNTER', 60) -A7XX_PERF_CP_CLUSTER_FE_US_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_US_FULL', 61) -A7XX_PERF_CP_CLUSTER_FE_S_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_FE_S_FULL', 62) -A7XX_PERF_CP_CLUSTER_SP_VS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_VS_FULL', 63) -A7XX_PERF_CP_CLUSTER_VPC_US_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_US_FULL', 64) -A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', 65) -A7XX_PERF_CP_CLUSTER_GRAS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_GRAS_FULL', 66) -A7XX_PERF_CP_CLUSTER_SP_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_SP_PS_FULL', 67) -A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_VPC_PS_FULL', 68) -A7XX_PERF_CP_CLUSTER_PS_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_CLUSTER_PS_FULL', 69) -A7XX_PERF_CP_ICACHE_MISSES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_MISSES', 70) -A7XX_PERF_CP_ICACHE_HITS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_HITS', 71) -A7XX_PERF_CP_ICACHE_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ICACHE_STALL', 72) -A7XX_PERF_CP_DCACHE_MISSES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_MISSES', 73) -A7XX_PERF_CP_DCACHE_HITS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_HITS', 74) -A7XX_PERF_CP_DCACHE_STALLS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_DCACHE_STALLS', 75) -A7XX_PERF_CP_AQE_SQE_STALL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_SQE_STALL', 76) -A7XX_PERF_CP_SQE_AQE_STARVE = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_AQE_STARVE', 77) -A7XX_PERF_CP_ISR_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_ISR_CYCLES', 78) -A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MD8_STALL_CYCLES', 79) -A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES', 80) -A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_NUM_AS_CHUNKS', 81) -A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', 82) -A7XX_PERF_CP_S_SKEW_BUFFER_FULL = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_S_SKEW_BUFFER_FULL', 83) -A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = enum_a7xx_cp_perfcounter_select.define('A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH', 84) - -enum_a7xx_rbbm_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_RBBM_NEVER_COUNT = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_NEVER_COUNT', 0) -A7XX_PERF_RBBM_US_ALWAYS_COUNT = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_ALWAYS_COUNT', 1) -A7XX_PERF_RBBM_US_ALWAYS_ON = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_ALWAYS_ON', 2) -A7XX_PERF_RBBM_US_STATUS_MASKED = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_STATUS_MASKED', 3) -A7XX_PERF_RBBM_US_PC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_PC_BUSY', 4) -A7XX_PERF_RBBM_US_COM_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_COM_BUSY', 5) -A7XX_PERF_RBBM_US_DCOM_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_DCOM_BUSY', 6) -A7XX_PERF_RBBM_US_VBIF_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_VBIF_BUSY', 7) -A7XX_PERF_RBBM_US_VSC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_VSC_BUSY', 8) -A7XX_PERF_RBBM_US_UCHE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_UCHE_BUSY', 9) -A7XX_PERF_RBBM_US_HLSQ_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_US_HLSQ_BUSY', 10) -A7XX_PERF_RBBM_S_HLSQ_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_HLSQ_BUSY', 11) -A7XX_PERF_RBBM_S_PC_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_PC_BUSY', 12) -A7XX_PERF_RBBM_S_TESS_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TESS_BUSY', 13) -A7XX_PERF_RBBM_S_TSEFE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TSEFE_BUSY', 14) -A7XX_PERF_RBBM_S_TSEBE_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_TSEBE_BUSY', 15) -A7XX_PERF_RBBM_S_RAS_BUSY = enum_a7xx_rbbm_perfcounter_select.define('A7XX_PERF_RBBM_S_RAS_BUSY', 16) - -enum_a7xx_pc_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_PC_NEVER_COUNT = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_NEVER_COUNT', 0) -A7XX_PERF_PC_US_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BUSY_CYCLES', 1) -A7XX_PERF_PC_US_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_WORKING_CYCLES', 2) -A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS', 3) -A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES', 4) -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX', 5) -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF', 6) -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM', 7) -A7XX_PERF_PC_US_STARVE_CYCLES_DI = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_DI', 8) -A7XX_PERF_PC_US_VIS_STREAMS_LOADED = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VIS_STREAMS_LOADED', 9) -A7XX_PERF_PC_US_INSTANCES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_INSTANCES', 10) -A7XX_PERF_PC_US_DEAD_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DEAD_PRIM', 11) -A7XX_PERF_PC_US_SLICE_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_SLICE_LIVE_PRIM', 12) -A7XX_PERF_PC_US_3D_DRAWCALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_3D_DRAWCALLS', 13) -A7XX_PERF_PC_US_2D_DRAWCALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_2D_DRAWCALLS', 14) -A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS', 15) -A7XX_PERF_PC_US_MESH_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DRAWS', 16) -A7XX_PERF_PC_US_MESH_DEAD_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DEAD_DRAWS', 17) -A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS', 18) -A7XX_PERF_PC_US_MESH_DEAD_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_DEAD_PRIM', 19) -A7XX_PERF_PC_US_MESH_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_LIVE_PRIM', 20) -A7XX_PERF_PC_US_MESH_PA_EN_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_MESH_PA_EN_PRIM', 21) -A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM', 22) -A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW', 23) -A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX', 24) -A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE', 25) -A7XX_PERF_PC_US_PREDRAW_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PREDRAW_STALLS', 26) -A7XX_PERF_PC_US_DP0_INPUT_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_INPUT_STALLS', 27) -A7XX_PERF_PC_US_DP1_INPUT_STALLS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_INPUT_STALLS', 28) -A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD', 29) -A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD', 30) -A7XX_PERF_PC_US_PASSPAIR_STALL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_PASSPAIR_STALL', 31) -A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_UCHE0', 32) -A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_UCHE1', 33) -A7XX_PERF_PC_US_UCHE_0_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_0_TRANS', 34) -A7XX_PERF_PC_US_UCHE_1_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_UCHE_1_TRANS', 35) -A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLED_BY_ATTR', 36) -A7XX_PERF_PC_US_BV_STARVED_BY_RARB = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STARVED_BY_RARB', 37) -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR', 38) -A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV', 39) -A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK', 40) -A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL', 41) -A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL', 42) -A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL', 43) -A7XX_PERF_PC_US_DP0_RARB_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_RARB_FULL', 44) -A7XX_PERF_PC_US_DP1_RARB_FULL = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_RARB_FULL', 45) -A7XX_PERF_PC_US_DP0_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP0_LIVE_PRIM', 46) -A7XX_PERF_PC_US_DP1_LIVE_PRIM = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_DP1_LIVE_PRIM', 47) -A7XX_PERF_PC_US_BV2BR_SWITCH = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BV2BR_SWITCH', 48) -A7XX_PERF_PC_US_BR2BV_SWITCH = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_BR2BV_SWITCH', 49) -A7XX_PERF_PC_US_STALL_CYCLES_PC_S = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_US_STALL_CYCLES_PC_S', 50) -A7XX_PERF_PC_RESERVED_51 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_51', 51) -A7XX_PERF_PC_RESERVED_52 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_52', 52) -A7XX_PERF_PC_RESERVED_53 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_53', 53) -A7XX_PERF_PC_RESERVED_54 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_54', 54) -A7XX_PERF_PC_RESERVED_55 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_55', 55) -A7XX_PERF_PC_RESERVED_56 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_56', 56) -A7XX_PERF_PC_RESERVED_57 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_57', 57) -A7XX_PERF_PC_RESERVED_58 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_58', 58) -A7XX_PERF_PC_RESERVED_59 = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_RESERVED_59', 59) -A7XX_PERF_PC_S_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_BUSY_CYCLES', 60) -A7XX_PERF_PC_S_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_WORKING_CYCLES', 61) -A7XX_PERF_PC_S_STALL_CYCLES_VFD = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VFD', 62) -A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE', 63) -A7XX_PERF_PC_S_STALL_CYCLES_TESS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_TESS', 64) -A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY', 65) -A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY', 66) -A7XX_PERF_PC_S_VPC_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VPC_PRIMITIVES', 67) -A7XX_PERF_PC_S_VERTEX_HITS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VERTEX_HITS', 68) -A7XX_PERF_PC_S_IA_VERTICES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_IA_VERTICES', 69) -A7XX_PERF_PC_S_IA_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_IA_PRIMITIVES', 70) -A7XX_PERF_PC_S_HS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_HS_INVOCATIONS', 71) -A7XX_PERF_PC_S_DS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_DS_INVOCATIONS', 72) -A7XX_PERF_PC_S_VS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_VS_INVOCATIONS', 73) -A7XX_PERF_PC_S_GS_INVOCATIONS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_GS_INVOCATIONS', 74) -A7XX_PERF_PC_S_DS_PRIMITIVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_DS_PRIMITIVES', 75) -A7XX_PERF_PC_S_TESS_BUSY_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_BUSY_CYCLES', 76) -A7XX_PERF_PC_S_TESS_WORKING_CYCLES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_WORKING_CYCLES', 77) -A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC', 78) -A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC', 79) -A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_SETUP_ACTIVE', 80) -A7XX_PERF_PC_S_TESS_PID_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PID_ACTIVE', 81) -A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE', 82) -A7XX_PERF_PC_S_TESS_FACTOR_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_FACTOR_TRANS', 83) -A7XX_PERF_PC_S_TESS_PC_UV_TRANS = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PC_UV_TRANS', 84) -A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_TESS_PC_UV_PATCHES', 85) -A7XX_PERF_PC_S_MESH_VS_WAVES = enum_a7xx_pc_perfcounter_select.define('A7XX_PERF_PC_S_MESH_VS_WAVES', 86) - -enum_a7xx_vfd_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_VFD_NEVER_COUNT = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_NEVER_COUNT', 0) -A7XX_PERF_VFD_BUSY_CYCLES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_BUSY_CYCLES', 1) -A7XX_PERF_VFD_STALL_CYCLES_UCHE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_UCHE', 2) -A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC', 3) -A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_SP_INFO', 4) -A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR', 5) -A7XX_PERF_VFD_STARVE_CYCLES_UCHE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STARVE_CYCLES_UCHE', 6) -A7XX_PERF_VFD_RBUFFER_FULL = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_RBUFFER_FULL', 7) -A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', 8) -A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES', 9) -A7XX_PERF_VFD_NUM_ATTRIBUTES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_NUM_ATTRIBUTES', 10) -A7XX_PERF_VFD_UPPER_SHADER_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_UPPER_SHADER_FIBERS', 11) -A7XX_PERF_VFD_LOWER_SHADER_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_LOWER_SHADER_FIBERS', 12) -A7XX_PERF_VFD_MODE_0_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_0_FIBERS', 13) -A7XX_PERF_VFD_MODE_1_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_1_FIBERS', 14) -A7XX_PERF_VFD_MODE_2_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_2_FIBERS', 15) -A7XX_PERF_VFD_MODE_3_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_3_FIBERS', 16) -A7XX_PERF_VFD_MODE_4_FIBERS = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_MODE_4_FIBERS', 17) -A7XX_PERF_VFD_TOTAL_VERTICES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_TOTAL_VERTICES', 18) -A7XX_PERF_VFDP_STALL_CYCLES_VFD = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD', 19) -A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX', 20) -A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG', 21) -A7XX_PERF_VFDP_STARVE_CYCLES_PC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_STARVE_CYCLES_PC', 22) -A7XX_PERF_VFDP_VS_STAGE_WAVES = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFDP_VS_STAGE_WAVES', 23) -A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE', 24) -A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = enum_a7xx_vfd_perfcounter_select.define('A7XX_PERF_VFD_STALL_CYCLES_CBSYNC', 25) - -enum_a7xx_hlsq_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_HLSQ_NEVER_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_NEVER_COUNT', 0) -A7XX_PERF_HLSQ_BUSY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BUSY_CYCLES', 1) -A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE', 2) -A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE', 3) -A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES', 4) -A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT', 5) -A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_UCHE', 6) -A7XX_PERF_HLSQ_RESERVED_7 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_7', 7) -A7XX_PERF_HLSQ_RESERVED_8 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_8', 8) -A7XX_PERF_HLSQ_RESERVED_9 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_9', 9) -A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS', 10) -A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING', 11) -A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 12) -A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE', 13) -A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO', 14) -A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO', 15) -A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD', 16) -A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE', 17) -A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE', 18) -A7XX_PERF_HLSQ_RESERVED_19 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_19', 19) -A7XX_PERF_HLSQ_RESERVED_20 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_20', 20) -A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_STALL_CYCLES', 21) -A7XX_PERF_HLSQ_FS_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_STALL_CYCLES', 22) -A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_STALL_CYCLES', 23) -A7XX_PERF_HLSQ_BV_STALL_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_STALL_CYCLES', 24) -A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES', 25) -A7XX_PERF_HLSQ_FS_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DEREF_CYCLES', 26) -A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES', 27) -A7XX_PERF_HLSQ_BV_DEREF_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DEREF_CYCLES', 28) -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_S2W_CYCLES', 29) -A7XX_PERF_HLSQ_FS_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_S2W_CYCLES', 30) -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_S2W_CYCLES', 31) -A7XX_PERF_HLSQ_BV_S2W_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_S2W_CYCLES', 32) -A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W', 33) -A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_WAIT_VS_S2W', 34) -A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W', 35) -A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_WAIT_FS_S2W', 36) -A7XX_PERF_HLSQ_RESERVED_37 = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_RESERVED_37', 37) -A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W', 38) -A7XX_PERF_HLSQ_FS_STARVING_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_STARVING_SP', 39) -A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING', 40) -A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING', 41) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS', 42) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS', 43) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS', 44) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS', 45) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV', 46) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV', 47) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC', 48) -A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC', 49) -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS', 50) -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS', 51) -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV', 52) -A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC', 53) -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS', 54) -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS', 55) -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV', 56) -A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC', 57) -A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP', 58) -A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP', 59) -A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP', 60) -A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP', 61) -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_HLSQ', 62) -A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT', 63) -A7XX_PERF_HLSQ_L2STC_REQ_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_SP', 64) -A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT', 65) -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ', 66) -A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT', 67) -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_SP', 68) -A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT', 69) -A7XX_PERF_HLSQ_L2STC_REQ_UCHE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_REQ_UCHE', 70) -A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES', 71) -A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT', 72) -A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ', 73) -A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT', 74) -A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT', 75) -A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT', 76) -A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT', 77) -A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN', 78) -A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W', 79) -A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD', 80) -A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_MISS', 81) -A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_HIT', 82) -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT', 83) -A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE', 84) -A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT', 85) -A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE', 86) -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ', 87) -A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ', 88) -A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING', 89) -A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY', 90) -A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY', 91) -A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL', 92) -A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL', 93) -A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI', 94) -A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI', 95) -A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI', 96) -A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI', 97) -A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI', 98) -A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI', 99) -A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI', 100) -A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI', 101) -A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI', 102) -A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI', 103) -A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI', 104) -A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI', 105) -A7XX_PERF_HLSQ_PRIMITIVE_COUNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_PRIMITIVE_COUNT', 106) -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT', 107) -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT', 108) -A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC', 109) -A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC', 110) -A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = enum_a7xx_hlsq_perfcounter_select.define('A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC', 111) - -enum_a7xx_vpc_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_VPC_NEVER_COUNT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_NEVER_COUNT', 0) -A7XX_PERF_VPC_FE_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_BUSY_CYCLES', 1) -A7XX_PERF_VPC_FE_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_WORKING_CYCLES', 2) -A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK', 3) -A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STARVE_CYCLES_SP', 4) -A7XX_PERF_VPC_FE_PC_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_PC_PRIMITIVES', 5) -A7XX_PERF_VPC_FE_SP_COMPONENTS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_SP_COMPONENTS', 6) -A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS', 7) -A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VS_BUSY_CYCLES', 8) -A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VS_WORKING_CYCLES', 9) -A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS', 10) -A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_WIT_FULL_CYCLES', 11) -A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES', 12) -A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE', 13) -A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE', 14) -A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US', 15) -A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES', 16) -A7XX_PERF_VPC_FE_GS_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GS_PRIMITIVES', 17) -A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS', 18) -A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_CCU', 19) -A7XX_PERF_VPC_FE_NUM_WM_HIT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_NUM_WM_HIT', 20) -A7XX_PERF_VPC_FE_STALL_DQ_WACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_DQ_WACK', 21) -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE', 22) -A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS', 23) -A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES', 24) -A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES', 25) -A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES', 26) -A7XX_PERF_VPC_FE_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_FE_BOTTLENECK', 27) -A7XX_PERF_VPC_US_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_BUSY_CYCLES', 28) -A7XX_PERF_VPC_US_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_WORKING_CYCLES', 29) -A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE', 30) -A7XX_PERF_VPC_US_PTUS_FULL = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_PTUS_FULL', 31) -A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT', 32) -A7XX_PERF_VPC_US_STALL_CYCLES_VSC = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_VSC', 33) -A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE', 34) -A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_UCHE', 35) -A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION', 36) -A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', 37) -A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD', 38) -A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS', 39) -A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER', 40) -A7XX_PERF_VPC_US_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_US_BOTTLENECK', 41) -A7XX_PERF_VPC_RESERVED_42 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_42', 42) -A7XX_PERF_VPC_RESERVED_43 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_43', 43) -A7XX_PERF_VPC_RESERVED_44 = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_RESERVED_44', 44) -A7XX_PERF_VPC_BE_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_BUSY_CYCLES', 45) -A7XX_PERF_VPC_BE_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_WORKING_CYCLES', 46) -A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE', 47) -A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES', 48) -A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS', 49) -A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ', 50) -A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES', 51) -A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES', 52) -A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_RB', 53) -A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC', 54) -A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM', 55) -A7XX_PERF_VPC_BE_NUM_PA_REQ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_PA_REQ', 56) -A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', 57) -A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM', 58) -A7XX_PERF_VPC_BE_LM_TRANSACTION = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LM_TRANSACTION', 59) -A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_PS_BUSY_CYCLES', 60) -A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_PS_WORKING_CYCLES', 61) -A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE', 62) -A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE', 63) -A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END', 64) -A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL', 65) -A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ', 66) -A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK', 67) -A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS', 68) -A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR', 69) -A7XX_PERF_VPC_BE_BOTTLENECK = enum_a7xx_vpc_perfcounter_select.define('A7XX_PERF_VPC_BE_BOTTLENECK', 70) - -enum_a7xx_tse_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_TSE_NEVER_COUNT = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_NEVER_COUNT', 0) -A7XX_PERF_TSE_BE_BUSY_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BUSY_CYCLES', 1) -A7XX_PERF_TSE_BE_CLIPPING_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIPPING_CYCLES', 2) -A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_RAS', 3) -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE', 4) -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE', 5) -A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STARVE_CYCLES_PC', 6) -A7XX_PERF_TSE_BE_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_INPUT_PRIM', 7) -A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', 8) -A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM', 9) -A7XX_PERF_TSE_BE_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIPPED_PRIM', 10) -A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ZERO_AREA_PRIM', 11) -A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM', 12) -A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM', 13) -A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM', 14) -A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM', 15) -A7XX_PERF_TSE_BE_CINVOCATION = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CINVOCATION', 16) -A7XX_PERF_TSE_BE_CPRIMITIVES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CPRIMITIVES', 17) -A7XX_PERF_TSE_BE_2D_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_2D_INPUT_PRIM', 18) -A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES', 19) -A7XX_PERF_TSE_BE_CLIP_PLANES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_CLIP_PLANES', 20) -A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM', 21) -A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS', 22) -A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS', 23) -A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', 24) -A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM', 25) -A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_VP_OUT_IS_NAN', 26) -A7XX_PERF_TSE_BE_EXCLUDED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EXCLUDED_PRIM', 27) -A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM', 28) -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP', 29) -A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY', 30) -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP', 31) -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY', 32) -A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR', 33) -A7XX_PERF_TSE_FE_BUSY_CYCLES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BUSY_CYCLES', 34) -A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US', 35) -A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_STARVE_CYCLES_PC', 36) -A7XX_PERF_TSE_FE_INPUT_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_INPUT_PRIM', 37) -A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', 38) -A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM', 39) -A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ZERO_AREA_PRIM', 40) -A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM', 41) -A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', 42) -A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM', 43) -A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM', 44) -A7XX_PERF_TSE_FE_CINVOCATION = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CINVOCATION', 45) -A7XX_PERF_TSE_FE_CPRIMITIVES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CPRIMITIVES', 46) -A7XX_PERF_TSE_FE_CLIP_PLANES = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_CLIP_PLANES', 47) -A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM', 48) -A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS', 49) -A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS', 50) -A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS', 51) -A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM', 52) -A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_VP_OUT_IS_NAN', 53) -A7XX_PERF_TSE_FE_EXCLUDED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EXCLUDED_PRIM', 54) -A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM', 55) -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP', 56) -A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY', 57) -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP', 58) -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY', 59) -A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR', 60) -A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = enum_a7xx_tse_perfcounter_select.define('A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM', 61) - -enum_a7xx_ras_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_RAS_NEVER_COUNT = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_NEVER_COUNT', 0) -A7XX_PERF_RAS_BUSY_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_BUSY_CYCLES', 1) -A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES', 2) -A7XX_PERF_RAS_STALL_CYCLES_LRZ = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_STALL_CYCLES_LRZ', 3) -A7XX_PERF_RAS_STARVE_CYCLES_TSE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_STARVE_CYCLES_TSE', 4) -A7XX_PERF_RAS_SUPER_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPER_TILES', 5) -A7XX_PERF_RAS_8X4_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_8X4_TILES', 6) -A7XX_PERF_RAS_MASKGEN_ACTIVE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_MASKGEN_ACTIVE', 7) -A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES', 8) -A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES', 9) -A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_PRIM_KILLED_INVISILBE', 10) -A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 11) -A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES', 12) -A7XX_PERF_RAS_BLOCKS = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_BLOCKS', 13) -A7XX_PERF_RAS_FALSE_PARTIAL_STILE = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_FALSE_PARTIAL_STILE', 14) -A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY', 15) -A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SLICE_BLOCK_EMPTY', 16) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2', 17) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2', 18) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2', 19) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2', 20) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2', 21) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2', 22) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2', 23) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2', 24) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2', 25) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2', 26) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2', 27) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2', 28) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2', 29) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2', 30) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2', 31) -A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = enum_a7xx_ras_perfcounter_select.define('A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2', 32) - -enum_a7xx_uche_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_UCHE_NEVER_COUNT = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_NEVER_COUNT', 0) -A7XX_PERF_UCHE_BUSY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BUSY_CYCLES', 1) -A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STALL_CYCLES_ARBITER', 2) -A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA', 3) -A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP', 4) -A7XX_PERF_UCHE_STALL_CYCLES_DECMP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_STALL_CYCLES_DECMP', 5) -A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF', 6) -A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES', 7) -A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES', 8) -A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', 9) -A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES', 10) -A7XX_PERF_UCHE_READ_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_SP', 11) -A7XX_PERF_UCHE_READ_REQUESTS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP', 12) -A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC', 13) -A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF', 14) -A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM', 15) -A7XX_PERF_UCHE_READ_REQUESTS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD', 16) -A7XX_PERF_UCHE_READ_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VPC', 17) -A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_HLSQ', 18) -A7XX_PERF_UCHE_READ_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_LRZ', 19) -A7XX_PERF_UCHE_READ_REQUESTS_PC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_PC', 20) -A7XX_PERF_UCHE_WRITE_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_SP', 21) -A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ', 22) -A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_VPC', 23) -A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', 24) -A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_SP', 25) -A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_TP', 26) -A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD', 27) -A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC', 28) -A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ', 29) -A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ', 30) -A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_PC', 31) -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0', 32) -A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1', 33) -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0', 34) -A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1', 35) -A7XX_PERF_UCHE_GMEM_READ_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_GMEM_READ_BEATS', 36) -A7XX_PERF_UCHE_GMEM_WRITE_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_GMEM_WRITE_BEATS', 37) -A7XX_PERF_UCHE_UBWC_READ_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_UBWC_READ_BEATS', 38) -A7XX_PERF_UCHE_UBWC_WRITE_BEATS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_UBWC_WRITE_BEATS', 39) -A7XX_PERF_UCHE_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS', 40) -A7XX_PERF_UCHE_BANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ0', 41) -A7XX_PERF_UCHE_BANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ1', 42) -A7XX_PERF_UCHE_BANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ2', 43) -A7XX_PERF_UCHE_BANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ3', 44) -A7XX_PERF_UCHE_BANK_REQ4 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ4', 45) -A7XX_PERF_UCHE_BANK_REQ5 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ5', 46) -A7XX_PERF_UCHE_BANK_REQ6 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ6', 47) -A7XX_PERF_UCHE_BANK_REQ7 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_BANK_REQ7', 48) -A7XX_PERF_UCHE_TPH_REF_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_REF_FULL', 49) -A7XX_PERF_UCHE_TPH_VICTIM_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_VICTIM_FULL', 50) -A7XX_PERF_UCHE_TPH_EXT_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_EXT_FULL', 51) -A7XX_PERF_UCHE_RAM_READ_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RAM_READ_REQ', 52) -A7XX_PERF_UCHE_RAM_WRITE_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RAM_WRITE_REQ', 53) -A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS', 54) -A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS', 55) -A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE', 56) -A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER', 57) -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE', 58) -A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS', 59) -A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL', 60) -A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL', 61) -A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL', 62) -A7XX_PERF_UCHE_EVICTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS_SP', 63) -A7XX_PERF_UCHE_EVICTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_EVICTS_LRZ', 64) -A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VPCUS', 65) -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV', 66) -A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR', 67) -A7XX_PERF_BYPC_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_FULL', 68) -A7XX_PERF_BYPC_FULL_CCHE_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_FULL_CCHE_STALL', 69) -A7XX_PERF_BYPC_VHUB_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPC_VHUB_STALL', 70) -A7XX_PERF_BYPD_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPD_FULL', 71) -A7XX_PERF_BYPD_FULL_GBIF_STALL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_BYPD_FULL_GBIF_STALL', 72) -A7XX_PERF_VHUB_PTABLE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_VHUB_PTABLE_FULL', 73) -A7XX_PERF_DHUB_PTABLE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_DHUB_PTABLE_FULL', 74) -A7XX_PERF_UCHE_RESERVED_75 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_75', 75) -A7XX_PERF_UCHE_RESERVED_76 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_76', 76) -A7XX_PERF_UCHE_RESERVED_77 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_77', 77) -A7XX_PERF_UCHE_RESERVED_78 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_78', 78) -A7XX_PERF_UCHE_RESERVED_79 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_79', 79) -A7XX_PERF_UCHE_RESERVED_80 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_80', 80) -A7XX_PERF_UCHE_RESERVED_81 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_81', 81) -A7XX_PERF_UCHE_RESERVED_82 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_82', 82) -A7XX_PERF_UCHE_RESERVED_83 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_83', 83) -A7XX_PERF_UCHE_RESERVED_84 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_84', 84) -A7XX_PERF_UCHE_RESERVED_85 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_85', 85) -A7XX_PERF_UCHE_RESERVED_86 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_86', 86) -A7XX_PERF_UCHE_RESERVED_87 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_87', 87) -A7XX_PERF_UCHE_RESERVED_88 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_88', 88) -A7XX_PERF_UCHE_RESERVED_89 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_89', 89) -A7XX_PERF_UCHE_RESERVED_90 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_90', 90) -A7XX_PERF_UCHE_RESERVED_91 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_91', 91) -A7XX_PERF_UCHE_RESERVED_92 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_92', 92) -A7XX_PERF_UCHE_RESERVED_93 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_93', 93) -A7XX_PERF_UCHE_RESERVED_94 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_94', 94) -A7XX_PERF_UCHE_RESERVED_95 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_95', 95) -A7XX_PERF_UCHE_RESERVED_96 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_96', 96) -A7XX_PERF_UCHE_RESERVED_97 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_97', 97) -A7XX_PERF_UCHE_RESERVED_98 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_98', 98) -A7XX_PERF_UCHE_RESERVED_99 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_99', 99) -A7XX_PERF_UCHE_RESERVED_100 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_100', 100) -A7XX_PERF_UCHE_RESERVED_101 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_101', 101) -A7XX_PERF_UCHE_RESERVED_102 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_102', 102) -A7XX_PERF_UCHE_RESERVED_103 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_103', 103) -A7XX_PERF_UCHE_RESERVED_104 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_104', 104) -A7XX_PERF_UCHE_RESERVED_105 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_105', 105) -A7XX_PERF_UCHE_RESERVED_106 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_106', 106) -A7XX_PERF_UCHE_RESERVED_107 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_107', 107) -A7XX_PERF_UCHE_RESERVED_108 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_108', 108) -A7XX_PERF_UCHE_RESERVED_109 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_109', 109) -A7XX_PERF_UCHE_RESERVED_110 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_110', 110) -A7XX_PERF_UCHE_RESERVED_111 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_111', 111) -A7XX_PERF_UCHE_RESERVED_112 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_112', 112) -A7XX_PERF_UCHE_RESERVED_113 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_113', 113) -A7XX_PERF_UCHE_RESERVED_114 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_114', 114) -A7XX_PERF_UCHE_RESERVED_115 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_115', 115) -A7XX_PERF_UCHE_RESERVED_116 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_116', 116) -A7XX_PERF_UCHE_RESERVED_117 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_117', 117) -A7XX_PERF_UCHE_RESERVED_118 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_118', 118) -A7XX_PERF_UCHE_RESERVED_119 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_119', 119) -A7XX_PERF_UCHE_RESERVED_120 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_120', 120) -A7XX_PERF_UCHE_RESERVED_121 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_121', 121) -A7XX_PERF_UCHE_RESERVED_122 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_122', 122) -A7XX_PERF_UCHE_RESERVED_123 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_123', 123) -A7XX_PERF_UCHE_RESERVED_124 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_124', 124) -A7XX_PERF_UCHE_RESERVED_125 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_125', 125) -A7XX_PERF_UCHE_RESERVED_126 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_126', 126) -A7XX_PERF_UCHE_RESERVED_127 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_UCHE_RESERVED_127', 127) -A7XX_PERF_CCHE_BUSY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BUSY_CYCLES', 128) -A7XX_PERF_CCHE_STALL_CYCLES_UCHE = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_STALL_CYCLES_UCHE', 129) -A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA', 130) -A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES', 131) -A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES', 132) -A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL', 133) -A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC', 134) -A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF', 135) -A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM', 136) -A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL', 137) -A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC', 138) -A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF', 139) -A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM', 140) -A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL', 141) -A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM', 142) -A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF', 143) -A7XX_PERF_CCHE_READ_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_LRZ', 144) -A7XX_PERF_CCHE_READ_REQUESTS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_VPC', 145) -A7XX_PERF_CCHE_WRITE_REQUESTS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_SP', 146) -A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ', 147) -A7XX_PERF_CCHE_READ_REQUESTS_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_READ_REQUESTS_GMEM', 148) -A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM', 149) -A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_TP', 150) -A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD', 151) -A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_SP', 152) -A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC', 153) -A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ', 154) -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0', 155) -A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1', 156) -A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC', 157) -A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_TP', 158) -A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_SP', 159) -A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD', 160) -A7XX_PERF_CCHE_BANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ0', 161) -A7XX_PERF_CCHE_BANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ1', 162) -A7XX_PERF_CCHE_BANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ2', 163) -A7XX_PERF_CCHE_BANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ3', 164) -A7XX_PERF_CCHE_BANK_REQ4 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ4', 165) -A7XX_PERF_CCHE_BANK_REQ5 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ5', 166) -A7XX_PERF_CCHE_BANK_REQ6 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ6', 167) -A7XX_PERF_CCHE_BANK_REQ7 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ7', 168) -A7XX_PERF_CCHE_BANK_REQ8 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ8', 169) -A7XX_PERF_CCHE_BANK_REQ9 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ9', 170) -A7XX_PERF_CCHE_BANK_REQ10 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ10', 171) -A7XX_PERF_CCHE_BANK_REQ11 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ11', 172) -A7XX_PERF_CCHE_BANK_REQ12 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ12', 173) -A7XX_PERF_CCHE_BANK_REQ13 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ13', 174) -A7XX_PERF_CCHE_BANK_REQ14 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ14', 175) -A7XX_PERF_CCHE_BANK_REQ15 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_BANK_REQ15', 176) -A7XX_PERF_CCHE_GBANK_REQ0 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ0', 177) -A7XX_PERF_CCHE_GBANK_REQ1 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ1', 178) -A7XX_PERF_CCHE_GBANK_REQ2 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ2', 179) -A7XX_PERF_CCHE_GBANK_REQ3 = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GBANK_REQ3', 180) -A7XX_PERF_CCHE_TPH_REF_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_REF_FULL', 181) -A7XX_PERF_CCHE_TPH_VICTIM_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_VICTIM_FULL', 182) -A7XX_PERF_CCHE_TPH_EXT_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_EXT_FULL', 183) -A7XX_PERF_CCHE_RAM_READ_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_RAM_READ_REQ', 184) -A7XX_PERF_CCHE_RAM_WRITE_REQ = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_RAM_WRITE_REQ', 185) -A7XX_PERF_CCHE_TPH_CONFLICT_CL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_CONFLICT_CL', 186) -A7XX_PERF_CCHE_DBANK_CONFLICT = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_DBANK_CONFLICT', 187) -A7XX_PERF_CCHE_TPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_TPH_QUEUE_FULL', 188) -A7XX_PERF_CCHE_DPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_DPH_QUEUE_FULL', 189) -A7XX_PERF_CCHE_OPH_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_OPH_QUEUE_FULL', 190) -A7XX_PERF_CCHE_WACK_QUEUE_FULL = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_WACK_QUEUE_FULL', 191) -A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST', 192) -A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST', 193) -A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST', 194) -A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST', 195) -A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST', 196) -A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST', 197) -A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST', 198) -A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST', 199) -A7XX_PERF_CCHE_STALL_CYCLES_TP = enum_a7xx_uche_perfcounter_select.define('A7XX_PERF_CCHE_STALL_CYCLES_TP', 200) - -enum_a7xx_tp_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_TP_NEVER_COUNT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_NEVER_COUNT', 0) -A7XX_PERF_TP_BUSY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_BUSY_CYCLES', 1) -A7XX_PERF_TP_STALL_CYCLES_UCHE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STALL_CYCLES_UCHE', 2) -A7XX_PERF_TP_LATENCY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_CYCLES', 3) -A7XX_PERF_TP_LATENCY_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_TRANS', 4) -A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES', 5) -A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES', 6) -A7XX_PERF_TP_L1_CACHELINE_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_CACHELINE_REQUESTS', 7) -A7XX_PERF_TP_L1_CACHELINE_MISSES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_CACHELINE_MISSES', 8) -A7XX_PERF_TP_SP_TP_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_SP_TP_TRANS', 9) -A7XX_PERF_TP_TP_SP_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_TP_SP_TRANS', 10) -A7XX_PERF_TP_OUTPUT_PIXELS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS', 11) -A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_WORKLOAD_16BIT', 12) -A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_WORKLOAD_32BIT', 13) -A7XX_PERF_TP_QUADS_RECEIVED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_RECEIVED', 14) -A7XX_PERF_TP_QUADS_OFFSET = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_OFFSET', 15) -A7XX_PERF_TP_QUADS_SHADOW = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_SHADOW', 16) -A7XX_PERF_TP_QUADS_ARRAY = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_ARRAY', 17) -A7XX_PERF_TP_QUADS_GRADIENT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_GRADIENT', 18) -A7XX_PERF_TP_QUADS_1D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_1D', 19) -A7XX_PERF_TP_QUADS_2D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_2D', 20) -A7XX_PERF_TP_QUADS_BUFFER = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_BUFFER', 21) -A7XX_PERF_TP_QUADS_3D = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_3D', 22) -A7XX_PERF_TP_QUADS_CUBE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_CUBE', 23) -A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED', 24) -A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', 25) -A7XX_PERF_TP_OUTPUT_PIXELS_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_POINT', 26) -A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR', 27) -A7XX_PERF_TP_OUTPUT_PIXELS_MIP = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_MIP', 28) -A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_ANISO', 29) -A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD', 30) -A7XX_PERF_TP_FLAG_CACHE_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_CACHE_REQUESTS', 31) -A7XX_PERF_TP_FLAG_CACHE_MISSES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FLAG_CACHE_MISSES', 32) -A7XX_PERF_TP_L1_5_L2_REQUESTS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_L2_REQUESTS', 33) -A7XX_PERF_TP_2D_OUTPUT_PIXELS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS', 34) -A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT', 35) -A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR', 36) -A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT', 37) -A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT', 38) -A7XX_PERF_TP_TPA2TPC_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_TPA2TPC_TRANS', 39) -A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_1TILE', 40) -A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_2TILE', 41) -A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_MISSES_ASTC_4TILE', 42) -A7XX_PERF_TP_L1_5_COMPRESS_REQS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_COMPRESS_REQS', 43) -A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS', 44) -A7XX_PERF_TP_L1_BANK_CONFLICT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_BANK_CONFLICT', 45) -A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES', 46) -A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS', 47) -A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED', 48) -A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FRONTEND_WORKING_CYCLES', 49) -A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_TAG_WORKING_CYCLES', 50) -A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES', 51) -A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES', 52) -A7XX_PERF_TP_BACKEND_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_BACKEND_WORKING_CYCLES', 53) -A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES', 54) -A7XX_PERF_TP_STARVE_CYCLES_SP = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STARVE_CYCLES_SP', 55) -A7XX_PERF_TP_STARVE_CYCLES_UCHE = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STARVE_CYCLES_UCHE', 56) -A7XX_PERF_TP_STALL_CYCLES_UFC = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_STALL_CYCLES_UFC', 57) -A7XX_PERF_TP_FORMAT_DECOMP_POINT = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FORMAT_DECOMP_POINT', 58) -A7XX_PERF_TP_FILTER_POINT_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_POINT_FP16', 59) -A7XX_PERF_TP_FILTER_POINT_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FILTER_POINT_FP32', 60) -A7XX_PERF_TP_LATENCY_FIFO_FULL = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_LATENCY_FIFO_FULL', 61) -A7XX_PERF_TP_RESERVED_62 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_62', 62) -A7XX_PERF_TP_RESERVED_63 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_63', 63) -A7XX_PERF_TP_RESERVED_64 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_64', 64) -A7XX_PERF_TP_RESERVED_65 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_65', 65) -A7XX_PERF_TP_RESERVED_66 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_66', 66) -A7XX_PERF_TP_RESERVED_67 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_67', 67) -A7XX_PERF_TP_RESERVED_68 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_68', 68) -A7XX_PERF_TP_RESERVED_69 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_69', 69) -A7XX_PERF_TP_RESERVED_70 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_70', 70) -A7XX_PERF_TP_RESERVED_71 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_71', 71) -A7XX_PERF_TP_RESERVED_72 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_72', 72) -A7XX_PERF_TP_RESERVED_73 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_73', 73) -A7XX_PERF_TP_RESERVED_74 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_74', 74) -A7XX_PERF_TP_RESERVED_75 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_75', 75) -A7XX_PERF_TP_RESERVED_76 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_76', 76) -A7XX_PERF_TP_RESERVED_77 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_77', 77) -A7XX_PERF_TP_RESERVED_78 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_78', 78) -A7XX_PERF_TP_RESERVED_79 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_79', 79) -A7XX_PERF_TP_RESERVED_80 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_80', 80) -A7XX_PERF_TP_RESERVED_81 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_81', 81) -A7XX_PERF_TP_RESERVED_82 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_82', 82) -A7XX_PERF_TP_RESERVED_83 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_83', 83) -A7XX_PERF_TP_RESERVED_84 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_84', 84) -A7XX_PERF_TP_RESERVED_85 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_85', 85) -A7XX_PERF_TP_RESERVED_86 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_86', 86) -A7XX_PERF_TP_RESERVED_87 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_87', 87) -A7XX_PERF_TP_RESERVED_88 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_88', 88) -A7XX_PERF_TP_RESERVED_89 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_89', 89) -A7XX_PERF_TP_RESERVED_90 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_90', 90) -A7XX_PERF_TP_RESERVED_91 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_91', 91) -A7XX_PERF_TP_RESERVED_92 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_92', 92) -A7XX_PERF_TP_RESERVED_93 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_93', 93) -A7XX_PERF_TP_RESERVED_94 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_94', 94) -A7XX_PERF_TP_RESERVED_95 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_95', 95) -A7XX_PERF_TP_RESERVED_96 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_96', 96) -A7XX_PERF_TP_RESERVED_97 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_97', 97) -A7XX_PERF_TP_RESERVED_98 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_98', 98) -A7XX_PERF_TP_RESERVED_99 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_99', 99) -A7XX_PERF_TP_RESERVED_100 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_100', 100) -A7XX_PERF_TP_RESERVED_101 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_101', 101) -A7XX_PERF_TP_RESERVED_102 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_102', 102) -A7XX_PERF_TP_RESERVED_103 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_103', 103) -A7XX_PERF_TP_RESERVED_104 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_104', 104) -A7XX_PERF_TP_RESERVED_105 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_105', 105) -A7XX_PERF_TP_RESERVED_106 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_106', 106) -A7XX_PERF_TP_RESERVED_107 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_107', 107) -A7XX_PERF_TP_RESERVED_108 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_108', 108) -A7XX_PERF_TP_RESERVED_109 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_109', 109) -A7XX_PERF_TP_RESERVED_110 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_110', 110) -A7XX_PERF_TP_RESERVED_111 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_111', 111) -A7XX_PERF_TP_RESERVED_112 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_112', 112) -A7XX_PERF_TP_RESERVED_113 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_113', 113) -A7XX_PERF_TP_RESERVED_114 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_114', 114) -A7XX_PERF_TP_RESERVED_115 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_115', 115) -A7XX_PERF_TP_RESERVED_116 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_116', 116) -A7XX_PERF_TP_RESERVED_117 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_117', 117) -A7XX_PERF_TP_RESERVED_118 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_118', 118) -A7XX_PERF_TP_RESERVED_119 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_119', 119) -A7XX_PERF_TP_RESERVED_120 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_120', 120) -A7XX_PERF_TP_RESERVED_121 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_121', 121) -A7XX_PERF_TP_RESERVED_122 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_122', 122) -A7XX_PERF_TP_RESERVED_123 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_123', 123) -A7XX_PERF_TP_RESERVED_124 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_124', 124) -A7XX_PERF_TP_RESERVED_125 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_125', 125) -A7XX_PERF_TP_RESERVED_126 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_126', 126) -A7XX_PERF_TP_RESERVED_127 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_RESERVED_127', 127) -A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR', 128) -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16', 129) -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16', 130) -A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32', 131) -A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = enum_a7xx_tp_perfcounter_select.define('A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32', 132) - -enum_a7xx_sp_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_SP_NEVER_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NEVER_COUNT', 0) -A7XX_PERF_SP_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BUSY_CYCLES', 1) -A7XX_PERF_SP_ALU_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_WORKING_CYCLES', 2) -A7XX_PERF_SP_STALL_CYCLES_VPC_BE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_VPC_BE', 3) -A7XX_PERF_SP_STALL_CYCLES_TP = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_TP', 4) -A7XX_PERF_SP_STALL_CYCLES_UCHE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_UCHE', 5) -A7XX_PERF_SP_STALL_CYCLES_RB = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STALL_CYCLES_RB', 6) -A7XX_PERF_SP_NON_EXECUTION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NON_EXECUTION_CYCLES', 7) -A7XX_PERF_SP_WAVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CONTEXTS', 8) -A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CONTEXT_CYCLES', 9) -A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES', 10) -A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES', 11) -A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES', 12) -A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES', 13) -A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES', 14) -A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES', 15) -A7XX_PERF_SP_WAVE_CTRL_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CTRL_CYCLES', 16) -A7XX_PERF_SP_WAVE_LOAD_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_LOAD_CYCLES', 17) -A7XX_PERF_SP_WAVE_EMIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_EMIT_CYCLES', 18) -A7XX_PERF_SP_WAVE_NOP_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_NOP_CYCLES', 19) -A7XX_PERF_SP_WAVE_WAIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_WAIT_CYCLES', 20) -A7XX_PERF_SP_WAVE_FETCH_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_FETCH_CYCLES', 21) -A7XX_PERF_SP_WAVE_IDLE_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_IDLE_CYCLES', 22) -A7XX_PERF_SP_WAVE_END_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_END_CYCLES', 23) -A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES', 24) -A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES', 25) -A7XX_PERF_SP_WAVE_JOIN_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_JOIN_CYCLES', 26) -A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS', 27) -A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_STORE_INSTRUCTIONS', 28) -A7XX_PERF_SP_LM_ATOMICS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_ATOMICS', 29) -A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS', 30) -A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', 31) -A7XX_PERF_SP_GM_ATOMICS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_ATOMICS', 32) -A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS', 33) -A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS', 34) -A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS', 35) -A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS', 36) -A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS', 37) -A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS', 38) -A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS', 39) -A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS', 40) -A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS', 41) -A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS', 42) -A7XX_PERF_SP_VS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_INSTRUCTIONS', 43) -A7XX_PERF_SP_FS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_INSTRUCTIONS', 44) -A7XX_PERF_SP_ADDR_LOCK_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ADDR_LOCK_COUNT', 45) -A7XX_PERF_SP_UCHE_READ_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_UCHE_READ_TRANS', 46) -A7XX_PERF_SP_UCHE_WRITE_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_UCHE_WRITE_TRANS', 47) -A7XX_PERF_SP_EXPORT_VPC_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXPORT_VPC_TRANS', 48) -A7XX_PERF_SP_EXPORT_RB_TRANS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXPORT_RB_TRANS', 49) -A7XX_PERF_SP_PIXELS_KILLED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PIXELS_KILLED', 50) -A7XX_PERF_SP_ICL1_REQUESTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_REQUESTS', 51) -A7XX_PERF_SP_ICL1_MISSES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_MISSES', 52) -A7XX_PERF_SP_HS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HS_INSTRUCTIONS', 53) -A7XX_PERF_SP_DS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_DS_INSTRUCTIONS', 54) -A7XX_PERF_SP_GS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GS_INSTRUCTIONS', 55) -A7XX_PERF_SP_CS_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CS_INSTRUCTIONS', 56) -A7XX_PERF_SP_GPR_READ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ', 57) -A7XX_PERF_SP_GPR_WRITE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE', 58) -A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS', 59) -A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS', 60) -A7XX_PERF_SP_LM_BANK_CONFLICTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_BANK_CONFLICTS', 61) -A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES', 62) -A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES', 63) -A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES', 64) -A7XX_PERF_SP_LM_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_WORKING_CYCLES', 65) -A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES', 66) -A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES', 67) -A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP', 68) -A7XX_PERF_SP_STARVE_CYCLES_HLSQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STARVE_CYCLES_HLSQ', 69) -A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES', 70) -A7XX_PERF_SP_WORKING_EU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU', 71) -A7XX_PERF_SP_ANY_EU_WORKING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING', 72) -A7XX_PERF_SP_WORKING_EU_FS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_FS_STAGE', 73) -A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE', 74) -A7XX_PERF_SP_WORKING_EU_VS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_VS_STAGE', 75) -A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE', 76) -A7XX_PERF_SP_WORKING_EU_CS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WORKING_EU_CS_STAGE', 77) -A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE', 78) -A7XX_PERF_SP_GPR_READ_PREFETCH = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_PREFETCH', 79) -A7XX_PERF_SP_GPR_READ_CONFLICT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_CONFLICT', 80) -A7XX_PERF_SP_GPR_WRITE_CONFLICT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE_CONFLICT', 81) -A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES', 82) -A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES', 83) -A7XX_PERF_SP_EXECUTABLE_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EXECUTABLE_WAVES', 84) -A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES', 85) -A7XX_PERF_SP_RESERVED_86 = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RESERVED_86', 86) -A7XX_PERF_SP_BYPASS_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BYPASS_BUSY_CYCLES', 87) -A7XX_PERF_SP_ANY_EU_WORKING_LPAC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ANY_EU_WORKING_LPAC', 88) -A7XX_PERF_SP_WAVE_ALU_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_ALU_CYCLES', 89) -A7XX_PERF_SP_WAVE_EFU_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_EFU_CYCLES', 90) -A7XX_PERF_SP_WAVE_INT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_INT_CYCLES', 91) -A7XX_PERF_SP_WAVE_CSP_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_CSP_CYCLES', 92) -A7XX_PERF_SP_EWAVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EWAVE_CONTEXTS', 93) -A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES', 94) -A7XX_PERF_SP_LPAC_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_BUSY_CYCLES', 95) -A7XX_PERF_SP_LPAC_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_INSTRUCTIONS', 96) -A7XX_PERF_SP_FS_STAGE_1X_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_1X_WAVES', 97) -A7XX_PERF_SP_FS_STAGE_2X_WAVES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_2X_WAVES', 98) -A7XX_PERF_SP_QUADS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_QUADS', 99) -A7XX_PERF_SP_CS_INVOCATIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CS_INVOCATIONS', 100) -A7XX_PERF_SP_PIXELS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PIXELS', 101) -A7XX_PERF_SP_LPAC_DRAWCALLS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_DRAWCALLS', 102) -A7XX_PERF_SP_PI_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PI_WORKING_CYCLES', 103) -A7XX_PERF_SP_WAVE_INPUT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_INPUT_CYCLES', 104) -A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_OUTPUT_CYCLES', 105) -A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES', 106) -A7XX_PERF_SP_WAVE_HWAVE_SYNC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_HWAVE_SYNC', 107) -A7XX_PERF_SP_OUTPUT_3D_PIXELS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_OUTPUT_3D_PIXELS', 108) -A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS', 109) -A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS', 110) -A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS', 111) -A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS', 112) -A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS', 113) -A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS', 114) -A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS', 115) -A7XX_PERF_SP_ALU_GPR_READ_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_GPR_READ_CYCLES', 116) -A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES', 117) -A7XX_PERF_SP_LM_FULL_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LM_FULL_CYCLES', 118) -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES', 119) -A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES', 120) -A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION', 121) -A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS', 122) -A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', 123) -A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RBRT_KICKOFF_DQUADS', 124) -A7XX_PERF_SP_RTU_BUSY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BUSY_CYCLES', 125) -A7XX_PERF_SP_RTU_L0_HITS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_HITS', 126) -A7XX_PERF_SP_RTU_L0_MISSES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_MISSES', 127) -A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_L0_HIT_ON_MISS', 128) -A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE', 129) -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE', 130) -A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE', 131) -A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE', 132) -A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA', 133) -A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT', 134) -A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT', 135) -A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE', 136) -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0', 137) -A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO', 138) -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES', 139) -A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES', 140) -A7XX_PERF_SP_STCHE_MISS_INC_VS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_VS', 141) -A7XX_PERF_SP_STCHE_MISS_INC_FS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_FS', 142) -A7XX_PERF_SP_STCHE_MISS_INC_BV = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_BV', 143) -A7XX_PERF_SP_STCHE_MISS_INC_LPAC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_STCHE_MISS_INC_LPAC', 144) -A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS', 145) -A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', 146) -A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS', 147) -A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS', 148) -A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS', 149) -A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_SCH_STALL_CYCLES_RTU', 150) -A7XX_PERF_SP_EFU_WORKING_CYCLES = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_EFU_WORKING_CYCLES', 151) -A7XX_PERF_SP_BRANCH_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_TAKEN', 152) -A7XX_PERF_SP_BRANCH_NOT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_NOT_TAKEN', 153) -A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT', 154) -A7XX_PERF_SP_BRANCH_INS_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_BRANCH_INS_COUNT', 155) -A7XX_PERF_SP_PREDICT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_TAKEN', 156) -A7XX_PERF_SP_PREDICT_NOT_TAKEN = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_NOT_TAKEN', 157) -A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT', 158) -A7XX_PERF_SP_PREDICT_INS_COUNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_PREDICT_INS_COUNT', 159) -A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', 160) -A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD', 161) -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ', 162) -A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD', 163) -A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ', 164) -A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD', 165) -A7XX_PERF_SP_LB_READ_XFER_ALU = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_READ_XFER_ALU', 166) -A7XX_PERF_SP_LB_ALU_READ_CONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_ALU_READ_CONS', 167) -A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER', 168) -A7XX_PERF_SP_LB_WRITE_XFER_VPC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_WRITE_XFER_VPC', 169) -A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER', 170) -A7XX_PERF_SP_LB_LDST_RW_LM = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_RW_LM', 171) -A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED', 172) -A7XX_PERF_SP_LB_LDST_WRITE_CONS = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_WRITE_CONS', 173) -A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED', 174) -A7XX_PERF_SP_GPR_READ_BANK = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_READ_BANK', 175) -A7XX_PERF_SP_GPR_WRITE_BANK = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_GPR_WRITE_BANK', 176) -A7XX_PERF_SP_VS_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_VS_WAVE_REQ_PENDING', 177) -A7XX_PERF_SP_FS_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_WAVE_REQ_PENDING', 178) -A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', 179) -A7XX_PERF_SP_WAVE_SPLIT_CNT = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_WAVE_SPLIT_CNT', 180) -A7XX_PERF_SP_FS_OOO_WAVE_ACC = enum_a7xx_sp_perfcounter_select.define('A7XX_PERF_SP_FS_OOO_WAVE_ACC', 181) - -enum_a7xx_rb_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_RB_NEVER_COUNT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_NEVER_COUNT', 0) -A7XX_PERF_RB_BUSY_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BUSY_CYCLES', 1) -A7XX_PERF_RB_STALL_CYCLES_HLSQ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_HLSQ', 2) -A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL', 3) -A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL', 4) -A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL', 5) -A7XX_PERF_RB_STARVE_CYCLES_SP = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_SP', 6) -A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE', 7) -A7XX_PERF_RB_STARVE_CYCLES_CCU = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_CCU', 8) -A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', 9) -A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE', 10) -A7XX_PERF_RB_Z_WORKLOAD = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_WORKLOAD', 11) -A7XX_PERF_RB_HLSQ_ACTIVE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_HLSQ_ACTIVE', 12) -A7XX_PERF_RB_Z_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_READ', 13) -A7XX_PERF_RB_Z_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_WRITE', 14) -A7XX_PERF_RB_C_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_C_READ', 15) -A7XX_PERF_RB_C_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_C_WRITE', 16) -A7XX_PERF_RB_TOTAL_PASS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_TOTAL_PASS', 17) -A7XX_PERF_RB_Z_PASS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_PASS', 18) -A7XX_PERF_RB_Z_FAIL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_Z_FAIL', 19) -A7XX_PERF_RB_S_FAIL = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_S_FAIL', 20) -A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FXP_COMPONENTS', 21) -A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FP16_COMPONENTS', 22) -A7XX_PERF_RB_PS_INVOCATIONS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_PS_INVOCATIONS', 23) -A7XX_PERF_RB_2D_ALIVE_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_ALIVE_CYCLES', 24) -A7XX_PERF_RB_2D_STARVE_CYCLES_SP = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_STARVE_CYCLES_SP', 25) -A7XX_PERF_RB_2D_VALID_PIXELS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_2D_VALID_PIXELS', 26) -A7XX_PERF_RB_3D_PIXELS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_3D_PIXELS', 27) -A7XX_PERF_RB_BLENDER_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDER_WORKING_CYCLES', 28) -A7XX_PERF_RB_ZPROC_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_ZPROC_WORKING_CYCLES', 29) -A7XX_PERF_RB_CPROC_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_CPROC_WORKING_CYCLES', 30) -A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_SAMPLER_WORKING_CYCLES', 31) -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ', 32) -A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE', 33) -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ', 34) -A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE', 35) -A7XX_PERF_RB_STALL_CYCLES_VPC_BE = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_VPC_BE', 36) -A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_BLENDED_FP32_COMPONENTS', 37) -A7XX_PERF_RB_COLOR_PIX_TILES = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_COLOR_PIX_TILES', 38) -A7XX_PERF_RB_STALL_CYCLES_CCU = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_STALL_CYCLES_CCU', 39) -A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_EARLY_Z_ARB3_GRANT', 40) -A7XX_PERF_RB_LATE_Z_ARB3_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_LATE_Z_ARB3_GRANT', 41) -A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', 42) -A7XX_PERF_RB_VRS_1X1_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_1X1_QUADS', 43) -A7XX_PERF_RB_VRS_2X1_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X1_QUADS', 44) -A7XX_PERF_RB_VRS_1X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_1X2_QUADS', 45) -A7XX_PERF_RB_VRS_2X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X2_QUADS', 46) -A7XX_PERF_RB_VRS_2X4_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_2X4_QUADS', 47) -A7XX_PERF_RB_VRS_4X2_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_4X2_QUADS', 48) -A7XX_PERF_RB_VRS_4X4_QUADS = enum_a7xx_rb_perfcounter_select.define('A7XX_PERF_RB_VRS_4X4_QUADS', 49) - -enum_a7xx_vsc_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_VSC_NEVER_COUNT = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_NEVER_COUNT', 0) -A7XX_PERF_VSC_BUSY_CYCLES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_BUSY_CYCLES', 1) -A7XX_PERF_VSC_WORKING_CYCLES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_WORKING_CYCLES', 2) -A7XX_PERF_VSC_STALL_CYCLES_UCHE = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_STALL_CYCLES_UCHE', 3) -A7XX_PERF_VSC_EOT_NUM = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_EOT_NUM', 4) -A7XX_PERF_VSC_INPUT_TILES = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_INPUT_TILES', 5) -A7XX_PERF_VSC_TILE_COMP_TRAN = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_TILE_COMP_TRAN', 6) -A7XX_PERF_VSC_TILE_BYPASS_TRAN = enum_a7xx_vsc_perfcounter_select.define('A7XX_PERF_VSC_TILE_BYPASS_TRAN', 7) - -enum_a7xx_ccu_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_CCU_NEVER_COUNT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_NEVER_COUNT', 0) -A7XX_PERF_CCU_BUSY_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_BUSY_CYCLES', 1) -A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN', 2) -A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN', 3) -A7XX_PERF_CCU_DEPTH_BLOCKS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_BLOCKS', 4) -A7XX_PERF_CCU_COLOR_BLOCKS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_BLOCKS', 5) -A7XX_PERF_CCU_DEPTH_BLOCK_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_BLOCK_HIT', 6) -A7XX_PERF_CCU_COLOR_BLOCK_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_BLOCK_HIT', 7) -A7XX_PERF_CCU_PARTIAL_BLOCK_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_PARTIAL_BLOCK_READ', 8) -A7XX_PERF_CCU_GMEM_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_READ', 9) -A7XX_PERF_CCU_GMEM_WRITE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_WRITE', 10) -A7XX_PERF_CCU_2D_RD_REQ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_2D_RD_REQ', 11) -A7XX_PERF_CCU_2D_WR_REQ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_2D_WR_REQ', 12) -A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT', 13) -A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT', 14) -A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED', 15) -A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED', 16) -A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT', 17) -A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT', 18) -A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER', 19) -A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER', 20) -A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', 21) -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_COLOR_READ_4AA', 22) -A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL', 23) -A7XX_PERF_CCU_COLOR_EVB_STALL = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_COLOR_EVB_STALL', 24) -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C', 25) -A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z', 26) -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C', 27) -A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z', 28) -A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES', 29) -A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE', 30) -A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE', 31) -A7XX_PERF_CCU_RESERVED_32 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_32', 32) -A7XX_PERF_CCU_RESERVED_33 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_33', 33) -A7XX_PERF_CCU_RESERVED_34 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_34', 34) -A7XX_PERF_CCU_RESERVED_35 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_35', 35) -A7XX_PERF_CCU_RESERVED_36 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_36', 36) -A7XX_PERF_CCU_RESERVED_37 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_37', 37) -A7XX_PERF_CCU_RESERVED_38 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_38', 38) -A7XX_PERF_CCU_RESERVED_39 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_39', 39) -A7XX_PERF_CCU_RESERVED_40 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_40', 40) -A7XX_PERF_CCU_RESERVED_41 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_41', 41) -A7XX_PERF_CCU_RESERVED_42 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_42', 42) -A7XX_PERF_CCU_RESERVED_43 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_43', 43) -A7XX_PERF_CCU_RESERVED_44 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_44', 44) -A7XX_PERF_CCU_RESERVED_45 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_45', 45) -A7XX_PERF_CCU_RESERVED_46 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_46', 46) -A7XX_PERF_CCU_RESERVED_47 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_47', 47) -A7XX_PERF_CCU_RESERVED_48 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_48', 48) -A7XX_PERF_CCU_RESERVED_49 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_49', 49) -A7XX_PERF_CCU_RESERVED_50 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_50', 50) -A7XX_PERF_CCU_RESERVED_51 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_51', 51) -A7XX_PERF_CCU_RESERVED_52 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_52', 52) -A7XX_PERF_CCU_RESERVED_53 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_53', 53) -A7XX_PERF_CCU_RESERVED_54 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_54', 54) -A7XX_PERF_CCU_RESERVED_55 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_55', 55) -A7XX_PERF_CCU_RESERVED_56 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_56', 56) -A7XX_PERF_CCU_RESERVED_57 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_57', 57) -A7XX_PERF_CCU_RESERVED_58 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_58', 58) -A7XX_PERF_CCU_RESERVED_59 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_59', 59) -A7XX_PERF_CCU_RESERVED_60 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_60', 60) -A7XX_PERF_CCU_RESERVED_61 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_61', 61) -A7XX_PERF_CCU_RESERVED_62 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_62', 62) -A7XX_PERF_CCU_RESERVED_63 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_63', 63) -A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_REQUESTS', 64) -A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS', 65) -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY', 66) -A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY', 67) -A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR', 68) -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0', 69) -A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1', 70) -A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP', 71) -A7XX_PERF_UFC_L0_SP_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_REQUESTS', 72) -A7XX_PERF_UFC_L0_SP_FILTER_HIT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_FILTER_HIT', 73) -A7XX_PERF_UFC_L0_SP_FILTER_MISS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_FILTER_MISS', 74) -A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES', 75) -A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES', 76) -A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES', 77) -A7XX_PERF_CCU_RESERVED_78 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_78', 78) -A7XX_PERF_CCU_RESERVED_79 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_79', 79) -A7XX_PERF_CCU_RESERVED_80 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_80', 80) -A7XX_PERF_CCU_RESERVED_81 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_81', 81) -A7XX_PERF_CCU_RESERVED_82 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_82', 82) -A7XX_PERF_CCU_RESERVED_83 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_83', 83) -A7XX_PERF_CCU_RESERVED_84 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_84', 84) -A7XX_PERF_CCU_RESERVED_85 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_85', 85) -A7XX_PERF_CCU_RESERVED_86 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_86', 86) -A7XX_PERF_CCU_RESERVED_87 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_87', 87) -A7XX_PERF_CCU_RESERVED_88 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_88', 88) -A7XX_PERF_CCU_RESERVED_89 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_89', 89) -A7XX_PERF_CCU_RESERVED_90 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_90', 90) -A7XX_PERF_CCU_RESERVED_91 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_91', 91) -A7XX_PERF_CCU_RESERVED_92 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_92', 92) -A7XX_PERF_CCU_RESERVED_93 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_93', 93) -A7XX_PERF_CCU_RESERVED_94 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_94', 94) -A7XX_PERF_CCU_RESERVED_95 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_95', 95) -A7XX_PERF_CCU_RESERVED_96 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_96', 96) -A7XX_PERF_CCU_RESERVED_97 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_97', 97) -A7XX_PERF_CCU_RESERVED_98 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_98', 98) -A7XX_PERF_CCU_RESERVED_99 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_99', 99) -A7XX_PERF_CCU_RESERVED_100 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_100', 100) -A7XX_PERF_CCU_RESERVED_101 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_101', 101) -A7XX_PERF_CCU_RESERVED_102 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_102', 102) -A7XX_PERF_CCU_RESERVED_103 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_103', 103) -A7XX_PERF_CCU_RESERVED_104 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_104', 104) -A7XX_PERF_CCU_RESERVED_105 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_105', 105) -A7XX_PERF_CCU_RESERVED_106 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_106', 106) -A7XX_PERF_CCU_RESERVED_107 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_107', 107) -A7XX_PERF_CCU_RESERVED_108 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_108', 108) -A7XX_PERF_CCU_RESERVED_109 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_109', 109) -A7XX_PERF_CCU_RESERVED_110 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_110', 110) -A7XX_PERF_CCU_RESERVED_111 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_111', 111) -A7XX_PERF_CCU_RESERVED_112 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_112', 112) -A7XX_PERF_CCU_RESERVED_113 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_113', 113) -A7XX_PERF_CCU_RESERVED_114 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_114', 114) -A7XX_PERF_CCU_RESERVED_115 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_115', 115) -A7XX_PERF_CCU_RESERVED_116 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_116', 116) -A7XX_PERF_CCU_RESERVED_117 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_117', 117) -A7XX_PERF_CCU_RESERVED_118 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_118', 118) -A7XX_PERF_CCU_RESERVED_119 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_119', 119) -A7XX_PERF_CCU_RESERVED_120 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_120', 120) -A7XX_PERF_CCU_RESERVED_121 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_121', 121) -A7XX_PERF_CCU_RESERVED_122 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_122', 122) -A7XX_PERF_CCU_RESERVED_123 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_123', 123) -A7XX_PERF_CCU_RESERVED_124 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_124', 124) -A7XX_PERF_CCU_RESERVED_125 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_125', 125) -A7XX_PERF_CCU_RESERVED_126 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_126', 126) -A7XX_PERF_CCU_RESERVED_127 = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CCU_RESERVED_127', 127) -A7XX_PERF_CRE_RESOLVE_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_EVENTS', 128) -A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS', 129) -A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS', 130) -A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT', 131) -A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT', 132) -A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS', 133) -A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS', 134) -A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS', 135) -A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = enum_a7xx_ccu_perfcounter_select.define('A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS', 136) - -enum_a7xx_lrz_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_LRZ_NEVER_COUNT = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_NEVER_COUNT', 0) -A7XX_PERF_LRZ_BUSY_CYCLES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_BUSY_CYCLES', 1) -A7XX_PERF_LRZ_STARVE_CYCLES_RAS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STARVE_CYCLES_RAS', 2) -A7XX_PERF_LRZ_STALL_CYCLES_RB = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB', 3) -A7XX_PERF_LRZ_STALL_CYCLES_VSC = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_VSC', 4) -A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE', 5) -A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR', 6) -A7XX_PERF_LRZ_STALL_CYCLES_UCHE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_UCHE', 7) -A7XX_PERF_LRZ_LRZ_READ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_LRZ_READ', 8) -A7XX_PERF_LRZ_LRZ_WRITE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_LRZ_WRITE', 9) -A7XX_PERF_LRZ_READ_LATENCY = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_READ_LATENCY', 10) -A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_MERGE_CACHE_UPDATING', 11) -A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN', 12) -A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ', 13) -A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 14) -A7XX_PERF_LRZ_FULL_8X8_TILES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FULL_8X8_TILES', 15) -A7XX_PERF_LRZ_PARTIAL_8X8_TILES = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_PARTIAL_8X8_TILES', 16) -A7XX_PERF_LRZ_TILE_KILLED = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED', 17) -A7XX_PERF_LRZ_TOTAL_PIXEL = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TOTAL_PIXEL', 18) -A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ', 19) -A7XX_PERF_LRZ_FEEDBACK_ACCEPT = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_ACCEPT', 20) -A7XX_PERF_LRZ_FEEDBACK_DISCARD = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_DISCARD', 21) -A7XX_PERF_LRZ_FEEDBACK_STALL = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_FEEDBACK_STALL', 22) -A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 23) -A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE', 24) -A7XX_PERF_LRZ_RAS_MASK_TRANS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_RAS_MASK_TRANS', 25) -A7XX_PERF_LRZ_STALL_CYCLES_MVC = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_MVC', 26) -A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS', 27) -A7XX_PERF_LRZ_TILE_KILLED_BY_Z = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_TILE_KILLED_BY_Z', 28) -A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH', 29) -A7XX_PERF_LRZ_NUM_FLOCK = enum_a7xx_lrz_perfcounter_select.define('A7XX_PERF_LRZ_NUM_FLOCK', 30) - -enum_a7xx_cmp_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_CMPDECMP_NEVER_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_NEVER_COUNT', 0) -A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB', 1) -A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES', 2) -A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES', 3) -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU', 4) -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU', 5) -A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST', 6) -A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST', 7) -A7XX_PERF_CMPDECMP_VBIF_READ_DATA = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA', 8) -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA', 9) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT', 10) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT', 11) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT', 12) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT', 13) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT', 14) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT', 15) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT', 16) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT', 17) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT', 18) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT', 19) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT', 20) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT', 21) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT', 22) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT', 23) -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0', 24) -A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1', 25) -A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE', 26) -A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT', 27) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT', 28) -A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT', 29) -A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_CDP_FILTER_HIT', 30) -A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_CDP_FILTER_MISS', 31) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT', 32) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT', 33) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT', 34) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT', 35) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT', 36) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT', 37) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT', 38) -A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT', 39) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT', 40) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT', 41) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT', 42) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT', 43) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT', 44) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT', 45) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT', 46) -A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = enum_a7xx_cmp_perfcounter_select.define('A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT', 47) - -enum_a7xx_gbif_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_GBIF_NEVER_COUNT = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_NEVER_COUNT', 0) -A7XX_PERF_GBIF_RESERVED_1 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_1', 1) -A7XX_PERF_GBIF_RESERVED_2 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_2', 2) -A7XX_PERF_GBIF_RESERVED_3 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_3', 3) -A7XX_PERF_GBIF_RESERVED_4 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_4', 4) -A7XX_PERF_GBIF_RESERVED_5 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_5', 5) -A7XX_PERF_GBIF_RESERVED_6 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_6', 6) -A7XX_PERF_GBIF_RESERVED_7 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_7', 7) -A7XX_PERF_GBIF_RESERVED_8 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_8', 8) -A7XX_PERF_GBIF_RESERVED_9 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_9', 9) -A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL', 10) -A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL', 11) -A7XX_PERF_GBIF_RESERVED_12 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_12', 12) -A7XX_PERF_GBIF_RESERVED_13 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_13', 13) -A7XX_PERF_GBIF_RESERVED_14 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_14', 14) -A7XX_PERF_GBIF_RESERVED_15 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_15', 15) -A7XX_PERF_GBIF_RESERVED_16 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_16', 16) -A7XX_PERF_GBIF_RESERVED_17 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_17', 17) -A7XX_PERF_GBIF_RESERVED_18 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_18', 18) -A7XX_PERF_GBIF_RESERVED_19 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_19', 19) -A7XX_PERF_GBIF_RESERVED_20 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_20', 20) -A7XX_PERF_GBIF_RESERVED_21 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_21', 21) -A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL', 22) -A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL', 23) -A7XX_PERF_GBIF_RESERVED_24 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_24', 24) -A7XX_PERF_GBIF_RESERVED_25 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_25', 25) -A7XX_PERF_GBIF_RESERVED_26 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_26', 26) -A7XX_PERF_GBIF_RESERVED_27 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_27', 27) -A7XX_PERF_GBIF_RESERVED_28 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_28', 28) -A7XX_PERF_GBIF_RESERVED_29 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_29', 29) -A7XX_PERF_GBIF_RESERVED_30 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_30', 30) -A7XX_PERF_GBIF_RESERVED_31 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_31', 31) -A7XX_PERF_GBIF_RESERVED_32 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_32', 32) -A7XX_PERF_GBIF_RESERVED_33 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_33', 33) -A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL', 34) -A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL', 35) -A7XX_PERF_GBIF_RESERVED_36 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_36', 36) -A7XX_PERF_GBIF_RESERVED_37 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_37', 37) -A7XX_PERF_GBIF_RESERVED_38 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_38', 38) -A7XX_PERF_GBIF_RESERVED_39 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_39', 39) -A7XX_PERF_GBIF_RESERVED_40 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_40', 40) -A7XX_PERF_GBIF_RESERVED_41 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_41', 41) -A7XX_PERF_GBIF_RESERVED_42 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_42', 42) -A7XX_PERF_GBIF_RESERVED_43 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_43', 43) -A7XX_PERF_GBIF_RESERVED_44 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_44', 44) -A7XX_PERF_GBIF_RESERVED_45 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_45', 45) -A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL', 46) -A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL', 47) -A7XX_PERF_GBIF_RESERVED_48 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_48', 48) -A7XX_PERF_GBIF_RESERVED_49 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_49', 49) -A7XX_PERF_GBIF_RESERVED_50 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_50', 50) -A7XX_PERF_GBIF_RESERVED_51 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_51', 51) -A7XX_PERF_GBIF_RESERVED_52 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_52', 52) -A7XX_PERF_GBIF_RESERVED_53 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_53', 53) -A7XX_PERF_GBIF_RESERVED_54 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_54', 54) -A7XX_PERF_GBIF_RESERVED_55 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_55', 55) -A7XX_PERF_GBIF_RESERVED_56 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_56', 56) -A7XX_PERF_GBIF_RESERVED_57 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_57', 57) -A7XX_PERF_GBIF_RESERVED_58 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_58', 58) -A7XX_PERF_GBIF_RESERVED_59 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_59', 59) -A7XX_PERF_GBIF_RESERVED_60 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_60', 60) -A7XX_PERF_GBIF_RESERVED_61 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_61', 61) -A7XX_PERF_GBIF_RESERVED_62 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_62', 62) -A7XX_PERF_GBIF_RESERVED_63 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_63', 63) -A7XX_PERF_GBIF_RESERVED_64 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_64', 64) -A7XX_PERF_GBIF_RESERVED_65 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_65', 65) -A7XX_PERF_GBIF_RESERVED_66 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_66', 66) -A7XX_PERF_GBIF_RESERVED_67 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_67', 67) -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL', 68) -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL', 69) -A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL', 70) -A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL', 71) -A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF', 72) -A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF', 73) -A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF', 74) -A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF', 75) -A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF', 76) -A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF', 77) -A7XX_PERF_GBIF_RESERVED_78 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_78', 78) -A7XX_PERF_GBIF_RESERVED_79 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_79', 79) -A7XX_PERF_GBIF_RESERVED_80 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_80', 80) -A7XX_PERF_GBIF_RESERVED_81 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_81', 81) -A7XX_PERF_GBIF_RESERVED_82 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_82', 82) -A7XX_PERF_GBIF_RESERVED_83 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_83', 83) -A7XX_PERF_GBIF_RESERVED_84 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_84', 84) -A7XX_PERF_GBIF_RESERVED_85 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_85', 85) -A7XX_PERF_GBIF_RESERVED_86 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_86', 86) -A7XX_PERF_GBIF_RESERVED_87 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_87', 87) -A7XX_PERF_GBIF_RESERVED_88 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_88', 88) -A7XX_PERF_GBIF_RESERVED_89 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_89', 89) -A7XX_PERF_GBIF_RESERVED_90 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_90', 90) -A7XX_PERF_GBIF_RESERVED_91 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_91', 91) -A7XX_PERF_GBIF_RESERVED_92 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_92', 92) -A7XX_PERF_GBIF_RESERVED_93 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_93', 93) -A7XX_PERF_GBIF_RESERVED_94 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_94', 94) -A7XX_PERF_GBIF_RESERVED_95 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_95', 95) -A7XX_PERF_GBIF_RESERVED_96 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_96', 96) -A7XX_PERF_GBIF_RESERVED_97 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_97', 97) -A7XX_PERF_GBIF_RESERVED_98 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_98', 98) -A7XX_PERF_GBIF_RESERVED_99 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_99', 99) -A7XX_PERF_GBIF_RESERVED_100 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_100', 100) -A7XX_PERF_GBIF_RESERVED_101 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_101', 101) -A7XX_PERF_GBIF_RESERVED_102 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_102', 102) -A7XX_PERF_GBIF_RESERVED_103 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_103', 103) -A7XX_PERF_GBIF_RESERVED_104 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_104', 104) -A7XX_PERF_GBIF_RESERVED_105 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_105', 105) -A7XX_PERF_GBIF_RESERVED_106 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_106', 106) -A7XX_PERF_GBIF_RESERVED_107 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_107', 107) -A7XX_PERF_GBIF_RESERVED_108 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_108', 108) -A7XX_PERF_GBIF_RESERVED_109 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_109', 109) -A7XX_PERF_GBIF_RESERVED_110 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_110', 110) -A7XX_PERF_GBIF_RESERVED_111 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_111', 111) -A7XX_PERF_GBIF_RESERVED_112 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_112', 112) -A7XX_PERF_GBIF_RESERVED_113 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_113', 113) -A7XX_PERF_GBIF_RESERVED_114 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_114', 114) -A7XX_PERF_GBIF_RESERVED_115 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_115', 115) -A7XX_PERF_GBIF_RESERVED_116 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_116', 116) -A7XX_PERF_GBIF_RESERVED_117 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_117', 117) -A7XX_PERF_GBIF_RESERVED_118 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_118', 118) -A7XX_PERF_GBIF_RESERVED_119 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_119', 119) -A7XX_PERF_GBIF_RESERVED_120 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_120', 120) -A7XX_PERF_GBIF_RESERVED_121 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_121', 121) -A7XX_PERF_GBIF_RESERVED_122 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_122', 122) -A7XX_PERF_GBIF_RESERVED_123 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_123', 123) -A7XX_PERF_GBIF_RESERVED_124 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_124', 124) -A7XX_PERF_GBIF_RESERVED_125 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_125', 125) -A7XX_PERF_GBIF_RESERVED_126 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_126', 126) -A7XX_PERF_GBIF_RESERVED_127 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_127', 127) -A7XX_PERF_GBIF_RESERVED_128 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_128', 128) -A7XX_PERF_GBIF_RESERVED_129 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_129', 129) -A7XX_PERF_GBIF_RESERVED_130 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_130', 130) -A7XX_PERF_GBIF_RESERVED_131 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_131', 131) -A7XX_PERF_GBIF_RESERVED_132 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_132', 132) -A7XX_PERF_GBIF_RESERVED_133 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_133', 133) -A7XX_PERF_GBIF_RESERVED_134 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_134', 134) -A7XX_PERF_GBIF_RESERVED_135 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_135', 135) -A7XX_PERF_GBIF_RESERVED_136 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_136', 136) -A7XX_PERF_GBIF_RESERVED_137 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_137', 137) -A7XX_PERF_GBIF_RESERVED_138 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_138', 138) -A7XX_PERF_GBIF_RESERVED_139 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_139', 139) -A7XX_PERF_GBIF_RESERVED_140 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_140', 140) -A7XX_PERF_GBIF_RESERVED_141 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_141', 141) -A7XX_PERF_GBIF_RESERVED_142 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_142', 142) -A7XX_PERF_GBIF_RESERVED_143 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_143', 143) -A7XX_PERF_GBIF_RESERVED_144 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_144', 144) -A7XX_PERF_GBIF_RESERVED_145 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_145', 145) -A7XX_PERF_GBIF_RESERVED_146 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_146', 146) -A7XX_PERF_GBIF_RESERVED_147 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_147', 147) -A7XX_PERF_GBIF_RESERVED_148 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_148', 148) -A7XX_PERF_GBIF_RESERVED_149 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_149', 149) -A7XX_PERF_GBIF_RESERVED_150 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_150', 150) -A7XX_PERF_GBIF_RESERVED_151 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_151', 151) -A7XX_PERF_GBIF_RESERVED_152 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_152', 152) -A7XX_PERF_GBIF_RESERVED_153 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_153', 153) -A7XX_PERF_GBIF_RESERVED_154 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_154', 154) -A7XX_PERF_GBIF_RESERVED_155 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_155', 155) -A7XX_PERF_GBIF_RESERVED_156 = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RESERVED_156', 156) -A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS', 157) -A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS', 158) -A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS', 159) -A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL', 160) -A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = enum_a7xx_gbif_perfcounter_select.define('A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL', 161) - -enum_a7xx_ufc_perfcounter_select = CEnum(ctypes.c_uint32) -A7XX_PERF_UFC_NEVER_COUNT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_NEVER_COUNT', 0) -A7XX_PERF_UFC_BUSY_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_BUSY_CYCLES', 1) -A7XX_PERF_UFC_READ_DATA_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_READ_DATA_VBIF', 2) -A7XX_PERF_UFC_WRITE_DATA_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_WRITE_DATA_VBIF', 3) -A7XX_PERF_UFC_READ_REQUEST_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_READ_REQUEST_VBIF', 4) -A7XX_PERF_UFC_WRITE_REQUEST_VBIF = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_WRITE_REQUEST_VBIF', 5) -A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH', 6) -A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH', 7) -A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH', 8) -A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_UBWC_READ', 9) -A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE', 10) -A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH', 11) -A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH', 12) -A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH', 13) -A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_UBWC_READ', 14) -A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE', 15) -A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY', 16) -A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_UBWC_RD_RDY', 17) -A7XX_PERF_UFC_MAIN_TP_RD_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_TP_RD_NRDY', 18) -A7XX_PERF_UFC_MAIN_TP_RD_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MAIN_TP_RD_RDY', 19) -A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD', 20) -A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA', 21) -A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA', 22) -A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG', 23) -A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN', 24) -A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT', 25) -A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES', 26) -A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES', 27) -A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES', 28) -A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES', 29) -A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_EVICTION_STALLED_CYCLES', 30) -A7XX_PERF_UFC_LOCK_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_LOCK_STALLED_CYCLES', 31) -A7XX_PERF_UFC_MISS_LATENCY_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MISS_LATENCY_CYCLES', 32) -A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', 33) -A7XX_PERF_UFC_L1_CRE_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_REQUESTS', 34) -A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES', 35) -A7XX_PERF_UFC_L1_CRE_FILTER_HIT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_FILTER_HIT', 36) -A7XX_PERF_UFC_L1_CRE_FILTER_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_CRE_FILTER_MISS', 37) -A7XX_PERF_UFC_L1_SP_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_REQUESTS', 38) -A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_STALLED_CYCLES', 39) -A7XX_PERF_UFC_L1_SP_FILTER_HIT = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_FILTER_HIT', 40) -A7XX_PERF_UFC_L1_SP_FILTER_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_SP_FILTER_MISS', 41) -A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_REQUESTS', 42) -A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_STALLED_CYCLES', 43) -A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS', 44) -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY', 45) -A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = enum_a7xx_ufc_perfcounter_select.define('A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY', 46) - -enum_a6xx_sequenced_thread_dist = CEnum(ctypes.c_uint32) -DIST_SCREEN_COORD = enum_a6xx_sequenced_thread_dist.define('DIST_SCREEN_COORD', 0) -DIST_ALL_TO_RB0 = enum_a6xx_sequenced_thread_dist.define('DIST_ALL_TO_RB0', 1) - -enum_a6xx_single_prim_mode = CEnum(ctypes.c_uint32) -NO_FLUSH = enum_a6xx_single_prim_mode.define('NO_FLUSH', 0) -FLUSH_PER_OVERLAP_AND_OVERWRITE = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP_AND_OVERWRITE', 1) -FLUSH_PER_OVERLAP = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP', 3) - -enum_a6xx_raster_mode = CEnum(ctypes.c_uint32) -TYPE_TILED = enum_a6xx_raster_mode.define('TYPE_TILED', 0) -TYPE_WRITER = enum_a6xx_raster_mode.define('TYPE_WRITER', 1) - -enum_a6xx_raster_direction = CEnum(ctypes.c_uint32) -LR_TB = enum_a6xx_raster_direction.define('LR_TB', 0) -RL_TB = enum_a6xx_raster_direction.define('RL_TB', 1) -LR_BT = enum_a6xx_raster_direction.define('LR_BT', 2) -RB_BT = enum_a6xx_raster_direction.define('RB_BT', 3) - -enum_a6xx_render_mode = CEnum(ctypes.c_uint32) -RENDERING_PASS = enum_a6xx_render_mode.define('RENDERING_PASS', 0) -BINNING_PASS = enum_a6xx_render_mode.define('BINNING_PASS', 1) - -enum_a6xx_buffers_location = CEnum(ctypes.c_uint32) -BUFFERS_IN_GMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_GMEM', 0) -BUFFERS_IN_SYSMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_SYSMEM', 3) - -enum_a6xx_lrz_dir_status = CEnum(ctypes.c_uint32) -LRZ_DIR_LE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_LE', 1) -LRZ_DIR_GE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_GE', 2) -LRZ_DIR_INVALID = enum_a6xx_lrz_dir_status.define('LRZ_DIR_INVALID', 3) - -enum_a6xx_fragcoord_sample_mode = CEnum(ctypes.c_uint32) -FRAGCOORD_CENTER = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_CENTER', 0) -FRAGCOORD_SAMPLE = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_SAMPLE', 3) - -enum_a6xx_rotation = CEnum(ctypes.c_uint32) -ROTATE_0 = enum_a6xx_rotation.define('ROTATE_0', 0) -ROTATE_90 = enum_a6xx_rotation.define('ROTATE_90', 1) -ROTATE_180 = enum_a6xx_rotation.define('ROTATE_180', 2) -ROTATE_270 = enum_a6xx_rotation.define('ROTATE_270', 3) -ROTATE_HFLIP = enum_a6xx_rotation.define('ROTATE_HFLIP', 4) -ROTATE_VFLIP = enum_a6xx_rotation.define('ROTATE_VFLIP', 5) - -enum_a6xx_ccu_cache_size = CEnum(ctypes.c_uint32) -CCU_CACHE_SIZE_FULL = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_FULL', 0) -CCU_CACHE_SIZE_HALF = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_HALF', 1) -CCU_CACHE_SIZE_QUARTER = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_QUARTER', 2) -CCU_CACHE_SIZE_EIGHTH = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_EIGHTH', 3) - -enum_a6xx_varying_interp_mode = CEnum(ctypes.c_uint32) -INTERP_SMOOTH = enum_a6xx_varying_interp_mode.define('INTERP_SMOOTH', 0) -INTERP_FLAT = enum_a6xx_varying_interp_mode.define('INTERP_FLAT', 1) -INTERP_ZERO = enum_a6xx_varying_interp_mode.define('INTERP_ZERO', 2) -INTERP_ONE = enum_a6xx_varying_interp_mode.define('INTERP_ONE', 3) - -enum_a6xx_varying_ps_repl_mode = CEnum(ctypes.c_uint32) -PS_REPL_NONE = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_NONE', 0) -PS_REPL_S = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_S', 1) -PS_REPL_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_T', 2) -PS_REPL_ONE_MINUS_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_ONE_MINUS_T', 3) - -enum_a6xx_threadsize = CEnum(ctypes.c_uint32) -THREAD64 = enum_a6xx_threadsize.define('THREAD64', 0) -THREAD128 = enum_a6xx_threadsize.define('THREAD128', 1) - -enum_a6xx_bindless_descriptor_size = CEnum(ctypes.c_uint32) -BINDLESS_DESCRIPTOR_16B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_16B', 1) -BINDLESS_DESCRIPTOR_64B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_64B', 3) - -enum_a6xx_isam_mode = CEnum(ctypes.c_uint32) -ISAMMODE_CL = enum_a6xx_isam_mode.define('ISAMMODE_CL', 1) -ISAMMODE_GL = enum_a6xx_isam_mode.define('ISAMMODE_GL', 2) - -enum_a7xx_cs_yalign = CEnum(ctypes.c_uint32) -CS_YALIGN_1 = enum_a7xx_cs_yalign.define('CS_YALIGN_1', 8) -CS_YALIGN_2 = enum_a7xx_cs_yalign.define('CS_YALIGN_2', 4) -CS_YALIGN_4 = enum_a7xx_cs_yalign.define('CS_YALIGN_4', 2) -CS_YALIGN_8 = enum_a7xx_cs_yalign.define('CS_YALIGN_8', 1) - -enum_a6xx_tex_filter = CEnum(ctypes.c_uint32) -A6XX_TEX_NEAREST = enum_a6xx_tex_filter.define('A6XX_TEX_NEAREST', 0) -A6XX_TEX_LINEAR = enum_a6xx_tex_filter.define('A6XX_TEX_LINEAR', 1) -A6XX_TEX_ANISO = enum_a6xx_tex_filter.define('A6XX_TEX_ANISO', 2) -A6XX_TEX_CUBIC = enum_a6xx_tex_filter.define('A6XX_TEX_CUBIC', 3) - -enum_a6xx_tex_clamp = CEnum(ctypes.c_uint32) -A6XX_TEX_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_REPEAT', 0) -A6XX_TEX_CLAMP_TO_EDGE = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_EDGE', 1) -A6XX_TEX_MIRROR_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_REPEAT', 2) -A6XX_TEX_CLAMP_TO_BORDER = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_BORDER', 3) -A6XX_TEX_MIRROR_CLAMP = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_CLAMP', 4) - -enum_a6xx_tex_aniso = CEnum(ctypes.c_uint32) -A6XX_TEX_ANISO_1 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_1', 0) -A6XX_TEX_ANISO_2 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_2', 1) -A6XX_TEX_ANISO_4 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_4', 2) -A6XX_TEX_ANISO_8 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_8', 3) -A6XX_TEX_ANISO_16 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_16', 4) - -enum_a6xx_reduction_mode = CEnum(ctypes.c_uint32) -A6XX_REDUCTION_MODE_AVERAGE = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_AVERAGE', 0) -A6XX_REDUCTION_MODE_MIN = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MIN', 1) -A6XX_REDUCTION_MODE_MAX = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MAX', 2) - -enum_a6xx_tex_swiz = CEnum(ctypes.c_uint32) -A6XX_TEX_X = enum_a6xx_tex_swiz.define('A6XX_TEX_X', 0) -A6XX_TEX_Y = enum_a6xx_tex_swiz.define('A6XX_TEX_Y', 1) -A6XX_TEX_Z = enum_a6xx_tex_swiz.define('A6XX_TEX_Z', 2) -A6XX_TEX_W = enum_a6xx_tex_swiz.define('A6XX_TEX_W', 3) -A6XX_TEX_ZERO = enum_a6xx_tex_swiz.define('A6XX_TEX_ZERO', 4) -A6XX_TEX_ONE = enum_a6xx_tex_swiz.define('A6XX_TEX_ONE', 5) - -enum_a6xx_tex_type = CEnum(ctypes.c_uint32) -A6XX_TEX_1D = enum_a6xx_tex_type.define('A6XX_TEX_1D', 0) -A6XX_TEX_2D = enum_a6xx_tex_type.define('A6XX_TEX_2D', 1) -A6XX_TEX_CUBE = enum_a6xx_tex_type.define('A6XX_TEX_CUBE', 2) -A6XX_TEX_3D = enum_a6xx_tex_type.define('A6XX_TEX_3D', 3) -A6XX_TEX_BUFFER = enum_a6xx_tex_type.define('A6XX_TEX_BUFFER', 4) - -__struct__cast = lambda X: (struct_X) -REG_CP_LOAD_STATE_0 = 0x00000000 -CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff -CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 -CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 -CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 -CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 -CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 -CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 -CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 -REG_CP_LOAD_STATE_1 = 0x00000001 -CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 -CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 -CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc -CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 -REG_CP_LOAD_STATE4_0 = 0x00000000 -CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff -CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 -CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 -CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 -CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 -CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 -CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 -CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 -REG_CP_LOAD_STATE4_1 = 0x00000001 -CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 -CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 -CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc -CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 -REG_CP_LOAD_STATE4_2 = 0x00000002 -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff -CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 -REG_CP_LOAD_STATE6_0 = 0x00000000 -CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff -CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 -CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 -CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 -CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 -CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 -CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 -CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 -CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 -CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 -REG_CP_LOAD_STATE6_1 = 0x00000001 -CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc -CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 -REG_CP_LOAD_STATE6_2 = 0x00000002 -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff -CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 -REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 -REG_CP_DRAW_INDX_0 = 0x00000000 -CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff -CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 -REG_CP_DRAW_INDX_1 = 0x00000001 -CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f -CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 -CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 -CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 -CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 -CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 -CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 -CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 -CP_DRAW_INDX_1_NOT_EOP = 0x00001000 -CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 -CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 -CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 -CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 -REG_CP_DRAW_INDX_2 = 0x00000002 -CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff -CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 -REG_CP_DRAW_INDX_3 = 0x00000003 -CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff -CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 -REG_CP_DRAW_INDX_4 = 0x00000004 -CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff -CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 -REG_CP_DRAW_INDX_2_0 = 0x00000000 -CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff -CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 -REG_CP_DRAW_INDX_2_1 = 0x00000001 -CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f -CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 -CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 -CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 -CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 -CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 -CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 -CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 -CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 -CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 -CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 -CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 -CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 -REG_CP_DRAW_INDX_2_2 = 0x00000002 -CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff -CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 -REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f -CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 -CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 -CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 -CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 -CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 -CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 -CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 -CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 -REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff -CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 -REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff -CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 -REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff -CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 -REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 -REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 -CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff -CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 -REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff -CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 -REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f -A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 -A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 -A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 -A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 -A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 -A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 -A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 -REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff -A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 -REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff -A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 -REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff -A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 -REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 -REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f -A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 -A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 -A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 -A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 -A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 -A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 -A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 -REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff -A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 -REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff -A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 -REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff -A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 -REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff -A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 -REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 -REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f -A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 -A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 -A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 -A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 -A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 -A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 -A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 -REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f -A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 -A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 -REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 -REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 -REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 -REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 -REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a -REG_CP_DRAW_AUTO_0 = 0x00000000 -CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f -CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 -CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 -CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 -CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 -CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 -CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 -CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 -CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 -CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 -CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 -CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 -REG_CP_DRAW_AUTO_1 = 0x00000001 -CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff -CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 -REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 -REG_CP_DRAW_AUTO_4 = 0x00000004 -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff -CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 -REG_CP_DRAW_AUTO_5 = 0x00000005 -CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff -CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 -REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 -CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 -REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 -CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 -REG_CP_DRAW_PRED_SET_0 = 0x00000000 -CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 -CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 -CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 -CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 -REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 -REG_CP_SET_DRAW_STATE_ = lambda i0: (0x00000000 + 0x3*i0 ) -CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff -CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 -CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 -CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 -CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 -CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 -CP_SET_DRAW_STATE__0_BINNING = 0x00100000 -CP_SET_DRAW_STATE__0_GMEM = 0x00200000 -CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 -CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 -CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 -CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff -CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 -CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff -CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 -REG_CP_SET_BIN_0 = 0x00000000 -REG_CP_SET_BIN_1 = 0x00000001 -CP_SET_BIN_1_X1__MASK = 0x0000ffff -CP_SET_BIN_1_X1__SHIFT = 0 -CP_SET_BIN_1_Y1__MASK = 0xffff0000 -CP_SET_BIN_1_Y1__SHIFT = 16 -REG_CP_SET_BIN_2 = 0x00000002 -CP_SET_BIN_2_X2__MASK = 0x0000ffff -CP_SET_BIN_2_X2__SHIFT = 0 -CP_SET_BIN_2_Y2__MASK = 0xffff0000 -CP_SET_BIN_2_Y2__SHIFT = 16 -REG_CP_SET_BIN_DATA_0 = 0x00000000 -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff -CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 -REG_CP_SET_BIN_DATA_1 = 0x00000001 -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff -CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 -REG_CP_SET_BIN_DATA5_0 = 0x00000000 -CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 -CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 -CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 -CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 -REG_CP_SET_BIN_DATA5_1 = 0x00000001 -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff -CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 -REG_CP_SET_BIN_DATA5_2 = 0x00000002 -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff -CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 -REG_CP_SET_BIN_DATA5_3 = 0x00000003 -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff -CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 -REG_CP_SET_BIN_DATA5_4 = 0x00000004 -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff -CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 -REG_CP_SET_BIN_DATA5_5 = 0x00000005 -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff -CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 -REG_CP_SET_BIN_DATA5_6 = 0x00000006 -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff -CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 -REG_CP_SET_BIN_DATA5_7 = 0x00000007 -REG_CP_SET_BIN_DATA5_9 = 0x00000009 -REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 -CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 -CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 -REG_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff -CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 -REG_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff -CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 -REG_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff -CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 -REG_CP_REG_RMW_0 = 0x00000000 -CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff -CP_REG_RMW_0_DST_REG__SHIFT = 0 -CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 -CP_REG_RMW_0_ROTATE__SHIFT = 24 -CP_REG_RMW_0_SRC1_ADD = 0x20000000 -CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 -CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 -REG_CP_REG_RMW_1 = 0x00000001 -CP_REG_RMW_1_SRC0__MASK = 0xffffffff -CP_REG_RMW_1_SRC0__SHIFT = 0 -REG_CP_REG_RMW_2 = 0x00000002 -CP_REG_RMW_2_SRC1__MASK = 0xffffffff -CP_REG_RMW_2_SRC1__SHIFT = 0 -REG_CP_REG_TO_MEM_0 = 0x00000000 -CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff -CP_REG_TO_MEM_0_REG__SHIFT = 0 -CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 -CP_REG_TO_MEM_0_CNT__SHIFT = 18 -CP_REG_TO_MEM_0_64B = 0x40000000 -CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 -REG_CP_REG_TO_MEM_1 = 0x00000001 -CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff -CP_REG_TO_MEM_1_DEST__SHIFT = 0 -REG_CP_REG_TO_MEM_2 = 0x00000002 -CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff -CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 -CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff -CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 -CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 -CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 -CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 -CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 -REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 -CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 -CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 -REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 -CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff -CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 -CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 -CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 -CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 -REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 -REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff -CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 -REG_CP_MEM_TO_REG_0 = 0x00000000 -CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff -CP_MEM_TO_REG_0_REG__SHIFT = 0 -CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 -CP_MEM_TO_REG_0_CNT__SHIFT = 19 -CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 -CP_MEM_TO_REG_0_UNK31 = 0x80000000 -REG_CP_MEM_TO_REG_1 = 0x00000001 -CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff -CP_MEM_TO_REG_1_SRC__SHIFT = 0 -REG_CP_MEM_TO_REG_2 = 0x00000002 -CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff -CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 -REG_CP_MEM_TO_MEM_0 = 0x00000000 -CP_MEM_TO_MEM_0_NEG_A = 0x00000001 -CP_MEM_TO_MEM_0_NEG_B = 0x00000002 -CP_MEM_TO_MEM_0_NEG_C = 0x00000004 -CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 -CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 -CP_MEM_TO_MEM_0_UNK31 = 0x80000000 -REG_CP_MEMCPY_0 = 0x00000000 -CP_MEMCPY_0_DWORDS__MASK = 0xffffffff -CP_MEMCPY_0_DWORDS__SHIFT = 0 -REG_CP_MEMCPY_1 = 0x00000001 -CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff -CP_MEMCPY_1_SRC_LO__SHIFT = 0 -REG_CP_MEMCPY_2 = 0x00000002 -CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff -CP_MEMCPY_2_SRC_HI__SHIFT = 0 -REG_CP_MEMCPY_3 = 0x00000003 -CP_MEMCPY_3_DST_LO__MASK = 0xffffffff -CP_MEMCPY_3_DST_LO__SHIFT = 0 -REG_CP_MEMCPY_4 = 0x00000004 -CP_MEMCPY_4_DST_HI__MASK = 0xffffffff -CP_MEMCPY_4_DST_HI__SHIFT = 0 -REG_CP_REG_TO_SCRATCH_0 = 0x00000000 -CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff -CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 -CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 -CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 -CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 -CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 -REG_CP_SCRATCH_TO_REG_0 = 0x00000000 -CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff -CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 -CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 -CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 -CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 -CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 -CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 -REG_CP_SCRATCH_WRITE_0 = 0x00000000 -CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 -CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 -REG_CP_MEM_WRITE_0 = 0x00000000 -CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff -CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 -REG_CP_MEM_WRITE_1 = 0x00000001 -CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff -CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 -REG_CP_COND_WRITE_0 = 0x00000000 -CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 -CP_COND_WRITE_0_FUNCTION__SHIFT = 0 -CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 -CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 -REG_CP_COND_WRITE_1 = 0x00000001 -CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff -CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 -REG_CP_COND_WRITE_2 = 0x00000002 -CP_COND_WRITE_2_REF__MASK = 0xffffffff -CP_COND_WRITE_2_REF__SHIFT = 0 -REG_CP_COND_WRITE_3 = 0x00000003 -CP_COND_WRITE_3_MASK__MASK = 0xffffffff -CP_COND_WRITE_3_MASK__SHIFT = 0 -REG_CP_COND_WRITE_4 = 0x00000004 -CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff -CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 -REG_CP_COND_WRITE_5 = 0x00000005 -CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff -CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 -REG_CP_COND_WRITE5_0 = 0x00000000 -CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 -CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 -CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 -CP_COND_WRITE5_0_POLL__MASK = 0x00000030 -CP_COND_WRITE5_0_POLL__SHIFT = 4 -CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 -REG_CP_COND_WRITE5_1 = 0x00000001 -CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff -CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 -REG_CP_COND_WRITE5_2 = 0x00000002 -CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff -CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 -REG_CP_COND_WRITE5_3 = 0x00000003 -CP_COND_WRITE5_3_REF__MASK = 0xffffffff -CP_COND_WRITE5_3_REF__SHIFT = 0 -REG_CP_COND_WRITE5_4 = 0x00000004 -CP_COND_WRITE5_4_MASK__MASK = 0xffffffff -CP_COND_WRITE5_4_MASK__SHIFT = 0 -REG_CP_COND_WRITE5_5 = 0x00000005 -CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff -CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 -REG_CP_COND_WRITE5_6 = 0x00000006 -CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff -CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 -REG_CP_COND_WRITE5_7 = 0x00000007 -CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff -CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 -REG_CP_WAIT_MEM_GTE_0 = 0x00000000 -CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff -CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 -REG_CP_WAIT_MEM_GTE_1 = 0x00000001 -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff -CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 -REG_CP_WAIT_MEM_GTE_2 = 0x00000002 -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff -CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 -REG_CP_WAIT_MEM_GTE_3 = 0x00000003 -CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff -CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 -REG_CP_WAIT_REG_MEM_0 = 0x00000000 -CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 -CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 -CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 -CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 -CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 -CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 -REG_CP_WAIT_REG_MEM_1 = 0x00000001 -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff -CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 -REG_CP_WAIT_REG_MEM_2 = 0x00000002 -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff -CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 -REG_CP_WAIT_REG_MEM_3 = 0x00000003 -CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff -CP_WAIT_REG_MEM_3_REF__SHIFT = 0 -REG_CP_WAIT_REG_MEM_4 = 0x00000004 -CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff -CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 -REG_CP_WAIT_REG_MEM_5 = 0x00000005 -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff -CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 -REG_CP_WAIT_TWO_REGS_0 = 0x00000000 -CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff -CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 -REG_CP_WAIT_TWO_REGS_1 = 0x00000001 -CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff -CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 -REG_CP_WAIT_TWO_REGS_2 = 0x00000002 -CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff -CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 -REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 -REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 -CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff -CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 -REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 -CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff -CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 -REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 -CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff -CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 -REG_CP_SET_RENDER_MODE_0 = 0x00000000 -CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff -CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 -REG_CP_SET_RENDER_MODE_1 = 0x00000001 -CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff -CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 -REG_CP_SET_RENDER_MODE_2 = 0x00000002 -CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff -CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 -REG_CP_SET_RENDER_MODE_3 = 0x00000003 -CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 -CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 -REG_CP_SET_RENDER_MODE_4 = 0x00000004 -REG_CP_SET_RENDER_MODE_5 = 0x00000005 -CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff -CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 -REG_CP_SET_RENDER_MODE_6 = 0x00000006 -CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff -CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 -REG_CP_SET_RENDER_MODE_7 = 0x00000007 -CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff -CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff -CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff -CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 -REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 -REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff -CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff -CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff -CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 -REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 -REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 -REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff -CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 -REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff -CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 -REG_CP_EVENT_WRITE_0 = 0x00000000 -CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff -CP_EVENT_WRITE_0_EVENT__SHIFT = 0 -CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 -CP_EVENT_WRITE_0_IRQ = 0x80000000 -REG_CP_EVENT_WRITE_1 = 0x00000001 -CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff -CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 -REG_CP_EVENT_WRITE_2 = 0x00000002 -CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff -CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 -REG_CP_EVENT_WRITE_3 = 0x00000003 -REG_CP_EVENT_WRITE7_0 = 0x00000000 -CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff -CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 -CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 -CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 -CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 -CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 -CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 -CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 -CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 -CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 -CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 -CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 -CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 -CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 -REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK = 0xffffffff -EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT = 0 -REG_EV_DST_RAM_CP_EVENT_WRITE7_2 = 0x00000002 -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK = 0xffffffff -EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT = 0 -REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff -EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 -REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff -EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff -EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff -EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 -REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff -EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 -REG_CP_BLIT_0 = 0x00000000 -CP_BLIT_0_OP__MASK = 0x0000000f -CP_BLIT_0_OP__SHIFT = 0 -REG_CP_BLIT_1 = 0x00000001 -CP_BLIT_1_SRC_X1__MASK = 0x00003fff -CP_BLIT_1_SRC_X1__SHIFT = 0 -CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 -CP_BLIT_1_SRC_Y1__SHIFT = 16 -REG_CP_BLIT_2 = 0x00000002 -CP_BLIT_2_SRC_X2__MASK = 0x00003fff -CP_BLIT_2_SRC_X2__SHIFT = 0 -CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 -CP_BLIT_2_SRC_Y2__SHIFT = 16 -REG_CP_BLIT_3 = 0x00000003 -CP_BLIT_3_DST_X1__MASK = 0x00003fff -CP_BLIT_3_DST_X1__SHIFT = 0 -CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 -CP_BLIT_3_DST_Y1__SHIFT = 16 -REG_CP_BLIT_4 = 0x00000004 -CP_BLIT_4_DST_X2__MASK = 0x00003fff -CP_BLIT_4_DST_X2__SHIFT = 0 -CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 -CP_BLIT_4_DST_Y2__SHIFT = 16 -REG_CP_EXEC_CS_0 = 0x00000000 -REG_CP_EXEC_CS_1 = 0x00000001 -CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff -CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 -REG_CP_EXEC_CS_2 = 0x00000002 -CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff -CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 -REG_CP_EXEC_CS_3 = 0x00000003 -CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff -CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 -REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 -REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff -A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 -REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 -A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 -REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff -A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 -REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff -A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 -REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 -A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 -REG_A6XX_CP_SET_MARKER_0 = 0x00000000 -A6XX_CP_SET_MARKER_0_MODE__MASK = 0x000001ff -A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 -A6XX_CP_SET_MARKER_0_MARKER__MASK = 0x0000000f -A6XX_CP_SET_MARKER_0_MARKER__SHIFT = 0 -REG_A6XX_CP_SET_PSEUDO_REG_ = lambda i0: (0x00000000 + 0x3*i0 ) -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff -A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 -A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff -A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 -A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff -A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 -REG_A6XX_CP_REG_TEST_0 = 0x00000000 -A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff -A6XX_CP_REG_TEST_0_REG__SHIFT = 0 -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff -A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 -A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 -A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 -A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 -A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 -A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 -A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 -A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 -A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 -REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 -REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 -REG_CP_COND_REG_EXEC_0 = 0x00000000 -CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff -CP_COND_REG_EXEC_0_REG0__SHIFT = 0 -CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 -CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 -CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 -CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 -CP_COND_REG_EXEC_0_BINNING = 0x02000000 -CP_COND_REG_EXEC_0_GMEM = 0x04000000 -CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 -CP_COND_REG_EXEC_0_BV = 0x02000000 -CP_COND_REG_EXEC_0_BR = 0x04000000 -CP_COND_REG_EXEC_0_LPAC = 0x08000000 -CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 -CP_COND_REG_EXEC_0_MODE__SHIFT = 28 -REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff -PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 -REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff -REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 -REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 -REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff -RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 -REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff -REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 -REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff -THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 -REG_CP_COND_REG_EXEC_2 = 0x00000002 -CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff -CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 -REG_CP_COND_EXEC_0 = 0x00000000 -CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff -CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 -REG_CP_COND_EXEC_1 = 0x00000001 -CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff -CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 -REG_CP_COND_EXEC_2 = 0x00000002 -CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff -CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 -REG_CP_COND_EXEC_3 = 0x00000003 -CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff -CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 -REG_CP_COND_EXEC_4 = 0x00000004 -CP_COND_EXEC_4_REF__MASK = 0xffffffff -CP_COND_EXEC_4_REF__SHIFT = 0 -REG_CP_COND_EXEC_5 = 0x00000005 -CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff -CP_COND_EXEC_5_DWORDS__SHIFT = 0 -REG_CP_SET_CTXSWITCH_IB_0 = 0x00000000 -CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK = 0xffffffff -CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT = 0 -REG_CP_SET_CTXSWITCH_IB_1 = 0x00000001 -CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK = 0xffffffff -CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT = 0 -REG_CP_SET_CTXSWITCH_IB_2 = 0x00000002 -CP_SET_CTXSWITCH_IB_2_DWORDS__MASK = 0x000fffff -CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT = 0 -CP_SET_CTXSWITCH_IB_2_TYPE__MASK = 0x00300000 -CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT = 20 -REG_CP_REG_WRITE_0 = 0x00000000 -CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f -CP_REG_WRITE_0_TRACKER__SHIFT = 0 -REG_CP_REG_WRITE_1 = 0x00000001 -REG_CP_REG_WRITE_2 = 0x00000002 -REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff -CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 -REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff -CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 -CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 -CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 -REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff -CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 -REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff -CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 -REG_CP_START_BIN_BIN_COUNT = 0x00000000 -REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 -REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 -REG_CP_START_BIN_BODY_DWORDS = 0x00000004 -REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 -CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 -CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 -CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 -REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 -REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 -REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 -REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 -REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 -CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f -CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 -REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff -CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 -REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 -CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff -CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 -CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 -CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 -REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 -CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f -CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 -REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f -CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 -REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 -CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff -CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 -REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff -CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 -REG_CP_THREAD_CONTROL_0 = 0x00000000 -CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 -CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 -CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 -CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 -REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 -REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff -CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 -CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 -REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff -CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 -REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 -CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 -CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 -CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS = 0x00000004 -REG_AXXX_CP_RB_BASE = 0x000001c0 -REG_AXXX_CP_RB_CNTL = 0x000001c1 -AXXX_CP_RB_CNTL_BUFSZ__MASK = 0x0000003f -AXXX_CP_RB_CNTL_BUFSZ__SHIFT = 0 -AXXX_CP_RB_CNTL_BLKSZ__MASK = 0x00003f00 -AXXX_CP_RB_CNTL_BLKSZ__SHIFT = 8 -AXXX_CP_RB_CNTL_BUF_SWAP__MASK = 0x00030000 -AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT = 16 -AXXX_CP_RB_CNTL_POLL_EN = 0x00100000 -AXXX_CP_RB_CNTL_NO_UPDATE = 0x08000000 -AXXX_CP_RB_CNTL_RPTR_WR_EN = 0x80000000 -REG_AXXX_CP_RB_RPTR_ADDR = 0x000001c3 -AXXX_CP_RB_RPTR_ADDR_SWAP__MASK = 0x00000003 -AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT = 0 -AXXX_CP_RB_RPTR_ADDR_ADDR__MASK = 0xfffffffc -AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT = 2 -REG_AXXX_CP_RB_RPTR = 0x000001c4 -REG_AXXX_CP_RB_WPTR = 0x000001c5 -REG_AXXX_CP_RB_WPTR_DELAY = 0x000001c6 -REG_AXXX_CP_RB_RPTR_WR = 0x000001c7 -REG_AXXX_CP_RB_WPTR_BASE = 0x000001c8 -REG_AXXX_CP_QUEUE_THRESHOLDS = 0x000001d5 -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK = 0x0000000f -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT = 0 -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK = 0x00000f00 -AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT = 8 -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK = 0x000f0000 -AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT = 16 -REG_AXXX_CP_MEQ_THRESHOLDS = 0x000001d6 -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK = 0x001f0000 -AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT = 16 -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK = 0x1f000000 -AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT = 24 -REG_AXXX_CP_CSQ_AVAIL = 0x000001d7 -AXXX_CP_CSQ_AVAIL_RING__MASK = 0x0000007f -AXXX_CP_CSQ_AVAIL_RING__SHIFT = 0 -AXXX_CP_CSQ_AVAIL_IB1__MASK = 0x00007f00 -AXXX_CP_CSQ_AVAIL_IB1__SHIFT = 8 -AXXX_CP_CSQ_AVAIL_IB2__MASK = 0x007f0000 -AXXX_CP_CSQ_AVAIL_IB2__SHIFT = 16 -REG_AXXX_CP_STQ_AVAIL = 0x000001d8 -AXXX_CP_STQ_AVAIL_ST__MASK = 0x0000007f -AXXX_CP_STQ_AVAIL_ST__SHIFT = 0 -REG_AXXX_CP_MEQ_AVAIL = 0x000001d9 -AXXX_CP_MEQ_AVAIL_MEQ__MASK = 0x0000001f -AXXX_CP_MEQ_AVAIL_MEQ__SHIFT = 0 -REG_AXXX_SCRATCH_UMSK = 0x000001dc -AXXX_SCRATCH_UMSK_UMSK__MASK = 0x000000ff -AXXX_SCRATCH_UMSK_UMSK__SHIFT = 0 -AXXX_SCRATCH_UMSK_SWAP__MASK = 0x00030000 -AXXX_SCRATCH_UMSK_SWAP__SHIFT = 16 -REG_AXXX_SCRATCH_ADDR = 0x000001dd -REG_AXXX_CP_ME_RDADDR = 0x000001ea -REG_AXXX_CP_STATE_DEBUG_INDEX = 0x000001ec -REG_AXXX_CP_STATE_DEBUG_DATA = 0x000001ed -REG_AXXX_CP_INT_CNTL = 0x000001f2 -AXXX_CP_INT_CNTL_SW_INT_MASK = 0x00080000 -AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK = 0x00800000 -AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK = 0x01000000 -AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK = 0x02000000 -AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK = 0x04000000 -AXXX_CP_INT_CNTL_IB_ERROR_MASK = 0x08000000 -AXXX_CP_INT_CNTL_IB2_INT_MASK = 0x20000000 -AXXX_CP_INT_CNTL_IB1_INT_MASK = 0x40000000 -AXXX_CP_INT_CNTL_RB_INT_MASK = 0x80000000 -REG_AXXX_CP_INT_STATUS = 0x000001f3 -REG_AXXX_CP_INT_ACK = 0x000001f4 -REG_AXXX_CP_ME_CNTL = 0x000001f6 -AXXX_CP_ME_CNTL_BUSY = 0x20000000 -AXXX_CP_ME_CNTL_HALT = 0x10000000 -REG_AXXX_CP_ME_STATUS = 0x000001f7 -REG_AXXX_CP_ME_RAM_WADDR = 0x000001f8 -REG_AXXX_CP_ME_RAM_RADDR = 0x000001f9 -REG_AXXX_CP_ME_RAM_DATA = 0x000001fa -REG_AXXX_CP_DEBUG = 0x000001fc -AXXX_CP_DEBUG_PREDICATE_DISABLE = 0x00800000 -AXXX_CP_DEBUG_PROG_END_PTR_ENABLE = 0x01000000 -AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE = 0x02000000 -AXXX_CP_DEBUG_PREFETCH_PASS_NOPS = 0x04000000 -AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE = 0x08000000 -AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE = 0x10000000 -AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL = 0x40000000 -AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE = 0x80000000 -REG_AXXX_CP_CSQ_RB_STAT = 0x000001fd -AXXX_CP_CSQ_RB_STAT_RPTR__MASK = 0x0000007f -AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT = 0 -AXXX_CP_CSQ_RB_STAT_WPTR__MASK = 0x007f0000 -AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT = 16 -REG_AXXX_CP_CSQ_IB1_STAT = 0x000001fe -AXXX_CP_CSQ_IB1_STAT_RPTR__MASK = 0x0000007f -AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT = 0 -AXXX_CP_CSQ_IB1_STAT_WPTR__MASK = 0x007f0000 -AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT = 16 -REG_AXXX_CP_CSQ_IB2_STAT = 0x000001ff -AXXX_CP_CSQ_IB2_STAT_RPTR__MASK = 0x0000007f -AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT = 0 -AXXX_CP_CSQ_IB2_STAT_WPTR__MASK = 0x007f0000 -AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT = 16 -REG_AXXX_CP_NON_PREFETCH_CNTRS = 0x00000440 -REG_AXXX_CP_STQ_ST_STAT = 0x00000443 -REG_AXXX_CP_ST_BASE = 0x0000044d -REG_AXXX_CP_ST_BUFSZ = 0x0000044e -REG_AXXX_CP_MEQ_STAT = 0x0000044f -REG_AXXX_CP_MIU_TAG_STAT = 0x00000452 -REG_AXXX_CP_BIN_MASK_LO = 0x00000454 -REG_AXXX_CP_BIN_MASK_HI = 0x00000455 -REG_AXXX_CP_BIN_SELECT_LO = 0x00000456 -REG_AXXX_CP_BIN_SELECT_HI = 0x00000457 -REG_AXXX_CP_IB1_BASE = 0x00000458 -REG_AXXX_CP_IB1_BUFSZ = 0x00000459 -REG_AXXX_CP_IB2_BASE = 0x0000045a -REG_AXXX_CP_IB2_BUFSZ = 0x0000045b -REG_AXXX_CP_STAT = 0x0000047f -AXXX_CP_STAT_CP_BUSY = 0x80000000 -AXXX_CP_STAT_VS_EVENT_FIFO_BUSY = 0x40000000 -AXXX_CP_STAT_PS_EVENT_FIFO_BUSY = 0x20000000 -AXXX_CP_STAT_CF_EVENT_FIFO_BUSY = 0x10000000 -AXXX_CP_STAT_RB_EVENT_FIFO_BUSY = 0x08000000 -AXXX_CP_STAT_ME_BUSY = 0x04000000 -AXXX_CP_STAT_MIU_WR_C_BUSY = 0x02000000 -AXXX_CP_STAT_CP_3D_BUSY = 0x00800000 -AXXX_CP_STAT_CP_NRT_BUSY = 0x00400000 -AXXX_CP_STAT_RBIU_SCRATCH_BUSY = 0x00200000 -AXXX_CP_STAT_RCIU_ME_BUSY = 0x00100000 -AXXX_CP_STAT_RCIU_PFP_BUSY = 0x00080000 -AXXX_CP_STAT_MEQ_RING_BUSY = 0x00040000 -AXXX_CP_STAT_PFP_BUSY = 0x00020000 -AXXX_CP_STAT_ST_QUEUE_BUSY = 0x00010000 -AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY = 0x00002000 -AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY = 0x00001000 -AXXX_CP_STAT_RING_QUEUE_BUSY = 0x00000800 -AXXX_CP_STAT_CSF_BUSY = 0x00000400 -AXXX_CP_STAT_CSF_ST_BUSY = 0x00000200 -AXXX_CP_STAT_EVENT_BUSY = 0x00000100 -AXXX_CP_STAT_CSF_INDIRECT2_BUSY = 0x00000080 -AXXX_CP_STAT_CSF_INDIRECTS_BUSY = 0x00000040 -AXXX_CP_STAT_CSF_RING_BUSY = 0x00000020 -AXXX_CP_STAT_RCIU_BUSY = 0x00000010 -AXXX_CP_STAT_RBIU_BUSY = 0x00000008 -AXXX_CP_STAT_MIU_RD_RETURN_BUSY = 0x00000004 -AXXX_CP_STAT_MIU_RD_REQ_BUSY = 0x00000002 -AXXX_CP_STAT_MIU_WR_BUSY = 0x00000001 -REG_AXXX_CP_SCRATCH_REG0 = 0x00000578 -REG_AXXX_CP_SCRATCH_REG1 = 0x00000579 -REG_AXXX_CP_SCRATCH_REG2 = 0x0000057a -REG_AXXX_CP_SCRATCH_REG3 = 0x0000057b -REG_AXXX_CP_SCRATCH_REG4 = 0x0000057c -REG_AXXX_CP_SCRATCH_REG5 = 0x0000057d -REG_AXXX_CP_SCRATCH_REG6 = 0x0000057e -REG_AXXX_CP_SCRATCH_REG7 = 0x0000057f -REG_AXXX_CP_ME_VS_EVENT_SRC = 0x00000600 -REG_AXXX_CP_ME_VS_EVENT_ADDR = 0x00000601 -REG_AXXX_CP_ME_VS_EVENT_DATA = 0x00000602 -REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM = 0x00000603 -REG_AXXX_CP_ME_VS_EVENT_DATA_SWM = 0x00000604 -REG_AXXX_CP_ME_PS_EVENT_SRC = 0x00000605 -REG_AXXX_CP_ME_PS_EVENT_ADDR = 0x00000606 -REG_AXXX_CP_ME_PS_EVENT_DATA = 0x00000607 -REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM = 0x00000608 -REG_AXXX_CP_ME_PS_EVENT_DATA_SWM = 0x00000609 -REG_AXXX_CP_ME_CF_EVENT_SRC = 0x0000060a -REG_AXXX_CP_ME_CF_EVENT_ADDR = 0x0000060b -REG_AXXX_CP_ME_CF_EVENT_DATA = 0x0000060c -REG_AXXX_CP_ME_NRT_ADDR = 0x0000060d -REG_AXXX_CP_ME_NRT_DATA = 0x0000060e -REG_AXXX_CP_ME_VS_FETCH_DONE_SRC = 0x00000612 -REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR = 0x00000613 -REG_AXXX_CP_ME_VS_FETCH_DONE_DATA = 0x00000614 -A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 -A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 -A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 -A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 -A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 -A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 -A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 -A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 -A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 -A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 -A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 -A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 -A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 -A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 -A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 -A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 -A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 -A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 -A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 -A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 -A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 -A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 -A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 -A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 -A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 -A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 -A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 -A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 -A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 -A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 -A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 -A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 -A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 -A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 -A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 -A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 -A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 -A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 -REG_A6XX_CP_RB_BASE = 0x00000800 -REG_A6XX_CP_RB_CNTL = 0x00000802 -REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 -REG_A6XX_CP_RB_RPTR = 0x00000806 -REG_A6XX_CP_RB_WPTR = 0x00000807 -REG_A6XX_CP_SQE_CNTL = 0x00000808 -REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 -A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 -REG_A6XX_CP_HW_FAULT = 0x00000821 -REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 -REG_A6XX_CP_PROTECT_STATUS = 0x00000824 -REG_A6XX_CP_STATUS_1 = 0x00000825 -REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 -REG_A6XX_CP_MISC_CNTL = 0x00000840 -REG_A6XX_CP_APRIV_CNTL = 0x00000844 -A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 -A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 -A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 -A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 -A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 -A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 -REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 -REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff -A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 -A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 -A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 -A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 -REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff -A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 -A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 -REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 -REG_A6XX_CP_CHICKEN_DBG = 0x00000841 -REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 -REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 -REG_A6XX_CP_PROTECT_CNTL = 0x0000084f -A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 -A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 -A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 -REG_A6XX_CP_SCRATCH = lambda i0: (0x00000883 + 0x1*i0 ) -REG_A6XX_CP_PROTECT = lambda i0: (0x00000850 + 0x1*i0 ) -A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff -A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 -A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 -A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 -A6XX_CP_PROTECT_REG_READ = 0x80000000 -REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 -REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 -REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 -REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 -REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab -REG_A6XX_CP_PERFCTR_CP_SEL = lambda i0: (0x000008d0 + 0x1*i0 ) -REG_A7XX_CP_BV_PERFCTR_CP_SEL = lambda i0: (0x000008e0 + 0x1*i0 ) -REG_A6XX_CP_CRASH_SCRIPT_BASE = 0x00000900 -REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 -REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 -REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 -REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 -REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a -REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b -REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c -REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d -REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e -REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f -REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 -REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 -REG_A6XX_CP_IB1_BASE = 0x00000928 -REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a -REG_A6XX_CP_IB2_BASE = 0x0000092b -REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d -REG_A6XX_CP_SDS_BASE = 0x0000092e -REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 -REG_A6XX_CP_MRB_BASE = 0x00000931 -REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 -REG_A6XX_CP_VSD_BASE = 0x00000934 -REG_A6XX_CP_ROQ_RB_STAT = 0x00000939 -A6XX_CP_ROQ_RB_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_RB_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_ROQ_IB1_STAT = 0x0000093a -A6XX_CP_ROQ_IB1_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_IB1_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_ROQ_IB2_STAT = 0x0000093b -A6XX_CP_ROQ_IB2_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_IB2_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_ROQ_SDS_STAT = 0x0000093c -A6XX_CP_ROQ_SDS_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_SDS_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_ROQ_MRB_STAT = 0x0000093d -A6XX_CP_ROQ_MRB_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_MRB_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_ROQ_VSD_STAT = 0x0000093e -A6XX_CP_ROQ_VSD_STAT_RPTR__MASK = 0x000003ff -A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT = 0 -A6XX_CP_ROQ_VSD_STAT_WPTR__MASK = 0x03ff0000 -A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT = 16 -REG_A6XX_CP_IB1_DWORDS = 0x00000943 -REG_A6XX_CP_IB2_DWORDS = 0x00000944 -REG_A6XX_CP_SDS_DWORDS = 0x00000945 -REG_A6XX_CP_MRB_DWORDS = 0x00000946 -REG_A6XX_CP_VSD_DWORDS = 0x00000947 -REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 -A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 -REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 -A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 -REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a -A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 -REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b -A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 -REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c -A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 -REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d -A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 -A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 -REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 -REG_A6XX_CP_AHB_CNTL = 0x0000098d -REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 -REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 -A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 -A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 -A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 -A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 -REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 -REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 -A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 -A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 -A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 -A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 -REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 -REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 -REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 -REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 -REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 -REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 -REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 -REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 -REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 -REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 -REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 -REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 -REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 -REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR = 0x00000a9a -REG_A7XX_CP_RESOURCE_TBL_DBG_DATA = 0x00000a9b -REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 -REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada -REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a -REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b -REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c -REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 -REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 -REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 -REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a -REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 -REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 -REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 -REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 -REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 -REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 -REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 -REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 -REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 -REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 -REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 -REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac -REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 -REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 -REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 -REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 -REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 -REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 -REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc -REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd -REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 -REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 -REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 -REG_A6XX_RBBM_STATUS = 0x00000210 -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 -A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 -A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 -A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 -A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 -A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 -A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 -A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 -A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 -A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 -A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 -A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 -A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 -A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 -A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 -A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 -A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 -A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 -A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 -A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 -A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 -A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 -A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 -A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 -REG_A6XX_RBBM_STATUS1 = 0x00000211 -REG_A6XX_RBBM_STATUS2 = 0x00000212 -REG_A6XX_RBBM_STATUS3 = 0x00000213 -A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 -REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 -REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 -REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 -REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 -REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 -REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 -REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 -REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 -REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 -REG_A6XX_RBBM_PERFCTR_CP = lambda i0: (0x00000400 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000041c + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_PC = lambda i0: (0x00000424 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000434 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000444 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000450 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000045c + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000466 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000046e + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000476 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_TP = lambda i0: (0x0000048e + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_SP = lambda i0: (0x000004a6 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_RB = lambda i0: (0x000004d6 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_VSC = lambda i0: (0x000004e6 + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000004ea + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_CMP = lambda i0: (0x000004f2 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_CP = lambda i0: (0x00000300 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000031c + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_PC = lambda i0: (0x00000324 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000334 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000344 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000350 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000035c + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000366 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000036e + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000376 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_TP = lambda i0: (0x0000038e + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_SP = lambda i0: (0x000003a6 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_RB = lambda i0: (0x000003d6 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_VSC = lambda i0: (0x000003e6 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000003ea + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_CMP = lambda i0: (0x000003f2 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_UFC = lambda i0: (0x000003fa + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR2_HLSQ = lambda i0: (0x00000410 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR2_CP = lambda i0: (0x0000041c + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR2_SP = lambda i0: (0x0000042a + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR2_TP = lambda i0: (0x00000442 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR2_UFC = lambda i0: (0x0000044e + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_PC = lambda i0: (0x00000460 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_VFD = lambda i0: (0x00000470 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_VPC = lambda i0: (0x00000480 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_TSE = lambda i0: (0x0000048c + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_RAS = lambda i0: (0x00000494 + 0x2*i0 ) -REG_A7XX_RBBM_PERFCTR_BV_LRZ = lambda i0: (0x0000049c + 0x2*i0 ) -REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 -REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 -REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 -REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 -REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 -REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 -REG_A6XX_RBBM_PERFCTR_RBBM_SEL = lambda i0: (0x00000507 + 0x1*i0 ) -REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e -REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f -REG_A6XX_RBBM_ISDB_CNT = 0x00000533 -REG_A7XX_RBBM_NC_MODE_CNTL = 0x00000534 -REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 -REG_A6XX_RBBM_PRIMCTR_0_LO = 0x00000540 -REG_A6XX_RBBM_PRIMCTR_0_HI = 0x00000541 -REG_A6XX_RBBM_PRIMCTR_1_LO = 0x00000542 -REG_A6XX_RBBM_PRIMCTR_1_HI = 0x00000543 -REG_A6XX_RBBM_PRIMCTR_2_LO = 0x00000544 -REG_A6XX_RBBM_PRIMCTR_2_HI = 0x00000545 -REG_A6XX_RBBM_PRIMCTR_3_LO = 0x00000546 -REG_A6XX_RBBM_PRIMCTR_3_HI = 0x00000547 -REG_A6XX_RBBM_PRIMCTR_4_LO = 0x00000548 -REG_A6XX_RBBM_PRIMCTR_4_HI = 0x00000549 -REG_A6XX_RBBM_PRIMCTR_5_LO = 0x0000054a -REG_A6XX_RBBM_PRIMCTR_5_HI = 0x0000054b -REG_A6XX_RBBM_PRIMCTR_6_LO = 0x0000054c -REG_A6XX_RBBM_PRIMCTR_6_HI = 0x0000054d -REG_A6XX_RBBM_PRIMCTR_7_LO = 0x0000054e -REG_A6XX_RBBM_PRIMCTR_7_HI = 0x0000054f -REG_A6XX_RBBM_PRIMCTR_8_LO = 0x00000550 -REG_A6XX_RBBM_PRIMCTR_8_HI = 0x00000551 -REG_A6XX_RBBM_PRIMCTR_9_LO = 0x00000552 -REG_A6XX_RBBM_PRIMCTR_9_HI = 0x00000553 -REG_A6XX_RBBM_PRIMCTR_10_LO = 0x00000554 -REG_A6XX_RBBM_PRIMCTR_10_HI = 0x00000555 -REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 -REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 -REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 -REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 -REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 -REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 -REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 -REG_A6XX_RBBM_GBIF_HALT = 0x00000016 -REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 -REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c -A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 -REG_A7XX_RBBM_GBIF_HALT = 0x00000016 -REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 -REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f -REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 -REG_A6XX_RBBM_INT_0_MASK = 0x00000038 -REG_A7XX_RBBM_INT_2_MASK = 0x0000003a -REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 -REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 -REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 -REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 -REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad -REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae -REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 -REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 -REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 -REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 -REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 -REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 -REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 -REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 -REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 -REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 -REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba -REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb -REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc -REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd -REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be -REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf -REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 -REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 -REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 -REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 -REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 -REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 -REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 -REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 -REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 -REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 -REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca -REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb -REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc -REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd -REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce -REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf -REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 -REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 -REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 -REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 -REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 -REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 -REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 -REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 -REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 -REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 -REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da -REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db -REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc -REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd -REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de -REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df -REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 -REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 -REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 -REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 -REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 -REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 -REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 -REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 -REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 -REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 -REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea -REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb -REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec -REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed -REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee -REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef -REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 -REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 -REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 -REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 -REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 -REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 -REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 -REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 -REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 -REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 -REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa -REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 -REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 -REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 -REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 -REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 -REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 -REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 -REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 -REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a -REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b -REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c -REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d -REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e -REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f -REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 -REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 -REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 -REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 -REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 -REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 -REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 -REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 -REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 -REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a -REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b -REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c -REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d -REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e -REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f -REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 -REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 -REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 -REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 -A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 -REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 -REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 -REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 -REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 -REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 -REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 -REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 -REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a -REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b -REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f -REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff -REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 -REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 -REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 -REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 -A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 -REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f -A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 -A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 -A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 -REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 -A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a -REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e -REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 -REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 -A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f -REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 -REG_A6XX_VSC_PERFCTR_VSC_SEL = lambda i0: (0x00000cd8 + 0x1*i0 ) -REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 -A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 -REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 -REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 -REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 -REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 -REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 -REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 -REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 -REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b -REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d -REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 -REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 -REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 -A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff -A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 -REG_A6XX_UCHE_PERFCTR_UCHE_SEL = lambda i0: (0x00000e1c + 0x1*i0 ) -REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a -REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c -REG_A6XX_VBIF_VERSION = 0x00003000 -REG_A6XX_VBIF_CLKON = 0x00003001 -A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 -REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a -REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 -REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 -REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 -REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 -REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f -A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 -REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 -REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff -A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 -REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c -REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 -REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 -REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 -REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 -REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 -REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 -REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da -REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db -REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 -REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 -REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 -REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 -REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 -REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 -REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 -REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 -REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 -REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 -REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a -REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 -REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 -REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 -REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 -REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 -REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 -REG_A6XX_GBIF_HALT = 0x00003c45 -REG_A6XX_GBIF_HALT_ACK = 0x00003c46 -REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 -REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 -REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 -REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 -REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 -REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 -REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 -REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 -REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 -REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 -REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca -REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb -REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc -REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd -REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce -REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf -REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 -REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 -REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 -REG_A6XX_VSC_BIN_SIZE = 0x00000c02 -A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff -A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 -A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 -A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 -REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS = 0x00000c03 -REG_A6XX_VSC_BIN_COUNT = 0x00000c06 -A6XX_VSC_BIN_COUNT_NX__MASK = 0x000007fe -A6XX_VSC_BIN_COUNT_NX__SHIFT = 1 -A6XX_VSC_BIN_COUNT_NY__MASK = 0x001ff800 -A6XX_VSC_BIN_COUNT_NY__SHIFT = 11 -REG_A6XX_VSC_PIPE_CONFIG = lambda i0: (0x00000c10 + 0x1*i0 ) -A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff -A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 -A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 -A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 -A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 -A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 -A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 -A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 -REG_A6XX_VSC_PRIM_STRM_ADDRESS = 0x00000c30 -REG_A6XX_VSC_PRIM_STRM_PITCH = 0x00000c32 -REG_A6XX_VSC_PRIM_STRM_LIMIT = 0x00000c33 -REG_A6XX_VSC_DRAW_STRM_ADDRESS = 0x00000c34 -REG_A6XX_VSC_DRAW_STRM_PITCH = 0x00000c36 -REG_A6XX_VSC_DRAW_STRM_LIMIT = 0x00000c37 -REG_A6XX_VSC_STATE = lambda i0: (0x00000c38 + 0x1*i0 ) -REG_A6XX_VSC_PRIM_STRM_SIZE = lambda i0: (0x00000c58 + 0x1*i0 ) -REG_A6XX_VSC_DRAW_STRM_SIZE = lambda i0: (0x00000c78 + 0x1*i0 ) -REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 -REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 -REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 -REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 -REG_A6XX_GRAS_CL_CNTL = 0x00008000 -A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 -A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 -A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 -A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 -A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 -A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 -A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 -A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 -REG_A6XX_GRAS_VS_CL_CNTL = 0x00008001 -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 -A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT = 8 -REG_A6XX_GRAS_DS_CL_CNTL = 0x00008002 -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 -A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT = 8 -REG_A6XX_GRAS_GS_CL_CNTL = 0x00008003 -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 -A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT = 8 -REG_A6XX_GRAS_MAX_LAYER_INDEX = 0x00008004 -REG_A6XX_GRAS_CNTL = 0x00008005 -A6XX_GRAS_CNTL_IJ_PERSP_PIXEL = 0x00000001 -A6XX_GRAS_CNTL_IJ_PERSP_CENTROID = 0x00000002 -A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE = 0x00000004 -A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL = 0x00000008 -A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID = 0x00000010 -A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 -A6XX_GRAS_CNTL_COORD_MASK__MASK = 0x000003c0 -A6XX_GRAS_CNTL_COORD_MASK__SHIFT = 6 -A6XX_GRAS_CNTL_UNK10 = 0x00000400 -A6XX_GRAS_CNTL_UNK11 = 0x00000800 -REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 -A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 -REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 -REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 -REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 -REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a -REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b -REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c -REG_A6XX_GRAS_CL_VPORT = lambda i0: (0x00008010 + 0x6*i0 ) -A6XX_GRAS_CL_VPORT_XOFFSET__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT = 0 -A6XX_GRAS_CL_VPORT_XSCALE__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_XSCALE__SHIFT = 0 -A6XX_GRAS_CL_VPORT_YOFFSET__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT = 0 -A6XX_GRAS_CL_VPORT_YSCALE__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_YSCALE__SHIFT = 0 -A6XX_GRAS_CL_VPORT_ZOFFSET__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT = 0 -A6XX_GRAS_CL_VPORT_ZSCALE__MASK = 0xffffffff -A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT = 0 -REG_A6XX_GRAS_CL_Z_CLAMP = lambda i0: (0x00008070 + 0x2*i0 ) -A6XX_GRAS_CL_Z_CLAMP_MIN__MASK = 0xffffffff -A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT = 0 -A6XX_GRAS_CL_Z_CLAMP_MAX__MASK = 0xffffffff -A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT = 0 -REG_A6XX_GRAS_SU_CNTL = 0x00008090 -A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 -A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 -A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 -A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 -A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 -A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 -A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 -A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 -A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 -A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 -A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 -A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 -A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 -A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 -A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 -REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 -A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff -A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 -A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 -A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 -REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 -A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff -A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 -REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 -A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 -REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 -A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff -A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff -A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 -REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff -A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 -REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 -A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 -REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 -A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 -REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a -A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 -A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 -REG_A6XX_GRAS_VS_LAYER_CNTL = 0x0000809b -A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER = 0x00000001 -A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW = 0x00000002 -REG_A6XX_GRAS_GS_LAYER_CNTL = 0x0000809c -A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER = 0x00000001 -A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW = 0x00000002 -REG_A6XX_GRAS_DS_LAYER_CNTL = 0x0000809d -A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER = 0x00000001 -A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW = 0x00000002 -REG_A6XX_GRAS_SC_CNTL = 0x000080a0 -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 -A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 -A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 -A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 -A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 -A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 -A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 -A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 -A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 -A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 -A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 -REG_A6XX_GRAS_BIN_CONTROL = 0x000080a1 -A6XX_GRAS_BIN_CONTROL_BINW__MASK = 0x0000003f -A6XX_GRAS_BIN_CONTROL_BINW__SHIFT = 0 -A6XX_GRAS_BIN_CONTROL_BINH__MASK = 0x00007f00 -A6XX_GRAS_BIN_CONTROL_BINH__SHIFT = 8 -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 -A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT = 18 -A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 -A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 -A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 -A6XX_GRAS_BIN_CONTROL_UNK27 = 0x08000000 -REG_A6XX_GRAS_RAS_MSAA_CNTL = 0x000080a2 -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_GRAS_RAS_MSAA_CNTL_UNK2 = 0x00000004 -A6XX_GRAS_RAS_MSAA_CNTL_UNK3 = 0x00000008 -REG_A6XX_GRAS_DEST_MSAA_CNTL = 0x000080a3 -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 -REG_A6XX_GRAS_SAMPLE_CONFIG = 0x000080a4 -A6XX_GRAS_SAMPLE_CONFIG_UNK0 = 0x00000001 -A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 -REG_A6XX_GRAS_SAMPLE_LOCATION_0 = 0x000080a5 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 -REG_A6XX_GRAS_SAMPLE_LOCATION_1 = 0x000080a6 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 -REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 -REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af -REG_A6XX_GRAS_SC_SCREEN_SCISSOR = lambda i0: (0x000080b0 + 0x2*i0 ) -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 -A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 -A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 -REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR = lambda i0: (0x000080d0 + 0x2*i0 ) -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 -A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 -A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 -A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 -REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 -A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 -REG_A7XX_GRAS_UNKNOWN_80F4 = 0x000080f4 -REG_A7XX_GRAS_UNKNOWN_80F5 = 0x000080f5 -REG_A7XX_GRAS_UNKNOWN_80F6 = 0x000080f6 -REG_A7XX_GRAS_UNKNOWN_80F8 = 0x000080f8 -REG_A7XX_GRAS_UNKNOWN_80F9 = 0x000080f9 -REG_A7XX_GRAS_UNKNOWN_80FA = 0x000080fa -REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 -A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 -A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 -A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 -A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 -A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE = 0x00000010 -A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 -A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 -A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 -A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 -A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 -A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 -A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 -REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 -A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 -A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 -REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 = 0x00008102 -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK = 0x000000ff -A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT = 0 -REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 -REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff -A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 -A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 -REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 -REG_A6XX_GRAS_SAMPLE_CNTL = 0x00008109 -A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 -REG_A6XX_GRAS_LRZ_DEPTH_VIEW = 0x0000810a -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK = 0x000007ff -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT = 0 -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK = 0x07ff0000 -A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT = 16 -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK = 0xf0000000 -A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT = 28 -REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b -A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 -A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 -REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 -REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 = 0x00008111 -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK = 0xffffffff -A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT = 0 -REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 -A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 -REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 -REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 -REG_A6XX_GRAS_2D_BLIT_CNTL = 0x00008400 -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 -A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT = 0 -A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 -A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 -A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT = 4 -A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 -A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 -A6XX_GRAS_2D_BLIT_CNTL_SCISSOR = 0x00010000 -A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 -A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT = 17 -A6XX_GRAS_2D_BLIT_CNTL_D24S8 = 0x00080000 -A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 -A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT = 20 -A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 -A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT = 24 -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 -A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 -A6XX_GRAS_2D_BLIT_CNTL_UNK30 = 0x40000000 -REG_A6XX_GRAS_2D_SRC_TL_X = 0x00008401 -A6XX_GRAS_2D_SRC_TL_X__MASK = 0x01ffff00 -A6XX_GRAS_2D_SRC_TL_X__SHIFT = 8 -REG_A6XX_GRAS_2D_SRC_BR_X = 0x00008402 -A6XX_GRAS_2D_SRC_BR_X__MASK = 0x01ffff00 -A6XX_GRAS_2D_SRC_BR_X__SHIFT = 8 -REG_A6XX_GRAS_2D_SRC_TL_Y = 0x00008403 -A6XX_GRAS_2D_SRC_TL_Y__MASK = 0x01ffff00 -A6XX_GRAS_2D_SRC_TL_Y__SHIFT = 8 -REG_A6XX_GRAS_2D_SRC_BR_Y = 0x00008404 -A6XX_GRAS_2D_SRC_BR_Y__MASK = 0x01ffff00 -A6XX_GRAS_2D_SRC_BR_Y__SHIFT = 8 -REG_A6XX_GRAS_2D_DST_TL = 0x00008405 -A6XX_GRAS_2D_DST_TL_X__MASK = 0x00003fff -A6XX_GRAS_2D_DST_TL_X__SHIFT = 0 -A6XX_GRAS_2D_DST_TL_Y__MASK = 0x3fff0000 -A6XX_GRAS_2D_DST_TL_Y__SHIFT = 16 -REG_A6XX_GRAS_2D_DST_BR = 0x00008406 -A6XX_GRAS_2D_DST_BR_X__MASK = 0x00003fff -A6XX_GRAS_2D_DST_BR_X__SHIFT = 0 -A6XX_GRAS_2D_DST_BR_Y__MASK = 0x3fff0000 -A6XX_GRAS_2D_DST_BR_Y__SHIFT = 16 -REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 -REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 -REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 -REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 = 0x0000840a -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK = 0x00003fff -A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT = 0 -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 -A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT = 16 -REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 = 0x0000840b -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK = 0x00003fff -A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT = 0 -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 -A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT = 16 -REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 -A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 -A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 -REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 -REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 -REG_A6XX_GRAS_PERFCTR_TSE_SEL = lambda i0: (0x00008610 + 0x1*i0 ) -REG_A6XX_GRAS_PERFCTR_RAS_SEL = lambda i0: (0x00008614 + 0x1*i0 ) -REG_A6XX_GRAS_PERFCTR_LRZ_SEL = lambda i0: (0x00008618 + 0x1*i0 ) -REG_A6XX_RB_BIN_CONTROL = 0x00008800 -A6XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f -A6XX_RB_BIN_CONTROL_BINW__SHIFT = 0 -A6XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 -A6XX_RB_BIN_CONTROL_BINH__SHIFT = 8 -A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 -A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 -A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 -A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 -A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 -REG_A7XX_RB_BIN_CONTROL = 0x00008800 -A7XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f -A7XX_RB_BIN_CONTROL_BINW__SHIFT = 0 -A7XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 -A7XX_RB_BIN_CONTROL_BINH__SHIFT = 8 -A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 -A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 -A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 -A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 -REG_A6XX_RB_RENDER_CNTL = 0x00008801 -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 -A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 -A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 -A6XX_RB_RENDER_CNTL_BINNING = 0x00000080 -A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 -A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 -A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 -A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 -A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 -A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 -A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 -A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 -A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 -A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 -REG_A7XX_RB_RENDER_CNTL = 0x00008801 -A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 -A7XX_RB_RENDER_CNTL_BINNING = 0x00000080 -A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 -A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 -A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 -A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 -A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 -REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 -A7XX_GRAS_SU_RENDER_CNTL_BINNING = 0x00000080 -REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 -A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 -REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 -REG_A6XX_RB_SAMPLE_CONFIG = 0x00008804 -A6XX_RB_SAMPLE_CONFIG_UNK0 = 0x00000001 -A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 -REG_A6XX_RB_SAMPLE_LOCATION_0 = 0x00008805 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 -REG_A6XX_RB_SAMPLE_LOCATION_1 = 0x00008806 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 -REG_A6XX_RB_RENDER_CONTROL0 = 0x00008809 -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL = 0x00000001 -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID = 0x00000002 -A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE = 0x00000004 -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL = 0x00000008 -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID = 0x00000010 -A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE = 0x00000020 -A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK = 0x000003c0 -A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT = 6 -A6XX_RB_RENDER_CONTROL0_UNK10 = 0x00000400 -REG_A6XX_RB_RENDER_CONTROL1 = 0x0000880a -A6XX_RB_RENDER_CONTROL1_SAMPLEMASK = 0x00000001 -A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE = 0x00000002 -A6XX_RB_RENDER_CONTROL1_FACENESS = 0x00000004 -A6XX_RB_RENDER_CONTROL1_SAMPLEID = 0x00000008 -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 -A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT = 4 -A6XX_RB_RENDER_CONTROL1_CENTERRHW = 0x00000040 -A6XX_RB_RENDER_CONTROL1_LINELENGTHEN = 0x00000080 -A6XX_RB_RENDER_CONTROL1_FOVEATION = 0x00000100 -REG_A6XX_RB_FS_OUTPUT_CNTL0 = 0x0000880b -A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z = 0x00000002 -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK = 0x00000004 -A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF = 0x00000008 -REG_A6XX_RB_FS_OUTPUT_CNTL1 = 0x0000880c -A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f -A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 -REG_A6XX_RB_RENDER_COMPONENTS = 0x0000880d -A6XX_RB_RENDER_COMPONENTS_RT0__MASK = 0x0000000f -A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT = 0 -A6XX_RB_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 -A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT = 4 -A6XX_RB_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 -A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT = 8 -A6XX_RB_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 -A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT = 12 -A6XX_RB_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 -A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT = 16 -A6XX_RB_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 -A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT = 20 -A6XX_RB_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 -A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT = 24 -A6XX_RB_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 -A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT = 28 -REG_A6XX_RB_DITHER_CNTL = 0x0000880e -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 -A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 -REG_A6XX_RB_SRGB_CNTL = 0x0000880f -A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 -A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 -A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 -A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 -A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 -A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 -A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 -A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 -REG_A6XX_RB_SAMPLE_CNTL = 0x00008810 -A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 -REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 -REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 -REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 -REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 -REG_A6XX_RB_UNKNOWN_881A = 0x0000881a -REG_A6XX_RB_UNKNOWN_881B = 0x0000881b -REG_A6XX_RB_UNKNOWN_881C = 0x0000881c -REG_A6XX_RB_UNKNOWN_881D = 0x0000881d -REG_A6XX_RB_UNKNOWN_881E = 0x0000881e -REG_A6XX_RB_MRT = lambda i0: (0x00008820 + 0x8*i0 ) -A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 -A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 -A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 -A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 -A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 -A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f -A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 -A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 -A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 -A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff -A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 -A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 -A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 -A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff -A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 -A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 -A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 -A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 -A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 -A6XX_RB_MRT_PITCH__MASK = 0xffffffff -A6XX_RB_MRT_PITCH__SHIFT = 0 -A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff -A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 -REG_A6XX_RB_BLEND_RED_F32 = 0x00008860 -A6XX_RB_BLEND_RED_F32__MASK = 0xffffffff -A6XX_RB_BLEND_RED_F32__SHIFT = 0 -REG_A6XX_RB_BLEND_GREEN_F32 = 0x00008861 -A6XX_RB_BLEND_GREEN_F32__MASK = 0xffffffff -A6XX_RB_BLEND_GREEN_F32__SHIFT = 0 -REG_A6XX_RB_BLEND_BLUE_F32 = 0x00008862 -A6XX_RB_BLEND_BLUE_F32__MASK = 0xffffffff -A6XX_RB_BLEND_BLUE_F32__SHIFT = 0 -REG_A6XX_RB_BLEND_ALPHA_F32 = 0x00008863 -A6XX_RB_BLEND_ALPHA_F32__MASK = 0xffffffff -A6XX_RB_BLEND_ALPHA_F32__SHIFT = 0 -REG_A6XX_RB_ALPHA_CONTROL = 0x00008864 -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK = 0x000000ff -A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT = 0 -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST = 0x00000100 -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK = 0x00000e00 -A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT = 9 -REG_A6XX_RB_BLEND_CNTL = 0x00008865 -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff -A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 -A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 -A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 -A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 -A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 -A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 -REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 -A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 -REG_A6XX_RB_DEPTH_CNTL = 0x00008871 -A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 -A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 -A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c -A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 -A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 -A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 -A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 -REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 -A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 -REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 -A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 -A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 -REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 -A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 -A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 -A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 -A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 -REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 -A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff -A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 -REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff -A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 -REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 -REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM = 0x00008877 -REG_A6XX_RB_Z_BOUNDS_MIN = 0x00008878 -A6XX_RB_Z_BOUNDS_MIN__MASK = 0xffffffff -A6XX_RB_Z_BOUNDS_MIN__SHIFT = 0 -REG_A6XX_RB_Z_BOUNDS_MAX = 0x00008879 -A6XX_RB_Z_BOUNDS_MAX__MASK = 0xffffffff -A6XX_RB_Z_BOUNDS_MAX__SHIFT = 0 -REG_A6XX_RB_STENCIL_CONTROL = 0x00008880 -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE = 0x00000001 -A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF = 0x00000002 -A6XX_RB_STENCIL_CONTROL_STENCIL_READ = 0x00000004 -A6XX_RB_STENCIL_CONTROL_FUNC__MASK = 0x00000700 -A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT = 8 -A6XX_RB_STENCIL_CONTROL_FAIL__MASK = 0x00003800 -A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT = 11 -A6XX_RB_STENCIL_CONTROL_ZPASS__MASK = 0x0001c000 -A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT = 14 -A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK = 0x000e0000 -A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT = 17 -A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK = 0x00700000 -A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT = 20 -A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK = 0x03800000 -A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT = 23 -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK = 0x1c000000 -A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT = 26 -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK = 0xe0000000 -A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT = 29 -REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 -A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 -REG_A6XX_RB_STENCIL_INFO = 0x00008881 -A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 -A6XX_RB_STENCIL_INFO_UNK1 = 0x00000002 -REG_A7XX_RB_STENCIL_INFO = 0x00008881 -A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 -A7XX_RB_STENCIL_INFO_UNK1 = 0x00000002 -A7XX_RB_STENCIL_INFO_TILEMODE__MASK = 0x0000000c -A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT = 2 -REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 -A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff -A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 -REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff -A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 -REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 -REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM = 0x00008886 -REG_A6XX_RB_STENCILREF = 0x00008887 -A6XX_RB_STENCILREF_REF__MASK = 0x000000ff -A6XX_RB_STENCILREF_REF__SHIFT = 0 -A6XX_RB_STENCILREF_BFREF__MASK = 0x0000ff00 -A6XX_RB_STENCILREF_BFREF__SHIFT = 8 -REG_A6XX_RB_STENCILMASK = 0x00008888 -A6XX_RB_STENCILMASK_MASK__MASK = 0x000000ff -A6XX_RB_STENCILMASK_MASK__SHIFT = 0 -A6XX_RB_STENCILMASK_BFMASK__MASK = 0x0000ff00 -A6XX_RB_STENCILMASK_BFMASK__SHIFT = 8 -REG_A6XX_RB_STENCILWRMASK = 0x00008889 -A6XX_RB_STENCILWRMASK_WRMASK__MASK = 0x000000ff -A6XX_RB_STENCILWRMASK_WRMASK__SHIFT = 0 -A6XX_RB_STENCILWRMASK_BFWRMASK__MASK = 0x0000ff00 -A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT = 8 -REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 -A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff -A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 -A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 -A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 -REG_A6XX_RB_SAMPLE_COUNT_CONTROL = 0x00008891 -A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE = 0x00000001 -A6XX_RB_SAMPLE_COUNT_CONTROL_COPY = 0x00000002 -REG_A6XX_RB_LRZ_CNTL = 0x00008898 -A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 -REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 -REG_A6XX_RB_Z_CLAMP_MIN = 0x000088c0 -A6XX_RB_Z_CLAMP_MIN__MASK = 0xffffffff -A6XX_RB_Z_CLAMP_MIN__SHIFT = 0 -REG_A6XX_RB_Z_CLAMP_MAX = 0x000088c1 -A6XX_RB_Z_CLAMP_MAX__MASK = 0xffffffff -A6XX_RB_Z_CLAMP_MAX__SHIFT = 0 -REG_A6XX_RB_UNKNOWN_88D0 = 0x000088d0 -A6XX_RB_UNKNOWN_88D0_UNK0__MASK = 0x00001fff -A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT = 0 -A6XX_RB_UNKNOWN_88D0_UNK16__MASK = 0x07ff0000 -A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT = 16 -REG_A6XX_RB_BLIT_SCISSOR_TL = 0x000088d1 -A6XX_RB_BLIT_SCISSOR_TL_X__MASK = 0x00003fff -A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT = 0 -A6XX_RB_BLIT_SCISSOR_TL_Y__MASK = 0x3fff0000 -A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT = 16 -REG_A6XX_RB_BLIT_SCISSOR_BR = 0x000088d2 -A6XX_RB_BLIT_SCISSOR_BR_X__MASK = 0x00003fff -A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT = 0 -A6XX_RB_BLIT_SCISSOR_BR_Y__MASK = 0x3fff0000 -A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT = 16 -REG_A6XX_RB_BIN_CONTROL2 = 0x000088d3 -A6XX_RB_BIN_CONTROL2_BINW__MASK = 0x0000003f -A6XX_RB_BIN_CONTROL2_BINW__SHIFT = 0 -A6XX_RB_BIN_CONTROL2_BINH__MASK = 0x00007f00 -A6XX_RB_BIN_CONTROL2_BINH__SHIFT = 8 -REG_A6XX_RB_WINDOW_OFFSET2 = 0x000088d4 -A6XX_RB_WINDOW_OFFSET2_X__MASK = 0x00003fff -A6XX_RB_WINDOW_OFFSET2_X__SHIFT = 0 -A6XX_RB_WINDOW_OFFSET2_Y__MASK = 0x3fff0000 -A6XX_RB_WINDOW_OFFSET2_Y__SHIFT = 16 -REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL = 0x000088d5 -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK = 0x00000018 -A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT = 3 -REG_A6XX_RB_BLIT_BASE_GMEM = 0x000088d6 -REG_A6XX_RB_BLIT_DST_INFO = 0x000088d7 -A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK = 0x00000003 -A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT = 0 -A6XX_RB_BLIT_DST_INFO_FLAGS = 0x00000004 -A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK = 0x00000018 -A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT = 3 -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK = 0x00000060 -A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT = 5 -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK = 0x00007f80 -A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT = 7 -A6XX_RB_BLIT_DST_INFO_UNK15 = 0x00008000 -REG_A6XX_RB_BLIT_DST = 0x000088d8 -REG_A6XX_RB_BLIT_DST_PITCH = 0x000088da -A6XX_RB_BLIT_DST_PITCH__MASK = 0x0000ffff -A6XX_RB_BLIT_DST_PITCH__SHIFT = 0 -REG_A6XX_RB_BLIT_DST_ARRAY_PITCH = 0x000088db -A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK = 0x1fffffff -A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT = 0 -REG_A6XX_RB_BLIT_FLAG_DST = 0x000088dc -REG_A6XX_RB_BLIT_FLAG_DST_PITCH = 0x000088de -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK = 0x000007ff -A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT = 0 -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 -A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT = 11 -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 = 0x000088df -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 = 0x000088e0 -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 = 0x000088e1 -REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 = 0x000088e2 -REG_A6XX_RB_BLIT_INFO = 0x000088e3 -A6XX_RB_BLIT_INFO_UNK0 = 0x00000001 -A6XX_RB_BLIT_INFO_GMEM = 0x00000002 -A6XX_RB_BLIT_INFO_SAMPLE_0 = 0x00000004 -A6XX_RB_BLIT_INFO_DEPTH = 0x00000008 -A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK = 0x000000f0 -A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT = 4 -A6XX_RB_BLIT_INFO_LAST__MASK = 0x00000300 -A6XX_RB_BLIT_INFO_LAST__SHIFT = 8 -A6XX_RB_BLIT_INFO_BUFFER_ID__MASK = 0x0000f000 -A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT = 12 -REG_A7XX_RB_UNKNOWN_88E4 = 0x000088e4 -A7XX_RB_UNKNOWN_88E4_UNK0 = 0x00000001 -REG_A7XX_RB_CCU_CNTL2 = 0x000088e5 -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK = 0x00000001 -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT = 0 -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK = 0x00000004 -A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT = 2 -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK = 0x00000c00 -A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT = 10 -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK = 0x001ff000 -A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT = 12 -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK = 0x00600000 -A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT = 21 -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK = 0xff800000 -A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT = 23 -REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 -REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 -REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff -A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 -A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 -REG_A6XX_RB_UNKNOWN_88F4 = 0x000088f4 -REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 -REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 -REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 -A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 -REG_A6XX_RB_MRT_FLAG_BUFFER = lambda i0: (0x00008903 + 0x3*i0 ) -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff -A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 -A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 -REG_A6XX_RB_SAMPLE_COUNT_ADDR = 0x00008927 -REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 -REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 -REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 -REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 -REG_A6XX_RB_2D_BLIT_CNTL = 0x00008c00 -A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 -A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT = 0 -A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 -A6XX_RB_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 -A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT = 4 -A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 -A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 -A6XX_RB_2D_BLIT_CNTL_SCISSOR = 0x00010000 -A6XX_RB_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 -A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT = 17 -A6XX_RB_2D_BLIT_CNTL_D24S8 = 0x00080000 -A6XX_RB_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 -A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT = 20 -A6XX_RB_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 -A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT = 24 -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 -A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 -A6XX_RB_2D_BLIT_CNTL_UNK30 = 0x40000000 -REG_A6XX_RB_2D_UNKNOWN_8C01 = 0x00008c01 -REG_A6XX_RB_2D_DST_INFO = 0x00008c17 -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK = 0x000000ff -A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT = 0 -A6XX_RB_2D_DST_INFO_TILE_MODE__MASK = 0x00000300 -A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT = 8 -A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK = 0x00000c00 -A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT = 10 -A6XX_RB_2D_DST_INFO_FLAGS = 0x00001000 -A6XX_RB_2D_DST_INFO_SRGB = 0x00002000 -A6XX_RB_2D_DST_INFO_SAMPLES__MASK = 0x0000c000 -A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT = 14 -A6XX_RB_2D_DST_INFO_FILTER = 0x00010000 -A6XX_RB_2D_DST_INFO_UNK17 = 0x00020000 -A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE = 0x00040000 -A6XX_RB_2D_DST_INFO_UNK19 = 0x00080000 -A6XX_RB_2D_DST_INFO_UNK20 = 0x00100000 -A6XX_RB_2D_DST_INFO_UNK21 = 0x00200000 -A6XX_RB_2D_DST_INFO_UNK22 = 0x00400000 -A6XX_RB_2D_DST_INFO_UNK23__MASK = 0x07800000 -A6XX_RB_2D_DST_INFO_UNK23__SHIFT = 23 -A6XX_RB_2D_DST_INFO_UNK28 = 0x10000000 -REG_A6XX_RB_2D_DST = 0x00008c18 -REG_A6XX_RB_2D_DST_PITCH = 0x00008c1a -A6XX_RB_2D_DST_PITCH__MASK = 0x0000ffff -A6XX_RB_2D_DST_PITCH__SHIFT = 0 -REG_A6XX_RB_2D_DST_PLANE1 = 0x00008c1b -REG_A6XX_RB_2D_DST_PLANE_PITCH = 0x00008c1d -A6XX_RB_2D_DST_PLANE_PITCH__MASK = 0x0000ffff -A6XX_RB_2D_DST_PLANE_PITCH__SHIFT = 0 -REG_A6XX_RB_2D_DST_PLANE2 = 0x00008c1e -REG_A6XX_RB_2D_DST_FLAGS = 0x00008c20 -REG_A6XX_RB_2D_DST_FLAGS_PITCH = 0x00008c22 -A6XX_RB_2D_DST_FLAGS_PITCH__MASK = 0x000000ff -A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT = 0 -REG_A6XX_RB_2D_DST_FLAGS_PLANE = 0x00008c23 -REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH = 0x00008c25 -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK = 0x000000ff -A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT = 0 -REG_A6XX_RB_2D_SRC_SOLID_C0 = 0x00008c2c -REG_A6XX_RB_2D_SRC_SOLID_C1 = 0x00008c2d -REG_A6XX_RB_2D_SRC_SOLID_C2 = 0x00008c2e -REG_A6XX_RB_2D_SRC_SOLID_C3 = 0x00008c2f -REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 -REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 -REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 -REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 -REG_A7XX_RB_UNKNOWN_8E06 = 0x00008e06 -REG_A6XX_RB_CCU_CNTL = 0x00008e07 -A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 -A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 -A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 -A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 -A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 -A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 -A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 -A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 -A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 -REG_A7XX_RB_CCU_CNTL = 0x00008e07 -A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 -A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 -REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 -A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 -A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 -A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 -A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 -A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 -A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 -A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 -A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 -REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 -REG_A6XX_RB_PERFCTR_RB_SEL = lambda i0: (0x00008e10 + 0x1*i0 ) -REG_A6XX_RB_PERFCTR_CCU_SEL = lambda i0: (0x00008e18 + 0x1*i0 ) -REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 -REG_A6XX_RB_PERFCTR_CMP_SEL = lambda i0: (0x00008e2c + 0x1*i0 ) -REG_A7XX_RB_PERFCTR_UFC_SEL = lambda i0: (0x00008e30 + 0x1*i0 ) -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b -REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d -REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE = 0x00008e50 -REG_A6XX_RB_UNKNOWN_8E51 = 0x00008e51 -REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 -REG_A6XX_VPC_GS_PARAM = 0x00009100 -A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff -A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 -REG_A6XX_VPC_VS_CLIP_CNTL = 0x00009101 -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_GS_CLIP_CNTL = 0x00009102 -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_DS_CLIP_CNTL = 0x00009103 -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_VS_CLIP_CNTL_V2 = 0x00009311 -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_GS_CLIP_CNTL_V2 = 0x00009312 -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_DS_CLIP_CNTL_V2 = 0x00009313 -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 -A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 -REG_A6XX_VPC_VS_LAYER_CNTL = 0x00009104 -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT = 0 -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT = 8 -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_GS_LAYER_CNTL = 0x00009105 -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT = 0 -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT = 8 -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_DS_LAYER_CNTL = 0x00009106 -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT = 0 -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT = 8 -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_VS_LAYER_CNTL_V2 = 0x00009314 -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_GS_LAYER_CNTL_V2 = 0x00009315 -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_DS_LAYER_CNTL_V2 = 0x00009316 -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff -A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 -A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 -A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 -REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 -A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 -A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 -REG_A6XX_VPC_POLYGON_MODE = 0x00009108 -A6XX_VPC_POLYGON_MODE_MODE__MASK = 0x00000003 -A6XX_VPC_POLYGON_MODE_MODE__SHIFT = 0 -REG_A7XX_VPC_PRIMITIVE_CNTL_0 = 0x00009109 -A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 -A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 -A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 -A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 -REG_A7XX_VPC_PRIMITIVE_CNTL_5 = 0x0000910a -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff -A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 -A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 -A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 -A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 -A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 -REG_A7XX_VPC_MULTIVIEW_MASK = 0x0000910b -REG_A7XX_VPC_MULTIVIEW_CNTL = 0x0000910c -A7XX_VPC_MULTIVIEW_CNTL_ENABLE = 0x00000001 -A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c -A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 -REG_A6XX_VPC_VARYING_INTERP = lambda i0: (0x00009200 + 0x1*i0 ) -REG_A6XX_VPC_VARYING_PS_REPL = lambda i0: (0x00009208 + 0x1*i0 ) -REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 -REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 -REG_A6XX_VPC_VAR = lambda i0: (0x00009212 + 0x1*i0 ) -REG_A6XX_VPC_SO_CNTL = 0x00009216 -A6XX_VPC_SO_CNTL_ADDR__MASK = 0x000000ff -A6XX_VPC_SO_CNTL_ADDR__SHIFT = 0 -A6XX_VPC_SO_CNTL_RESET = 0x00010000 -REG_A6XX_VPC_SO_PROG = 0x00009217 -A6XX_VPC_SO_PROG_A_BUF__MASK = 0x00000003 -A6XX_VPC_SO_PROG_A_BUF__SHIFT = 0 -A6XX_VPC_SO_PROG_A_OFF__MASK = 0x000007fc -A6XX_VPC_SO_PROG_A_OFF__SHIFT = 2 -A6XX_VPC_SO_PROG_A_EN = 0x00000800 -A6XX_VPC_SO_PROG_B_BUF__MASK = 0x00003000 -A6XX_VPC_SO_PROG_B_BUF__SHIFT = 12 -A6XX_VPC_SO_PROG_B_OFF__MASK = 0x007fc000 -A6XX_VPC_SO_PROG_B_OFF__SHIFT = 14 -A6XX_VPC_SO_PROG_B_EN = 0x00800000 -REG_A6XX_VPC_SO_STREAM_COUNTS = 0x00009218 -REG_A6XX_VPC_SO = lambda i0: (0x0000921a + 0x7*i0 ) -REG_A6XX_VPC_POINT_COORD_INVERT = 0x00009236 -A6XX_VPC_POINT_COORD_INVERT_INVERT = 0x00000001 -REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 -REG_A6XX_VPC_VS_PACK = 0x00009301 -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT = 0 -A6XX_VPC_VS_PACK_POSITIONLOC__MASK = 0x0000ff00 -A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT = 8 -A6XX_VPC_VS_PACK_PSIZELOC__MASK = 0x00ff0000 -A6XX_VPC_VS_PACK_PSIZELOC__SHIFT = 16 -A6XX_VPC_VS_PACK_EXTRAPOS__MASK = 0x0f000000 -A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT = 24 -REG_A6XX_VPC_GS_PACK = 0x00009302 -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT = 0 -A6XX_VPC_GS_PACK_POSITIONLOC__MASK = 0x0000ff00 -A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT = 8 -A6XX_VPC_GS_PACK_PSIZELOC__MASK = 0x00ff0000 -A6XX_VPC_GS_PACK_PSIZELOC__SHIFT = 16 -A6XX_VPC_GS_PACK_EXTRAPOS__MASK = 0x0f000000 -A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT = 24 -REG_A6XX_VPC_DS_PACK = 0x00009303 -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT = 0 -A6XX_VPC_DS_PACK_POSITIONLOC__MASK = 0x0000ff00 -A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT = 8 -A6XX_VPC_DS_PACK_PSIZELOC__MASK = 0x00ff0000 -A6XX_VPC_DS_PACK_PSIZELOC__SHIFT = 16 -A6XX_VPC_DS_PACK_EXTRAPOS__MASK = 0x0f000000 -A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT = 24 -REG_A6XX_VPC_CNTL_0 = 0x00009304 -A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK = 0x000000ff -A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT = 0 -A6XX_VPC_CNTL_0_PRIMIDLOC__MASK = 0x0000ff00 -A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT = 8 -A6XX_VPC_CNTL_0_VARYING = 0x00010000 -A6XX_VPC_CNTL_0_VIEWIDLOC__MASK = 0xff000000 -A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT = 24 -REG_A6XX_VPC_SO_STREAM_CNTL = 0x00009305 -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK = 0x00000007 -A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT = 0 -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK = 0x00000038 -A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT = 3 -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK = 0x000001c0 -A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT = 6 -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK = 0x00000e00 -A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT = 9 -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 -A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 -REG_A6XX_VPC_SO_DISABLE = 0x00009306 -A6XX_VPC_SO_DISABLE_DISABLE = 0x00000001 -REG_A7XX_VPC_POLYGON_MODE2 = 0x00009307 -A7XX_VPC_POLYGON_MODE2_MODE__MASK = 0x00000003 -A7XX_VPC_POLYGON_MODE2_MODE__SHIFT = 0 -REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM = 0x00009308 -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff -A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 -REG_A7XX_VPC_ATTR_BUF_BASE_GMEM = 0x00009309 -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK = 0xffffffff -A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT = 0 -REG_A7XX_PC_ATTR_BUF_SIZE_GMEM = 0x00009b09 -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff -A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 -REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 -REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 -REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 -REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 -REG_A6XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x00009604 + 0x1*i0 ) -REG_A7XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x0000960b + 0x1*i0 ) -REG_A6XX_PC_TESS_NUM_VERTEX = 0x00009800 -REG_A6XX_PC_HS_INPUT_SIZE = 0x00009801 -A6XX_PC_HS_INPUT_SIZE_SIZE__MASK = 0x000007ff -A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT = 0 -A6XX_PC_HS_INPUT_SIZE_UNK13 = 0x00002000 -REG_A6XX_PC_TESS_CNTL = 0x00009802 -A6XX_PC_TESS_CNTL_SPACING__MASK = 0x00000003 -A6XX_PC_TESS_CNTL_SPACING__SHIFT = 0 -A6XX_PC_TESS_CNTL_OUTPUT__MASK = 0x0000000c -A6XX_PC_TESS_CNTL_OUTPUT__SHIFT = 2 -REG_A6XX_PC_RESTART_INDEX = 0x00009803 -REG_A6XX_PC_MODE_CNTL = 0x00009804 -REG_A6XX_PC_POWER_CNTL = 0x00009805 -REG_A6XX_PC_PS_CNTL = 0x00009806 -A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 -REG_A6XX_PC_SO_STREAM_CNTL = 0x00009808 -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 -A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 -REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a -A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 -REG_A6XX_PC_DRAW_CMD = 0x00009840 -A6XX_PC_DRAW_CMD_STATE_ID__MASK = 0x000000ff -A6XX_PC_DRAW_CMD_STATE_ID__SHIFT = 0 -REG_A6XX_PC_DISPATCH_CMD = 0x00009841 -A6XX_PC_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff -A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT = 0 -REG_A6XX_PC_EVENT_CMD = 0x00009842 -A6XX_PC_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 -A6XX_PC_EVENT_CMD_STATE_ID__SHIFT = 16 -A6XX_PC_EVENT_CMD_EVENT__MASK = 0x0000007f -A6XX_PC_EVENT_CMD_EVENT__SHIFT = 0 -REG_A6XX_PC_MARKER = 0x00009880 -REG_A6XX_PC_POLYGON_MODE = 0x00009981 -A6XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 -A6XX_PC_POLYGON_MODE_MODE__SHIFT = 0 -REG_A7XX_PC_POLYGON_MODE = 0x00009809 -A7XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 -A7XX_PC_POLYGON_MODE_MODE__SHIFT = 0 -REG_A6XX_PC_RASTER_CNTL = 0x00009980 -A6XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 -A6XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 -A6XX_PC_RASTER_CNTL_DISCARD = 0x00000004 -REG_A7XX_PC_RASTER_CNTL = 0x00009107 -A7XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 -A7XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 -A7XX_PC_RASTER_CNTL_DISCARD = 0x00000004 -REG_A7XX_PC_RASTER_CNTL_V2 = 0x00009317 -A7XX_PC_RASTER_CNTL_V2_STREAM__MASK = 0x00000003 -A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT = 0 -A7XX_PC_RASTER_CNTL_V2_DISCARD = 0x00000004 -REG_A7XX_PC_TESS_PARAM_SIZE = 0x00009885 -REG_A7XX_PC_TESS_FACTOR_SIZE = 0x00009886 -REG_A6XX_PC_PRIMITIVE_CNTL_0 = 0x00009b00 -A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 -A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 -A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 -A6XX_PC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 -REG_A6XX_PC_VS_OUT_CNTL = 0x00009b01 -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 -A6XX_PC_VS_OUT_CNTL_PSIZE = 0x00000100 -A6XX_PC_VS_OUT_CNTL_LAYER = 0x00000200 -A6XX_PC_VS_OUT_CNTL_VIEW = 0x00000400 -A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 -A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT = 16 -A6XX_PC_VS_OUT_CNTL_SHADINGRATE = 0x01000000 -REG_A6XX_PC_GS_OUT_CNTL = 0x00009b02 -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 -A6XX_PC_GS_OUT_CNTL_PSIZE = 0x00000100 -A6XX_PC_GS_OUT_CNTL_LAYER = 0x00000200 -A6XX_PC_GS_OUT_CNTL_VIEW = 0x00000400 -A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 -A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT = 16 -A6XX_PC_GS_OUT_CNTL_SHADINGRATE = 0x01000000 -REG_A6XX_PC_HS_OUT_CNTL = 0x00009b03 -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 -A6XX_PC_HS_OUT_CNTL_PSIZE = 0x00000100 -A6XX_PC_HS_OUT_CNTL_LAYER = 0x00000200 -A6XX_PC_HS_OUT_CNTL_VIEW = 0x00000400 -A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 -A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT = 16 -A6XX_PC_HS_OUT_CNTL_SHADINGRATE = 0x01000000 -REG_A6XX_PC_DS_OUT_CNTL = 0x00009b04 -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff -A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 -A6XX_PC_DS_OUT_CNTL_PSIZE = 0x00000100 -A6XX_PC_DS_OUT_CNTL_LAYER = 0x00000200 -A6XX_PC_DS_OUT_CNTL_VIEW = 0x00000400 -A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 -A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT = 16 -A6XX_PC_DS_OUT_CNTL_SHADINGRATE = 0x01000000 -REG_A6XX_PC_PRIMITIVE_CNTL_5 = 0x00009b05 -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff -A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 -A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 -A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 -A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 -A6XX_PC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 -REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff -A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 -REG_A6XX_PC_MULTIVIEW_CNTL = 0x00009b07 -A6XX_PC_MULTIVIEW_CNTL_ENABLE = 0x00000001 -A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 -A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c -A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 -REG_A6XX_PC_MULTIVIEW_MASK = 0x00009b08 -REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 -A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f -A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 -A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 -A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 -REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 -REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 -REG_A6XX_PC_DRAW_INDX_BASE = 0x00009e04 -REG_A6XX_PC_DRAW_FIRST_INDX = 0x00009e06 -REG_A6XX_PC_DRAW_MAX_INDICES = 0x00009e07 -REG_A6XX_PC_TESSFACTOR_ADDR = 0x00009e08 -REG_A7XX_PC_TESSFACTOR_ADDR = 0x00009810 -REG_A6XX_PC_DRAW_INITIATOR = 0x00009e0b -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK = 0x0000003f -A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT = 0 -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK = 0x000000c0 -A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT = 6 -A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK = 0x00000300 -A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT = 8 -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK = 0x00000c00 -A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT = 10 -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK = 0x00003000 -A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT = 12 -A6XX_PC_DRAW_INITIATOR_GS_ENABLE = 0x00010000 -A6XX_PC_DRAW_INITIATOR_TESS_ENABLE = 0x00020000 -REG_A6XX_PC_DRAW_NUM_INSTANCES = 0x00009e0c -REG_A6XX_PC_DRAW_NUM_INDICES = 0x00009e0d -REG_A6XX_PC_VSTREAM_CONTROL = 0x00009e11 -A6XX_PC_VSTREAM_CONTROL_UNK0__MASK = 0x0000ffff -A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT = 0 -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK = 0x003f0000 -A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT = 16 -A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK = 0x07c00000 -A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT = 22 -REG_A6XX_PC_BIN_PRIM_STRM = 0x00009e12 -REG_A6XX_PC_BIN_DRAW_STRM = 0x00009e14 -REG_A6XX_PC_VISIBILITY_OVERRIDE = 0x00009e1c -A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE = 0x00000001 -REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 -REG_A6XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e34 + 0x1*i0 ) -REG_A7XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e42 + 0x1*i0 ) -REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 -REG_A6XX_VFD_CONTROL_0 = 0x0000a000 -A6XX_VFD_CONTROL_0_FETCH_CNT__MASK = 0x0000003f -A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT = 0 -A6XX_VFD_CONTROL_0_DECODE_CNT__MASK = 0x00003f00 -A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT = 8 -REG_A6XX_VFD_CONTROL_1 = 0x0000a001 -A6XX_VFD_CONTROL_1_REGID4VTX__MASK = 0x000000ff -A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT = 0 -A6XX_VFD_CONTROL_1_REGID4INST__MASK = 0x0000ff00 -A6XX_VFD_CONTROL_1_REGID4INST__SHIFT = 8 -A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK = 0x00ff0000 -A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT = 16 -A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK = 0xff000000 -A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT = 24 -REG_A6XX_VFD_CONTROL_2 = 0x0000a002 -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK = 0x000000ff -A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT = 0 -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 -A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT = 8 -REG_A6XX_VFD_CONTROL_3 = 0x0000a003 -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK = 0x000000ff -A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT = 0 -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 -A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT = 8 -A6XX_VFD_CONTROL_3_REGID_TESSX__MASK = 0x00ff0000 -A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT = 16 -A6XX_VFD_CONTROL_3_REGID_TESSY__MASK = 0xff000000 -A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT = 24 -REG_A6XX_VFD_CONTROL_4 = 0x0000a004 -A6XX_VFD_CONTROL_4_UNK0__MASK = 0x000000ff -A6XX_VFD_CONTROL_4_UNK0__SHIFT = 0 -REG_A6XX_VFD_CONTROL_5 = 0x0000a005 -A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK = 0x000000ff -A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT = 0 -A6XX_VFD_CONTROL_5_UNK8__MASK = 0x0000ff00 -A6XX_VFD_CONTROL_5_UNK8__SHIFT = 8 -REG_A6XX_VFD_CONTROL_6 = 0x0000a006 -A6XX_VFD_CONTROL_6_PRIMID4PSEN = 0x00000001 -REG_A6XX_VFD_MODE_CNTL = 0x0000a007 -A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK = 0x00000007 -A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT = 0 -REG_A6XX_VFD_MULTIVIEW_CNTL = 0x0000a008 -A6XX_VFD_MULTIVIEW_CNTL_ENABLE = 0x00000001 -A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c -A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 -REG_A6XX_VFD_ADD_OFFSET = 0x0000a009 -A6XX_VFD_ADD_OFFSET_VERTEX = 0x00000001 -A6XX_VFD_ADD_OFFSET_INSTANCE = 0x00000002 -REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e -REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f -REG_A6XX_VFD_FETCH = lambda i0: (0x0000a010 + 0x4*i0 ) -REG_A6XX_VFD_DECODE = lambda i0: (0x0000a090 + 0x2*i0 ) -A6XX_VFD_DECODE_INSTR_IDX__MASK = 0x0000001f -A6XX_VFD_DECODE_INSTR_IDX__SHIFT = 0 -A6XX_VFD_DECODE_INSTR_OFFSET__MASK = 0x0001ffe0 -A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT = 5 -A6XX_VFD_DECODE_INSTR_INSTANCED = 0x00020000 -A6XX_VFD_DECODE_INSTR_FORMAT__MASK = 0x0ff00000 -A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT = 20 -A6XX_VFD_DECODE_INSTR_SWAP__MASK = 0x30000000 -A6XX_VFD_DECODE_INSTR_SWAP__SHIFT = 28 -A6XX_VFD_DECODE_INSTR_UNK30 = 0x40000000 -A6XX_VFD_DECODE_INSTR_FLOAT = 0x80000000 -REG_A6XX_VFD_DEST_CNTL = lambda i0: (0x0000a0d0 + 0x1*i0 ) -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f -A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 -A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 -A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 -REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 -REG_A7XX_VFD_UNKNOWN_A600 = 0x0000a600 -REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 -REG_A6XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) -REG_A7XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) -REG_A6XX_SP_VS_CTRL_REG0 = 0x0000a800 -A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_VS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_VS_CTRL_REG0_MERGEDREGS = 0x00100000 -A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE = 0x00200000 -REG_A6XX_SP_VS_BRANCH_COND = 0x0000a801 -REG_A6XX_SP_VS_PRIMITIVE_CNTL = 0x0000a802 -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f -A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT = 0 -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 -A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 -REG_A6XX_SP_VS_OUT = lambda i0: (0x0000a803 + 0x1*i0 ) -A6XX_SP_VS_OUT_REG_A_REGID__MASK = 0x000000ff -A6XX_SP_VS_OUT_REG_A_REGID__SHIFT = 0 -A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 -A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT = 8 -A6XX_SP_VS_OUT_REG_B_REGID__MASK = 0x00ff0000 -A6XX_SP_VS_OUT_REG_B_REGID__SHIFT = 16 -A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 -A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT = 24 -REG_A6XX_SP_VS_VPC_DST = lambda i0: (0x0000a813 + 0x1*i0 ) -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff -A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT = 0 -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 -A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT = 8 -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 -A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT = 16 -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 -A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT = 24 -REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET = 0x0000a81b -REG_A6XX_SP_VS_OBJ_START = 0x0000a81c -REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_VS_PVT_MEM_ADDR = 0x0000a81f -REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_VS_TEX_COUNT = 0x0000a822 -REG_A6XX_SP_VS_CONFIG = 0x0000a823 -A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_VS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_VS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_VS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_VS_INSTRLEN = 0x0000a824 -REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET = 0x0000a825 -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A7XX_SP_VS_VGPR_CONFIG = 0x0000a82d -REG_A6XX_SP_HS_CTRL_REG0 = 0x0000a830 -A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_HS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 -REG_A6XX_SP_HS_WAVE_INPUT_SIZE = 0x0000a831 -REG_A6XX_SP_HS_BRANCH_COND = 0x0000a832 -REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET = 0x0000a833 -REG_A6XX_SP_HS_OBJ_START = 0x0000a834 -REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_HS_PVT_MEM_ADDR = 0x0000a837 -REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_HS_TEX_COUNT = 0x0000a83a -REG_A6XX_SP_HS_CONFIG = 0x0000a83b -A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_HS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_HS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_HS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_HS_INSTRLEN = 0x0000a83c -REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET = 0x0000a83d -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A7XX_SP_HS_VGPR_CONFIG = 0x0000a82f -REG_A6XX_SP_DS_CTRL_REG0 = 0x0000a840 -A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_DS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 -REG_A6XX_SP_DS_BRANCH_COND = 0x0000a841 -REG_A6XX_SP_DS_PRIMITIVE_CNTL = 0x0000a842 -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f -A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT = 0 -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 -A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 -REG_A6XX_SP_DS_OUT = lambda i0: (0x0000a843 + 0x1*i0 ) -A6XX_SP_DS_OUT_REG_A_REGID__MASK = 0x000000ff -A6XX_SP_DS_OUT_REG_A_REGID__SHIFT = 0 -A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 -A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT = 8 -A6XX_SP_DS_OUT_REG_B_REGID__MASK = 0x00ff0000 -A6XX_SP_DS_OUT_REG_B_REGID__SHIFT = 16 -A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 -A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT = 24 -REG_A6XX_SP_DS_VPC_DST = lambda i0: (0x0000a853 + 0x1*i0 ) -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff -A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT = 0 -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 -A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT = 8 -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 -A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT = 16 -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 -A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT = 24 -REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET = 0x0000a85b -REG_A6XX_SP_DS_OBJ_START = 0x0000a85c -REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_DS_PVT_MEM_ADDR = 0x0000a85f -REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_DS_TEX_COUNT = 0x0000a862 -REG_A6XX_SP_DS_CONFIG = 0x0000a863 -A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_DS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_DS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_DS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_DS_INSTRLEN = 0x0000a864 -REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET = 0x0000a865 -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A7XX_SP_DS_VGPR_CONFIG = 0x0000a868 -REG_A6XX_SP_GS_CTRL_REG0 = 0x0000a870 -A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_GS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 -REG_A6XX_SP_GS_PRIM_SIZE = 0x0000a871 -REG_A6XX_SP_GS_BRANCH_COND = 0x0000a872 -REG_A6XX_SP_GS_PRIMITIVE_CNTL = 0x0000a873 -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f -A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT = 0 -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 -A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 -REG_A6XX_SP_GS_OUT = lambda i0: (0x0000a874 + 0x1*i0 ) -A6XX_SP_GS_OUT_REG_A_REGID__MASK = 0x000000ff -A6XX_SP_GS_OUT_REG_A_REGID__SHIFT = 0 -A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 -A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT = 8 -A6XX_SP_GS_OUT_REG_B_REGID__MASK = 0x00ff0000 -A6XX_SP_GS_OUT_REG_B_REGID__SHIFT = 16 -A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 -A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT = 24 -REG_A6XX_SP_GS_VPC_DST = lambda i0: (0x0000a884 + 0x1*i0 ) -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff -A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT = 0 -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 -A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT = 8 -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 -A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT = 16 -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 -A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT = 24 -REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET = 0x0000a88c -REG_A6XX_SP_GS_OBJ_START = 0x0000a88d -REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_GS_PVT_MEM_ADDR = 0x0000a890 -REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_GS_TEX_COUNT = 0x0000a893 -REG_A6XX_SP_GS_CONFIG = 0x0000a894 -A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_GS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_GS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_GS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_GS_INSTRLEN = 0x0000a895 -REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET = 0x0000a896 -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A7XX_SP_GS_VGPR_CONFIG = 0x0000a899 -REG_A6XX_SP_VS_TEX_SAMP = 0x0000a8a0 -REG_A6XX_SP_HS_TEX_SAMP = 0x0000a8a2 -REG_A6XX_SP_DS_TEX_SAMP = 0x0000a8a4 -REG_A6XX_SP_GS_TEX_SAMP = 0x0000a8a6 -REG_A6XX_SP_VS_TEX_CONST = 0x0000a8a8 -REG_A6XX_SP_HS_TEX_CONST = 0x0000a8aa -REG_A6XX_SP_DS_TEX_CONST = 0x0000a8ac -REG_A6XX_SP_GS_TEX_CONST = 0x0000a8ae -REG_A6XX_SP_FS_CTRL_REG0 = 0x0000a980 -A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_FS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 -A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT = 20 -A6XX_SP_FS_CTRL_REG0_UNK21 = 0x00200000 -A6XX_SP_FS_CTRL_REG0_VARYING = 0x00400000 -A6XX_SP_FS_CTRL_REG0_LODPIXMASK = 0x00800000 -A6XX_SP_FS_CTRL_REG0_UNK24 = 0x01000000 -A6XX_SP_FS_CTRL_REG0_UNK25 = 0x02000000 -A6XX_SP_FS_CTRL_REG0_PIXLODENABLE = 0x04000000 -A6XX_SP_FS_CTRL_REG0_UNK27 = 0x08000000 -A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE = 0x10000000 -A6XX_SP_FS_CTRL_REG0_MERGEDREGS = 0x80000000 -REG_A6XX_SP_FS_BRANCH_COND = 0x0000a981 -REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET = 0x0000a982 -REG_A6XX_SP_FS_OBJ_START = 0x0000a983 -REG_A6XX_SP_FS_PVT_MEM_PARAM = 0x0000a985 -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_FS_PVT_MEM_ADDR = 0x0000a986 -REG_A6XX_SP_FS_PVT_MEM_SIZE = 0x0000a988 -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_BLEND_CNTL = 0x0000a989 -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff -A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 -A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 -A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 -A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 -REG_A6XX_SP_SRGB_CNTL = 0x0000a98a -A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 -A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 -A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 -A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 -A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 -A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 -A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 -A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 -REG_A6XX_SP_FS_RENDER_COMPONENTS = 0x0000a98b -A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK = 0x0000000f -A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT = 0 -A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 -A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT = 4 -A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 -A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT = 8 -A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 -A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT = 12 -A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 -A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT = 16 -A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 -A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT = 20 -A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 -A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT = 24 -A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 -A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT = 28 -REG_A6XX_SP_FS_OUTPUT_CNTL0 = 0x0000a98c -A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK = 0x0000ff00 -A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT = 8 -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK = 0x00ff0000 -A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT = 16 -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK = 0xff000000 -A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT = 24 -REG_A6XX_SP_FS_OUTPUT_CNTL1 = 0x0000a98d -A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f -A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 -REG_A6XX_SP_FS_OUTPUT = lambda i0: (0x0000a98e + 0x1*i0 ) -A6XX_SP_FS_OUTPUT_REG_REGID__MASK = 0x000000ff -A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT = 0 -A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION = 0x00000100 -REG_A6XX_SP_FS_MRT = lambda i0: (0x0000a996 + 0x1*i0 ) -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff -A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT = 0 -A6XX_SP_FS_MRT_REG_COLOR_SINT = 0x00000100 -A6XX_SP_FS_MRT_REG_COLOR_UINT = 0x00000200 -A6XX_SP_FS_MRT_REG_UNK10 = 0x00000400 -REG_A6XX_SP_FS_PREFETCH_CNTL = 0x0000a99e -A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK = 0x00000007 -A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT = 0 -A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE = 0x00000008 -A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD = 0x00000010 -A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK = 0x00007fc0 -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT = 6 -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 -A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT = 16 -REG_A6XX_SP_FS_PREFETCH = lambda i0: (0x0000a99f + 0x1*i0 ) -A6XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f -A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000780 -A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x0000f800 -A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 11 -A6XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x003f0000 -A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 16 -A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x03c00000 -A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 22 -A6XX_SP_FS_PREFETCH_CMD_HALF = 0x04000000 -A6XX_SP_FS_PREFETCH_CMD_UNK27 = 0x08000000 -A6XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x10000000 -A6XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0xe0000000 -A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 29 -REG_A7XX_SP_FS_PREFETCH = lambda i0: (0x0000a99f + 0x1*i0 ) -A7XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f -A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000380 -A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x00001c00 -A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 10 -A7XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x0007e000 -A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 13 -A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x00780000 -A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 19 -A7XX_SP_FS_PREFETCH_CMD_HALF = 0x00800000 -A7XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x02000000 -A7XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0x3c000000 -A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 26 -REG_A6XX_SP_FS_BINDLESS_PREFETCH = lambda i0: (0x0000a9a3 + 0x1*i0 ) -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK = 0x0000ffff -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT = 0 -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK = 0xffff0000 -A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT = 16 -REG_A6XX_SP_FS_TEX_COUNT = 0x0000a9a7 -REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 -REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9a9 -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A6XX_SP_CS_CTRL_REG0 = 0x0000a9b0 -A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK = 0x00000001 -A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT = 0 -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e -A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 -A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 -A6XX_SP_CS_CTRL_REG0_UNK13 = 0x00002000 -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 -A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 -A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 -A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT = 20 -A6XX_SP_CS_CTRL_REG0_UNK21 = 0x00200000 -A6XX_SP_CS_CTRL_REG0_UNK22 = 0x00400000 -A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE = 0x00800000 -A6XX_SP_CS_CTRL_REG0_MERGEDREGS = 0x80000000 -REG_A6XX_SP_CS_UNKNOWN_A9B1 = 0x0000a9b1 -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK = 0x0000001f -A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT = 0 -A6XX_SP_CS_UNKNOWN_A9B1_UNK5 = 0x00000020 -A6XX_SP_CS_UNKNOWN_A9B1_UNK6 = 0x00000040 -REG_A6XX_SP_CS_BRANCH_COND = 0x0000a9b2 -REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET = 0x0000a9b3 -REG_A6XX_SP_CS_OBJ_START = 0x0000a9b4 -REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff -A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 -A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 -REG_A6XX_SP_CS_PVT_MEM_ADDR = 0x0000a9b7 -REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff -A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 -A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 -REG_A6XX_SP_CS_TEX_COUNT = 0x0000a9ba -REG_A6XX_SP_CS_CONFIG = 0x0000a9bb -A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_CS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_CS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_CS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_CS_INSTRLEN = 0x0000a9bc -REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9bd -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff -A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 -REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be -REG_A7XX_SP_CS_VGPR_CONFIG = 0x0000a9c5 -REG_A6XX_SP_CS_CNTL_0 = 0x0000a9c2 -A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff -A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 -A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 -A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 -A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 -A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 -REG_A6XX_SP_CS_CNTL_1 = 0x0000a9c3 -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff -A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 -A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 -A6XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 -A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 9 -A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 -REG_A7XX_SP_CS_CNTL_1 = 0x0000a9c3 -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff -A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 -A7XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000100 -A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 8 -A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000200 -A7XX_SP_CS_CNTL_1_UNK15 = 0x00008000 -REG_A6XX_SP_FS_TEX_SAMP = 0x0000a9e0 -REG_A6XX_SP_CS_TEX_SAMP = 0x0000a9e2 -REG_A6XX_SP_FS_TEX_CONST = 0x0000a9e4 -REG_A6XX_SP_CS_TEX_CONST = 0x0000a9e6 -REG_A6XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A7XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A6XX_SP_CS_IBO = 0x0000a9f2 -REG_A6XX_SP_CS_IBO_COUNT = 0x0000aa00 -REG_A7XX_SP_FS_VGPR_CONFIG = 0x0000aa01 -REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL = 0x0000aa02 -A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED = 0x00000001 -REG_A7XX_SP_PS_ALIASED_COMPONENTS = 0x0000aa03 -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK = 0x0000000f -A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT = 0 -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK = 0x000000f0 -A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT = 4 -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK = 0x00000f00 -A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT = 8 -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK = 0x0000f000 -A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT = 12 -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK = 0x000f0000 -A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT = 16 -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK = 0x00f00000 -A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT = 20 -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK = 0x0f000000 -A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT = 24 -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK = 0xf0000000 -A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT = 28 -REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 -REG_A6XX_SP_MODE_CONTROL = 0x0000ab00 -A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE = 0x00000001 -A6XX_SP_MODE_CONTROL_ISAMMODE__MASK = 0x00000006 -A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT = 1 -A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE = 0x00000008 -REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 -REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 -REG_A6XX_SP_FS_CONFIG = 0x0000ab04 -A6XX_SP_FS_CONFIG_BINDLESS_TEX = 0x00000001 -A6XX_SP_FS_CONFIG_BINDLESS_SAMP = 0x00000002 -A6XX_SP_FS_CONFIG_BINDLESS_IBO = 0x00000004 -A6XX_SP_FS_CONFIG_BINDLESS_UBO = 0x00000008 -A6XX_SP_FS_CONFIG_ENABLED = 0x00000100 -A6XX_SP_FS_CONFIG_NTEX__MASK = 0x0001fe00 -A6XX_SP_FS_CONFIG_NTEX__SHIFT = 9 -A6XX_SP_FS_CONFIG_NSAMP__MASK = 0x003e0000 -A6XX_SP_FS_CONFIG_NSAMP__SHIFT = 17 -A6XX_SP_FS_CONFIG_NIBO__MASK = 0x1fc00000 -A6XX_SP_FS_CONFIG_NIBO__SHIFT = 22 -REG_A6XX_SP_FS_INSTRLEN = 0x0000ab05 -REG_A6XX_SP_BINDLESS_BASE = lambda i0: (0x0000ab10 + 0x2*i0 ) -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A7XX_SP_BINDLESS_BASE = lambda i0: (0x0000ab0a + 0x2*i0 ) -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A6XX_SP_IBO = 0x0000ab1a -REG_A6XX_SP_IBO_COUNT = 0x0000ab20 -REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 -REG_A6XX_SP_2D_DST_FORMAT = 0x0000acc0 -A6XX_SP_2D_DST_FORMAT_NORM = 0x00000001 -A6XX_SP_2D_DST_FORMAT_SINT = 0x00000002 -A6XX_SP_2D_DST_FORMAT_UINT = 0x00000004 -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 -A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 -A6XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 -A6XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 -A6XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 -REG_A7XX_SP_2D_DST_FORMAT = 0x0000a9bf -A7XX_SP_2D_DST_FORMAT_NORM = 0x00000001 -A7XX_SP_2D_DST_FORMAT_SINT = 0x00000002 -A7XX_SP_2D_DST_FORMAT_UINT = 0x00000004 -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 -A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 -A7XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 -A7XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 -A7XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 -REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 -REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 -REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 -REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 -REG_A6XX_SP_FLOAT_CNTL = 0x0000ae04 -A6XX_SP_FLOAT_CNTL_F16_NO_INF = 0x00000008 -REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 -REG_A7XX_SP_UNKNOWN_AE08 = 0x0000ae08 -REG_A7XX_SP_UNKNOWN_AE09 = 0x0000ae09 -REG_A7XX_SP_UNKNOWN_AE0A = 0x0000ae0a -REG_A6XX_SP_PERFCTR_ENABLE = 0x0000ae0f -A6XX_SP_PERFCTR_ENABLE_VS = 0x00000001 -A6XX_SP_PERFCTR_ENABLE_HS = 0x00000002 -A6XX_SP_PERFCTR_ENABLE_DS = 0x00000004 -A6XX_SP_PERFCTR_ENABLE_GS = 0x00000008 -A6XX_SP_PERFCTR_ENABLE_FS = 0x00000010 -A6XX_SP_PERFCTR_ENABLE_CS = 0x00000020 -REG_A6XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae10 + 0x1*i0 ) -REG_A7XX_SP_PERFCTR_HLSQ_SEL = lambda i0: (0x0000ae60 + 0x1*i0 ) -REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a -REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b -REG_A7XX_SP_UNKNOWN_AE6C = 0x0000ae6c -REG_A7XX_SP_READ_SEL = 0x0000ae6d -A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 -A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 -A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 -A7XX_SP_READ_SEL_PIPE__SHIFT = 16 -A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 -A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 -A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 -A7XX_SP_READ_SEL_USPTP__SHIFT = 4 -A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f -A7XX_SP_READ_SEL_SPTP__SHIFT = 0 -REG_A7XX_SP_DBG_CNTL = 0x0000ae71 -REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 -REG_A7XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae80 + 0x1*i0 ) -REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 -REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR = 0x0000b180 -REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 -REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 -REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 -REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 -REG_A6XX_SP_TP_RAS_MSAA_CNTL = 0x0000b300 -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c -A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT = 2 -REG_A6XX_SP_TP_DEST_MSAA_CNTL = 0x0000b301 -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 -A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 -A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 -REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR = 0x0000b302 -REG_A6XX_SP_TP_SAMPLE_CONFIG = 0x0000b304 -A6XX_SP_TP_SAMPLE_CONFIG_UNK0 = 0x00000001 -A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 -REG_A6XX_SP_TP_SAMPLE_LOCATION_0 = 0x0000b305 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 -REG_A6XX_SP_TP_SAMPLE_LOCATION_1 = 0x0000b306 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 -A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 -REG_A6XX_SP_TP_WINDOW_OFFSET = 0x0000b307 -A6XX_SP_TP_WINDOW_OFFSET_X__MASK = 0x00003fff -A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT = 0 -A6XX_SP_TP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 -A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT = 16 -REG_A6XX_SP_TP_MODE_CNTL = 0x0000b309 -A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK = 0x00000003 -A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT = 0 -A6XX_SP_TP_MODE_CNTL_UNK3__MASK = 0x000000fc -A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT = 2 -REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 -REG_A6XX_SP_PS_2D_SRC_INFO = 0x0000b4c0 -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff -A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 -A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 -A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 -A6XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 -A6XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 -A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 -A6XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 -A6XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 -A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 -A6XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 -A6XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 -A6XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 -A6XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 -A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 -A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 -A6XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 -REG_A6XX_SP_PS_2D_SRC_SIZE = 0x0000b4c1 -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff -A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 -A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 -REG_A6XX_SP_PS_2D_SRC = 0x0000b4c2 -REG_A6XX_SP_PS_2D_SRC_PITCH = 0x0000b4c4 -A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff -A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 -A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 -A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 -REG_A7XX_SP_PS_2D_SRC_INFO = 0x0000b2c0 -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff -A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 -A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 -A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 -A7XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 -A7XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 -A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 -A7XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 -A7XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 -A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 -A7XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 -A7XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 -A7XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 -A7XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 -A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 -A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 -A7XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 -REG_A7XX_SP_PS_2D_SRC_SIZE = 0x0000b2c1 -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff -A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 -A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 -REG_A7XX_SP_PS_2D_SRC = 0x0000b2c2 -REG_A7XX_SP_PS_2D_SRC_PITCH = 0x0000b2c4 -A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff -A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 -A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 -A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 -REG_A6XX_SP_PS_2D_SRC_PLANE1 = 0x0000b4c5 -REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b4c7 -A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff -A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 -REG_A6XX_SP_PS_2D_SRC_PLANE2 = 0x0000b4c8 -REG_A7XX_SP_PS_2D_SRC_PLANE1 = 0x0000b2c5 -REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b2c7 -A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff -A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 -REG_A7XX_SP_PS_2D_SRC_PLANE2 = 0x0000b2c8 -REG_A6XX_SP_PS_2D_SRC_FLAGS = 0x0000b4ca -REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b4cc -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff -A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 -REG_A7XX_SP_PS_2D_SRC_FLAGS = 0x0000b2ca -REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b2cc -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff -A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 -REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd -REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce -REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf -REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 -REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 -A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff -A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 -A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 -A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 -REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd -REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce -REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf -REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 -REG_A7XX_SP_PS_2D_WINDOW_OFFSET = 0x0000b2d1 -A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK = 0x00003fff -A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT = 0 -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 -A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT = 16 -REG_A7XX_SP_PS_UNKNOWN_B2D2 = 0x0000b2d2 -REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 -A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff -A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 -A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 -A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 -REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 -REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 -REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 -A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND = 0x00040000 -REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 -A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 -A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 -A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 -A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 -A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 -A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 -REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b -REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b -REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c -REG_A6XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) -REG_A7XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) -REG_A6XX_HLSQ_VS_CNTL = 0x0000b800 -A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A6XX_HLSQ_HS_CNTL = 0x0000b801 -A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A6XX_HLSQ_DS_CNTL = 0x0000b802 -A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A6XX_HLSQ_GS_CNTL = 0x0000b803 -A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_VS_CNTL = 0x0000a827 -A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_HS_CNTL = 0x0000a83f -A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_DS_CNTL = 0x0000a867 -A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_GS_CNTL = 0x0000a898 -A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_FS_UNKNOWN_A9AA = 0x0000a9aa -A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE = 0x00000001 -REG_A7XX_HLSQ_UNKNOWN_A9AC = 0x0000a9ac -REG_A7XX_HLSQ_UNKNOWN_A9AD = 0x0000a9ad -REG_A7XX_HLSQ_UNKNOWN_A9AE = 0x0000a9ae -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK = 0x000000ff -A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT = 0 -A7XX_HLSQ_UNKNOWN_A9AE_UNK8 = 0x00000100 -A7XX_HLSQ_UNKNOWN_A9AE_UNK9 = 0x00000200 -REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 -REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 -REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 -REG_A6XX_HLSQ_FS_CNTL_0 = 0x0000b980 -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 -A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 -A6XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 -A6XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc -A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 -REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 -REG_A6XX_HLSQ_CONTROL_1_REG = 0x0000b982 -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 -A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 -REG_A6XX_HLSQ_CONTROL_2_REG = 0x0000b983 -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff -A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 -A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 -A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 -A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 -REG_A6XX_HLSQ_CONTROL_3_REG = 0x0000b984 -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 -A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 -A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 -REG_A6XX_HLSQ_CONTROL_4_REG = 0x0000b985 -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff -A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 -A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 -A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 -A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 -REG_A6XX_HLSQ_CONTROL_5_REG = 0x0000b986 -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff -A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 -A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 -REG_A6XX_HLSQ_CS_CNTL = 0x0000b987 -A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_FS_CNTL_0 = 0x0000a9c6 -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 -A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 -A7XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 -A7XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc -A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 -REG_A7XX_HLSQ_CONTROL_1_REG = 0x0000a9c7 -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 -A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 -REG_A7XX_HLSQ_CONTROL_2_REG = 0x0000a9c8 -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff -A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 -A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 -A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 -A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 -REG_A7XX_HLSQ_CONTROL_3_REG = 0x0000a9c9 -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 -A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 -A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 -REG_A7XX_HLSQ_CONTROL_4_REG = 0x0000a9ca -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff -A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 -A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 -A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 -A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 -REG_A7XX_HLSQ_CONTROL_5_REG = 0x0000a9cb -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff -A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 -A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 -REG_A7XX_HLSQ_CS_CNTL = 0x0000a9cd -A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A6XX_HLSQ_CS_NDRANGE_0 = 0x0000b990 -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 -A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 -A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 -REG_A6XX_HLSQ_CS_NDRANGE_1 = 0x0000b991 -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 -REG_A6XX_HLSQ_CS_NDRANGE_2 = 0x0000b992 -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 -REG_A6XX_HLSQ_CS_NDRANGE_3 = 0x0000b993 -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 -REG_A6XX_HLSQ_CS_NDRANGE_4 = 0x0000b994 -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 -REG_A6XX_HLSQ_CS_NDRANGE_5 = 0x0000b995 -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 -REG_A6XX_HLSQ_CS_NDRANGE_6 = 0x0000b996 -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff -A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 -REG_A6XX_HLSQ_CS_CNTL_0 = 0x0000b997 -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff -A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 -A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 -A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 -A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 -REG_A6XX_HLSQ_CS_CNTL_1 = 0x0000b998 -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff -A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 -A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 -A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 -A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 -REG_A6XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000b999 -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000b99a -REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000b99b -REG_A7XX_HLSQ_CS_NDRANGE_0 = 0x0000a9d4 -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 -A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 -A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 -REG_A7XX_HLSQ_CS_NDRANGE_1 = 0x0000a9d5 -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 -REG_A7XX_HLSQ_CS_NDRANGE_2 = 0x0000a9d6 -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 -REG_A7XX_HLSQ_CS_NDRANGE_3 = 0x0000a9d7 -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 -REG_A7XX_HLSQ_CS_NDRANGE_4 = 0x0000a9d8 -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 -REG_A7XX_HLSQ_CS_NDRANGE_5 = 0x0000a9d9 -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 -REG_A7XX_HLSQ_CS_NDRANGE_6 = 0x0000a9da -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff -A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 -REG_A7XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000a9dc -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000a9dd -REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000a9de -REG_A7XX_HLSQ_CS_CNTL_1 = 0x0000a9db -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff -A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 -A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 -A7XX_HLSQ_CS_CNTL_1_UNK11 = 0x00000800 -A7XX_HLSQ_CS_CNTL_1_UNK22 = 0x00400000 -A7XX_HLSQ_CS_CNTL_1_UNK26 = 0x04000000 -A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK = 0x78000000 -A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT = 27 -REG_A7XX_HLSQ_CS_LOCAL_SIZE = 0x0000a9df -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK = 0x00000ffc -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT = 2 -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK = 0x003ff000 -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT = 12 -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK = 0xffc00000 -A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT = 22 -REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 -REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 -REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 -REG_A6XX_HLSQ_CS_BINDLESS_BASE = lambda i0: (0x0000b9c0 + 0x2*i0 ) -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 = 0x0000b9d0 -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK = 0x0000001f -A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT = 0 -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 = 0x00000020 -A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 = 0x00000040 -REG_A6XX_HLSQ_DRAW_CMD = 0x0000bb00 -A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff -A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 -REG_A6XX_HLSQ_DISPATCH_CMD = 0x0000bb01 -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff -A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 -REG_A6XX_HLSQ_EVENT_CMD = 0x0000bb02 -A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 -A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 -A6XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f -A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 -REG_A6XX_HLSQ_INVALIDATE_CMD = 0x0000bb08 -A6XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 -A6XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 -A6XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 -A6XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 -A6XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 -A6XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 -A6XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 -A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 -A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST = 0x00080000 -A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST = 0x00000100 -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x00003e00 -A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x0007c000 -A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 14 -REG_A7XX_HLSQ_DRAW_CMD = 0x0000ab1c -A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff -A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 -REG_A7XX_HLSQ_DISPATCH_CMD = 0x0000ab1d -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff -A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 -REG_A7XX_HLSQ_EVENT_CMD = 0x0000ab1e -A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 -A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 -A7XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f -A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 -REG_A7XX_HLSQ_INVALIDATE_CMD = 0x0000ab1f -A7XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 -A7XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 -A7XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 -A7XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 -A7XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 -A7XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 -A7XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 -A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x0001fe00 -A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x01fe0000 -A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 17 -REG_A6XX_HLSQ_FS_CNTL = 0x0000bb10 -A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff -A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 -A6XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 -A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_FS_CNTL = 0x0000ab03 -A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff -A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 -A7XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 -A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 -REG_A7XX_HLSQ_SHARED_CONSTS_IMM = lambda i0: (0x0000ab40 + 0x1*i0 ) -REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 -A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 -REG_A6XX_HLSQ_BINDLESS_BASE = lambda i0: (0x0000bb20 + 0x2*i0 ) -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc -A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 -REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 -A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 -A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f -A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 -REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 -REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 -REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 -REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 -REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 -REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL = lambda i0: (0x0000be10 + 0x1*i0 ) -REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 -REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 -REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 -REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 -REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 -REG_A6XX_CP_EVENT_START = 0x0000d600 -A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff -A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 -REG_A6XX_CP_EVENT_END = 0x0000d601 -A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff -A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 -REG_A6XX_CP_2D_EVENT_START = 0x0000d700 -A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff -A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 -REG_A6XX_CP_2D_EVENT_END = 0x0000d701 -A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff -A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 -REG_A6XX_TEX_SAMP_0 = 0x00000000 -A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 -A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 -A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 -A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 -A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 -A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 -A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 -A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 -A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 -A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 -A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 -A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 -A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 -A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 -A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 -REG_A6XX_TEX_SAMP_1 = 0x00000001 -A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 -A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e -A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 -A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 -A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 -A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 -A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 -A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 -A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 -A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 -REG_A6XX_TEX_SAMP_2 = 0x00000002 -A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 -A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 -A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 -A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 -A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 -REG_A6XX_TEX_SAMP_3 = 0x00000003 -REG_A6XX_TEX_CONST_0 = 0x00000000 -A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 -A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 -A6XX_TEX_CONST_0_SRGB = 0x00000004 -A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 -A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 -A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 -A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 -A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 -A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 -A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 -A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 -A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 -A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 -A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 -A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 -A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 -A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 -A6XX_TEX_CONST_0_FMT__SHIFT = 22 -A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 -A6XX_TEX_CONST_0_SWAP__SHIFT = 30 -REG_A6XX_TEX_CONST_1 = 0x00000001 -A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff -A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 -A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 -A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 -REG_A6XX_TEX_CONST_2 = 0x00000002 -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 -A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 -A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 -A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f -A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 -A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 -A6XX_TEX_CONST_2_PITCH__SHIFT = 7 -A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 -A6XX_TEX_CONST_2_TYPE__SHIFT = 29 -REG_A6XX_TEX_CONST_3 = 0x00000003 -A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff -A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 -A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 -A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 -A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 -A6XX_TEX_CONST_3_FLAG = 0x10000000 -REG_A6XX_TEX_CONST_4 = 0x00000004 -A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 -A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 -REG_A6XX_TEX_CONST_5 = 0x00000005 -A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff -A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 -A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 -A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 -REG_A6XX_TEX_CONST_6 = 0x00000006 -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff -A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 -A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 -A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 -REG_A6XX_TEX_CONST_7 = 0x00000007 -A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 -A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 -REG_A6XX_TEX_CONST_8 = 0x00000008 -A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff -A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 -REG_A6XX_TEX_CONST_9 = 0x00000009 -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff -A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 -REG_A6XX_TEX_CONST_10 = 0x0000000a -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f -A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 -A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 -REG_A6XX_TEX_CONST_11 = 0x0000000b -REG_A6XX_TEX_CONST_12 = 0x0000000c -REG_A6XX_TEX_CONST_13 = 0x0000000d -REG_A6XX_TEX_CONST_14 = 0x0000000e -REG_A6XX_TEX_CONST_15 = 0x0000000f -REG_A6XX_UBO_0 = 0x00000000 -A6XX_UBO_0_BASE_LO__MASK = 0xffffffff -A6XX_UBO_0_BASE_LO__SHIFT = 0 -REG_A6XX_UBO_1 = 0x00000001 -A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff -A6XX_UBO_1_BASE_HI__SHIFT = 0 -A6XX_UBO_1_SIZE__MASK = 0xfffe0000 -A6XX_UBO_1_SIZE__SHIFT = 17 -REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 -REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 -REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 -REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 -REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 -REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 -REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 -REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 -REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 -REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 -REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 -REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 -REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 -REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 -REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 -REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 -REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 -REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 -REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 -REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 -REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 -REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 -REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 -REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 -REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da -REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db -REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 -A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 -REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 -REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 -A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a -REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e -REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 -REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 -A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f -REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 -REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 -REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 -REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 -A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 -A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 -A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/mesa.py b/tinygrad/runtime/autogen/mesa.py index bca22fd023..e241938e68 100644 --- a/tinygrad/runtime/autogen/mesa.py +++ b/tinygrad/runtime/autogen/mesa.py @@ -8241,6 +8241,998 @@ try: glsl_type_builtin_utextureSubpassInput = struct_glsl_type.in_dll(dll, 'glsl except (ValueError,AttributeError): pass try: glsl_type_builtin_utextureSubpassInputMS = struct_glsl_type.in_dll(dll, 'glsl_type_builtin_utextureSubpassInputMS') except (ValueError,AttributeError): pass +enum_a6xx_shift_amount = CEnum(ctypes.c_uint32) +NO_SHIFT = enum_a6xx_shift_amount.define('NO_SHIFT', 0) +HALF_PIXEL_SHIFT = enum_a6xx_shift_amount.define('HALF_PIXEL_SHIFT', 1) +FULL_PIXEL_SHIFT = enum_a6xx_shift_amount.define('FULL_PIXEL_SHIFT', 2) + +enum_a6xx_sequenced_thread_dist = CEnum(ctypes.c_uint32) +DIST_SCREEN_COORD = enum_a6xx_sequenced_thread_dist.define('DIST_SCREEN_COORD', 0) +DIST_ALL_TO_RB0 = enum_a6xx_sequenced_thread_dist.define('DIST_ALL_TO_RB0', 1) + +enum_a6xx_single_prim_mode = CEnum(ctypes.c_uint32) +NO_FLUSH = enum_a6xx_single_prim_mode.define('NO_FLUSH', 0) +FLUSH_PER_OVERLAP_AND_OVERWRITE = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP_AND_OVERWRITE', 1) +FLUSH_PER_OVERLAP = enum_a6xx_single_prim_mode.define('FLUSH_PER_OVERLAP', 3) + +enum_a6xx_raster_mode = CEnum(ctypes.c_uint32) +TYPE_TILED = enum_a6xx_raster_mode.define('TYPE_TILED', 0) +TYPE_WRITER = enum_a6xx_raster_mode.define('TYPE_WRITER', 1) + +enum_a6xx_raster_direction = CEnum(ctypes.c_uint32) +LR_TB = enum_a6xx_raster_direction.define('LR_TB', 0) +RL_TB = enum_a6xx_raster_direction.define('RL_TB', 1) +LR_BT = enum_a6xx_raster_direction.define('LR_BT', 2) +RB_BT = enum_a6xx_raster_direction.define('RB_BT', 3) + +enum_a6xx_render_mode = CEnum(ctypes.c_uint32) +RENDERING_PASS = enum_a6xx_render_mode.define('RENDERING_PASS', 0) +BINNING_PASS = enum_a6xx_render_mode.define('BINNING_PASS', 1) + +enum_a6xx_buffers_location = CEnum(ctypes.c_uint32) +BUFFERS_IN_GMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_GMEM', 0) +BUFFERS_IN_SYSMEM = enum_a6xx_buffers_location.define('BUFFERS_IN_SYSMEM', 3) + +enum_a6xx_lrz_feedback_mask = CEnum(ctypes.c_uint32) +LRZ_FEEDBACK_NONE = enum_a6xx_lrz_feedback_mask.define('LRZ_FEEDBACK_NONE', 0) +LRZ_FEEDBACK_EARLY_Z = enum_a6xx_lrz_feedback_mask.define('LRZ_FEEDBACK_EARLY_Z', 1) +LRZ_FEEDBACK_EARLY_Z_LATE_Z = enum_a6xx_lrz_feedback_mask.define('LRZ_FEEDBACK_EARLY_Z_LATE_Z', 2) +LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z = enum_a6xx_lrz_feedback_mask.define('LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z', 3) +LRZ_FEEDBACK_LATE_Z = enum_a6xx_lrz_feedback_mask.define('LRZ_FEEDBACK_LATE_Z', 4) + +enum_a6xx_fsr_combiner = CEnum(ctypes.c_uint32) +FSR_COMBINER_OP_KEEP = enum_a6xx_fsr_combiner.define('FSR_COMBINER_OP_KEEP', 0) +FSR_COMBINER_OP_REPLACE = enum_a6xx_fsr_combiner.define('FSR_COMBINER_OP_REPLACE', 1) +FSR_COMBINER_OP_MIN = enum_a6xx_fsr_combiner.define('FSR_COMBINER_OP_MIN', 2) +FSR_COMBINER_OP_MAX = enum_a6xx_fsr_combiner.define('FSR_COMBINER_OP_MAX', 3) +FSR_COMBINER_OP_MUL = enum_a6xx_fsr_combiner.define('FSR_COMBINER_OP_MUL', 4) + +enum_a6xx_lrz_dir_status = CEnum(ctypes.c_uint32) +LRZ_DIR_LE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_LE', 1) +LRZ_DIR_GE = enum_a6xx_lrz_dir_status.define('LRZ_DIR_GE', 2) +LRZ_DIR_INVALID = enum_a6xx_lrz_dir_status.define('LRZ_DIR_INVALID', 3) + +enum_a6xx_fragcoord_sample_mode = CEnum(ctypes.c_uint32) +FRAGCOORD_CENTER = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_CENTER', 0) +FRAGCOORD_SAMPLE = enum_a6xx_fragcoord_sample_mode.define('FRAGCOORD_SAMPLE', 3) + +enum_a6xx_rotation = CEnum(ctypes.c_uint32) +ROTATE_0 = enum_a6xx_rotation.define('ROTATE_0', 0) +ROTATE_90 = enum_a6xx_rotation.define('ROTATE_90', 1) +ROTATE_180 = enum_a6xx_rotation.define('ROTATE_180', 2) +ROTATE_270 = enum_a6xx_rotation.define('ROTATE_270', 3) +ROTATE_HFLIP = enum_a6xx_rotation.define('ROTATE_HFLIP', 4) +ROTATE_VFLIP = enum_a6xx_rotation.define('ROTATE_VFLIP', 5) + +enum_a6xx_blit_event_type = CEnum(ctypes.c_uint32) +BLIT_EVENT_STORE = enum_a6xx_blit_event_type.define('BLIT_EVENT_STORE', 0) +BLIT_EVENT_STORE_AND_CLEAR = enum_a6xx_blit_event_type.define('BLIT_EVENT_STORE_AND_CLEAR', 1) +BLIT_EVENT_CLEAR = enum_a6xx_blit_event_type.define('BLIT_EVENT_CLEAR', 2) +BLIT_EVENT_LOAD = enum_a6xx_blit_event_type.define('BLIT_EVENT_LOAD', 3) + +enum_a7xx_blit_clear_mode = CEnum(ctypes.c_uint32) +CLEAR_MODE_SYSMEM = enum_a7xx_blit_clear_mode.define('CLEAR_MODE_SYSMEM', 0) +CLEAR_MODE_GMEM = enum_a7xx_blit_clear_mode.define('CLEAR_MODE_GMEM', 1) + +enum_a6xx_ccu_cache_size = CEnum(ctypes.c_uint32) +CCU_CACHE_SIZE_FULL = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_FULL', 0) +CCU_CACHE_SIZE_HALF = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_HALF', 1) +CCU_CACHE_SIZE_QUARTER = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_QUARTER', 2) +CCU_CACHE_SIZE_EIGHTH = enum_a6xx_ccu_cache_size.define('CCU_CACHE_SIZE_EIGHTH', 3) + +enum_a7xx_concurrent_resolve_mode = CEnum(ctypes.c_uint32) +CONCURRENT_RESOLVE_MODE_DISABLED = enum_a7xx_concurrent_resolve_mode.define('CONCURRENT_RESOLVE_MODE_DISABLED', 0) +CONCURRENT_RESOLVE_MODE_1 = enum_a7xx_concurrent_resolve_mode.define('CONCURRENT_RESOLVE_MODE_1', 1) +CONCURRENT_RESOLVE_MODE_2 = enum_a7xx_concurrent_resolve_mode.define('CONCURRENT_RESOLVE_MODE_2', 2) + +enum_a7xx_concurrent_unresolve_mode = CEnum(ctypes.c_uint32) +CONCURRENT_UNRESOLVE_MODE_DISABLED = enum_a7xx_concurrent_unresolve_mode.define('CONCURRENT_UNRESOLVE_MODE_DISABLED', 0) +CONCURRENT_UNRESOLVE_MODE_PARTIAL = enum_a7xx_concurrent_unresolve_mode.define('CONCURRENT_UNRESOLVE_MODE_PARTIAL', 1) +CONCURRENT_UNRESOLVE_MODE_FULL = enum_a7xx_concurrent_unresolve_mode.define('CONCURRENT_UNRESOLVE_MODE_FULL', 3) + +enum_a6xx_varying_interp_mode = CEnum(ctypes.c_uint32) +INTERP_SMOOTH = enum_a6xx_varying_interp_mode.define('INTERP_SMOOTH', 0) +INTERP_FLAT = enum_a6xx_varying_interp_mode.define('INTERP_FLAT', 1) +INTERP_ZERO = enum_a6xx_varying_interp_mode.define('INTERP_ZERO', 2) +INTERP_ONE = enum_a6xx_varying_interp_mode.define('INTERP_ONE', 3) + +enum_a6xx_varying_ps_repl_mode = CEnum(ctypes.c_uint32) +PS_REPL_NONE = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_NONE', 0) +PS_REPL_S = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_S', 1) +PS_REPL_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_T', 2) +PS_REPL_ONE_MINUS_T = enum_a6xx_varying_ps_repl_mode.define('PS_REPL_ONE_MINUS_T', 3) + +enum_a6xx_threadsize = CEnum(ctypes.c_uint32) +THREAD64 = enum_a6xx_threadsize.define('THREAD64', 0) +THREAD128 = enum_a6xx_threadsize.define('THREAD128', 1) + +enum_a6xx_const_ram_mode = CEnum(ctypes.c_uint32) +CONSTLEN_128 = enum_a6xx_const_ram_mode.define('CONSTLEN_128', 0) +CONSTLEN_192 = enum_a6xx_const_ram_mode.define('CONSTLEN_192', 1) +CONSTLEN_256 = enum_a6xx_const_ram_mode.define('CONSTLEN_256', 2) +CONSTLEN_512 = enum_a6xx_const_ram_mode.define('CONSTLEN_512', 3) + +enum_a7xx_workitem_rast_order = CEnum(ctypes.c_uint32) +WORKITEMRASTORDER_LINEAR = enum_a7xx_workitem_rast_order.define('WORKITEMRASTORDER_LINEAR', 0) +WORKITEMRASTORDER_TILED = enum_a7xx_workitem_rast_order.define('WORKITEMRASTORDER_TILED', 1) + +enum_a6xx_bindless_descriptor_size = CEnum(ctypes.c_uint32) +BINDLESS_DESCRIPTOR_16B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_16B', 1) +BINDLESS_DESCRIPTOR_64B = enum_a6xx_bindless_descriptor_size.define('BINDLESS_DESCRIPTOR_64B', 3) + +enum_a6xx_isam_mode = CEnum(ctypes.c_uint32) +ISAMMODE_CL = enum_a6xx_isam_mode.define('ISAMMODE_CL', 1) +ISAMMODE_GL = enum_a6xx_isam_mode.define('ISAMMODE_GL', 2) + +enum_a6xx_sp_a2d_output_ifmt_type = CEnum(ctypes.c_uint32) +OUTPUT_IFMT_2D_FLOAT = enum_a6xx_sp_a2d_output_ifmt_type.define('OUTPUT_IFMT_2D_FLOAT', 0) +OUTPUT_IFMT_2D_SINT = enum_a6xx_sp_a2d_output_ifmt_type.define('OUTPUT_IFMT_2D_SINT', 1) +OUTPUT_IFMT_2D_UINT = enum_a6xx_sp_a2d_output_ifmt_type.define('OUTPUT_IFMT_2D_UINT', 2) + +enum_a6xx_coord_round = CEnum(ctypes.c_uint32) +COORD_TRUNCATE = enum_a6xx_coord_round.define('COORD_TRUNCATE', 0) +COORD_ROUND_NEAREST_EVEN = enum_a6xx_coord_round.define('COORD_ROUND_NEAREST_EVEN', 1) + +enum_a6xx_nearest_mode = CEnum(ctypes.c_uint32) +ROUND_CLAMP_TRUNCATE = enum_a6xx_nearest_mode.define('ROUND_CLAMP_TRUNCATE', 0) +CLAMP_ROUND_TRUNCATE = enum_a6xx_nearest_mode.define('CLAMP_ROUND_TRUNCATE', 1) + +enum_a7xx_cs_yalign = CEnum(ctypes.c_uint32) +CS_YALIGN_1 = enum_a7xx_cs_yalign.define('CS_YALIGN_1', 8) +CS_YALIGN_2 = enum_a7xx_cs_yalign.define('CS_YALIGN_2', 4) +CS_YALIGN_4 = enum_a7xx_cs_yalign.define('CS_YALIGN_4', 2) +CS_YALIGN_8 = enum_a7xx_cs_yalign.define('CS_YALIGN_8', 1) + +enum_vgt_event_type = CEnum(ctypes.c_uint32) +VS_DEALLOC = enum_vgt_event_type.define('VS_DEALLOC', 0) +PS_DEALLOC = enum_vgt_event_type.define('PS_DEALLOC', 1) +VS_DONE_TS = enum_vgt_event_type.define('VS_DONE_TS', 2) +PS_DONE_TS = enum_vgt_event_type.define('PS_DONE_TS', 3) +CACHE_FLUSH_TS = enum_vgt_event_type.define('CACHE_FLUSH_TS', 4) +CONTEXT_DONE = enum_vgt_event_type.define('CONTEXT_DONE', 5) +CACHE_FLUSH = enum_vgt_event_type.define('CACHE_FLUSH', 6) +VIZQUERY_START = enum_vgt_event_type.define('VIZQUERY_START', 7) +HLSQ_FLUSH = enum_vgt_event_type.define('HLSQ_FLUSH', 7) +VIZQUERY_END = enum_vgt_event_type.define('VIZQUERY_END', 8) +SC_WAIT_WC = enum_vgt_event_type.define('SC_WAIT_WC', 9) +WRITE_PRIMITIVE_COUNTS = enum_vgt_event_type.define('WRITE_PRIMITIVE_COUNTS', 9) +START_PRIMITIVE_CTRS = enum_vgt_event_type.define('START_PRIMITIVE_CTRS', 11) +STOP_PRIMITIVE_CTRS = enum_vgt_event_type.define('STOP_PRIMITIVE_CTRS', 12) +RST_PIX_CNT = enum_vgt_event_type.define('RST_PIX_CNT', 13) +RST_VTX_CNT = enum_vgt_event_type.define('RST_VTX_CNT', 14) +TILE_FLUSH = enum_vgt_event_type.define('TILE_FLUSH', 15) +STAT_EVENT = enum_vgt_event_type.define('STAT_EVENT', 16) +CACHE_FLUSH_AND_INV_TS_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) +ZPASS_DONE = enum_vgt_event_type.define('ZPASS_DONE', 21) +CACHE_FLUSH_AND_INV_EVENT = enum_vgt_event_type.define('CACHE_FLUSH_AND_INV_EVENT', 22) +RB_DONE_TS = enum_vgt_event_type.define('RB_DONE_TS', 22) +PERFCOUNTER_START = enum_vgt_event_type.define('PERFCOUNTER_START', 23) +PERFCOUNTER_STOP = enum_vgt_event_type.define('PERFCOUNTER_STOP', 24) +VS_FETCH_DONE = enum_vgt_event_type.define('VS_FETCH_DONE', 27) +FACENESS_FLUSH = enum_vgt_event_type.define('FACENESS_FLUSH', 28) +WT_DONE_TS = enum_vgt_event_type.define('WT_DONE_TS', 8) +START_FRAGMENT_CTRS = enum_vgt_event_type.define('START_FRAGMENT_CTRS', 13) +STOP_FRAGMENT_CTRS = enum_vgt_event_type.define('STOP_FRAGMENT_CTRS', 14) +START_COMPUTE_CTRS = enum_vgt_event_type.define('START_COMPUTE_CTRS', 15) +STOP_COMPUTE_CTRS = enum_vgt_event_type.define('STOP_COMPUTE_CTRS', 16) +FLUSH_SO_0 = enum_vgt_event_type.define('FLUSH_SO_0', 17) +FLUSH_SO_1 = enum_vgt_event_type.define('FLUSH_SO_1', 18) +FLUSH_SO_2 = enum_vgt_event_type.define('FLUSH_SO_2', 19) +FLUSH_SO_3 = enum_vgt_event_type.define('FLUSH_SO_3', 20) +PC_CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('PC_CCU_INVALIDATE_DEPTH', 24) +PC_CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('PC_CCU_INVALIDATE_COLOR', 25) +PC_CCU_RESOLVE_TS = enum_vgt_event_type.define('PC_CCU_RESOLVE_TS', 26) +PC_CCU_FLUSH_DEPTH_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_DEPTH_TS', 28) +PC_CCU_FLUSH_COLOR_TS = enum_vgt_event_type.define('PC_CCU_FLUSH_COLOR_TS', 29) +BLIT = enum_vgt_event_type.define('BLIT', 30) +LRZ_FLIP_BUFFER = enum_vgt_event_type.define('LRZ_FLIP_BUFFER', 36) +LRZ_CLEAR = enum_vgt_event_type.define('LRZ_CLEAR', 37) +LRZ_FLUSH = enum_vgt_event_type.define('LRZ_FLUSH', 38) +BLIT_OP_FILL_2D = enum_vgt_event_type.define('BLIT_OP_FILL_2D', 39) +BLIT_OP_COPY_2D = enum_vgt_event_type.define('BLIT_OP_COPY_2D', 40) +UNK_40 = enum_vgt_event_type.define('UNK_40', 40) +LRZ_Q_CACHE_INVALIDATE = enum_vgt_event_type.define('LRZ_Q_CACHE_INVALIDATE', 41) +BLIT_OP_SCALE_2D = enum_vgt_event_type.define('BLIT_OP_SCALE_2D', 42) +CONTEXT_DONE_2D = enum_vgt_event_type.define('CONTEXT_DONE_2D', 43) +UNK_2C = enum_vgt_event_type.define('UNK_2C', 44) +UNK_2D = enum_vgt_event_type.define('UNK_2D', 45) +CACHE_INVALIDATE = enum_vgt_event_type.define('CACHE_INVALIDATE', 49) +LABEL = enum_vgt_event_type.define('LABEL', 63) +DUMMY_EVENT = enum_vgt_event_type.define('DUMMY_EVENT', 1) +CCU_INVALIDATE_DEPTH = enum_vgt_event_type.define('CCU_INVALIDATE_DEPTH', 24) +CCU_INVALIDATE_COLOR = enum_vgt_event_type.define('CCU_INVALIDATE_COLOR', 25) +CCU_RESOLVE_CLEAN = enum_vgt_event_type.define('CCU_RESOLVE_CLEAN', 26) +CCU_FLUSH_DEPTH = enum_vgt_event_type.define('CCU_FLUSH_DEPTH', 28) +CCU_FLUSH_COLOR = enum_vgt_event_type.define('CCU_FLUSH_COLOR', 29) +CCU_RESOLVE = enum_vgt_event_type.define('CCU_RESOLVE', 30) +CCU_END_RESOLVE_GROUP = enum_vgt_event_type.define('CCU_END_RESOLVE_GROUP', 31) +CCU_CLEAN_DEPTH = enum_vgt_event_type.define('CCU_CLEAN_DEPTH', 32) +CCU_CLEAN_COLOR = enum_vgt_event_type.define('CCU_CLEAN_COLOR', 33) +CACHE_RESET = enum_vgt_event_type.define('CACHE_RESET', 48) +CACHE_CLEAN = enum_vgt_event_type.define('CACHE_CLEAN', 49) +CACHE_FLUSH7 = enum_vgt_event_type.define('CACHE_FLUSH7', 50) +CACHE_INVALIDATE7 = enum_vgt_event_type.define('CACHE_INVALIDATE7', 51) + +enum_pc_di_primtype = CEnum(ctypes.c_uint32) +DI_PT_NONE = enum_pc_di_primtype.define('DI_PT_NONE', 0) +DI_PT_POINTLIST_PSIZE = enum_pc_di_primtype.define('DI_PT_POINTLIST_PSIZE', 1) +DI_PT_LINELIST = enum_pc_di_primtype.define('DI_PT_LINELIST', 2) +DI_PT_LINESTRIP = enum_pc_di_primtype.define('DI_PT_LINESTRIP', 3) +DI_PT_TRILIST = enum_pc_di_primtype.define('DI_PT_TRILIST', 4) +DI_PT_TRIFAN = enum_pc_di_primtype.define('DI_PT_TRIFAN', 5) +DI_PT_TRISTRIP = enum_pc_di_primtype.define('DI_PT_TRISTRIP', 6) +DI_PT_LINELOOP = enum_pc_di_primtype.define('DI_PT_LINELOOP', 7) +DI_PT_RECTLIST = enum_pc_di_primtype.define('DI_PT_RECTLIST', 8) +DI_PT_POINTLIST = enum_pc_di_primtype.define('DI_PT_POINTLIST', 9) +DI_PT_LINE_ADJ = enum_pc_di_primtype.define('DI_PT_LINE_ADJ', 10) +DI_PT_LINESTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_LINESTRIP_ADJ', 11) +DI_PT_TRI_ADJ = enum_pc_di_primtype.define('DI_PT_TRI_ADJ', 12) +DI_PT_TRISTRIP_ADJ = enum_pc_di_primtype.define('DI_PT_TRISTRIP_ADJ', 13) +DI_PT_PATCHES0 = enum_pc_di_primtype.define('DI_PT_PATCHES0', 31) +DI_PT_PATCHES1 = enum_pc_di_primtype.define('DI_PT_PATCHES1', 32) +DI_PT_PATCHES2 = enum_pc_di_primtype.define('DI_PT_PATCHES2', 33) +DI_PT_PATCHES3 = enum_pc_di_primtype.define('DI_PT_PATCHES3', 34) +DI_PT_PATCHES4 = enum_pc_di_primtype.define('DI_PT_PATCHES4', 35) +DI_PT_PATCHES5 = enum_pc_di_primtype.define('DI_PT_PATCHES5', 36) +DI_PT_PATCHES6 = enum_pc_di_primtype.define('DI_PT_PATCHES6', 37) +DI_PT_PATCHES7 = enum_pc_di_primtype.define('DI_PT_PATCHES7', 38) +DI_PT_PATCHES8 = enum_pc_di_primtype.define('DI_PT_PATCHES8', 39) +DI_PT_PATCHES9 = enum_pc_di_primtype.define('DI_PT_PATCHES9', 40) +DI_PT_PATCHES10 = enum_pc_di_primtype.define('DI_PT_PATCHES10', 41) +DI_PT_PATCHES11 = enum_pc_di_primtype.define('DI_PT_PATCHES11', 42) +DI_PT_PATCHES12 = enum_pc_di_primtype.define('DI_PT_PATCHES12', 43) +DI_PT_PATCHES13 = enum_pc_di_primtype.define('DI_PT_PATCHES13', 44) +DI_PT_PATCHES14 = enum_pc_di_primtype.define('DI_PT_PATCHES14', 45) +DI_PT_PATCHES15 = enum_pc_di_primtype.define('DI_PT_PATCHES15', 46) +DI_PT_PATCHES16 = enum_pc_di_primtype.define('DI_PT_PATCHES16', 47) +DI_PT_PATCHES17 = enum_pc_di_primtype.define('DI_PT_PATCHES17', 48) +DI_PT_PATCHES18 = enum_pc_di_primtype.define('DI_PT_PATCHES18', 49) +DI_PT_PATCHES19 = enum_pc_di_primtype.define('DI_PT_PATCHES19', 50) +DI_PT_PATCHES20 = enum_pc_di_primtype.define('DI_PT_PATCHES20', 51) +DI_PT_PATCHES21 = enum_pc_di_primtype.define('DI_PT_PATCHES21', 52) +DI_PT_PATCHES22 = enum_pc_di_primtype.define('DI_PT_PATCHES22', 53) +DI_PT_PATCHES23 = enum_pc_di_primtype.define('DI_PT_PATCHES23', 54) +DI_PT_PATCHES24 = enum_pc_di_primtype.define('DI_PT_PATCHES24', 55) +DI_PT_PATCHES25 = enum_pc_di_primtype.define('DI_PT_PATCHES25', 56) +DI_PT_PATCHES26 = enum_pc_di_primtype.define('DI_PT_PATCHES26', 57) +DI_PT_PATCHES27 = enum_pc_di_primtype.define('DI_PT_PATCHES27', 58) +DI_PT_PATCHES28 = enum_pc_di_primtype.define('DI_PT_PATCHES28', 59) +DI_PT_PATCHES29 = enum_pc_di_primtype.define('DI_PT_PATCHES29', 60) +DI_PT_PATCHES30 = enum_pc_di_primtype.define('DI_PT_PATCHES30', 61) +DI_PT_PATCHES31 = enum_pc_di_primtype.define('DI_PT_PATCHES31', 62) + +enum_pc_di_src_sel = CEnum(ctypes.c_uint32) +DI_SRC_SEL_DMA = enum_pc_di_src_sel.define('DI_SRC_SEL_DMA', 0) +DI_SRC_SEL_IMMEDIATE = enum_pc_di_src_sel.define('DI_SRC_SEL_IMMEDIATE', 1) +DI_SRC_SEL_AUTO_INDEX = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_INDEX', 2) +DI_SRC_SEL_AUTO_XFB = enum_pc_di_src_sel.define('DI_SRC_SEL_AUTO_XFB', 3) + +enum_pc_di_face_cull_sel = CEnum(ctypes.c_uint32) +DI_FACE_CULL_NONE = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_NONE', 0) +DI_FACE_CULL_FETCH = enum_pc_di_face_cull_sel.define('DI_FACE_CULL_FETCH', 1) +DI_FACE_BACKFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_BACKFACE_CULL', 2) +DI_FACE_FRONTFACE_CULL = enum_pc_di_face_cull_sel.define('DI_FACE_FRONTFACE_CULL', 3) + +enum_pc_di_index_size = CEnum(ctypes.c_uint32) +INDEX_SIZE_IGN = enum_pc_di_index_size.define('INDEX_SIZE_IGN', 0) +INDEX_SIZE_16_BIT = enum_pc_di_index_size.define('INDEX_SIZE_16_BIT', 0) +INDEX_SIZE_32_BIT = enum_pc_di_index_size.define('INDEX_SIZE_32_BIT', 1) +INDEX_SIZE_8_BIT = enum_pc_di_index_size.define('INDEX_SIZE_8_BIT', 2) +INDEX_SIZE_INVALID = enum_pc_di_index_size.define('INDEX_SIZE_INVALID', 0) + +enum_pc_di_vis_cull_mode = CEnum(ctypes.c_uint32) +IGNORE_VISIBILITY = enum_pc_di_vis_cull_mode.define('IGNORE_VISIBILITY', 0) +USE_VISIBILITY = enum_pc_di_vis_cull_mode.define('USE_VISIBILITY', 1) + +enum_adreno_pm4_packet_type = CEnum(ctypes.c_uint32) +CP_TYPE0_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE0_PKT', 0) +CP_TYPE1_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE1_PKT', 1073741824) +CP_TYPE2_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE2_PKT', 2147483648) +CP_TYPE3_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE3_PKT', 3221225472) +CP_TYPE4_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE4_PKT', 1073741824) +CP_TYPE7_PKT = enum_adreno_pm4_packet_type.define('CP_TYPE7_PKT', 1879048192) + +enum_adreno_pm4_type3_packets = CEnum(ctypes.c_uint32) +CP_ME_INIT = enum_adreno_pm4_type3_packets.define('CP_ME_INIT', 72) +CP_NOP = enum_adreno_pm4_type3_packets.define('CP_NOP', 16) +CP_PREEMPT_ENABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE', 28) +CP_PREEMPT_TOKEN = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_TOKEN', 30) +CP_INDIRECT_BUFFER = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER', 63) +CP_INDIRECT_BUFFER_CHAIN = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_CHAIN', 87) +CP_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFD', 55) +CP_WAIT_FOR_IDLE = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_IDLE', 38) +CP_WAIT_REG_MEM = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_MEM', 60) +CP_WAIT_REG_EQ = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_EQ', 82) +CP_WAIT_REG_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_REG_GTE', 83) +CP_WAIT_UNTIL_READ = enum_adreno_pm4_type3_packets.define('CP_WAIT_UNTIL_READ', 92) +CP_WAIT_IB_PFD_COMPLETE = enum_adreno_pm4_type3_packets.define('CP_WAIT_IB_PFD_COMPLETE', 93) +CP_REG_RMW = enum_adreno_pm4_type3_packets.define('CP_REG_RMW', 33) +CP_SET_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA', 47) +CP_SET_BIN_DATA5 = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5', 47) +CP_REG_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM', 62) +CP_MEM_WRITE = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE', 61) +CP_MEM_WRITE_CNTR = enum_adreno_pm4_type3_packets.define('CP_MEM_WRITE_CNTR', 79) +CP_COND_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_EXEC', 68) +CP_COND_WRITE = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE', 69) +CP_COND_WRITE5 = enum_adreno_pm4_type3_packets.define('CP_COND_WRITE5', 69) +CP_EVENT_WRITE = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE', 70) +CP_EVENT_WRITE7 = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE7', 70) +CP_EVENT_WRITE_SHD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_SHD', 88) +CP_EVENT_WRITE_CFL = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_CFL', 89) +CP_EVENT_WRITE_ZPD = enum_adreno_pm4_type3_packets.define('CP_EVENT_WRITE_ZPD', 91) +CP_RUN_OPENCL = enum_adreno_pm4_type3_packets.define('CP_RUN_OPENCL', 49) +CP_DRAW_INDX = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX', 34) +CP_DRAW_INDX_2 = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2', 54) +CP_DRAW_INDX_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_BIN', 52) +CP_DRAW_INDX_2_BIN = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_2_BIN', 53) +CP_VIZ_QUERY = enum_adreno_pm4_type3_packets.define('CP_VIZ_QUERY', 35) +CP_SET_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_STATE', 37) +CP_SET_CONSTANT = enum_adreno_pm4_type3_packets.define('CP_SET_CONSTANT', 45) +CP_IM_LOAD = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD', 39) +CP_IM_LOAD_IMMEDIATE = enum_adreno_pm4_type3_packets.define('CP_IM_LOAD_IMMEDIATE', 43) +CP_LOAD_CONSTANT_CONTEXT = enum_adreno_pm4_type3_packets.define('CP_LOAD_CONSTANT_CONTEXT', 46) +CP_INVALIDATE_STATE = enum_adreno_pm4_type3_packets.define('CP_INVALIDATE_STATE', 59) +CP_SET_SHADER_BASES = enum_adreno_pm4_type3_packets.define('CP_SET_SHADER_BASES', 74) +CP_SET_BIN_MASK = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_MASK', 80) +CP_SET_BIN_SELECT = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_SELECT', 81) +CP_CONTEXT_UPDATE = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_UPDATE', 94) +CP_INTERRUPT = enum_adreno_pm4_type3_packets.define('CP_INTERRUPT', 64) +CP_IM_STORE = enum_adreno_pm4_type3_packets.define('CP_IM_STORE', 44) +CP_SET_DRAW_INIT_FLAGS = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_INIT_FLAGS', 75) +CP_SET_PROTECTED_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_PROTECTED_MODE', 95) +CP_BOOTSTRAP_UCODE = enum_adreno_pm4_type3_packets.define('CP_BOOTSTRAP_UCODE', 111) +CP_LOAD_STATE = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE', 48) +CP_LOAD_STATE4 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE4', 48) +CP_COND_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFE', 58) +CP_COND_INDIRECT_BUFFER_PFD = enum_adreno_pm4_type3_packets.define('CP_COND_INDIRECT_BUFFER_PFD', 50) +CP_INDIRECT_BUFFER_PFE = enum_adreno_pm4_type3_packets.define('CP_INDIRECT_BUFFER_PFE', 63) +CP_SET_BIN = enum_adreno_pm4_type3_packets.define('CP_SET_BIN', 76) +CP_TEST_TWO_MEMS = enum_adreno_pm4_type3_packets.define('CP_TEST_TWO_MEMS', 113) +CP_REG_WR_NO_CTXT = enum_adreno_pm4_type3_packets.define('CP_REG_WR_NO_CTXT', 120) +CP_RECORD_PFP_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_RECORD_PFP_TIMESTAMP', 17) +CP_SET_SECURE_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_SECURE_MODE', 102) +CP_WAIT_FOR_ME = enum_adreno_pm4_type3_packets.define('CP_WAIT_FOR_ME', 19) +CP_SET_DRAW_STATE = enum_adreno_pm4_type3_packets.define('CP_SET_DRAW_STATE', 67) +CP_DRAW_INDX_OFFSET = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_OFFSET', 56) +CP_DRAW_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT', 40) +CP_DRAW_INDX_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDX_INDIRECT', 41) +CP_DRAW_INDIRECT_MULTI = enum_adreno_pm4_type3_packets.define('CP_DRAW_INDIRECT_MULTI', 42) +CP_DRAW_AUTO = enum_adreno_pm4_type3_packets.define('CP_DRAW_AUTO', 36) +CP_DRAW_PRED_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_GLOBAL', 25) +CP_DRAW_PRED_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_ENABLE_LOCAL', 26) +CP_DRAW_PRED_SET = enum_adreno_pm4_type3_packets.define('CP_DRAW_PRED_SET', 78) +CP_WIDE_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_WIDE_REG_WRITE', 116) +CP_SCRATCH_TO_REG = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_TO_REG', 77) +CP_REG_TO_SCRATCH = enum_adreno_pm4_type3_packets.define('CP_REG_TO_SCRATCH', 74) +CP_WAIT_MEM_WRITES = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_WRITES', 18) +CP_COND_REG_EXEC = enum_adreno_pm4_type3_packets.define('CP_COND_REG_EXEC', 71) +CP_MEM_TO_REG = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_REG', 66) +CP_EXEC_CS_INDIRECT = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS_INDIRECT', 65) +CP_EXEC_CS = enum_adreno_pm4_type3_packets.define('CP_EXEC_CS', 51) +CP_PERFCOUNTER_ACTION = enum_adreno_pm4_type3_packets.define('CP_PERFCOUNTER_ACTION', 80) +CP_SMMU_TABLE_UPDATE = enum_adreno_pm4_type3_packets.define('CP_SMMU_TABLE_UPDATE', 83) +CP_SET_MARKER = enum_adreno_pm4_type3_packets.define('CP_SET_MARKER', 101) +CP_SET_PSEUDO_REG = enum_adreno_pm4_type3_packets.define('CP_SET_PSEUDO_REG', 86) +CP_CONTEXT_REG_BUNCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH', 92) +CP_YIELD_ENABLE = enum_adreno_pm4_type3_packets.define('CP_YIELD_ENABLE', 28) +CP_SKIP_IB2_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_GLOBAL', 29) +CP_SKIP_IB2_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_SKIP_IB2_ENABLE_LOCAL', 35) +CP_SET_SUBDRAW_SIZE = enum_adreno_pm4_type3_packets.define('CP_SET_SUBDRAW_SIZE', 53) +CP_WHERE_AM_I = enum_adreno_pm4_type3_packets.define('CP_WHERE_AM_I', 98) +CP_SET_VISIBILITY_OVERRIDE = enum_adreno_pm4_type3_packets.define('CP_SET_VISIBILITY_OVERRIDE', 100) +CP_PREEMPT_ENABLE_GLOBAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_GLOBAL', 105) +CP_PREEMPT_ENABLE_LOCAL = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_ENABLE_LOCAL', 106) +CP_CONTEXT_SWITCH_YIELD = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH_YIELD', 107) +CP_SET_RENDER_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_RENDER_MODE', 108) +CP_COMPUTE_CHECKPOINT = enum_adreno_pm4_type3_packets.define('CP_COMPUTE_CHECKPOINT', 110) +CP_MEM_TO_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_MEM', 115) +CP_BLIT = enum_adreno_pm4_type3_packets.define('CP_BLIT', 44) +CP_REG_TEST = enum_adreno_pm4_type3_packets.define('CP_REG_TEST', 57) +CP_SET_MODE = enum_adreno_pm4_type3_packets.define('CP_SET_MODE', 99) +CP_LOAD_STATE6_GEOM = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_GEOM', 50) +CP_LOAD_STATE6_FRAG = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6_FRAG', 52) +CP_LOAD_STATE6 = enum_adreno_pm4_type3_packets.define('CP_LOAD_STATE6', 54) +IN_IB_PREFETCH_END = enum_adreno_pm4_type3_packets.define('IN_IB_PREFETCH_END', 23) +IN_SUBBLK_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_SUBBLK_PREFETCH', 31) +IN_INSTR_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_PREFETCH', 32) +IN_INSTR_MATCH = enum_adreno_pm4_type3_packets.define('IN_INSTR_MATCH', 71) +IN_CONST_PREFETCH = enum_adreno_pm4_type3_packets.define('IN_CONST_PREFETCH', 73) +IN_INCR_UPDT_STATE = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_STATE', 85) +IN_INCR_UPDT_CONST = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_CONST', 86) +IN_INCR_UPDT_INSTR = enum_adreno_pm4_type3_packets.define('IN_INCR_UPDT_INSTR', 87) +PKT4 = enum_adreno_pm4_type3_packets.define('PKT4', 4) +IN_IB_END = enum_adreno_pm4_type3_packets.define('IN_IB_END', 10) +IN_GMU_INTERRUPT = enum_adreno_pm4_type3_packets.define('IN_GMU_INTERRUPT', 11) +IN_PREEMPT = enum_adreno_pm4_type3_packets.define('IN_PREEMPT', 15) +CP_SCRATCH_WRITE = enum_adreno_pm4_type3_packets.define('CP_SCRATCH_WRITE', 76) +CP_REG_TO_MEM_OFFSET_MEM = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_MEM', 116) +CP_REG_TO_MEM_OFFSET_REG = enum_adreno_pm4_type3_packets.define('CP_REG_TO_MEM_OFFSET_REG', 114) +CP_WAIT_MEM_GTE = enum_adreno_pm4_type3_packets.define('CP_WAIT_MEM_GTE', 20) +CP_WAIT_TWO_REGS = enum_adreno_pm4_type3_packets.define('CP_WAIT_TWO_REGS', 112) +CP_MEMCPY = enum_adreno_pm4_type3_packets.define('CP_MEMCPY', 117) +CP_SET_BIN_DATA5_OFFSET = enum_adreno_pm4_type3_packets.define('CP_SET_BIN_DATA5_OFFSET', 46) +CP_SET_UNK_BIN_DATA = enum_adreno_pm4_type3_packets.define('CP_SET_UNK_BIN_DATA', 45) +CP_CONTEXT_SWITCH = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_SWITCH', 84) +CP_SET_AMBLE = enum_adreno_pm4_type3_packets.define('CP_SET_AMBLE', 85) +CP_REG_WRITE = enum_adreno_pm4_type3_packets.define('CP_REG_WRITE', 109) +CP_START_BIN = enum_adreno_pm4_type3_packets.define('CP_START_BIN', 80) +CP_END_BIN = enum_adreno_pm4_type3_packets.define('CP_END_BIN', 81) +CP_PREEMPT_DISABLE = enum_adreno_pm4_type3_packets.define('CP_PREEMPT_DISABLE', 108) +CP_WAIT_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_WAIT_TIMESTAMP', 20) +CP_GLOBAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_GLOBAL_TIMESTAMP', 21) +CP_LOCAL_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_LOCAL_TIMESTAMP', 22) +CP_THREAD_CONTROL = enum_adreno_pm4_type3_packets.define('CP_THREAD_CONTROL', 23) +CP_RESOURCE_LIST = enum_adreno_pm4_type3_packets.define('CP_RESOURCE_LIST', 24) +CP_BV_BR_COUNT_OPS = enum_adreno_pm4_type3_packets.define('CP_BV_BR_COUNT_OPS', 27) +CP_MODIFY_TIMESTAMP = enum_adreno_pm4_type3_packets.define('CP_MODIFY_TIMESTAMP', 28) +CP_CONTEXT_REG_BUNCH2 = enum_adreno_pm4_type3_packets.define('CP_CONTEXT_REG_BUNCH2', 93) +CP_MEM_TO_SCRATCH_MEM = enum_adreno_pm4_type3_packets.define('CP_MEM_TO_SCRATCH_MEM', 73) +CP_FIXED_STRIDE_DRAW_TABLE = enum_adreno_pm4_type3_packets.define('CP_FIXED_STRIDE_DRAW_TABLE', 127) +CP_RESET_CONTEXT_STATE = enum_adreno_pm4_type3_packets.define('CP_RESET_CONTEXT_STATE', 31) +CP_CCHE_INVALIDATE = enum_adreno_pm4_type3_packets.define('CP_CCHE_INVALIDATE', 58) +CP_SCOPE_CNTL = enum_adreno_pm4_type3_packets.define('CP_SCOPE_CNTL', 108) + +enum_adreno_state_block = CEnum(ctypes.c_uint32) +SB_VERT_TEX = enum_adreno_state_block.define('SB_VERT_TEX', 0) +SB_VERT_MIPADDR = enum_adreno_state_block.define('SB_VERT_MIPADDR', 1) +SB_FRAG_TEX = enum_adreno_state_block.define('SB_FRAG_TEX', 2) +SB_FRAG_MIPADDR = enum_adreno_state_block.define('SB_FRAG_MIPADDR', 3) +SB_VERT_SHADER = enum_adreno_state_block.define('SB_VERT_SHADER', 4) +SB_GEOM_SHADER = enum_adreno_state_block.define('SB_GEOM_SHADER', 5) +SB_FRAG_SHADER = enum_adreno_state_block.define('SB_FRAG_SHADER', 6) +SB_COMPUTE_SHADER = enum_adreno_state_block.define('SB_COMPUTE_SHADER', 7) + +enum_adreno_state_type = CEnum(ctypes.c_uint32) +ST_SHADER = enum_adreno_state_type.define('ST_SHADER', 0) +ST_CONSTANTS = enum_adreno_state_type.define('ST_CONSTANTS', 1) + +enum_adreno_state_src = CEnum(ctypes.c_uint32) +SS_DIRECT = enum_adreno_state_src.define('SS_DIRECT', 0) +SS_INVALID_ALL_IC = enum_adreno_state_src.define('SS_INVALID_ALL_IC', 2) +SS_INVALID_PART_IC = enum_adreno_state_src.define('SS_INVALID_PART_IC', 3) +SS_INDIRECT = enum_adreno_state_src.define('SS_INDIRECT', 4) +SS_INDIRECT_TCM = enum_adreno_state_src.define('SS_INDIRECT_TCM', 5) +SS_INDIRECT_STM = enum_adreno_state_src.define('SS_INDIRECT_STM', 6) + +enum_a4xx_state_block = CEnum(ctypes.c_uint32) +SB4_VS_TEX = enum_a4xx_state_block.define('SB4_VS_TEX', 0) +SB4_HS_TEX = enum_a4xx_state_block.define('SB4_HS_TEX', 1) +SB4_DS_TEX = enum_a4xx_state_block.define('SB4_DS_TEX', 2) +SB4_GS_TEX = enum_a4xx_state_block.define('SB4_GS_TEX', 3) +SB4_FS_TEX = enum_a4xx_state_block.define('SB4_FS_TEX', 4) +SB4_CS_TEX = enum_a4xx_state_block.define('SB4_CS_TEX', 5) +SB4_VS_SHADER = enum_a4xx_state_block.define('SB4_VS_SHADER', 8) +SB4_HS_SHADER = enum_a4xx_state_block.define('SB4_HS_SHADER', 9) +SB4_DS_SHADER = enum_a4xx_state_block.define('SB4_DS_SHADER', 10) +SB4_GS_SHADER = enum_a4xx_state_block.define('SB4_GS_SHADER', 11) +SB4_FS_SHADER = enum_a4xx_state_block.define('SB4_FS_SHADER', 12) +SB4_CS_SHADER = enum_a4xx_state_block.define('SB4_CS_SHADER', 13) +SB4_SSBO = enum_a4xx_state_block.define('SB4_SSBO', 14) +SB4_CS_SSBO = enum_a4xx_state_block.define('SB4_CS_SSBO', 15) + +enum_a4xx_state_type = CEnum(ctypes.c_uint32) +ST4_SHADER = enum_a4xx_state_type.define('ST4_SHADER', 0) +ST4_CONSTANTS = enum_a4xx_state_type.define('ST4_CONSTANTS', 1) +ST4_UBO = enum_a4xx_state_type.define('ST4_UBO', 2) + +enum_a4xx_state_src = CEnum(ctypes.c_uint32) +SS4_DIRECT = enum_a4xx_state_src.define('SS4_DIRECT', 0) +SS4_INDIRECT = enum_a4xx_state_src.define('SS4_INDIRECT', 2) + +enum_a6xx_state_block = CEnum(ctypes.c_uint32) +SB6_VS_TEX = enum_a6xx_state_block.define('SB6_VS_TEX', 0) +SB6_HS_TEX = enum_a6xx_state_block.define('SB6_HS_TEX', 1) +SB6_DS_TEX = enum_a6xx_state_block.define('SB6_DS_TEX', 2) +SB6_GS_TEX = enum_a6xx_state_block.define('SB6_GS_TEX', 3) +SB6_FS_TEX = enum_a6xx_state_block.define('SB6_FS_TEX', 4) +SB6_CS_TEX = enum_a6xx_state_block.define('SB6_CS_TEX', 5) +SB6_VS_SHADER = enum_a6xx_state_block.define('SB6_VS_SHADER', 8) +SB6_HS_SHADER = enum_a6xx_state_block.define('SB6_HS_SHADER', 9) +SB6_DS_SHADER = enum_a6xx_state_block.define('SB6_DS_SHADER', 10) +SB6_GS_SHADER = enum_a6xx_state_block.define('SB6_GS_SHADER', 11) +SB6_FS_SHADER = enum_a6xx_state_block.define('SB6_FS_SHADER', 12) +SB6_CS_SHADER = enum_a6xx_state_block.define('SB6_CS_SHADER', 13) +SB6_UAV = enum_a6xx_state_block.define('SB6_UAV', 14) +SB6_CS_UAV = enum_a6xx_state_block.define('SB6_CS_UAV', 15) + +enum_a6xx_state_type = CEnum(ctypes.c_uint32) +ST6_SHADER = enum_a6xx_state_type.define('ST6_SHADER', 0) +ST6_CONSTANTS = enum_a6xx_state_type.define('ST6_CONSTANTS', 1) +ST6_UBO = enum_a6xx_state_type.define('ST6_UBO', 2) +ST6_UAV = enum_a6xx_state_type.define('ST6_UAV', 3) + +enum_a6xx_state_src = CEnum(ctypes.c_uint32) +SS6_DIRECT = enum_a6xx_state_src.define('SS6_DIRECT', 0) +SS6_BINDLESS = enum_a6xx_state_src.define('SS6_BINDLESS', 1) +SS6_INDIRECT = enum_a6xx_state_src.define('SS6_INDIRECT', 2) +SS6_UBO = enum_a6xx_state_src.define('SS6_UBO', 3) + +enum_a4xx_index_size = CEnum(ctypes.c_uint32) +INDEX4_SIZE_8_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_8_BIT', 0) +INDEX4_SIZE_16_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_16_BIT', 1) +INDEX4_SIZE_32_BIT = enum_a4xx_index_size.define('INDEX4_SIZE_32_BIT', 2) + +enum_a6xx_patch_type = CEnum(ctypes.c_uint32) +TESS_QUADS = enum_a6xx_patch_type.define('TESS_QUADS', 0) +TESS_TRIANGLES = enum_a6xx_patch_type.define('TESS_TRIANGLES', 1) +TESS_ISOLINES = enum_a6xx_patch_type.define('TESS_ISOLINES', 2) + +enum_a6xx_draw_indirect_opcode = CEnum(ctypes.c_uint32) +INDIRECT_OP_NORMAL = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_NORMAL', 2) +INDIRECT_OP_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDEXED', 4) +INDIRECT_OP_INDIRECT_COUNT = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT', 6) +INDIRECT_OP_INDIRECT_COUNT_INDEXED = enum_a6xx_draw_indirect_opcode.define('INDIRECT_OP_INDIRECT_COUNT_INDEXED', 7) + +enum_cp_draw_pred_src = CEnum(ctypes.c_uint32) +PRED_SRC_MEM = enum_cp_draw_pred_src.define('PRED_SRC_MEM', 5) + +enum_cp_draw_pred_test = CEnum(ctypes.c_uint32) +NE_0_PASS = enum_cp_draw_pred_test.define('NE_0_PASS', 0) +EQ_0_PASS = enum_cp_draw_pred_test.define('EQ_0_PASS', 1) + +enum_a7xx_abs_mask_mode = CEnum(ctypes.c_uint32) +ABS_MASK = enum_a7xx_abs_mask_mode.define('ABS_MASK', 1) +NO_ABS_MASK = enum_a7xx_abs_mask_mode.define('NO_ABS_MASK', 0) + +enum_cp_cond_function = CEnum(ctypes.c_uint32) +WRITE_ALWAYS = enum_cp_cond_function.define('WRITE_ALWAYS', 0) +WRITE_LT = enum_cp_cond_function.define('WRITE_LT', 1) +WRITE_LE = enum_cp_cond_function.define('WRITE_LE', 2) +WRITE_EQ = enum_cp_cond_function.define('WRITE_EQ', 3) +WRITE_NE = enum_cp_cond_function.define('WRITE_NE', 4) +WRITE_GE = enum_cp_cond_function.define('WRITE_GE', 5) +WRITE_GT = enum_cp_cond_function.define('WRITE_GT', 6) + +enum_poll_memory_type = CEnum(ctypes.c_uint32) +POLL_REGISTER = enum_poll_memory_type.define('POLL_REGISTER', 0) +POLL_MEMORY = enum_poll_memory_type.define('POLL_MEMORY', 1) +POLL_SCRATCH = enum_poll_memory_type.define('POLL_SCRATCH', 2) +POLL_ON_CHIP = enum_poll_memory_type.define('POLL_ON_CHIP', 3) + +enum_render_mode_cmd = CEnum(ctypes.c_uint32) +BYPASS = enum_render_mode_cmd.define('BYPASS', 1) +BINNING = enum_render_mode_cmd.define('BINNING', 2) +GMEM = enum_render_mode_cmd.define('GMEM', 3) +BLIT2D = enum_render_mode_cmd.define('BLIT2D', 5) +BLIT2DSCALE = enum_render_mode_cmd.define('BLIT2DSCALE', 7) +END2D = enum_render_mode_cmd.define('END2D', 8) + +enum_event_write_src = CEnum(ctypes.c_uint32) +EV_WRITE_USER_32B = enum_event_write_src.define('EV_WRITE_USER_32B', 0) +EV_WRITE_USER_64B = enum_event_write_src.define('EV_WRITE_USER_64B', 1) +EV_WRITE_TIMESTAMP_SUM = enum_event_write_src.define('EV_WRITE_TIMESTAMP_SUM', 2) +EV_WRITE_ALWAYSON = enum_event_write_src.define('EV_WRITE_ALWAYSON', 3) +EV_WRITE_REGS_CONTENT = enum_event_write_src.define('EV_WRITE_REGS_CONTENT', 4) + +enum_event_write_dst = CEnum(ctypes.c_uint32) +EV_DST_RAM = enum_event_write_dst.define('EV_DST_RAM', 0) +EV_DST_ONCHIP = enum_event_write_dst.define('EV_DST_ONCHIP', 1) + +enum_cp_blit_cmd = CEnum(ctypes.c_uint32) +BLIT_OP_FILL = enum_cp_blit_cmd.define('BLIT_OP_FILL', 0) +BLIT_OP_COPY = enum_cp_blit_cmd.define('BLIT_OP_COPY', 1) +BLIT_OP_SCALE = enum_cp_blit_cmd.define('BLIT_OP_SCALE', 3) + +enum_set_marker_mode = CEnum(ctypes.c_uint32) +SET_RENDER_MODE = enum_set_marker_mode.define('SET_RENDER_MODE', 0) +SET_IFPC_MODE = enum_set_marker_mode.define('SET_IFPC_MODE', 1) + +enum_a6xx_ifpc_mode = CEnum(ctypes.c_uint32) +IFPC_ENABLE = enum_a6xx_ifpc_mode.define('IFPC_ENABLE', 0) +IFPC_DISABLE = enum_a6xx_ifpc_mode.define('IFPC_DISABLE', 1) + +enum_a6xx_marker = CEnum(ctypes.c_uint32) +RM6_DIRECT_RENDER = enum_a6xx_marker.define('RM6_DIRECT_RENDER', 1) +RM6_BIN_VISIBILITY = enum_a6xx_marker.define('RM6_BIN_VISIBILITY', 2) +RM6_BIN_DIRECT = enum_a6xx_marker.define('RM6_BIN_DIRECT', 3) +RM6_BIN_RENDER_START = enum_a6xx_marker.define('RM6_BIN_RENDER_START', 4) +RM6_BIN_END_OF_DRAWS = enum_a6xx_marker.define('RM6_BIN_END_OF_DRAWS', 5) +RM6_BIN_RESOLVE = enum_a6xx_marker.define('RM6_BIN_RESOLVE', 6) +RM6_BIN_RENDER_END = enum_a6xx_marker.define('RM6_BIN_RENDER_END', 7) +RM6_COMPUTE = enum_a6xx_marker.define('RM6_COMPUTE', 8) +RM6_BLIT2DSCALE = enum_a6xx_marker.define('RM6_BLIT2DSCALE', 12) +RM6_IB1LIST_START = enum_a6xx_marker.define('RM6_IB1LIST_START', 13) +RM6_IB1LIST_END = enum_a6xx_marker.define('RM6_IB1LIST_END', 14) + +enum_pseudo_reg = CEnum(ctypes.c_uint32) +SMMU_INFO = enum_pseudo_reg.define('SMMU_INFO', 0) +NON_SECURE_SAVE_ADDR = enum_pseudo_reg.define('NON_SECURE_SAVE_ADDR', 1) +SECURE_SAVE_ADDR = enum_pseudo_reg.define('SECURE_SAVE_ADDR', 2) +NON_PRIV_SAVE_ADDR = enum_pseudo_reg.define('NON_PRIV_SAVE_ADDR', 3) +COUNTER = enum_pseudo_reg.define('COUNTER', 4) +VSC_PIPE_DATA_DRAW_BASE = enum_pseudo_reg.define('VSC_PIPE_DATA_DRAW_BASE', 8) +VSC_SIZE_BASE = enum_pseudo_reg.define('VSC_SIZE_BASE', 9) +VSC_PIPE_DATA_PRIM_BASE = enum_pseudo_reg.define('VSC_PIPE_DATA_PRIM_BASE', 10) +UNK_STRM_ADDRESS = enum_pseudo_reg.define('UNK_STRM_ADDRESS', 11) +UNK_STRM_SIZE_ADDRESS = enum_pseudo_reg.define('UNK_STRM_SIZE_ADDRESS', 12) +BINDLESS_BASE_0_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_0_ADDR', 16) +BINDLESS_BASE_1_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_1_ADDR', 17) +BINDLESS_BASE_2_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_2_ADDR', 18) +BINDLESS_BASE_3_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_3_ADDR', 19) +BINDLESS_BASE_4_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_4_ADDR', 20) +BINDLESS_BASE_5_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_5_ADDR', 21) +BINDLESS_BASE_6_ADDR = enum_pseudo_reg.define('BINDLESS_BASE_6_ADDR', 22) + +enum_source_type = CEnum(ctypes.c_uint32) +SOURCE_REG = enum_source_type.define('SOURCE_REG', 0) +SOURCE_SCRATCH_MEM = enum_source_type.define('SOURCE_SCRATCH_MEM', 1) + +enum_compare_mode = CEnum(ctypes.c_uint32) +PRED_TEST = enum_compare_mode.define('PRED_TEST', 1) +REG_COMPARE = enum_compare_mode.define('REG_COMPARE', 2) +RENDER_MODE = enum_compare_mode.define('RENDER_MODE', 3) +REG_COMPARE_IMM = enum_compare_mode.define('REG_COMPARE_IMM', 4) +THREAD_MODE = enum_compare_mode.define('THREAD_MODE', 5) + +enum_amble_type = CEnum(ctypes.c_uint32) +PREAMBLE_AMBLE_TYPE = enum_amble_type.define('PREAMBLE_AMBLE_TYPE', 0) +BIN_PREAMBLE_AMBLE_TYPE = enum_amble_type.define('BIN_PREAMBLE_AMBLE_TYPE', 1) +POSTAMBLE_AMBLE_TYPE = enum_amble_type.define('POSTAMBLE_AMBLE_TYPE', 2) +KMD_AMBLE_TYPE = enum_amble_type.define('KMD_AMBLE_TYPE', 3) + +enum_reg_tracker = CEnum(ctypes.c_uint32) +TRACK_CNTL_REG = enum_reg_tracker.define('TRACK_CNTL_REG', 1) +TRACK_RENDER_CNTL = enum_reg_tracker.define('TRACK_RENDER_CNTL', 2) +UNK_EVENT_WRITE = enum_reg_tracker.define('UNK_EVENT_WRITE', 4) +TRACK_LRZ = enum_reg_tracker.define('TRACK_LRZ', 8) + +enum_ts_wait_value_src = CEnum(ctypes.c_uint32) +TS_WAIT_GE_32B = enum_ts_wait_value_src.define('TS_WAIT_GE_32B', 0) +TS_WAIT_GE_64B = enum_ts_wait_value_src.define('TS_WAIT_GE_64B', 1) +TS_WAIT_GE_TIMESTAMP_SUM = enum_ts_wait_value_src.define('TS_WAIT_GE_TIMESTAMP_SUM', 2) + +enum_ts_wait_type = CEnum(ctypes.c_uint32) +TS_WAIT_RAM = enum_ts_wait_type.define('TS_WAIT_RAM', 0) +TS_WAIT_ONCHIP = enum_ts_wait_type.define('TS_WAIT_ONCHIP', 1) + +enum_pipe_count_op = CEnum(ctypes.c_uint32) +PIPE_CLEAR_BV_BR = enum_pipe_count_op.define('PIPE_CLEAR_BV_BR', 1) +PIPE_SET_BR_OFFSET = enum_pipe_count_op.define('PIPE_SET_BR_OFFSET', 2) +PIPE_BR_WAIT_FOR_BV = enum_pipe_count_op.define('PIPE_BR_WAIT_FOR_BV', 3) +PIPE_BV_WAIT_FOR_BR = enum_pipe_count_op.define('PIPE_BV_WAIT_FOR_BR', 4) + +enum_timestamp_op = CEnum(ctypes.c_uint32) +MODIFY_TIMESTAMP_CLEAR = enum_timestamp_op.define('MODIFY_TIMESTAMP_CLEAR', 0) +MODIFY_TIMESTAMP_ADD_GLOBAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_GLOBAL', 1) +MODIFY_TIMESTAMP_ADD_LOCAL = enum_timestamp_op.define('MODIFY_TIMESTAMP_ADD_LOCAL', 2) + +enum_cp_thread = CEnum(ctypes.c_uint32) +CP_SET_THREAD_BR = enum_cp_thread.define('CP_SET_THREAD_BR', 1) +CP_SET_THREAD_BV = enum_cp_thread.define('CP_SET_THREAD_BV', 2) +CP_SET_THREAD_BOTH = enum_cp_thread.define('CP_SET_THREAD_BOTH', 3) + +enum_cp_scope = CEnum(ctypes.c_uint32) +INTERRUPTS = enum_cp_scope.define('INTERRUPTS', 0) + +enum_a6xx_tile_mode = CEnum(ctypes.c_uint32) +TILE6_LINEAR = enum_a6xx_tile_mode.define('TILE6_LINEAR', 0) +TILE6_2 = enum_a6xx_tile_mode.define('TILE6_2', 2) +TILE6_3 = enum_a6xx_tile_mode.define('TILE6_3', 3) + +enum_a6xx_format = CEnum(ctypes.c_uint32) +FMT6_A8_UNORM = enum_a6xx_format.define('FMT6_A8_UNORM', 2) +FMT6_8_UNORM = enum_a6xx_format.define('FMT6_8_UNORM', 3) +FMT6_8_SNORM = enum_a6xx_format.define('FMT6_8_SNORM', 4) +FMT6_8_UINT = enum_a6xx_format.define('FMT6_8_UINT', 5) +FMT6_8_SINT = enum_a6xx_format.define('FMT6_8_SINT', 6) +FMT6_4_4_4_4_UNORM = enum_a6xx_format.define('FMT6_4_4_4_4_UNORM', 8) +FMT6_5_5_5_1_UNORM = enum_a6xx_format.define('FMT6_5_5_5_1_UNORM', 10) +FMT6_1_5_5_5_UNORM = enum_a6xx_format.define('FMT6_1_5_5_5_UNORM', 12) +FMT6_5_6_5_UNORM = enum_a6xx_format.define('FMT6_5_6_5_UNORM', 14) +FMT6_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_UNORM', 15) +FMT6_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_SNORM', 16) +FMT6_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_UINT', 17) +FMT6_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_SINT', 18) +FMT6_L8_A8_UNORM = enum_a6xx_format.define('FMT6_L8_A8_UNORM', 19) +FMT6_16_UNORM = enum_a6xx_format.define('FMT6_16_UNORM', 21) +FMT6_16_SNORM = enum_a6xx_format.define('FMT6_16_SNORM', 22) +FMT6_16_FLOAT = enum_a6xx_format.define('FMT6_16_FLOAT', 23) +FMT6_16_UINT = enum_a6xx_format.define('FMT6_16_UINT', 24) +FMT6_16_SINT = enum_a6xx_format.define('FMT6_16_SINT', 25) +FMT6_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_UNORM', 33) +FMT6_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_SNORM', 34) +FMT6_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_UINT', 35) +FMT6_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_SINT', 36) +FMT6_8_8_8_8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_8_UNORM', 48) +FMT6_8_8_8_X8_UNORM = enum_a6xx_format.define('FMT6_8_8_8_X8_UNORM', 49) +FMT6_8_8_8_8_SNORM = enum_a6xx_format.define('FMT6_8_8_8_8_SNORM', 50) +FMT6_8_8_8_8_UINT = enum_a6xx_format.define('FMT6_8_8_8_8_UINT', 51) +FMT6_8_8_8_8_SINT = enum_a6xx_format.define('FMT6_8_8_8_8_SINT', 52) +FMT6_9_9_9_E5_FLOAT = enum_a6xx_format.define('FMT6_9_9_9_E5_FLOAT', 53) +FMT6_10_10_10_2_UNORM = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM', 54) +FMT6_10_10_10_2_UNORM_DEST = enum_a6xx_format.define('FMT6_10_10_10_2_UNORM_DEST', 55) +FMT6_10_10_10_2_SNORM = enum_a6xx_format.define('FMT6_10_10_10_2_SNORM', 57) +FMT6_10_10_10_2_UINT = enum_a6xx_format.define('FMT6_10_10_10_2_UINT', 58) +FMT6_10_10_10_2_SINT = enum_a6xx_format.define('FMT6_10_10_10_2_SINT', 59) +FMT6_11_11_10_FLOAT = enum_a6xx_format.define('FMT6_11_11_10_FLOAT', 66) +FMT6_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_UNORM', 67) +FMT6_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_SNORM', 68) +FMT6_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_FLOAT', 69) +FMT6_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_UINT', 70) +FMT6_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_SINT', 71) +FMT6_32_UNORM = enum_a6xx_format.define('FMT6_32_UNORM', 72) +FMT6_32_SNORM = enum_a6xx_format.define('FMT6_32_SNORM', 73) +FMT6_32_FLOAT = enum_a6xx_format.define('FMT6_32_FLOAT', 74) +FMT6_32_UINT = enum_a6xx_format.define('FMT6_32_UINT', 75) +FMT6_32_SINT = enum_a6xx_format.define('FMT6_32_SINT', 76) +FMT6_32_FIXED = enum_a6xx_format.define('FMT6_32_FIXED', 77) +FMT6_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_UNORM', 88) +FMT6_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_SNORM', 89) +FMT6_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_FLOAT', 90) +FMT6_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_UINT', 91) +FMT6_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_SINT', 92) +FMT6_16_16_16_16_UNORM = enum_a6xx_format.define('FMT6_16_16_16_16_UNORM', 96) +FMT6_16_16_16_16_SNORM = enum_a6xx_format.define('FMT6_16_16_16_16_SNORM', 97) +FMT6_16_16_16_16_FLOAT = enum_a6xx_format.define('FMT6_16_16_16_16_FLOAT', 98) +FMT6_16_16_16_16_UINT = enum_a6xx_format.define('FMT6_16_16_16_16_UINT', 99) +FMT6_16_16_16_16_SINT = enum_a6xx_format.define('FMT6_16_16_16_16_SINT', 100) +FMT6_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_UNORM', 101) +FMT6_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_SNORM', 102) +FMT6_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_FLOAT', 103) +FMT6_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_UINT', 104) +FMT6_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_SINT', 105) +FMT6_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_FIXED', 106) +FMT6_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_UNORM', 112) +FMT6_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_SNORM', 113) +FMT6_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_UINT', 114) +FMT6_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_SINT', 115) +FMT6_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_FLOAT', 116) +FMT6_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_FIXED', 117) +FMT6_32_32_32_32_UNORM = enum_a6xx_format.define('FMT6_32_32_32_32_UNORM', 128) +FMT6_32_32_32_32_SNORM = enum_a6xx_format.define('FMT6_32_32_32_32_SNORM', 129) +FMT6_32_32_32_32_FLOAT = enum_a6xx_format.define('FMT6_32_32_32_32_FLOAT', 130) +FMT6_32_32_32_32_UINT = enum_a6xx_format.define('FMT6_32_32_32_32_UINT', 131) +FMT6_32_32_32_32_SINT = enum_a6xx_format.define('FMT6_32_32_32_32_SINT', 132) +FMT6_32_32_32_32_FIXED = enum_a6xx_format.define('FMT6_32_32_32_32_FIXED', 133) +FMT6_G8R8B8R8_422_UNORM = enum_a6xx_format.define('FMT6_G8R8B8R8_422_UNORM', 140) +FMT6_R8G8R8B8_422_UNORM = enum_a6xx_format.define('FMT6_R8G8R8B8_422_UNORM', 141) +FMT6_R8_G8B8_2PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8B8_2PLANE_420_UNORM', 142) +FMT6_NV21 = enum_a6xx_format.define('FMT6_NV21', 143) +FMT6_R8_G8_B8_3PLANE_420_UNORM = enum_a6xx_format.define('FMT6_R8_G8_B8_3PLANE_420_UNORM', 144) +FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 145) +FMT6_NV12_Y = enum_a6xx_format.define('FMT6_NV12_Y', 148) +FMT6_NV12_UV = enum_a6xx_format.define('FMT6_NV12_UV', 149) +FMT6_NV12_VU = enum_a6xx_format.define('FMT6_NV12_VU', 150) +FMT6_NV12_4R = enum_a6xx_format.define('FMT6_NV12_4R', 151) +FMT6_NV12_4R_Y = enum_a6xx_format.define('FMT6_NV12_4R_Y', 152) +FMT6_NV12_4R_UV = enum_a6xx_format.define('FMT6_NV12_4R_UV', 153) +FMT6_P010 = enum_a6xx_format.define('FMT6_P010', 154) +FMT6_P010_Y = enum_a6xx_format.define('FMT6_P010_Y', 155) +FMT6_P010_UV = enum_a6xx_format.define('FMT6_P010_UV', 156) +FMT6_TP10 = enum_a6xx_format.define('FMT6_TP10', 157) +FMT6_TP10_Y = enum_a6xx_format.define('FMT6_TP10_Y', 158) +FMT6_TP10_UV = enum_a6xx_format.define('FMT6_TP10_UV', 159) +FMT6_Z24_UNORM_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UNORM_S8_UINT', 160) +FMT6_ETC2_RG11_UNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_UNORM', 171) +FMT6_ETC2_RG11_SNORM = enum_a6xx_format.define('FMT6_ETC2_RG11_SNORM', 172) +FMT6_ETC2_R11_UNORM = enum_a6xx_format.define('FMT6_ETC2_R11_UNORM', 173) +FMT6_ETC2_R11_SNORM = enum_a6xx_format.define('FMT6_ETC2_R11_SNORM', 174) +FMT6_ETC1 = enum_a6xx_format.define('FMT6_ETC1', 175) +FMT6_ETC2_RGB8 = enum_a6xx_format.define('FMT6_ETC2_RGB8', 176) +FMT6_ETC2_RGBA8 = enum_a6xx_format.define('FMT6_ETC2_RGBA8', 177) +FMT6_ETC2_RGB8A1 = enum_a6xx_format.define('FMT6_ETC2_RGB8A1', 178) +FMT6_DXT1 = enum_a6xx_format.define('FMT6_DXT1', 179) +FMT6_DXT3 = enum_a6xx_format.define('FMT6_DXT3', 180) +FMT6_DXT5 = enum_a6xx_format.define('FMT6_DXT5', 181) +FMT6_RGTC1_UNORM = enum_a6xx_format.define('FMT6_RGTC1_UNORM', 182) +FMT6_RGTC1_UNORM_FAST = enum_a6xx_format.define('FMT6_RGTC1_UNORM_FAST', 183) +FMT6_RGTC1_SNORM = enum_a6xx_format.define('FMT6_RGTC1_SNORM', 184) +FMT6_RGTC1_SNORM_FAST = enum_a6xx_format.define('FMT6_RGTC1_SNORM_FAST', 185) +FMT6_RGTC2_UNORM = enum_a6xx_format.define('FMT6_RGTC2_UNORM', 186) +FMT6_RGTC2_UNORM_FAST = enum_a6xx_format.define('FMT6_RGTC2_UNORM_FAST', 187) +FMT6_RGTC2_SNORM = enum_a6xx_format.define('FMT6_RGTC2_SNORM', 188) +FMT6_RGTC2_SNORM_FAST = enum_a6xx_format.define('FMT6_RGTC2_SNORM_FAST', 189) +FMT6_BPTC_UFLOAT = enum_a6xx_format.define('FMT6_BPTC_UFLOAT', 190) +FMT6_BPTC_FLOAT = enum_a6xx_format.define('FMT6_BPTC_FLOAT', 191) +FMT6_BPTC = enum_a6xx_format.define('FMT6_BPTC', 192) +FMT6_ASTC_4x4 = enum_a6xx_format.define('FMT6_ASTC_4x4', 193) +FMT6_ASTC_5x4 = enum_a6xx_format.define('FMT6_ASTC_5x4', 194) +FMT6_ASTC_5x5 = enum_a6xx_format.define('FMT6_ASTC_5x5', 195) +FMT6_ASTC_6x5 = enum_a6xx_format.define('FMT6_ASTC_6x5', 196) +FMT6_ASTC_6x6 = enum_a6xx_format.define('FMT6_ASTC_6x6', 197) +FMT6_ASTC_8x5 = enum_a6xx_format.define('FMT6_ASTC_8x5', 198) +FMT6_ASTC_8x6 = enum_a6xx_format.define('FMT6_ASTC_8x6', 199) +FMT6_ASTC_8x8 = enum_a6xx_format.define('FMT6_ASTC_8x8', 200) +FMT6_ASTC_10x5 = enum_a6xx_format.define('FMT6_ASTC_10x5', 201) +FMT6_ASTC_10x6 = enum_a6xx_format.define('FMT6_ASTC_10x6', 202) +FMT6_ASTC_10x8 = enum_a6xx_format.define('FMT6_ASTC_10x8', 203) +FMT6_ASTC_10x10 = enum_a6xx_format.define('FMT6_ASTC_10x10', 204) +FMT6_ASTC_12x10 = enum_a6xx_format.define('FMT6_ASTC_12x10', 205) +FMT6_ASTC_12x12 = enum_a6xx_format.define('FMT6_ASTC_12x12', 206) +FMT6_Z24_UINT_S8_UINT = enum_a6xx_format.define('FMT6_Z24_UINT_S8_UINT', 234) +FMT6_NONE = enum_a6xx_format.define('FMT6_NONE', 255) + +enum_a6xx_polygon_mode = CEnum(ctypes.c_uint32) +POLYMODE6_POINTS = enum_a6xx_polygon_mode.define('POLYMODE6_POINTS', 1) +POLYMODE6_LINES = enum_a6xx_polygon_mode.define('POLYMODE6_LINES', 2) +POLYMODE6_TRIANGLES = enum_a6xx_polygon_mode.define('POLYMODE6_TRIANGLES', 3) + +enum_a6xx_depth_format = CEnum(ctypes.c_uint32) +DEPTH6_NONE = enum_a6xx_depth_format.define('DEPTH6_NONE', 0) +DEPTH6_16 = enum_a6xx_depth_format.define('DEPTH6_16', 1) +DEPTH6_24_8 = enum_a6xx_depth_format.define('DEPTH6_24_8', 2) +DEPTH6_32 = enum_a6xx_depth_format.define('DEPTH6_32', 4) + +enum_a6xx_shader_id = CEnum(ctypes.c_uint32) +A6XX_TP0_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_TMO_DATA', 9) +A6XX_TP0_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP0_SMO_DATA', 10) +A6XX_TP0_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP0_MIPMAP_BASE_DATA', 11) +A6XX_TP1_TMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_TMO_DATA', 25) +A6XX_TP1_SMO_DATA = enum_a6xx_shader_id.define('A6XX_TP1_SMO_DATA', 26) +A6XX_TP1_MIPMAP_BASE_DATA = enum_a6xx_shader_id.define('A6XX_TP1_MIPMAP_BASE_DATA', 27) +A6XX_SP_INST_DATA = enum_a6xx_shader_id.define('A6XX_SP_INST_DATA', 41) +A6XX_SP_LB_0_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_0_DATA', 42) +A6XX_SP_LB_1_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_1_DATA', 43) +A6XX_SP_LB_2_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_2_DATA', 44) +A6XX_SP_LB_3_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_3_DATA', 45) +A6XX_SP_LB_4_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_4_DATA', 46) +A6XX_SP_LB_5_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_5_DATA', 47) +A6XX_SP_CB_BINDLESS_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_DATA', 48) +A6XX_SP_CB_LEGACY_DATA = enum_a6xx_shader_id.define('A6XX_SP_CB_LEGACY_DATA', 49) +A6XX_SP_GFX_UAV_BASE_DATA = enum_a6xx_shader_id.define('A6XX_SP_GFX_UAV_BASE_DATA', 50) +A6XX_SP_INST_TAG = enum_a6xx_shader_id.define('A6XX_SP_INST_TAG', 51) +A6XX_SP_CB_BINDLESS_TAG = enum_a6xx_shader_id.define('A6XX_SP_CB_BINDLESS_TAG', 52) +A6XX_SP_TMO_UMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_TMO_UMO_TAG', 53) +A6XX_SP_SMO_TAG = enum_a6xx_shader_id.define('A6XX_SP_SMO_TAG', 54) +A6XX_SP_STATE_DATA = enum_a6xx_shader_id.define('A6XX_SP_STATE_DATA', 55) +A6XX_HLSQ_CHUNK_CVS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM', 73) +A6XX_HLSQ_CHUNK_CPS_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM', 74) +A6XX_HLSQ_CHUNK_CVS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CVS_RAM_TAG', 75) +A6XX_HLSQ_CHUNK_CPS_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CHUNK_CPS_RAM_TAG', 76) +A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CVS_CB_BASE_TAG', 77) +A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 78) +A6XX_HLSQ_CVS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM', 80) +A6XX_HLSQ_CPS_MISC_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM', 81) +A6XX_HLSQ_INST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM', 82) +A6XX_HLSQ_GFX_CVS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM', 83) +A6XX_HLSQ_GFX_CPS_CONST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM', 84) +A6XX_HLSQ_CVS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CVS_MISC_RAM_TAG', 85) +A6XX_HLSQ_CPS_MISC_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_CPS_MISC_RAM_TAG', 86) +A6XX_HLSQ_INST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_TAG', 87) +A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG', 88) +A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG', 89) +A6XX_HLSQ_PWR_REST_RAM = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_RAM', 90) +A6XX_HLSQ_PWR_REST_TAG = enum_a6xx_shader_id.define('A6XX_HLSQ_PWR_REST_TAG', 91) +A6XX_HLSQ_DATAPATH_META = enum_a6xx_shader_id.define('A6XX_HLSQ_DATAPATH_META', 96) +A6XX_HLSQ_FRONTEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_FRONTEND_META', 97) +A6XX_HLSQ_INDIRECT_META = enum_a6xx_shader_id.define('A6XX_HLSQ_INDIRECT_META', 98) +A6XX_HLSQ_BACKEND_META = enum_a6xx_shader_id.define('A6XX_HLSQ_BACKEND_META', 99) +A6XX_SP_LB_6_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_6_DATA', 112) +A6XX_SP_LB_7_DATA = enum_a6xx_shader_id.define('A6XX_SP_LB_7_DATA', 113) +A6XX_HLSQ_INST_RAM_1 = enum_a6xx_shader_id.define('A6XX_HLSQ_INST_RAM_1', 115) + +enum_a6xx_debugbus_id = CEnum(ctypes.c_uint32) +A6XX_DBGBUS_CP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CP', 1) +A6XX_DBGBUS_RBBM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBBM', 2) +A6XX_DBGBUS_VBIF = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VBIF', 3) +A6XX_DBGBUS_HLSQ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ', 4) +A6XX_DBGBUS_UCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE', 5) +A6XX_DBGBUS_DPM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DPM', 6) +A6XX_DBGBUS_TESS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TESS', 7) +A6XX_DBGBUS_PC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_PC', 8) +A6XX_DBGBUS_VFDP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFDP', 9) +A6XX_DBGBUS_VPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VPC', 10) +A6XX_DBGBUS_TSE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TSE', 11) +A6XX_DBGBUS_RAS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RAS', 12) +A6XX_DBGBUS_VSC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VSC', 13) +A6XX_DBGBUS_COM = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_COM', 14) +A6XX_DBGBUS_LRZ = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LRZ', 16) +A6XX_DBGBUS_A2D = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_A2D', 17) +A6XX_DBGBUS_CCUFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCUFCHE', 18) +A6XX_DBGBUS_GMU_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_CX', 19) +A6XX_DBGBUS_RBP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RBP', 20) +A6XX_DBGBUS_DCS = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DCS', 21) +A6XX_DBGBUS_DBGC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_DBGC', 22) +A6XX_DBGBUS_CX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CX', 23) +A6XX_DBGBUS_GMU_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GMU_GX', 24) +A6XX_DBGBUS_TPFCHE = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPFCHE', 25) +A6XX_DBGBUS_GBIF_GX = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GBIF_GX', 26) +A6XX_DBGBUS_GPC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_GPC', 29) +A6XX_DBGBUS_LARC = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_LARC', 30) +A6XX_DBGBUS_HLSQ_SPTP = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_HLSQ_SPTP', 31) +A6XX_DBGBUS_RB_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_0', 32) +A6XX_DBGBUS_RB_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_1', 33) +A6XX_DBGBUS_RB_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_RB_2', 34) +A6XX_DBGBUS_UCHE_WRAPPER = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_UCHE_WRAPPER', 36) +A6XX_DBGBUS_CCU_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_0', 40) +A6XX_DBGBUS_CCU_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_1', 41) +A6XX_DBGBUS_CCU_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_CCU_2', 42) +A6XX_DBGBUS_VFD_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_0', 56) +A6XX_DBGBUS_VFD_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_1', 57) +A6XX_DBGBUS_VFD_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_2', 58) +A6XX_DBGBUS_VFD_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_3', 59) +A6XX_DBGBUS_VFD_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_4', 60) +A6XX_DBGBUS_VFD_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_VFD_5', 61) +A6XX_DBGBUS_SP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_0', 64) +A6XX_DBGBUS_SP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_1', 65) +A6XX_DBGBUS_SP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SP_2', 66) +A6XX_DBGBUS_TPL1_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_0', 72) +A6XX_DBGBUS_TPL1_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_1', 73) +A6XX_DBGBUS_TPL1_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_2', 74) +A6XX_DBGBUS_TPL1_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_3', 75) +A6XX_DBGBUS_TPL1_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_4', 76) +A6XX_DBGBUS_TPL1_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_TPL1_5', 77) +A6XX_DBGBUS_SPTP_0 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_0', 88) +A6XX_DBGBUS_SPTP_1 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_1', 89) +A6XX_DBGBUS_SPTP_2 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_2', 90) +A6XX_DBGBUS_SPTP_3 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_3', 91) +A6XX_DBGBUS_SPTP_4 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_4', 92) +A6XX_DBGBUS_SPTP_5 = enum_a6xx_debugbus_id.define('A6XX_DBGBUS_SPTP_5', 93) + +enum_a6xx_2d_ifmt = CEnum(ctypes.c_uint32) +R2D_INT32 = enum_a6xx_2d_ifmt.define('R2D_INT32', 7) +R2D_INT16 = enum_a6xx_2d_ifmt.define('R2D_INT16', 6) +R2D_INT8 = enum_a6xx_2d_ifmt.define('R2D_INT8', 5) +R2D_FLOAT32 = enum_a6xx_2d_ifmt.define('R2D_FLOAT32', 4) +R2D_FLOAT16 = enum_a6xx_2d_ifmt.define('R2D_FLOAT16', 3) +R2D_SNORM8 = enum_a6xx_2d_ifmt.define('R2D_SNORM8', 2) +R2D_UNORM8_SRGB = enum_a6xx_2d_ifmt.define('R2D_UNORM8_SRGB', 1) +R2D_UNORM8 = enum_a6xx_2d_ifmt.define('R2D_UNORM8', 0) + +enum_a6xx_tex_type = CEnum(ctypes.c_uint32) +A6XX_TEX_1D = enum_a6xx_tex_type.define('A6XX_TEX_1D', 0) +A6XX_TEX_2D = enum_a6xx_tex_type.define('A6XX_TEX_2D', 1) +A6XX_TEX_CUBE = enum_a6xx_tex_type.define('A6XX_TEX_CUBE', 2) +A6XX_TEX_3D = enum_a6xx_tex_type.define('A6XX_TEX_3D', 3) +A6XX_TEX_BUFFER = enum_a6xx_tex_type.define('A6XX_TEX_BUFFER', 4) +A6XX_TEX_IMG_BUFFER = enum_a6xx_tex_type.define('A6XX_TEX_IMG_BUFFER', 5) + +enum_a6xx_ztest_mode = CEnum(ctypes.c_uint32) +A6XX_EARLY_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_Z', 0) +A6XX_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_LATE_Z', 1) +A6XX_EARLY_Z_LATE_Z = enum_a6xx_ztest_mode.define('A6XX_EARLY_Z_LATE_Z', 2) +A6XX_INVALID_ZTEST = enum_a6xx_ztest_mode.define('A6XX_INVALID_ZTEST', 3) + +enum_a6xx_tess_spacing = CEnum(ctypes.c_uint32) +TESS_EQUAL = enum_a6xx_tess_spacing.define('TESS_EQUAL', 0) +TESS_FRACTIONAL_ODD = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_ODD', 2) +TESS_FRACTIONAL_EVEN = enum_a6xx_tess_spacing.define('TESS_FRACTIONAL_EVEN', 3) + +enum_a6xx_tess_output = CEnum(ctypes.c_uint32) +TESS_POINTS = enum_a6xx_tess_output.define('TESS_POINTS', 0) +TESS_LINES = enum_a6xx_tess_output.define('TESS_LINES', 1) +TESS_CW_TRIS = enum_a6xx_tess_output.define('TESS_CW_TRIS', 2) +TESS_CCW_TRIS = enum_a6xx_tess_output.define('TESS_CCW_TRIS', 3) + +enum_a6xx_tex_filter = CEnum(ctypes.c_uint32) +A6XX_TEX_NEAREST = enum_a6xx_tex_filter.define('A6XX_TEX_NEAREST', 0) +A6XX_TEX_LINEAR = enum_a6xx_tex_filter.define('A6XX_TEX_LINEAR', 1) +A6XX_TEX_ANISO = enum_a6xx_tex_filter.define('A6XX_TEX_ANISO', 2) +A6XX_TEX_CUBIC = enum_a6xx_tex_filter.define('A6XX_TEX_CUBIC', 3) + +enum_a6xx_tex_clamp = CEnum(ctypes.c_uint32) +A6XX_TEX_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_REPEAT', 0) +A6XX_TEX_CLAMP_TO_EDGE = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_EDGE', 1) +A6XX_TEX_MIRROR_REPEAT = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_REPEAT', 2) +A6XX_TEX_CLAMP_TO_BORDER = enum_a6xx_tex_clamp.define('A6XX_TEX_CLAMP_TO_BORDER', 3) +A6XX_TEX_MIRROR_CLAMP = enum_a6xx_tex_clamp.define('A6XX_TEX_MIRROR_CLAMP', 4) + +enum_a6xx_tex_aniso = CEnum(ctypes.c_uint32) +A6XX_TEX_ANISO_1 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_1', 0) +A6XX_TEX_ANISO_2 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_2', 1) +A6XX_TEX_ANISO_4 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_4', 2) +A6XX_TEX_ANISO_8 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_8', 3) +A6XX_TEX_ANISO_16 = enum_a6xx_tex_aniso.define('A6XX_TEX_ANISO_16', 4) + +enum_a6xx_reduction_mode = CEnum(ctypes.c_uint32) +A6XX_REDUCTION_MODE_AVERAGE = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_AVERAGE', 0) +A6XX_REDUCTION_MODE_MIN = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MIN', 1) +A6XX_REDUCTION_MODE_MAX = enum_a6xx_reduction_mode.define('A6XX_REDUCTION_MODE_MAX', 2) + +enum_a6xx_fast_border_color = CEnum(ctypes.c_uint32) +A6XX_BORDER_COLOR_0_0_0_0 = enum_a6xx_fast_border_color.define('A6XX_BORDER_COLOR_0_0_0_0', 0) +A6XX_BORDER_COLOR_0_0_0_1 = enum_a6xx_fast_border_color.define('A6XX_BORDER_COLOR_0_0_0_1', 1) +A6XX_BORDER_COLOR_1_1_1_0 = enum_a6xx_fast_border_color.define('A6XX_BORDER_COLOR_1_1_1_0', 2) +A6XX_BORDER_COLOR_1_1_1_1 = enum_a6xx_fast_border_color.define('A6XX_BORDER_COLOR_1_1_1_1', 3) + +enum_a6xx_tex_swiz = CEnum(ctypes.c_uint32) +A6XX_TEX_X = enum_a6xx_tex_swiz.define('A6XX_TEX_X', 0) +A6XX_TEX_Y = enum_a6xx_tex_swiz.define('A6XX_TEX_Y', 1) +A6XX_TEX_Z = enum_a6xx_tex_swiz.define('A6XX_TEX_Z', 2) +A6XX_TEX_W = enum_a6xx_tex_swiz.define('A6XX_TEX_W', 3) +A6XX_TEX_ZERO = enum_a6xx_tex_swiz.define('A6XX_TEX_ZERO', 4) +A6XX_TEX_ONE = enum_a6xx_tex_swiz.define('A6XX_TEX_ONE', 5) + NIR_DEBUG_CLONE = (1 << 0) NIR_DEBUG_SERIALIZE = (1 << 1) NIR_DEBUG_NOVALIDATE = (1 << 2) @@ -8320,4 +9312,4380 @@ DECLARE_RALLOC_CXX_OPERATORS = lambda type: DECLARE_RALLOC_CXX_OPERATORS_TEMPLAT DECLARE_RZALLOC_CXX_OPERATORS = lambda type: DECLARE_RALLOC_CXX_OPERATORS_TEMPLATE(type, rzalloc_size) DECLARE_LINEAR_ALLOC_CXX_OPERATORS = lambda type: DECLARE_LINEAR_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_alloc_child) DECLARE_LINEAR_ZALLOC_CXX_OPERATORS = lambda type: DECLARE_LINEAR_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_zalloc_child) +__struct__cast = lambda X: (struct_X) +A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 +A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 +A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 +A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 +A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 +A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 +A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 +A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 +A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 +A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 +A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 +A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 +A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 +A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 +A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 +A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 +A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 +A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 +A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 +A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 +A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 +A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 +A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 +A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 +A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 +A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 +A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 +A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 +A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 +A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 +A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 +A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 +A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 +A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 +A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 +A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 +A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 +A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 +A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 +A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 +A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 +A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 +A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 +REG_A6XX_CP_RB_BASE = 0x00000800 +REG_A6XX_CP_RB_CNTL = 0x00000802 +REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 +REG_A6XX_CP_RB_RPTR = 0x00000806 +REG_A6XX_CP_RB_WPTR = 0x00000807 +REG_A6XX_CP_SQE_CNTL = 0x00000808 +REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 +A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 +REG_A6XX_CP_HW_FAULT = 0x00000821 +REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 +REG_A6XX_CP_PROTECT_STATUS = 0x00000824 +REG_A6XX_CP_STATUS_1 = 0x00000825 +REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 +REG_A6XX_CP_MISC_CNTL = 0x00000840 +REG_A6XX_CP_APRIV_CNTL = 0x00000844 +A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 +A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 +A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 +A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 +A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 +A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 +REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 +REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 +A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff +A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 +A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 +A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 +A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 +A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 +A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 +A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 +REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 +A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff +A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 +A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 +A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 +REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 +REG_A6XX_CP_CHICKEN_DBG = 0x00000841 +REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 +REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 +REG_A6XX_CP_PROTECT_CNTL = 0x0000084f +A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 +A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 +A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 +REG_A6XX_CP_SCRATCH = lambda i0: (0x00000883 + 0x1*i0 ) +REG_A6XX_CP_PROTECT = lambda i0: (0x00000850 + 0x1*i0 ) +A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff +A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 +A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 +A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 +A6XX_CP_PROTECT_REG_READ = 0x80000000 +REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 +A6XX_CP_CONTEXT_SWITCH_CNTL_STOP = 0x00000001 +A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL__MASK = 0x000000c0 +A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL__SHIFT = 6 +A6XX_CP_CONTEXT_SWITCH_CNTL_USES_GMEM = 0x00000100 +A6XX_CP_CONTEXT_SWITCH_CNTL_SKIP_SAVE_RESTORE = 0x00000200 +REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 +REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 +REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 +REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 +REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab +REG_A6XX_CP_PERFCTR_CP_SEL = lambda i0: (0x000008d0 + 0x1*i0 ) +REG_A7XX_CP_BV_PERFCTR_CP_SEL = lambda i0: (0x000008e0 + 0x1*i0 ) +REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE = 0x00000900 +REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 +REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 +REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 +REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 +REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a +REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b +REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c +REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d +REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e +REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f +REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 +REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 +REG_A6XX_CP_IB1_BASE = 0x00000928 +REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a +REG_A6XX_CP_IB2_BASE = 0x0000092b +REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d +REG_A6XX_CP_SDS_BASE = 0x0000092e +REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 +REG_A6XX_CP_MRB_BASE = 0x00000931 +REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 +REG_A6XX_CP_VSD_BASE = 0x00000934 +REG_A6XX_CP_ROQ_RB_STATUS = 0x00000939 +A6XX_CP_ROQ_RB_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_RB_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_RB_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_RB_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_IB1_STATUS = 0x0000093a +A6XX_CP_ROQ_IB1_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_IB1_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_IB1_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_IB1_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_IB2_STATUS = 0x0000093b +A6XX_CP_ROQ_IB2_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_IB2_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_IB2_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_IB2_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_SDS_STATUS = 0x0000093c +A6XX_CP_ROQ_SDS_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_SDS_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_SDS_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_SDS_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_MRB_STATUS = 0x0000093d +A6XX_CP_ROQ_MRB_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_MRB_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_MRB_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_MRB_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_ROQ_VSD_STATUS = 0x0000093e +A6XX_CP_ROQ_VSD_STATUS_RPTR__MASK = 0x000003ff +A6XX_CP_ROQ_VSD_STATUS_RPTR__SHIFT = 0 +A6XX_CP_ROQ_VSD_STATUS_WPTR__MASK = 0x03ff0000 +A6XX_CP_ROQ_VSD_STATUS_WPTR__SHIFT = 16 +REG_A6XX_CP_IB1_INIT_SIZE = 0x00000943 +REG_A6XX_CP_IB2_INIT_SIZE = 0x00000944 +REG_A6XX_CP_SDS_INIT_SIZE = 0x00000945 +REG_A6XX_CP_MRB_INIT_SIZE = 0x00000946 +REG_A6XX_CP_VSD_INIT_SIZE = 0x00000947 +REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 +A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 +A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a +A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b +A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c +A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 +REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d +A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 +A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 +REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 +REG_A6XX_CP_AHB_CNTL = 0x0000098d +REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 +REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 +A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 +A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 +A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 +A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 +A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 +A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 +REG_A6XX_CP_APERTURE_CNTL_SQE = 0x00000a01 +REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 +REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 +A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 +A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 +A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 +A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 +A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 +A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 +REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 +REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 +REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 +REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 +REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 +REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 +REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 +REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 +REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 +REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 +REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 +REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 +REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 +REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR = 0x00000a9a +REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA = 0x00000a9b +REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 +REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada +REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a +REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b +REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c +REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 +REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 +REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 +REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a +REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 +REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 +REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 +REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 +REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 +REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 +REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 +REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 +REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 +REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 +REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 +REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 +REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac +REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad +REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 +REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 +REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 +REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 +REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 +REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 +REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc +REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd +REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 +REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 +REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 +REG_A6XX_RBBM_STATUS = 0x00000210 +A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 +A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 +A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 +A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 +A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 +A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 +A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 +A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 +A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 +A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 +A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 +A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 +A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 +A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 +A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 +A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 +A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 +A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 +A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 +A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 +A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 +A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 +A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 +A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 +REG_A6XX_RBBM_STATUS1 = 0x00000211 +REG_A6XX_RBBM_STATUS2 = 0x00000212 +REG_A6XX_RBBM_STATUS3 = 0x00000213 +A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 +REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 +REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 +REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 +REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 +REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 +REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 +REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 +REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 +REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 +REG_A6XX_RBBM_PERFCTR_CP = lambda i0: (0x00000400 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000041c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_PC = lambda i0: (0x00000424 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000434 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000444 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000450 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000045c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000466 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000046e + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000476 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_TP = lambda i0: (0x0000048e + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_SP = lambda i0: (0x000004a6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_RB = lambda i0: (0x000004d6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_VSC = lambda i0: (0x000004e6 + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000004ea + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CMP = lambda i0: (0x000004f2 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CP = lambda i0: (0x00000300 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RBBM = lambda i0: (0x0000031c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_PC = lambda i0: (0x00000324 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VFD = lambda i0: (0x00000334 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_HLSQ = lambda i0: (0x00000344 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VPC = lambda i0: (0x00000350 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CCU = lambda i0: (0x0000035c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_TSE = lambda i0: (0x00000366 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RAS = lambda i0: (0x0000036e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_UCHE = lambda i0: (0x00000376 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_TP = lambda i0: (0x0000038e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_SP = lambda i0: (0x000003a6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_RB = lambda i0: (0x000003d6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_VSC = lambda i0: (0x000003e6 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_LRZ = lambda i0: (0x000003ea + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_CMP = lambda i0: (0x000003f2 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_UFC = lambda i0: (0x000003fa + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_HLSQ = lambda i0: (0x00000410 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_CP = lambda i0: (0x0000041c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_SP = lambda i0: (0x0000042a + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_TP = lambda i0: (0x00000442 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR2_UFC = lambda i0: (0x0000044e + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_PC = lambda i0: (0x00000460 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_VFD = lambda i0: (0x00000470 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_VPC = lambda i0: (0x00000480 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_TSE = lambda i0: (0x0000048c + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_RAS = lambda i0: (0x00000494 + 0x2*i0 ) +REG_A7XX_RBBM_PERFCTR_BV_LRZ = lambda i0: (0x0000049c + 0x2*i0 ) +REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 +REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 +REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 +REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 +REG_A6XX_RBBM_PERFCTR_RBBM_SEL = lambda i0: (0x00000507 + 0x1*i0 ) +REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b +REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e +REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f +REG_A6XX_RBBM_ISDB_CNT = 0x00000533 +REG_A6XX_RBBM_NC_MODE_CNTL = 0x00000534 +REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 +REG_A6XX_RBBM_PIPESTAT_IAVERTICES = 0x00000540 +REG_A6XX_RBBM_PIPESTAT_IAPRIMITIVES = 0x00000542 +REG_A6XX_RBBM_PIPESTAT_VSINVOCATIONS = 0x00000544 +REG_A6XX_RBBM_PIPESTAT_HSINVOCATIONS = 0x00000546 +REG_A6XX_RBBM_PIPESTAT_DSINVOCATIONS = 0x00000548 +REG_A6XX_RBBM_PIPESTAT_GSINVOCATIONS = 0x0000054a +REG_A6XX_RBBM_PIPESTAT_GSPRIMITIVES = 0x0000054c +REG_A6XX_RBBM_PIPESTAT_CINVOCATIONS = 0x0000054e +REG_A6XX_RBBM_PIPESTAT_CPRIMITIVES = 0x00000550 +REG_A6XX_RBBM_PIPESTAT_PSINVOCATIONS = 0x00000552 +REG_A6XX_RBBM_PIPESTAT_CSINVOCATIONS = 0x00000554 +REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 +REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 +REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 +REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 +REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 +REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 +REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 +REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 +REG_A6XX_RBBM_GBIF_HALT = 0x00000016 +REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 +REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c +A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 +REG_A7XX_RBBM_GBIF_HALT = 0x00000016 +REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 +REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f +REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 +REG_A6XX_RBBM_INT_0_MASK = 0x00000038 +REG_A7XX_RBBM_INT_2_MASK = 0x0000003a +REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 +REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 +REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 +REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 +REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 +REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad +REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae +REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 +REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 +REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 +REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 +REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 +REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 +REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 +REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 +REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 +REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 +REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba +REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb +REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc +REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd +REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be +REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf +REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 +REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 +REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 +REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 +REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 +REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 +REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 +REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 +REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 +REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 +REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca +REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb +REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc +REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd +REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce +REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf +REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 +REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 +REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 +REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 +REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 +REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 +REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 +REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 +REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 +REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 +REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da +REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db +REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc +REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd +REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de +REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df +REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 +REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 +REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 +REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 +REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 +REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 +REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 +REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 +REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 +REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 +REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea +REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb +REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec +REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed +REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee +REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef +REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 +REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 +REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 +REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 +REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 +REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 +REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 +REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 +REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 +REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 +REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa +REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 +REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 +REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 +REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 +REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 +REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 +REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 +REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 +REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a +REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b +REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c +REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d +REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e +REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f +REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 +REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 +REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 +REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 +REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 +REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 +REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 +REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 +REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 +REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 +REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a +REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b +REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c +REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d +REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e +REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f +REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 +REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 +REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 +REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 +A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 +REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 +REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 +REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 +REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 +REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 +REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 +REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 +REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a +REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b +REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f +REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff +REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 +REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 +A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 +REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 +A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f +A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 +A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 +A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a +REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e +REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f +REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 +A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 +REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f +REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 +REG_A6XX_VSC_PERFCTR_VSC_SEL = lambda i0: (0x00000cd8 + 0x1*i0 ) +REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 +A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 +REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 +REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 +REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 +REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 +REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 +REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 +REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 +REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b +REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d +REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 +REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 +REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 +A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff +A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 +REG_A6XX_UCHE_PERFCTR_UCHE_SEL = lambda i0: (0x00000e1c + 0x1*i0 ) +REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a +REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c +REG_A6XX_VBIF_VERSION = 0x00003000 +REG_A6XX_VBIF_CLKON = 0x00003001 +A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 +REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a +REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 +REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 +REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 +REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 +REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 +A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f +A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 +REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 +REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 +A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff +A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 +REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c +REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 +REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 +REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 +REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 +REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 +REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 +REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da +REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db +REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 +REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 +REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 +REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 +REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 +REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 +REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 +REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 +REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a +REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 +REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 +REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 +REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 +REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 +REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 +REG_A6XX_GBIF_HALT = 0x00003c45 +REG_A6XX_GBIF_HALT_ACK = 0x00003c46 +REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 +REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 +REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 +REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 +REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 +REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 +REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 +REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 +REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 +REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 +REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca +REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb +REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc +REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd +REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce +REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf +REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 +REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 +REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 +REG_A6XX_VSC_BIN_SIZE = 0x00000c02 +A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff +A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 +A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 +A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 +REG_A6XX_VSC_SIZE_BASE = 0x00000c03 +REG_A6XX_VSC_EXPANDED_BIN_CNTL = 0x00000c06 +A6XX_VSC_EXPANDED_BIN_CNTL_NX__MASK = 0x000007fe +A6XX_VSC_EXPANDED_BIN_CNTL_NX__SHIFT = 1 +A6XX_VSC_EXPANDED_BIN_CNTL_NY__MASK = 0x001ff800 +A6XX_VSC_EXPANDED_BIN_CNTL_NY__SHIFT = 11 +REG_A6XX_VSC_PIPE_CONFIG = lambda i0: (0x00000c10 + 0x1*i0 ) +A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff +A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 +A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 +A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 +A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 +A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 +A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 +A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 +REG_A6XX_VSC_PIPE_DATA_PRIM_BASE = 0x00000c30 +REG_A6XX_VSC_PIPE_DATA_PRIM_STRIDE = 0x00000c32 +REG_A6XX_VSC_PIPE_DATA_PRIM_LENGTH = 0x00000c33 +REG_A6XX_VSC_PIPE_DATA_DRAW_BASE = 0x00000c34 +REG_A6XX_VSC_PIPE_DATA_DRAW_STRIDE = 0x00000c36 +REG_A6XX_VSC_PIPE_DATA_DRAW_LENGTH = 0x00000c37 +REG_A6XX_VSC_CHANNEL_VISIBILITY = lambda i0: (0x00000c38 + 0x1*i0 ) +REG_A6XX_VSC_PIPE_DATA_PRIM_SIZE = lambda i0: (0x00000c58 + 0x1*i0 ) +REG_A6XX_VSC_PIPE_DATA_DRAW_SIZE = lambda i0: (0x00000c78 + 0x1*i0 ) +REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 +REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 +REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 +REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 +REG_A6XX_GRAS_CL_CNTL = 0x00008000 +A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 +A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 +A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 +A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 +A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 +A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 +A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 +A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 +REG_A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE = 0x00008001 +A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE = 0x00008002 +A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE = 0x00008003 +A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE_CLIP_MASK__MASK = 0x000000ff +A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE_CLIP_MASK__SHIFT = 0 +A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE_CULL_MASK__MASK = 0x0000ff00 +A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE_CULL_MASK__SHIFT = 8 +REG_A6XX_GRAS_CL_ARRAY_SIZE = 0x00008004 +REG_A6XX_GRAS_CL_INTERP_CNTL = 0x00008005 +A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_PIXEL = 0x00000001 +A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_CENTROID = 0x00000002 +A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_SAMPLE = 0x00000004 +A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_PIXEL = 0x00000008 +A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_CENTROID = 0x00000010 +A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 +A6XX_GRAS_CL_INTERP_CNTL_COORD_MASK__MASK = 0x000003c0 +A6XX_GRAS_CL_INTERP_CNTL_COORD_MASK__SHIFT = 6 +A6XX_GRAS_CL_INTERP_CNTL_UNK10 = 0x00000400 +A6XX_GRAS_CL_INTERP_CNTL_UNK11 = 0x00000800 +REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 +A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 +REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 +REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 +REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 +REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a +REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b +REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c +REG_A6XX_GRAS_CL_VIEWPORT = lambda i0: (0x00008010 + 0x6*i0 ) +A6XX_GRAS_CL_VIEWPORT_XOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_XOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_XSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_XSCALE__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_YOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_YOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_YSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_YSCALE__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_ZOFFSET__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_ZOFFSET__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_ZSCALE__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_ZSCALE__SHIFT = 0 +REG_A6XX_GRAS_CL_VIEWPORT_ZCLAMP = lambda i0: (0x00008070 + 0x2*i0 ) +A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MIN__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MIN__SHIFT = 0 +A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MAX__MASK = 0xffffffff +A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MAX__SHIFT = 0 +REG_A6XX_GRAS_SU_CNTL = 0x00008090 +A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 +A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 +A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 +A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 +A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 +A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 +A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 +A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 +A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 +A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 +A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 +A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 +A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 +A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 +A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 +A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 +REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 +A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff +A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 +A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 +A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 +REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 +A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff +A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 +REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 +A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 +A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 +A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 +A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 +REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 +A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff +A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 +REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 +REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 +A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 +REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a +A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 +A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 +REG_A6XX_GRAS_SU_VS_SIV_CNTL = 0x0000809b +A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_SU_GS_SIV_CNTL = 0x0000809c +A6XX_GRAS_SU_GS_SIV_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_SU_GS_SIV_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_SU_DS_SIV_CNTL = 0x0000809d +A6XX_GRAS_SU_DS_SIV_CNTL_WRITES_LAYER = 0x00000001 +A6XX_GRAS_SU_DS_SIV_CNTL_WRITES_VIEW = 0x00000002 +REG_A6XX_GRAS_SC_CNTL = 0x000080a0 +A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 +A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 +A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 +A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 +A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 +A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 +A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 +A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 +A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 +A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 +A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 +A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 +A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 +A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 +REG_A6XX_GRAS_SC_BIN_CNTL = 0x000080a1 +A6XX_GRAS_SC_BIN_CNTL_BINW__MASK = 0x0000003f +A6XX_GRAS_SC_BIN_CNTL_BINW__SHIFT = 0 +A6XX_GRAS_SC_BIN_CNTL_BINH__MASK = 0x00007f00 +A6XX_GRAS_SC_BIN_CNTL_BINH__SHIFT = 8 +A6XX_GRAS_SC_BIN_CNTL_RENDER_MODE__MASK = 0x001c0000 +A6XX_GRAS_SC_BIN_CNTL_RENDER_MODE__SHIFT = 18 +A6XX_GRAS_SC_BIN_CNTL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A6XX_GRAS_SC_BIN_CNTL_BUFFERS_LOCATION__MASK = 0x00c00000 +A6XX_GRAS_SC_BIN_CNTL_BUFFERS_LOCATION__SHIFT = 22 +A6XX_GRAS_SC_BIN_CNTL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A6XX_GRAS_SC_BIN_CNTL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +A6XX_GRAS_SC_BIN_CNTL_UNK27 = 0x08000000 +REG_A6XX_GRAS_SC_RAS_MSAA_CNTL = 0x000080a2 +A6XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_GRAS_SC_RAS_MSAA_CNTL_UNK2 = 0x00000004 +A6XX_GRAS_SC_RAS_MSAA_CNTL_UNK3 = 0x00000008 +REG_A6XX_GRAS_SC_DEST_MSAA_CNTL = 0x000080a3 +A6XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL = 0x000080a4 +A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL_UNK0 = 0x00000001 +A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL_LOCATION_ENABLE = 0x00000002 +REG_A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0 = 0x000080a5 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__SHIFT = 0 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__SHIFT = 8 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__SHIFT = 16 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__SHIFT = 24 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1 = 0x000080a6 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__SHIFT = 0 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__SHIFT = 8 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__SHIFT = 16 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__SHIFT = 24 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__SHIFT = 28 +REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 +REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af +REG_A6XX_GRAS_SC_SCREEN_SCISSOR = lambda i0: (0x000080b0 + 0x2*i0 ) +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR = lambda i0: (0x000080d0 + 0x2*i0 ) +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 +A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 +A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 +REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 +A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 +REG_A7XX_GRAS_VRS_CONFIG = 0x000080f4 +A7XX_GRAS_VRS_CONFIG_PIPELINE_FSR_ENABLE = 0x00000001 +A7XX_GRAS_VRS_CONFIG_FRAG_SIZE_X__MASK = 0x00000006 +A7XX_GRAS_VRS_CONFIG_FRAG_SIZE_X__SHIFT = 1 +A7XX_GRAS_VRS_CONFIG_FRAG_SIZE_Y__MASK = 0x00000018 +A7XX_GRAS_VRS_CONFIG_FRAG_SIZE_Y__SHIFT = 3 +A7XX_GRAS_VRS_CONFIG_COMBINER_OP_1__MASK = 0x000000e0 +A7XX_GRAS_VRS_CONFIG_COMBINER_OP_1__SHIFT = 5 +A7XX_GRAS_VRS_CONFIG_COMBINER_OP_2__MASK = 0x00000700 +A7XX_GRAS_VRS_CONFIG_COMBINER_OP_2__SHIFT = 8 +A7XX_GRAS_VRS_CONFIG_ATTACHMENT_FSR_ENABLE = 0x00002000 +A7XX_GRAS_VRS_CONFIG_PRIMITIVE_FSR_ENABLE = 0x00100000 +REG_A7XX_GRAS_QUALITY_BUFFER_INFO = 0x000080f5 +A7XX_GRAS_QUALITY_BUFFER_INFO_LAYERED = 0x00000001 +A7XX_GRAS_QUALITY_BUFFER_INFO_TILE_MODE__MASK = 0x00000006 +A7XX_GRAS_QUALITY_BUFFER_INFO_TILE_MODE__SHIFT = 1 +REG_A7XX_GRAS_QUALITY_BUFFER_DIMENSION = 0x000080f6 +A7XX_GRAS_QUALITY_BUFFER_DIMENSION_WIDTH__MASK = 0x0000ffff +A7XX_GRAS_QUALITY_BUFFER_DIMENSION_WIDTH__SHIFT = 0 +A7XX_GRAS_QUALITY_BUFFER_DIMENSION_HEIGHT__MASK = 0xffff0000 +A7XX_GRAS_QUALITY_BUFFER_DIMENSION_HEIGHT__SHIFT = 16 +REG_A7XX_GRAS_QUALITY_BUFFER_BASE = 0x000080f8 +REG_A7XX_GRAS_QUALITY_BUFFER_PITCH = 0x000080fa +A7XX_GRAS_QUALITY_BUFFER_PITCH_PITCH__MASK = 0x000000ff +A7XX_GRAS_QUALITY_BUFFER_PITCH_PITCH__SHIFT = 0 +A7XX_GRAS_QUALITY_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 +A7XX_GRAS_QUALITY_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 +REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 +A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 +A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 +A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 +A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 +A6XX_GRAS_LRZ_CNTL_Z_WRITE_ENABLE = 0x00000010 +A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 +A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 +A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 +A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 +A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 +A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 +A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 +REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 +A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 +REG_A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0 = 0x00008102 +A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0_COLOR_FORMAT__MASK = 0x000000ff +A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0_COLOR_FORMAT__SHIFT = 0 +REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 +REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 +A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff +A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 +A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 +REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 +REG_A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL = 0x00008109 +A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE = 0x00000001 +REG_A6XX_GRAS_LRZ_VIEW_INFO = 0x0000810a +A6XX_GRAS_LRZ_VIEW_INFO_BASE_LAYER__MASK = 0x000007ff +A6XX_GRAS_LRZ_VIEW_INFO_BASE_LAYER__SHIFT = 0 +A6XX_GRAS_LRZ_VIEW_INFO_LAYER_COUNT__MASK = 0x07ff0000 +A6XX_GRAS_LRZ_VIEW_INFO_LAYER_COUNT__SHIFT = 16 +A6XX_GRAS_LRZ_VIEW_INFO_BASE_MIP_LEVEL__MASK = 0xf0000000 +A6XX_GRAS_LRZ_VIEW_INFO_BASE_MIP_LEVEL__SHIFT = 28 +REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b +A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 +A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 +REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 +REG_A7XX_GRAS_LRZ_DEPTH_CLEAR = 0x00008111 +A7XX_GRAS_LRZ_DEPTH_CLEAR__MASK = 0xffffffff +A7XX_GRAS_LRZ_DEPTH_CLEAR__SHIFT = 0 +REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 +REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 +REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 +REG_A6XX_GRAS_A2D_BLT_CNTL = 0x00008400 +A6XX_GRAS_A2D_BLT_CNTL_ROTATE__MASK = 0x00000007 +A6XX_GRAS_A2D_BLT_CNTL_ROTATE__SHIFT = 0 +A6XX_GRAS_A2D_BLT_CNTL_OVERWRITEEN = 0x00000008 +A6XX_GRAS_A2D_BLT_CNTL_UNK4__MASK = 0x00000070 +A6XX_GRAS_A2D_BLT_CNTL_UNK4__SHIFT = 4 +A6XX_GRAS_A2D_BLT_CNTL_SOLID_COLOR = 0x00000080 +A6XX_GRAS_A2D_BLT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 +A6XX_GRAS_A2D_BLT_CNTL_COLOR_FORMAT__SHIFT = 8 +A6XX_GRAS_A2D_BLT_CNTL_SCISSOR = 0x00010000 +A6XX_GRAS_A2D_BLT_CNTL_UNK17__MASK = 0x00060000 +A6XX_GRAS_A2D_BLT_CNTL_UNK17__SHIFT = 17 +A6XX_GRAS_A2D_BLT_CNTL_D24S8 = 0x00080000 +A6XX_GRAS_A2D_BLT_CNTL_MASK__MASK = 0x00f00000 +A6XX_GRAS_A2D_BLT_CNTL_MASK__SHIFT = 20 +A6XX_GRAS_A2D_BLT_CNTL_IFMT__MASK = 0x07000000 +A6XX_GRAS_A2D_BLT_CNTL_IFMT__SHIFT = 24 +A6XX_GRAS_A2D_BLT_CNTL_UNK27 = 0x08000000 +A6XX_GRAS_A2D_BLT_CNTL_UNK28 = 0x10000000 +A6XX_GRAS_A2D_BLT_CNTL_RASTER_MODE__MASK = 0x20000000 +A6XX_GRAS_A2D_BLT_CNTL_RASTER_MODE__SHIFT = 29 +A6XX_GRAS_A2D_BLT_CNTL_COPY = 0x40000000 +REG_A6XX_GRAS_A2D_SRC_XMIN = 0x00008401 +A6XX_GRAS_A2D_SRC_XMIN__MASK = 0x01ffff00 +A6XX_GRAS_A2D_SRC_XMIN__SHIFT = 8 +REG_A6XX_GRAS_A2D_SRC_XMAX = 0x00008402 +A6XX_GRAS_A2D_SRC_XMAX__MASK = 0x01ffff00 +A6XX_GRAS_A2D_SRC_XMAX__SHIFT = 8 +REG_A6XX_GRAS_A2D_SRC_YMIN = 0x00008403 +A6XX_GRAS_A2D_SRC_YMIN__MASK = 0x01ffff00 +A6XX_GRAS_A2D_SRC_YMIN__SHIFT = 8 +REG_A6XX_GRAS_A2D_SRC_YMAX = 0x00008404 +A6XX_GRAS_A2D_SRC_YMAX__MASK = 0x01ffff00 +A6XX_GRAS_A2D_SRC_YMAX__SHIFT = 8 +REG_A6XX_GRAS_A2D_DEST_TL = 0x00008405 +A6XX_GRAS_A2D_DEST_TL_X__MASK = 0x00003fff +A6XX_GRAS_A2D_DEST_TL_X__SHIFT = 0 +A6XX_GRAS_A2D_DEST_TL_Y__MASK = 0x3fff0000 +A6XX_GRAS_A2D_DEST_TL_Y__SHIFT = 16 +REG_A6XX_GRAS_A2D_DEST_BR = 0x00008406 +A6XX_GRAS_A2D_DEST_BR_X__MASK = 0x00003fff +A6XX_GRAS_A2D_DEST_BR_X__SHIFT = 0 +A6XX_GRAS_A2D_DEST_BR_Y__MASK = 0x3fff0000 +A6XX_GRAS_A2D_DEST_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 +REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 +REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 +REG_A6XX_GRAS_A2D_SCISSOR_TL = 0x0000840a +A6XX_GRAS_A2D_SCISSOR_TL_X__MASK = 0x00003fff +A6XX_GRAS_A2D_SCISSOR_TL_X__SHIFT = 0 +A6XX_GRAS_A2D_SCISSOR_TL_Y__MASK = 0x3fff0000 +A6XX_GRAS_A2D_SCISSOR_TL_Y__SHIFT = 16 +REG_A6XX_GRAS_A2D_SCISSOR_BR = 0x0000840b +A6XX_GRAS_A2D_SCISSOR_BR_X__MASK = 0x00003fff +A6XX_GRAS_A2D_SCISSOR_BR_X__SHIFT = 0 +A6XX_GRAS_A2D_SCISSOR_BR_Y__MASK = 0x3fff0000 +A6XX_GRAS_A2D_SCISSOR_BR_Y__SHIFT = 16 +REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 +A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 +A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 +REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 +REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 +REG_A6XX_GRAS_PERFCTR_TSE_SEL = lambda i0: (0x00008610 + 0x1*i0 ) +REG_A6XX_GRAS_PERFCTR_RAS_SEL = lambda i0: (0x00008614 + 0x1*i0 ) +REG_A6XX_GRAS_PERFCTR_LRZ_SEL = lambda i0: (0x00008618 + 0x1*i0 ) +REG_A6XX_RB_CNTL = 0x00008800 +A6XX_RB_CNTL_BINW__MASK = 0x0000003f +A6XX_RB_CNTL_BINW__SHIFT = 0 +A6XX_RB_CNTL_BINH__MASK = 0x00007f00 +A6XX_RB_CNTL_BINH__SHIFT = 8 +A6XX_RB_CNTL_RENDER_MODE__MASK = 0x001c0000 +A6XX_RB_CNTL_RENDER_MODE__SHIFT = 18 +A6XX_RB_CNTL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A6XX_RB_CNTL_BUFFERS_LOCATION__MASK = 0x00c00000 +A6XX_RB_CNTL_BUFFERS_LOCATION__SHIFT = 22 +A6XX_RB_CNTL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A6XX_RB_CNTL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +REG_A7XX_RB_CNTL = 0x00008800 +A7XX_RB_CNTL_BINW__MASK = 0x0000003f +A7XX_RB_CNTL_BINW__SHIFT = 0 +A7XX_RB_CNTL_BINH__MASK = 0x00007f00 +A7XX_RB_CNTL_BINH__SHIFT = 8 +A7XX_RB_CNTL_RENDER_MODE__MASK = 0x001c0000 +A7XX_RB_CNTL_RENDER_MODE__SHIFT = 18 +A7XX_RB_CNTL_FORCE_LRZ_WRITE_DIS = 0x00200000 +A7XX_RB_CNTL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 +A7XX_RB_CNTL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 +REG_A6XX_RB_RENDER_CNTL = 0x00008801 +A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 +A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 +A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 +A6XX_RB_RENDER_CNTL_FS_DISABLE = 0x00000080 +A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 +A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 +A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 +A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 +A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 +A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 +A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 +A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 +A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 +A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 +A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 +REG_A7XX_RB_RENDER_CNTL = 0x00008801 +A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 +A7XX_RB_RENDER_CNTL_FS_DISABLE = 0x00000080 +A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 +A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 +A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 +A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 +A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 +A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 +REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 +A7XX_GRAS_SU_RENDER_CNTL_FS_DISABLE = 0x00000080 +REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 +A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 +A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 +REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 +A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_RB_MSAA_SAMPLE_POS_CNTL = 0x00008804 +A6XX_RB_MSAA_SAMPLE_POS_CNTL_UNK0 = 0x00000001 +A6XX_RB_MSAA_SAMPLE_POS_CNTL_LOCATION_ENABLE = 0x00000002 +REG_A6XX_RB_PROGRAMMABLE_MSAA_POS_0 = 0x00008805 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__SHIFT = 0 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__SHIFT = 8 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__SHIFT = 16 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__SHIFT = 24 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_RB_PROGRAMMABLE_MSAA_POS_1 = 0x00008806 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__SHIFT = 0 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__SHIFT = 8 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__SHIFT = 16 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__SHIFT = 24 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_RB_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_RB_INTERP_CNTL = 0x00008809 +A6XX_RB_INTERP_CNTL_IJ_PERSP_PIXEL = 0x00000001 +A6XX_RB_INTERP_CNTL_IJ_PERSP_CENTROID = 0x00000002 +A6XX_RB_INTERP_CNTL_IJ_PERSP_SAMPLE = 0x00000004 +A6XX_RB_INTERP_CNTL_IJ_LINEAR_PIXEL = 0x00000008 +A6XX_RB_INTERP_CNTL_IJ_LINEAR_CENTROID = 0x00000010 +A6XX_RB_INTERP_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 +A6XX_RB_INTERP_CNTL_COORD_MASK__MASK = 0x000003c0 +A6XX_RB_INTERP_CNTL_COORD_MASK__SHIFT = 6 +A6XX_RB_INTERP_CNTL_UNK10 = 0x00000400 +REG_A6XX_RB_PS_INPUT_CNTL = 0x0000880a +A6XX_RB_PS_INPUT_CNTL_SAMPLEMASK = 0x00000001 +A6XX_RB_PS_INPUT_CNTL_POSTDEPTHCOVERAGE = 0x00000002 +A6XX_RB_PS_INPUT_CNTL_FACENESS = 0x00000004 +A6XX_RB_PS_INPUT_CNTL_SAMPLEID = 0x00000008 +A6XX_RB_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 +A6XX_RB_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 4 +A6XX_RB_PS_INPUT_CNTL_CENTERRHW = 0x00000040 +A6XX_RB_PS_INPUT_CNTL_LINELENGTHEN = 0x00000080 +A6XX_RB_PS_INPUT_CNTL_FOVEATION = 0x00000100 +REG_A6XX_RB_PS_OUTPUT_CNTL = 0x0000880b +A6XX_RB_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000001 +A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_Z = 0x00000002 +A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_SAMPMASK = 0x00000004 +A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_STENCILREF = 0x00000008 +REG_A6XX_RB_PS_MRT_CNTL = 0x0000880c +A6XX_RB_PS_MRT_CNTL_MRT__MASK = 0x0000000f +A6XX_RB_PS_MRT_CNTL_MRT__SHIFT = 0 +REG_A6XX_RB_PS_OUTPUT_MASK = 0x0000880d +A6XX_RB_PS_OUTPUT_MASK_RT0__MASK = 0x0000000f +A6XX_RB_PS_OUTPUT_MASK_RT0__SHIFT = 0 +A6XX_RB_PS_OUTPUT_MASK_RT1__MASK = 0x000000f0 +A6XX_RB_PS_OUTPUT_MASK_RT1__SHIFT = 4 +A6XX_RB_PS_OUTPUT_MASK_RT2__MASK = 0x00000f00 +A6XX_RB_PS_OUTPUT_MASK_RT2__SHIFT = 8 +A6XX_RB_PS_OUTPUT_MASK_RT3__MASK = 0x0000f000 +A6XX_RB_PS_OUTPUT_MASK_RT3__SHIFT = 12 +A6XX_RB_PS_OUTPUT_MASK_RT4__MASK = 0x000f0000 +A6XX_RB_PS_OUTPUT_MASK_RT4__SHIFT = 16 +A6XX_RB_PS_OUTPUT_MASK_RT5__MASK = 0x00f00000 +A6XX_RB_PS_OUTPUT_MASK_RT5__SHIFT = 20 +A6XX_RB_PS_OUTPUT_MASK_RT6__MASK = 0x0f000000 +A6XX_RB_PS_OUTPUT_MASK_RT6__SHIFT = 24 +A6XX_RB_PS_OUTPUT_MASK_RT7__MASK = 0xf0000000 +A6XX_RB_PS_OUTPUT_MASK_RT7__SHIFT = 28 +REG_A6XX_RB_DITHER_CNTL = 0x0000880e +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 +A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 +REG_A6XX_RB_SRGB_CNTL = 0x0000880f +A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 +A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 +A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 +A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 +A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 +A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 +A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 +A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 +REG_A6XX_RB_PS_SAMPLEFREQ_CNTL = 0x00008810 +A6XX_RB_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE = 0x00000001 +REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 +REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 +REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 +REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 +REG_A6XX_RB_UNKNOWN_881A = 0x0000881a +REG_A6XX_RB_UNKNOWN_881B = 0x0000881b +REG_A6XX_RB_UNKNOWN_881C = 0x0000881c +REG_A6XX_RB_UNKNOWN_881D = 0x0000881d +REG_A6XX_RB_UNKNOWN_881E = 0x0000881e +REG_A6XX_RB_MRT = lambda i0: (0x00008820 + 0x8*i0 ) +A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 +A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 +A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 +A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 +A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 +A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 +A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 +A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f +A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 +A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 +A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 +A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 +A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 +A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 +A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 +A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 +A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 +A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 +A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 +A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff +A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 +A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 +A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 +A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 +A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 +A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 +A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 +A7XX_RB_MRT_BUF_INFO_MUTABLEEN = 0x00010000 +A6XX_RB_MRT_PITCH__MASK = 0xffffffff +A6XX_RB_MRT_PITCH__SHIFT = 0 +A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff +A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_BLEND_CONSTANT_RED_FP32 = 0x00008860 +A6XX_RB_BLEND_CONSTANT_RED_FP32__MASK = 0xffffffff +A6XX_RB_BLEND_CONSTANT_RED_FP32__SHIFT = 0 +REG_A6XX_RB_BLEND_CONSTANT_GREEN_FP32 = 0x00008861 +A6XX_RB_BLEND_CONSTANT_GREEN_FP32__MASK = 0xffffffff +A6XX_RB_BLEND_CONSTANT_GREEN_FP32__SHIFT = 0 +REG_A6XX_RB_BLEND_CONSTANT_BLUE_FP32 = 0x00008862 +A6XX_RB_BLEND_CONSTANT_BLUE_FP32__MASK = 0xffffffff +A6XX_RB_BLEND_CONSTANT_BLUE_FP32__SHIFT = 0 +REG_A6XX_RB_BLEND_CONSTANT_ALPHA_FP32 = 0x00008863 +A6XX_RB_BLEND_CONSTANT_ALPHA_FP32__MASK = 0xffffffff +A6XX_RB_BLEND_CONSTANT_ALPHA_FP32__SHIFT = 0 +REG_A6XX_RB_ALPHA_TEST_CNTL = 0x00008864 +A6XX_RB_ALPHA_TEST_CNTL_ALPHA_REF__MASK = 0x000000ff +A6XX_RB_ALPHA_TEST_CNTL_ALPHA_REF__SHIFT = 0 +A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST = 0x00000100 +A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST_FUNC__MASK = 0x00000e00 +A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST_FUNC__SHIFT = 9 +REG_A6XX_RB_BLEND_CNTL = 0x00008865 +A6XX_RB_BLEND_CNTL_BLEND_READS_DEST__MASK = 0x000000ff +A6XX_RB_BLEND_CNTL_BLEND_READS_DEST__SHIFT = 0 +A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 +A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 +A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 +A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 +A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 +A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 +REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 +A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 +A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 +REG_A6XX_RB_DEPTH_CNTL = 0x00008871 +A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 +A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 +A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c +A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 +A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 +A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 +A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 +REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 +A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 +REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 +A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 +A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 +REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 +A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 +A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 +A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 +A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 +A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 +A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 +A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 +REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 +A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff +A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 +A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff +A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 +REG_A6XX_RB_DEPTH_GMEM_BASE = 0x00008877 +REG_A6XX_RB_DEPTH_BOUND_MIN = 0x00008878 +A6XX_RB_DEPTH_BOUND_MIN__MASK = 0xffffffff +A6XX_RB_DEPTH_BOUND_MIN__SHIFT = 0 +REG_A6XX_RB_DEPTH_BOUND_MAX = 0x00008879 +A6XX_RB_DEPTH_BOUND_MAX__MASK = 0xffffffff +A6XX_RB_DEPTH_BOUND_MAX__SHIFT = 0 +REG_A6XX_RB_STENCIL_CNTL = 0x00008880 +A6XX_RB_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 +A6XX_RB_STENCIL_CNTL_STENCIL_ENABLE_BF = 0x00000002 +A6XX_RB_STENCIL_CNTL_STENCIL_READ = 0x00000004 +A6XX_RB_STENCIL_CNTL_FUNC__MASK = 0x00000700 +A6XX_RB_STENCIL_CNTL_FUNC__SHIFT = 8 +A6XX_RB_STENCIL_CNTL_FAIL__MASK = 0x00003800 +A6XX_RB_STENCIL_CNTL_FAIL__SHIFT = 11 +A6XX_RB_STENCIL_CNTL_ZPASS__MASK = 0x0001c000 +A6XX_RB_STENCIL_CNTL_ZPASS__SHIFT = 14 +A6XX_RB_STENCIL_CNTL_ZFAIL__MASK = 0x000e0000 +A6XX_RB_STENCIL_CNTL_ZFAIL__SHIFT = 17 +A6XX_RB_STENCIL_CNTL_FUNC_BF__MASK = 0x00700000 +A6XX_RB_STENCIL_CNTL_FUNC_BF__SHIFT = 20 +A6XX_RB_STENCIL_CNTL_FAIL_BF__MASK = 0x03800000 +A6XX_RB_STENCIL_CNTL_FAIL_BF__SHIFT = 23 +A6XX_RB_STENCIL_CNTL_ZPASS_BF__MASK = 0x1c000000 +A6XX_RB_STENCIL_CNTL_ZPASS_BF__SHIFT = 26 +A6XX_RB_STENCIL_CNTL_ZFAIL_BF__MASK = 0xe0000000 +A6XX_RB_STENCIL_CNTL_ZFAIL_BF__SHIFT = 29 +REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 +A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 +REG_A6XX_RB_STENCIL_BUFFER_INFO = 0x00008881 +A6XX_RB_STENCIL_BUFFER_INFO_SEPARATE_STENCIL = 0x00000001 +A6XX_RB_STENCIL_BUFFER_INFO_UNK1 = 0x00000002 +REG_A7XX_RB_STENCIL_BUFFER_INFO = 0x00008881 +A7XX_RB_STENCIL_BUFFER_INFO_SEPARATE_STENCIL = 0x00000001 +A7XX_RB_STENCIL_BUFFER_INFO_UNK1 = 0x00000002 +A7XX_RB_STENCIL_BUFFER_INFO_TILEMODE__MASK = 0x0000000c +A7XX_RB_STENCIL_BUFFER_INFO_TILEMODE__SHIFT = 2 +REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 +A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff +A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 +A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff +A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 +REG_A6XX_RB_STENCIL_GMEM_BASE = 0x00008886 +REG_A6XX_RB_STENCIL_REF_CNTL = 0x00008887 +A6XX_RB_STENCIL_REF_CNTL_REF__MASK = 0x000000ff +A6XX_RB_STENCIL_REF_CNTL_REF__SHIFT = 0 +A6XX_RB_STENCIL_REF_CNTL_BFREF__MASK = 0x0000ff00 +A6XX_RB_STENCIL_REF_CNTL_BFREF__SHIFT = 8 +REG_A6XX_RB_STENCIL_MASK = 0x00008888 +A6XX_RB_STENCIL_MASK_MASK__MASK = 0x000000ff +A6XX_RB_STENCIL_MASK_MASK__SHIFT = 0 +A6XX_RB_STENCIL_MASK_BFMASK__MASK = 0x0000ff00 +A6XX_RB_STENCIL_MASK_BFMASK__SHIFT = 8 +REG_A6XX_RB_STENCIL_WRITE_MASK = 0x00008889 +A6XX_RB_STENCIL_WRITE_MASK_WRMASK__MASK = 0x000000ff +A6XX_RB_STENCIL_WRITE_MASK_WRMASK__SHIFT = 0 +A6XX_RB_STENCIL_WRITE_MASK_BFWRMASK__MASK = 0x0000ff00 +A6XX_RB_STENCIL_WRITE_MASK_BFWRMASK__SHIFT = 8 +REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 +A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_RB_SAMPLE_COUNTER_CNTL = 0x00008891 +A6XX_RB_SAMPLE_COUNTER_CNTL_DISABLE = 0x00000001 +A6XX_RB_SAMPLE_COUNTER_CNTL_COPY = 0x00000002 +REG_A6XX_RB_LRZ_CNTL = 0x00008898 +A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 +REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 +REG_A6XX_RB_VIEWPORT_ZCLAMP_MIN = 0x000088c0 +A6XX_RB_VIEWPORT_ZCLAMP_MIN__MASK = 0xffffffff +A6XX_RB_VIEWPORT_ZCLAMP_MIN__SHIFT = 0 +REG_A6XX_RB_VIEWPORT_ZCLAMP_MAX = 0x000088c1 +A6XX_RB_VIEWPORT_ZCLAMP_MAX__MASK = 0xffffffff +A6XX_RB_VIEWPORT_ZCLAMP_MAX__SHIFT = 0 +REG_A6XX_RB_RESOLVE_CNTL_0 = 0x000088d0 +A6XX_RB_RESOLVE_CNTL_0_UNK0__MASK = 0x00001fff +A6XX_RB_RESOLVE_CNTL_0_UNK0__SHIFT = 0 +A6XX_RB_RESOLVE_CNTL_0_UNK16__MASK = 0x07ff0000 +A6XX_RB_RESOLVE_CNTL_0_UNK16__SHIFT = 16 +REG_A6XX_RB_RESOLVE_CNTL_1 = 0x000088d1 +A6XX_RB_RESOLVE_CNTL_1_X__MASK = 0x00003fff +A6XX_RB_RESOLVE_CNTL_1_X__SHIFT = 0 +A6XX_RB_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 +A6XX_RB_RESOLVE_CNTL_1_Y__SHIFT = 16 +REG_A6XX_RB_RESOLVE_CNTL_2 = 0x000088d2 +A6XX_RB_RESOLVE_CNTL_2_X__MASK = 0x00003fff +A6XX_RB_RESOLVE_CNTL_2_X__SHIFT = 0 +A6XX_RB_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 +A6XX_RB_RESOLVE_CNTL_2_Y__SHIFT = 16 +REG_A6XX_RB_RESOLVE_CNTL_3 = 0x000088d3 +A6XX_RB_RESOLVE_CNTL_3_BINW__MASK = 0x0000003f +A6XX_RB_RESOLVE_CNTL_3_BINW__SHIFT = 0 +A6XX_RB_RESOLVE_CNTL_3_BINH__MASK = 0x00007f00 +A6XX_RB_RESOLVE_CNTL_3_BINH__SHIFT = 8 +REG_A6XX_RB_RESOLVE_WINDOW_OFFSET = 0x000088d4 +A6XX_RB_RESOLVE_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_RB_RESOLVE_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_RB_RESOLVE_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_RB_RESOLVE_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_RB_RESOLVE_GMEM_BUFFER_INFO = 0x000088d5 +A6XX_RB_RESOLVE_GMEM_BUFFER_INFO_SAMPLES__MASK = 0x00000018 +A6XX_RB_RESOLVE_GMEM_BUFFER_INFO_SAMPLES__SHIFT = 3 +REG_A6XX_RB_RESOLVE_GMEM_BUFFER_BASE = 0x000088d6 +REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO = 0x000088d7 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE__MASK = 0x00000003 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE__SHIFT = 0 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_FLAGS = 0x00000004 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES__MASK = 0x00000018 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES__SHIFT = 3 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_SWAP__MASK = 0x00000060 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_SWAP__SHIFT = 5 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT__MASK = 0x00007f80 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT__SHIFT = 7 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_UNK15 = 0x00008000 +A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_MUTABLEEN = 0x00010000 +REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_BASE = 0x000088d8 +REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_PITCH = 0x000088da +A6XX_RB_RESOLVE_SYSTEM_BUFFER_PITCH__MASK = 0x0000ffff +A6XX_RB_RESOLVE_SYSTEM_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH = 0x000088db +A6XX_RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH__MASK = 0x1fffffff +A6XX_RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE = 0x000088dc +REG_A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH = 0x000088de +A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 +A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0 = 0x000088df +REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW1 = 0x000088e0 +REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW2 = 0x000088e1 +REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW3 = 0x000088e2 +REG_A6XX_RB_RESOLVE_OPERATION = 0x000088e3 +A6XX_RB_RESOLVE_OPERATION_TYPE__MASK = 0x00000003 +A6XX_RB_RESOLVE_OPERATION_TYPE__SHIFT = 0 +A6XX_RB_RESOLVE_OPERATION_SAMPLE_0 = 0x00000004 +A6XX_RB_RESOLVE_OPERATION_DEPTH = 0x00000008 +A6XX_RB_RESOLVE_OPERATION_CLEAR_MASK__MASK = 0x000000f0 +A6XX_RB_RESOLVE_OPERATION_CLEAR_MASK__SHIFT = 4 +A6XX_RB_RESOLVE_OPERATION_LAST__MASK = 0x00000300 +A6XX_RB_RESOLVE_OPERATION_LAST__SHIFT = 8 +A6XX_RB_RESOLVE_OPERATION_BUFFER_ID__MASK = 0x0000f000 +A6XX_RB_RESOLVE_OPERATION_BUFFER_ID__SHIFT = 12 +REG_A7XX_RB_CLEAR_TARGET = 0x000088e4 +A7XX_RB_CLEAR_TARGET_CLEAR_MODE__MASK = 0x00000001 +A7XX_RB_CLEAR_TARGET_CLEAR_MODE__SHIFT = 0 +REG_A7XX_RB_CCU_CACHE_CNTL = 0x000088e5 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000001 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_OFFSET_HI__SHIFT = 0 +A7XX_RB_CCU_CACHE_CNTL_COLOR_OFFSET_HI__MASK = 0x00000004 +A7XX_RB_CCU_CACHE_CNTL_COLOR_OFFSET_HI__SHIFT = 2 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 +A7XX_RB_CCU_CACHE_CNTL_DEPTH_OFFSET__SHIFT = 12 +A7XX_RB_CCU_CACHE_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 +A7XX_RB_CCU_CACHE_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 +A7XX_RB_CCU_CACHE_CNTL_COLOR_OFFSET__MASK = 0xff800000 +A7XX_RB_CCU_CACHE_CNTL_COLOR_OFFSET__SHIFT = 23 +REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 +REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 +REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 +A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_VRS_CONFIG = 0x000088f4 +A6XX_RB_VRS_CONFIG_UNK2 = 0x00000004 +A6XX_RB_VRS_CONFIG_PIPELINE_FSR_ENABLE = 0x00000010 +A6XX_RB_VRS_CONFIG_ATTACHMENT_FSR_ENABLE = 0x00000020 +A6XX_RB_VRS_CONFIG_PRIMITIVE_FSR_ENABLE = 0x00040000 +REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 +REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 +REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 +A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_COLOR_FLAG_BUFFER = lambda i0: (0x00008903 + 0x3*i0 ) +A6XX_RB_COLOR_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff +A6XX_RB_COLOR_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 +A6XX_RB_COLOR_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 +A6XX_RB_COLOR_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 +REG_A6XX_RB_SAMPLE_COUNTER_BASE = 0x00008927 +REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 +REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 +REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 +REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 +REG_A6XX_RB_A2D_BLT_CNTL = 0x00008c00 +A6XX_RB_A2D_BLT_CNTL_ROTATE__MASK = 0x00000007 +A6XX_RB_A2D_BLT_CNTL_ROTATE__SHIFT = 0 +A6XX_RB_A2D_BLT_CNTL_OVERWRITEEN = 0x00000008 +A6XX_RB_A2D_BLT_CNTL_UNK4__MASK = 0x00000070 +A6XX_RB_A2D_BLT_CNTL_UNK4__SHIFT = 4 +A6XX_RB_A2D_BLT_CNTL_SOLID_COLOR = 0x00000080 +A6XX_RB_A2D_BLT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 +A6XX_RB_A2D_BLT_CNTL_COLOR_FORMAT__SHIFT = 8 +A6XX_RB_A2D_BLT_CNTL_SCISSOR = 0x00010000 +A6XX_RB_A2D_BLT_CNTL_UNK17__MASK = 0x00060000 +A6XX_RB_A2D_BLT_CNTL_UNK17__SHIFT = 17 +A6XX_RB_A2D_BLT_CNTL_D24S8 = 0x00080000 +A6XX_RB_A2D_BLT_CNTL_MASK__MASK = 0x00f00000 +A6XX_RB_A2D_BLT_CNTL_MASK__SHIFT = 20 +A6XX_RB_A2D_BLT_CNTL_IFMT__MASK = 0x07000000 +A6XX_RB_A2D_BLT_CNTL_IFMT__SHIFT = 24 +A6XX_RB_A2D_BLT_CNTL_UNK27 = 0x08000000 +A6XX_RB_A2D_BLT_CNTL_UNK28 = 0x10000000 +A6XX_RB_A2D_BLT_CNTL_RASTER_MODE__MASK = 0x20000000 +A6XX_RB_A2D_BLT_CNTL_RASTER_MODE__SHIFT = 29 +A6XX_RB_A2D_BLT_CNTL_COPY = 0x40000000 +REG_A6XX_RB_A2D_PIXEL_CNTL = 0x00008c01 +REG_A6XX_RB_A2D_DEST_BUFFER_INFO = 0x00008c17 +A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_RB_A2D_DEST_BUFFER_INFO_TILE_MODE__MASK = 0x00000300 +A6XX_RB_A2D_DEST_BUFFER_INFO_TILE_MODE__SHIFT = 8 +A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_SWAP__MASK = 0x00000c00 +A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_SWAP__SHIFT = 10 +A6XX_RB_A2D_DEST_BUFFER_INFO_FLAGS = 0x00001000 +A6XX_RB_A2D_DEST_BUFFER_INFO_SRGB = 0x00002000 +A6XX_RB_A2D_DEST_BUFFER_INFO_SAMPLES__MASK = 0x0000c000 +A6XX_RB_A2D_DEST_BUFFER_INFO_SAMPLES__SHIFT = 14 +A6XX_RB_A2D_DEST_BUFFER_INFO_MUTABLEEN = 0x00020000 +REG_A6XX_RB_A2D_DEST_BUFFER_BASE = 0x00008c18 +REG_A6XX_RB_A2D_DEST_BUFFER_PITCH = 0x00008c1a +A6XX_RB_A2D_DEST_BUFFER_PITCH__MASK = 0x0000ffff +A6XX_RB_A2D_DEST_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_A2D_DEST_BUFFER_BASE_1 = 0x00008c1b +REG_A6XX_RB_A2D_DEST_BUFFER_PITCH_1 = 0x00008c1d +A6XX_RB_A2D_DEST_BUFFER_PITCH_1__MASK = 0x0000ffff +A6XX_RB_A2D_DEST_BUFFER_PITCH_1__SHIFT = 0 +REG_A6XX_RB_A2D_DEST_BUFFER_BASE_2 = 0x00008c1e +REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_BASE = 0x00008c20 +REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH = 0x00008c22 +A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH__MASK = 0x000000ff +A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH__SHIFT = 0 +REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_BASE_1 = 0x00008c23 +REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH_1 = 0x00008c25 +A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH_1__MASK = 0x000000ff +A6XX_RB_A2D_DEST_FLAG_BUFFER_PITCH_1__SHIFT = 0 +REG_A6XX_RB_A2D_CLEAR_COLOR_DW0 = 0x00008c2c +REG_A6XX_RB_A2D_CLEAR_COLOR_DW1 = 0x00008c2d +REG_A6XX_RB_A2D_CLEAR_COLOR_DW2 = 0x00008c2e +REG_A6XX_RB_A2D_CLEAR_COLOR_DW3 = 0x00008c2f +REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 +REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 +REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 +REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 +REG_A7XX_RB_CCU_DBG_ECO_CNTL = 0x00008e06 +REG_A6XX_RB_CCU_CNTL = 0x00008e07 +A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 +A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 +A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 +A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 +A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 +A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 +A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 +A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 +A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 +A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 +A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 +REG_A7XX_RB_CCU_CNTL = 0x00008e07 +A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 +A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE_MODE__MASK = 0x0000000c +A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE_MODE__SHIFT = 2 +A7XX_RB_CCU_CNTL_CONCURRENT_UNRESOLVE_MODE__MASK = 0x00000060 +A7XX_RB_CCU_CNTL_CONCURRENT_UNRESOLVE_MODE__SHIFT = 5 +REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 +A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 +A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 +A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 +A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 +A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 +A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 +A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 +A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 +A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 +A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 +REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 +REG_A6XX_RB_PERFCTR_RB_SEL = lambda i0: (0x00008e10 + 0x1*i0 ) +REG_A6XX_RB_PERFCTR_CCU_SEL = lambda i0: (0x00008e18 + 0x1*i0 ) +REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 +REG_A6XX_RB_PERFCTR_CMP_SEL = lambda i0: (0x00008e2c + 0x1*i0 ) +REG_A7XX_RB_PERFCTR_UFC_SEL = lambda i0: (0x00008e30 + 0x1*i0 ) +REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b +REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d +REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE = 0x00008e50 +REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR = 0x00008e51 +REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 +REG_A6XX_VPC_GS_PARAM = 0x00009100 +A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff +A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 +REG_A6XX_VPC_VS_CLIP_CULL_CNTL = 0x00009101 +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_GS_CLIP_CULL_CNTL = 0x00009102 +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_GS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_DS_CLIP_CULL_CNTL = 0x00009103 +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_MASK__SHIFT = 0 +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_DS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_VS_CLIP_CULL_CNTL_V2 = 0x00009311 +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_VS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_GS_CLIP_CULL_CNTL_V2 = 0x00009312 +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_GS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_DS_CLIP_CULL_CNTL_V2 = 0x00009313 +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_MASK__MASK = 0x000000ff +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_MASK__SHIFT = 0 +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 +A6XX_VPC_DS_CLIP_CULL_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 +REG_A6XX_VPC_VS_SIV_CNTL = 0x00009104 +A6XX_VPC_VS_SIV_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_VS_SIV_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_VS_SIV_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_SIV_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_GS_SIV_CNTL = 0x00009105 +A6XX_VPC_GS_SIV_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_GS_SIV_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_GS_SIV_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_SIV_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_GS_SIV_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_SIV_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_DS_SIV_CNTL = 0x00009106 +A6XX_VPC_DS_SIV_CNTL_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_DS_SIV_CNTL_LAYERLOC__SHIFT = 0 +A6XX_VPC_DS_SIV_CNTL_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_SIV_CNTL_VIEWLOC__SHIFT = 8 +A6XX_VPC_DS_SIV_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_SIV_CNTL_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_VS_SIV_CNTL_V2 = 0x00009314 +A6XX_VPC_VS_SIV_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_VS_SIV_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_VS_SIV_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_SIV_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_VS_SIV_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_SIV_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_GS_SIV_CNTL_V2 = 0x00009315 +A6XX_VPC_GS_SIV_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_GS_SIV_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_GS_SIV_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_SIV_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_GS_SIV_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_SIV_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_DS_SIV_CNTL_V2 = 0x00009316 +A6XX_VPC_DS_SIV_CNTL_V2_LAYERLOC__MASK = 0x000000ff +A6XX_VPC_DS_SIV_CNTL_V2_LAYERLOC__SHIFT = 0 +A6XX_VPC_DS_SIV_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_SIV_CNTL_V2_VIEWLOC__SHIFT = 8 +A6XX_VPC_DS_SIV_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_SIV_CNTL_V2_SHADINGRATELOC__SHIFT = 16 +REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 +A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 +A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 +REG_A6XX_VPC_RAST_CNTL = 0x00009108 +A6XX_VPC_RAST_CNTL_MODE__MASK = 0x00000003 +A6XX_VPC_RAST_CNTL_MODE__SHIFT = 0 +REG_A7XX_VPC_PC_CNTL = 0x00009109 +A7XX_VPC_PC_CNTL_PRIMITIVE_RESTART = 0x00000001 +A7XX_VPC_PC_CNTL_PROVOKING_VTX_LAST = 0x00000002 +A7XX_VPC_PC_CNTL_D3D_VERTEX_ORDERING = 0x00000004 +A7XX_VPC_PC_CNTL_UNK3 = 0x00000008 +REG_A7XX_VPC_GS_PARAM_0 = 0x0000910a +A7XX_VPC_GS_PARAM_0_GS_VERTICES_OUT__MASK = 0x000000ff +A7XX_VPC_GS_PARAM_0_GS_VERTICES_OUT__SHIFT = 0 +A7XX_VPC_GS_PARAM_0_GS_INVOCATIONS__MASK = 0x00007c00 +A7XX_VPC_GS_PARAM_0_GS_INVOCATIONS__SHIFT = 10 +A7XX_VPC_GS_PARAM_0_LINELENGTHEN = 0x00008000 +A7XX_VPC_GS_PARAM_0_GS_OUTPUT__MASK = 0x00030000 +A7XX_VPC_GS_PARAM_0_GS_OUTPUT__SHIFT = 16 +A7XX_VPC_GS_PARAM_0_UNK18 = 0x00040000 +REG_A7XX_VPC_STEREO_RENDERING_VIEWMASK = 0x0000910b +REG_A7XX_VPC_STEREO_RENDERING_CNTL = 0x0000910c +A7XX_VPC_STEREO_RENDERING_CNTL_ENABLE = 0x00000001 +A7XX_VPC_STEREO_RENDERING_CNTL_DISABLEMULTIPOS = 0x00000002 +A7XX_VPC_STEREO_RENDERING_CNTL_VIEWS__MASK = 0x0000007c +A7XX_VPC_STEREO_RENDERING_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_VPC_VARYING_INTERP_MODE = lambda i0: (0x00009200 + 0x1*i0 ) +REG_A6XX_VPC_VARYING_REPLACE_MODE_0 = lambda i0: (0x00009208 + 0x1*i0 ) +REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 +REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 +REG_A6XX_VPC_VARYING_LM_TRANSFER_CNTL_0 = lambda i0: (0x00009212 + 0x1*i0 ) +REG_A6XX_VPC_SO_MAPPING_WPTR = 0x00009216 +A6XX_VPC_SO_MAPPING_WPTR_ADDR__MASK = 0x000000ff +A6XX_VPC_SO_MAPPING_WPTR_ADDR__SHIFT = 0 +A6XX_VPC_SO_MAPPING_WPTR_RESET = 0x00010000 +REG_A6XX_VPC_SO_MAPPING_PORT = 0x00009217 +A6XX_VPC_SO_MAPPING_PORT_A_BUF__MASK = 0x00000003 +A6XX_VPC_SO_MAPPING_PORT_A_BUF__SHIFT = 0 +A6XX_VPC_SO_MAPPING_PORT_A_OFF__MASK = 0x000007fc +A6XX_VPC_SO_MAPPING_PORT_A_OFF__SHIFT = 2 +A6XX_VPC_SO_MAPPING_PORT_A_EN = 0x00000800 +A6XX_VPC_SO_MAPPING_PORT_B_BUF__MASK = 0x00003000 +A6XX_VPC_SO_MAPPING_PORT_B_BUF__SHIFT = 12 +A6XX_VPC_SO_MAPPING_PORT_B_OFF__MASK = 0x007fc000 +A6XX_VPC_SO_MAPPING_PORT_B_OFF__SHIFT = 14 +A6XX_VPC_SO_MAPPING_PORT_B_EN = 0x00800000 +REG_A6XX_VPC_SO_QUERY_BASE = 0x00009218 +REG_A6XX_VPC_SO = lambda i0: (0x0000921a + 0x7*i0 ) +REG_A6XX_VPC_REPLACE_MODE_CNTL = 0x00009236 +A6XX_VPC_REPLACE_MODE_CNTL_INVERT = 0x00000001 +REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 +REG_A6XX_VPC_VS_CNTL = 0x00009301 +A6XX_VPC_VS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_VS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_VS_CNTL_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_VS_CNTL_POSITIONLOC__SHIFT = 8 +A6XX_VPC_VS_CNTL_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_VS_CNTL_PSIZELOC__SHIFT = 16 +A6XX_VPC_VS_CNTL_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_VS_CNTL_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_GS_CNTL = 0x00009302 +A6XX_VPC_GS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_GS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_GS_CNTL_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_GS_CNTL_POSITIONLOC__SHIFT = 8 +A6XX_VPC_GS_CNTL_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_GS_CNTL_PSIZELOC__SHIFT = 16 +A6XX_VPC_GS_CNTL_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_GS_CNTL_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_DS_CNTL = 0x00009303 +A6XX_VPC_DS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_VPC_DS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_VPC_DS_CNTL_POSITIONLOC__MASK = 0x0000ff00 +A6XX_VPC_DS_CNTL_POSITIONLOC__SHIFT = 8 +A6XX_VPC_DS_CNTL_PSIZELOC__MASK = 0x00ff0000 +A6XX_VPC_DS_CNTL_PSIZELOC__SHIFT = 16 +A6XX_VPC_DS_CNTL_EXTRAPOS__MASK = 0x0f000000 +A6XX_VPC_DS_CNTL_EXTRAPOS__SHIFT = 24 +REG_A6XX_VPC_PS_CNTL = 0x00009304 +A6XX_VPC_PS_CNTL_NUMNONPOSVAR__MASK = 0x000000ff +A6XX_VPC_PS_CNTL_NUMNONPOSVAR__SHIFT = 0 +A6XX_VPC_PS_CNTL_PRIMIDLOC__MASK = 0x0000ff00 +A6XX_VPC_PS_CNTL_PRIMIDLOC__SHIFT = 8 +A6XX_VPC_PS_CNTL_VARYING = 0x00010000 +A6XX_VPC_PS_CNTL_VIEWIDLOC__MASK = 0xff000000 +A6XX_VPC_PS_CNTL_VIEWIDLOC__SHIFT = 24 +REG_A6XX_VPC_SO_CNTL = 0x00009305 +A6XX_VPC_SO_CNTL_BUF0_STREAM__MASK = 0x00000007 +A6XX_VPC_SO_CNTL_BUF0_STREAM__SHIFT = 0 +A6XX_VPC_SO_CNTL_BUF1_STREAM__MASK = 0x00000038 +A6XX_VPC_SO_CNTL_BUF1_STREAM__SHIFT = 3 +A6XX_VPC_SO_CNTL_BUF2_STREAM__MASK = 0x000001c0 +A6XX_VPC_SO_CNTL_BUF2_STREAM__SHIFT = 6 +A6XX_VPC_SO_CNTL_BUF3_STREAM__MASK = 0x00000e00 +A6XX_VPC_SO_CNTL_BUF3_STREAM__SHIFT = 9 +A6XX_VPC_SO_CNTL_STREAM_ENABLE__MASK = 0x00078000 +A6XX_VPC_SO_CNTL_STREAM_ENABLE__SHIFT = 15 +REG_A6XX_VPC_SO_OVERRIDE = 0x00009306 +A6XX_VPC_SO_OVERRIDE_DISABLE = 0x00000001 +REG_A6XX_VPC_PS_RAST_CNTL = 0x00009307 +A6XX_VPC_PS_RAST_CNTL_MODE__MASK = 0x00000003 +A6XX_VPC_PS_RAST_CNTL_MODE__SHIFT = 0 +REG_A7XX_VPC_ATTR_BUF_GMEM_SIZE = 0x00009308 +A7XX_VPC_ATTR_BUF_GMEM_SIZE_SIZE_GMEM__MASK = 0xffffffff +A7XX_VPC_ATTR_BUF_GMEM_SIZE_SIZE_GMEM__SHIFT = 0 +REG_A7XX_VPC_ATTR_BUF_GMEM_BASE = 0x00009309 +A7XX_VPC_ATTR_BUF_GMEM_BASE_BASE_GMEM__MASK = 0xffffffff +A7XX_VPC_ATTR_BUF_GMEM_BASE_BASE_GMEM__SHIFT = 0 +REG_A7XX_PC_ATTR_BUF_GMEM_SIZE = 0x00009b09 +A7XX_PC_ATTR_BUF_GMEM_SIZE_SIZE_GMEM__MASK = 0xffffffff +A7XX_PC_ATTR_BUF_GMEM_SIZE_SIZE_GMEM__SHIFT = 0 +REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 +REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 +REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 +REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 +REG_A6XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x00009604 + 0x1*i0 ) +REG_A7XX_VPC_PERFCTR_VPC_SEL = lambda i0: (0x0000960b + 0x1*i0 ) +REG_A6XX_PC_HS_PARAM_0 = 0x00009800 +REG_A6XX_PC_HS_PARAM_1 = 0x00009801 +A6XX_PC_HS_PARAM_1_SIZE__MASK = 0x000007ff +A6XX_PC_HS_PARAM_1_SIZE__SHIFT = 0 +A6XX_PC_HS_PARAM_1_UNK13 = 0x00002000 +REG_A6XX_PC_DS_PARAM = 0x00009802 +A6XX_PC_DS_PARAM_SPACING__MASK = 0x00000003 +A6XX_PC_DS_PARAM_SPACING__SHIFT = 0 +A6XX_PC_DS_PARAM_OUTPUT__MASK = 0x0000000c +A6XX_PC_DS_PARAM_OUTPUT__SHIFT = 2 +REG_A6XX_PC_RESTART_INDEX = 0x00009803 +REG_A6XX_PC_MODE_CNTL = 0x00009804 +REG_A6XX_PC_POWER_CNTL = 0x00009805 +REG_A6XX_PC_PS_CNTL = 0x00009806 +A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 +REG_A6XX_PC_DGEN_SO_CNTL = 0x00009808 +A6XX_PC_DGEN_SO_CNTL_STREAM_ENABLE__MASK = 0x00078000 +A6XX_PC_DGEN_SO_CNTL_STREAM_ENABLE__SHIFT = 15 +REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a +A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 +REG_A6XX_PC_DRAW_INITIATOR = 0x00009840 +A6XX_PC_DRAW_INITIATOR_STATE_ID__MASK = 0x000000ff +A6XX_PC_DRAW_INITIATOR_STATE_ID__SHIFT = 0 +REG_A6XX_PC_KERNEL_INITIATOR = 0x00009841 +A6XX_PC_KERNEL_INITIATOR_STATE_ID__MASK = 0x000000ff +A6XX_PC_KERNEL_INITIATOR_STATE_ID__SHIFT = 0 +REG_A6XX_PC_EVENT_INITIATOR = 0x00009842 +A6XX_PC_EVENT_INITIATOR_STATE_ID__MASK = 0x00ff0000 +A6XX_PC_EVENT_INITIATOR_STATE_ID__SHIFT = 16 +A6XX_PC_EVENT_INITIATOR_EVENT__MASK = 0x0000007f +A6XX_PC_EVENT_INITIATOR_EVENT__SHIFT = 0 +REG_A6XX_PC_MARKER = 0x00009880 +REG_A6XX_PC_DGEN_RAST_CNTL = 0x00009981 +A6XX_PC_DGEN_RAST_CNTL_MODE__MASK = 0x00000003 +A6XX_PC_DGEN_RAST_CNTL_MODE__SHIFT = 0 +REG_A7XX_PC_DGEN_RAST_CNTL = 0x00009809 +A7XX_PC_DGEN_RAST_CNTL_MODE__MASK = 0x00000003 +A7XX_PC_DGEN_RAST_CNTL_MODE__SHIFT = 0 +REG_A6XX_VPC_RAST_STREAM_CNTL = 0x00009980 +A6XX_VPC_RAST_STREAM_CNTL_STREAM__MASK = 0x00000003 +A6XX_VPC_RAST_STREAM_CNTL_STREAM__SHIFT = 0 +A6XX_VPC_RAST_STREAM_CNTL_DISCARD = 0x00000004 +REG_A7XX_VPC_RAST_STREAM_CNTL = 0x00009107 +A7XX_VPC_RAST_STREAM_CNTL_STREAM__MASK = 0x00000003 +A7XX_VPC_RAST_STREAM_CNTL_STREAM__SHIFT = 0 +A7XX_VPC_RAST_STREAM_CNTL_DISCARD = 0x00000004 +REG_A7XX_VPC_RAST_STREAM_CNTL_V2 = 0x00009317 +A7XX_VPC_RAST_STREAM_CNTL_V2_STREAM__MASK = 0x00000003 +A7XX_VPC_RAST_STREAM_CNTL_V2_STREAM__SHIFT = 0 +A7XX_VPC_RAST_STREAM_CNTL_V2_DISCARD = 0x00000004 +REG_A7XX_PC_HS_BUFFER_SIZE = 0x00009885 +REG_A7XX_PC_TF_BUFFER_SIZE = 0x00009886 +REG_A6XX_PC_CNTL = 0x00009b00 +A6XX_PC_CNTL_PRIMITIVE_RESTART = 0x00000001 +A6XX_PC_CNTL_PROVOKING_VTX_LAST = 0x00000002 +A6XX_PC_CNTL_D3D_VERTEX_ORDERING = 0x00000004 +A6XX_PC_CNTL_UNK3 = 0x00000008 +REG_A6XX_PC_VS_CNTL = 0x00009b01 +A6XX_PC_VS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_VS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_VS_CNTL_PSIZE = 0x00000100 +A6XX_PC_VS_CNTL_LAYER = 0x00000200 +A6XX_PC_VS_CNTL_VIEW = 0x00000400 +A6XX_PC_VS_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_VS_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_VS_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_VS_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_GS_CNTL = 0x00009b02 +A6XX_PC_GS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_GS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_GS_CNTL_PSIZE = 0x00000100 +A6XX_PC_GS_CNTL_LAYER = 0x00000200 +A6XX_PC_GS_CNTL_VIEW = 0x00000400 +A6XX_PC_GS_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_GS_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_GS_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_GS_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_HS_CNTL = 0x00009b03 +A6XX_PC_HS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_HS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_HS_CNTL_PSIZE = 0x00000100 +A6XX_PC_HS_CNTL_LAYER = 0x00000200 +A6XX_PC_HS_CNTL_VIEW = 0x00000400 +A6XX_PC_HS_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_HS_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_HS_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_HS_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_DS_CNTL = 0x00009b04 +A6XX_PC_DS_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff +A6XX_PC_DS_CNTL_STRIDE_IN_VPC__SHIFT = 0 +A6XX_PC_DS_CNTL_PSIZE = 0x00000100 +A6XX_PC_DS_CNTL_LAYER = 0x00000200 +A6XX_PC_DS_CNTL_VIEW = 0x00000400 +A6XX_PC_DS_CNTL_PRIMITIVE_ID = 0x00000800 +A6XX_PC_DS_CNTL_CLIP_MASK__MASK = 0x00ff0000 +A6XX_PC_DS_CNTL_CLIP_MASK__SHIFT = 16 +A6XX_PC_DS_CNTL_SHADINGRATE = 0x01000000 +REG_A6XX_PC_GS_PARAM_0 = 0x00009b05 +A6XX_PC_GS_PARAM_0_GS_VERTICES_OUT__MASK = 0x000000ff +A6XX_PC_GS_PARAM_0_GS_VERTICES_OUT__SHIFT = 0 +A6XX_PC_GS_PARAM_0_GS_INVOCATIONS__MASK = 0x00007c00 +A6XX_PC_GS_PARAM_0_GS_INVOCATIONS__SHIFT = 10 +A6XX_PC_GS_PARAM_0_LINELENGTHEN = 0x00008000 +A6XX_PC_GS_PARAM_0_GS_OUTPUT__MASK = 0x00030000 +A6XX_PC_GS_PARAM_0_GS_OUTPUT__SHIFT = 16 +A6XX_PC_GS_PARAM_0_UNK18 = 0x00040000 +REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 +A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff +A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 +REG_A6XX_PC_STEREO_RENDERING_CNTL = 0x00009b07 +A6XX_PC_STEREO_RENDERING_CNTL_ENABLE = 0x00000001 +A6XX_PC_STEREO_RENDERING_CNTL_DISABLEMULTIPOS = 0x00000002 +A6XX_PC_STEREO_RENDERING_CNTL_VIEWS__MASK = 0x0000007c +A6XX_PC_STEREO_RENDERING_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_PC_STEREO_RENDERING_VIEWMASK = 0x00009b08 +REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 +A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 +A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 +A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 +REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 +REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 +REG_A6XX_PC_DMA_BASE = 0x00009e04 +REG_A6XX_PC_DMA_OFFSET = 0x00009e06 +REG_A6XX_PC_DMA_SIZE = 0x00009e07 +REG_A6XX_PC_TESS_BASE = 0x00009e08 +REG_A7XX_PC_TESS_BASE = 0x00009810 +REG_A6XX_PC_DRAWCALL_CNTL = 0x00009e0b +A6XX_PC_DRAWCALL_CNTL_PRIM_TYPE__MASK = 0x0000003f +A6XX_PC_DRAWCALL_CNTL_PRIM_TYPE__SHIFT = 0 +A6XX_PC_DRAWCALL_CNTL_SOURCE_SELECT__MASK = 0x000000c0 +A6XX_PC_DRAWCALL_CNTL_SOURCE_SELECT__SHIFT = 6 +A6XX_PC_DRAWCALL_CNTL_VIS_CULL__MASK = 0x00000300 +A6XX_PC_DRAWCALL_CNTL_VIS_CULL__SHIFT = 8 +A6XX_PC_DRAWCALL_CNTL_INDEX_SIZE__MASK = 0x00000c00 +A6XX_PC_DRAWCALL_CNTL_INDEX_SIZE__SHIFT = 10 +A6XX_PC_DRAWCALL_CNTL_PATCH_TYPE__MASK = 0x00003000 +A6XX_PC_DRAWCALL_CNTL_PATCH_TYPE__SHIFT = 12 +A6XX_PC_DRAWCALL_CNTL_GS_ENABLE = 0x00010000 +A6XX_PC_DRAWCALL_CNTL_TESS_ENABLE = 0x00020000 +REG_A6XX_PC_DRAWCALL_INSTANCE_NUM = 0x00009e0c +REG_A6XX_PC_DRAWCALL_SIZE = 0x00009e0d +REG_A6XX_PC_VIS_STREAM_CNTL = 0x00009e11 +A6XX_PC_VIS_STREAM_CNTL_UNK0__MASK = 0x0000ffff +A6XX_PC_VIS_STREAM_CNTL_UNK0__SHIFT = 0 +A6XX_PC_VIS_STREAM_CNTL_VSC_SIZE__MASK = 0x003f0000 +A6XX_PC_VIS_STREAM_CNTL_VSC_SIZE__SHIFT = 16 +A6XX_PC_VIS_STREAM_CNTL_VSC_N__MASK = 0x07c00000 +A6XX_PC_VIS_STREAM_CNTL_VSC_N__SHIFT = 22 +REG_A6XX_PC_PVIS_STREAM_BIN_BASE = 0x00009e12 +REG_A6XX_PC_DVIS_STREAM_BIN_BASE = 0x00009e14 +REG_A6XX_PC_DRAWCALL_CNTL_OVERRIDE = 0x00009e1c +A6XX_PC_DRAWCALL_CNTL_OVERRIDE_OVERRIDE = 0x00000001 +REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 +REG_A6XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e34 + 0x1*i0 ) +REG_A7XX_PC_PERFCTR_PC_SEL = lambda i0: (0x00009e42 + 0x1*i0 ) +REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 +REG_A6XX_VFD_CNTL_0 = 0x0000a000 +A6XX_VFD_CNTL_0_FETCH_CNT__MASK = 0x0000003f +A6XX_VFD_CNTL_0_FETCH_CNT__SHIFT = 0 +A6XX_VFD_CNTL_0_DECODE_CNT__MASK = 0x00003f00 +A6XX_VFD_CNTL_0_DECODE_CNT__SHIFT = 8 +REG_A6XX_VFD_CNTL_1 = 0x0000a001 +A6XX_VFD_CNTL_1_REGID4VTX__MASK = 0x000000ff +A6XX_VFD_CNTL_1_REGID4VTX__SHIFT = 0 +A6XX_VFD_CNTL_1_REGID4INST__MASK = 0x0000ff00 +A6XX_VFD_CNTL_1_REGID4INST__SHIFT = 8 +A6XX_VFD_CNTL_1_REGID4PRIMID__MASK = 0x00ff0000 +A6XX_VFD_CNTL_1_REGID4PRIMID__SHIFT = 16 +A6XX_VFD_CNTL_1_REGID4VIEWID__MASK = 0xff000000 +A6XX_VFD_CNTL_1_REGID4VIEWID__SHIFT = 24 +REG_A6XX_VFD_CNTL_2 = 0x0000a002 +A6XX_VFD_CNTL_2_REGID_HSRELPATCHID__MASK = 0x000000ff +A6XX_VFD_CNTL_2_REGID_HSRELPATCHID__SHIFT = 0 +A6XX_VFD_CNTL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 +A6XX_VFD_CNTL_2_REGID_INVOCATIONID__SHIFT = 8 +REG_A6XX_VFD_CNTL_3 = 0x0000a003 +A6XX_VFD_CNTL_3_REGID_DSPRIMID__MASK = 0x000000ff +A6XX_VFD_CNTL_3_REGID_DSPRIMID__SHIFT = 0 +A6XX_VFD_CNTL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 +A6XX_VFD_CNTL_3_REGID_DSRELPATCHID__SHIFT = 8 +A6XX_VFD_CNTL_3_REGID_TESSX__MASK = 0x00ff0000 +A6XX_VFD_CNTL_3_REGID_TESSX__SHIFT = 16 +A6XX_VFD_CNTL_3_REGID_TESSY__MASK = 0xff000000 +A6XX_VFD_CNTL_3_REGID_TESSY__SHIFT = 24 +REG_A6XX_VFD_CNTL_4 = 0x0000a004 +A6XX_VFD_CNTL_4_UNK0__MASK = 0x000000ff +A6XX_VFD_CNTL_4_UNK0__SHIFT = 0 +REG_A6XX_VFD_CNTL_5 = 0x0000a005 +A6XX_VFD_CNTL_5_REGID_GSHEADER__MASK = 0x000000ff +A6XX_VFD_CNTL_5_REGID_GSHEADER__SHIFT = 0 +A6XX_VFD_CNTL_5_UNK8__MASK = 0x0000ff00 +A6XX_VFD_CNTL_5_UNK8__SHIFT = 8 +REG_A6XX_VFD_CNTL_6 = 0x0000a006 +A6XX_VFD_CNTL_6_PRIMID4PSEN = 0x00000001 +REG_A6XX_VFD_RENDER_MODE = 0x0000a007 +A6XX_VFD_RENDER_MODE_RENDER_MODE__MASK = 0x00000007 +A6XX_VFD_RENDER_MODE_RENDER_MODE__SHIFT = 0 +REG_A6XX_VFD_STEREO_RENDERING_CNTL = 0x0000a008 +A6XX_VFD_STEREO_RENDERING_CNTL_ENABLE = 0x00000001 +A6XX_VFD_STEREO_RENDERING_CNTL_DISABLEMULTIPOS = 0x00000002 +A6XX_VFD_STEREO_RENDERING_CNTL_VIEWS__MASK = 0x0000007c +A6XX_VFD_STEREO_RENDERING_CNTL_VIEWS__SHIFT = 2 +REG_A6XX_VFD_MODE_CNTL = 0x0000a009 +A6XX_VFD_MODE_CNTL_VERTEX = 0x00000001 +A6XX_VFD_MODE_CNTL_INSTANCE = 0x00000002 +REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e +REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f +REG_A6XX_VFD_VERTEX_BUFFER = lambda i0: (0x0000a010 + 0x4*i0 ) +REG_A6XX_VFD_FETCH_INSTR = lambda i0: (0x0000a090 + 0x2*i0 ) +A6XX_VFD_FETCH_INSTR_INSTR_IDX__MASK = 0x0000001f +A6XX_VFD_FETCH_INSTR_INSTR_IDX__SHIFT = 0 +A6XX_VFD_FETCH_INSTR_INSTR_OFFSET__MASK = 0x0001ffe0 +A6XX_VFD_FETCH_INSTR_INSTR_OFFSET__SHIFT = 5 +A6XX_VFD_FETCH_INSTR_INSTR_INSTANCED = 0x00020000 +A6XX_VFD_FETCH_INSTR_INSTR_FORMAT__MASK = 0x0ff00000 +A6XX_VFD_FETCH_INSTR_INSTR_FORMAT__SHIFT = 20 +A6XX_VFD_FETCH_INSTR_INSTR_SWAP__MASK = 0x30000000 +A6XX_VFD_FETCH_INSTR_INSTR_SWAP__SHIFT = 28 +A6XX_VFD_FETCH_INSTR_INSTR_UNK30 = 0x40000000 +A6XX_VFD_FETCH_INSTR_INSTR_FLOAT = 0x80000000 +REG_A6XX_VFD_DEST_CNTL = lambda i0: (0x0000a0d0 + 0x1*i0 ) +A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f +A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 +A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 +A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 +REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 +REG_A7XX_VFD_DBG_ECO_CNTL = 0x0000a600 +REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 +REG_A6XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) +REG_A7XX_VFD_PERFCTR_VFD_SEL = lambda i0: (0x0000a610 + 0x1*i0 ) +REG_A6XX_SP_VS_CNTL_0 = 0x0000a800 +A6XX_SP_VS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_VS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_VS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_VS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_VS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_VS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_VS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_VS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_VS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_VS_CNTL_0_MERGEDREGS = 0x00100000 +A6XX_SP_VS_CNTL_0_EARLYPREAMBLE = 0x00200000 +REG_A6XX_SP_VS_BOOLEAN_CF_MASK = 0x0000a801 +REG_A6XX_SP_VS_OUTPUT_CNTL = 0x0000a802 +A6XX_SP_VS_OUTPUT_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_VS_OUTPUT_CNTL_OUT__SHIFT = 0 +A6XX_SP_VS_OUTPUT_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_VS_OUTPUT_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_VS_OUTPUT = lambda i0: (0x0000a803 + 0x1*i0 ) +A6XX_SP_VS_OUTPUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_VS_OUTPUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_VS_OUTPUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_VS_OUTPUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_VS_OUTPUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_VS_OUTPUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_VS_OUTPUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_VS_OUTPUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_VS_VPC_DEST = lambda i0: (0x0000a813 + 0x1*i0 ) +A6XX_SP_VS_VPC_DEST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_VS_VPC_DEST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_VS_VPC_DEST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_VS_PROGRAM_COUNTER_OFFSET = 0x0000a81b +REG_A6XX_SP_VS_BASE = 0x0000a81c +REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e +A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_VS_PVT_MEM_BASE = 0x0000a81f +REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 +A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_VS_TSIZE = 0x0000a822 +REG_A6XX_SP_VS_CONFIG = 0x0000a823 +A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_VS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_VS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_VS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_VS_INSTR_SIZE = 0x0000a824 +REG_A6XX_SP_VS_PVT_MEM_STACK_OFFSET = 0x0000a825 +A6XX_SP_VS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_VS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_VS_VGS_CNTL = 0x0000a82d +REG_A6XX_SP_HS_CNTL_0 = 0x0000a830 +A6XX_SP_HS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_HS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_HS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_HS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_HS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_HS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_HS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_HS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_HS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_HS_CNTL_0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_HS_CNTL_1 = 0x0000a831 +REG_A6XX_SP_HS_BOOLEAN_CF_MASK = 0x0000a832 +REG_A6XX_SP_HS_PROGRAM_COUNTER_OFFSET = 0x0000a833 +REG_A6XX_SP_HS_BASE = 0x0000a834 +REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 +A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_HS_PVT_MEM_BASE = 0x0000a837 +REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 +A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_HS_TSIZE = 0x0000a83a +REG_A6XX_SP_HS_CONFIG = 0x0000a83b +A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_HS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_HS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_HS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_HS_INSTR_SIZE = 0x0000a83c +REG_A6XX_SP_HS_PVT_MEM_STACK_OFFSET = 0x0000a83d +A6XX_SP_HS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_HS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_HS_VGS_CNTL = 0x0000a82f +REG_A6XX_SP_DS_CNTL_0 = 0x0000a840 +A6XX_SP_DS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_DS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_DS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_DS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_DS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_DS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_DS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_DS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_DS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_DS_CNTL_0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_DS_BOOLEAN_CF_MASK = 0x0000a841 +REG_A6XX_SP_DS_OUTPUT_CNTL = 0x0000a842 +A6XX_SP_DS_OUTPUT_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_DS_OUTPUT_CNTL_OUT__SHIFT = 0 +A6XX_SP_DS_OUTPUT_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_DS_OUTPUT_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_DS_OUTPUT = lambda i0: (0x0000a843 + 0x1*i0 ) +A6XX_SP_DS_OUTPUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_DS_OUTPUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_DS_OUTPUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_DS_OUTPUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_DS_OUTPUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_DS_OUTPUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_DS_OUTPUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_DS_OUTPUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_DS_VPC_DEST = lambda i0: (0x0000a853 + 0x1*i0 ) +A6XX_SP_DS_VPC_DEST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_DS_VPC_DEST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_DS_VPC_DEST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_DS_PROGRAM_COUNTER_OFFSET = 0x0000a85b +REG_A6XX_SP_DS_BASE = 0x0000a85c +REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e +A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_DS_PVT_MEM_BASE = 0x0000a85f +REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 +A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_DS_TSIZE = 0x0000a862 +REG_A6XX_SP_DS_CONFIG = 0x0000a863 +A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_DS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_DS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_DS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_DS_INSTR_SIZE = 0x0000a864 +REG_A6XX_SP_DS_PVT_MEM_STACK_OFFSET = 0x0000a865 +A6XX_SP_DS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_DS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_DS_VGS_CNTL = 0x0000a868 +REG_A6XX_SP_GS_CNTL_0 = 0x0000a870 +A6XX_SP_GS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_GS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_GS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_GS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_GS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_GS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_GS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_GS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_GS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_GS_CNTL_0_EARLYPREAMBLE = 0x00100000 +REG_A6XX_SP_GS_CNTL_1 = 0x0000a871 +REG_A6XX_SP_GS_BOOLEAN_CF_MASK = 0x0000a872 +REG_A6XX_SP_GS_OUTPUT_CNTL = 0x0000a873 +A6XX_SP_GS_OUTPUT_CNTL_OUT__MASK = 0x0000003f +A6XX_SP_GS_OUTPUT_CNTL_OUT__SHIFT = 0 +A6XX_SP_GS_OUTPUT_CNTL_FLAGS_REGID__MASK = 0x00003fc0 +A6XX_SP_GS_OUTPUT_CNTL_FLAGS_REGID__SHIFT = 6 +REG_A6XX_SP_GS_OUTPUT = lambda i0: (0x0000a874 + 0x1*i0 ) +A6XX_SP_GS_OUTPUT_REG_A_REGID__MASK = 0x000000ff +A6XX_SP_GS_OUTPUT_REG_A_REGID__SHIFT = 0 +A6XX_SP_GS_OUTPUT_REG_A_COMPMASK__MASK = 0x00000f00 +A6XX_SP_GS_OUTPUT_REG_A_COMPMASK__SHIFT = 8 +A6XX_SP_GS_OUTPUT_REG_B_REGID__MASK = 0x00ff0000 +A6XX_SP_GS_OUTPUT_REG_B_REGID__SHIFT = 16 +A6XX_SP_GS_OUTPUT_REG_B_COMPMASK__MASK = 0x0f000000 +A6XX_SP_GS_OUTPUT_REG_B_COMPMASK__SHIFT = 24 +REG_A6XX_SP_GS_VPC_DEST = lambda i0: (0x0000a884 + 0x1*i0 ) +A6XX_SP_GS_VPC_DEST_REG_OUTLOC0__MASK = 0x000000ff +A6XX_SP_GS_VPC_DEST_REG_OUTLOC0__SHIFT = 0 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC1__MASK = 0x0000ff00 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC1__SHIFT = 8 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC2__MASK = 0x00ff0000 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC2__SHIFT = 16 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC3__MASK = 0xff000000 +A6XX_SP_GS_VPC_DEST_REG_OUTLOC3__SHIFT = 24 +REG_A6XX_SP_GS_PROGRAM_COUNTER_OFFSET = 0x0000a88c +REG_A6XX_SP_GS_BASE = 0x0000a88d +REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f +A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_GS_PVT_MEM_BASE = 0x0000a890 +REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 +A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_GS_TSIZE = 0x0000a893 +REG_A6XX_SP_GS_CONFIG = 0x0000a894 +A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_GS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_GS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_GS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_GS_INSTR_SIZE = 0x0000a895 +REG_A6XX_SP_GS_PVT_MEM_STACK_OFFSET = 0x0000a896 +A6XX_SP_GS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_GS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_GS_VGS_CNTL = 0x0000a899 +REG_A6XX_SP_VS_SAMPLER_BASE = 0x0000a8a0 +REG_A6XX_SP_HS_SAMPLER_BASE = 0x0000a8a2 +REG_A6XX_SP_DS_SAMPLER_BASE = 0x0000a8a4 +REG_A6XX_SP_GS_SAMPLER_BASE = 0x0000a8a6 +REG_A6XX_SP_VS_TEXMEMOBJ_BASE = 0x0000a8a8 +REG_A6XX_SP_HS_TEXMEMOBJ_BASE = 0x0000a8aa +REG_A6XX_SP_DS_TEXMEMOBJ_BASE = 0x0000a8ac +REG_A6XX_SP_GS_TEXMEMOBJ_BASE = 0x0000a8ae +REG_A6XX_SP_PS_CNTL_0 = 0x0000a980 +A6XX_SP_PS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_PS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_PS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_PS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_PS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_PS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_PS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_PS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_PS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_PS_CNTL_0_THREADSIZE__MASK = 0x00100000 +A6XX_SP_PS_CNTL_0_THREADSIZE__SHIFT = 20 +A6XX_SP_PS_CNTL_0_UNK21 = 0x00200000 +A6XX_SP_PS_CNTL_0_VARYING = 0x00400000 +A6XX_SP_PS_CNTL_0_LODPIXMASK = 0x00800000 +A6XX_SP_PS_CNTL_0_INOUTREGOVERLAP = 0x01000000 +A6XX_SP_PS_CNTL_0_UNK25 = 0x02000000 +A6XX_SP_PS_CNTL_0_PIXLODENABLE = 0x04000000 +A6XX_SP_PS_CNTL_0_UNK27 = 0x08000000 +A6XX_SP_PS_CNTL_0_EARLYPREAMBLE = 0x10000000 +A6XX_SP_PS_CNTL_0_MERGEDREGS = 0x80000000 +REG_A6XX_SP_PS_BOOLEAN_CF_MASK = 0x0000a981 +REG_A6XX_SP_PS_PROGRAM_COUNTER_OFFSET = 0x0000a982 +REG_A6XX_SP_PS_BASE = 0x0000a983 +REG_A6XX_SP_PS_PVT_MEM_PARAM = 0x0000a985 +A6XX_SP_PS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_PS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_PS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_PS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_PS_PVT_MEM_BASE = 0x0000a986 +REG_A6XX_SP_PS_PVT_MEM_SIZE = 0x0000a988 +A6XX_SP_PS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_PS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_PS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_BLEND_CNTL = 0x0000a989 +A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff +A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 +A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 +A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 +A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 +REG_A6XX_SP_SRGB_CNTL = 0x0000a98a +A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 +A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 +A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 +A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 +A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 +A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 +A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 +A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 +REG_A6XX_SP_PS_OUTPUT_MASK = 0x0000a98b +A6XX_SP_PS_OUTPUT_MASK_RT0__MASK = 0x0000000f +A6XX_SP_PS_OUTPUT_MASK_RT0__SHIFT = 0 +A6XX_SP_PS_OUTPUT_MASK_RT1__MASK = 0x000000f0 +A6XX_SP_PS_OUTPUT_MASK_RT1__SHIFT = 4 +A6XX_SP_PS_OUTPUT_MASK_RT2__MASK = 0x00000f00 +A6XX_SP_PS_OUTPUT_MASK_RT2__SHIFT = 8 +A6XX_SP_PS_OUTPUT_MASK_RT3__MASK = 0x0000f000 +A6XX_SP_PS_OUTPUT_MASK_RT3__SHIFT = 12 +A6XX_SP_PS_OUTPUT_MASK_RT4__MASK = 0x000f0000 +A6XX_SP_PS_OUTPUT_MASK_RT4__SHIFT = 16 +A6XX_SP_PS_OUTPUT_MASK_RT5__MASK = 0x00f00000 +A6XX_SP_PS_OUTPUT_MASK_RT5__SHIFT = 20 +A6XX_SP_PS_OUTPUT_MASK_RT6__MASK = 0x0f000000 +A6XX_SP_PS_OUTPUT_MASK_RT6__SHIFT = 24 +A6XX_SP_PS_OUTPUT_MASK_RT7__MASK = 0xf0000000 +A6XX_SP_PS_OUTPUT_MASK_RT7__SHIFT = 28 +REG_A6XX_SP_PS_OUTPUT_CNTL = 0x0000a98c +A6XX_SP_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000001 +A6XX_SP_PS_OUTPUT_CNTL_DEPTH_REGID__MASK = 0x0000ff00 +A6XX_SP_PS_OUTPUT_CNTL_DEPTH_REGID__SHIFT = 8 +A6XX_SP_PS_OUTPUT_CNTL_SAMPMASK_REGID__MASK = 0x00ff0000 +A6XX_SP_PS_OUTPUT_CNTL_SAMPMASK_REGID__SHIFT = 16 +A6XX_SP_PS_OUTPUT_CNTL_STENCILREF_REGID__MASK = 0xff000000 +A6XX_SP_PS_OUTPUT_CNTL_STENCILREF_REGID__SHIFT = 24 +REG_A6XX_SP_PS_MRT_CNTL = 0x0000a98d +A6XX_SP_PS_MRT_CNTL_MRT__MASK = 0x0000000f +A6XX_SP_PS_MRT_CNTL_MRT__SHIFT = 0 +REG_A6XX_SP_PS_OUTPUT = lambda i0: (0x0000a98e + 0x1*i0 ) +A6XX_SP_PS_OUTPUT_REG_REGID__MASK = 0x000000ff +A6XX_SP_PS_OUTPUT_REG_REGID__SHIFT = 0 +A6XX_SP_PS_OUTPUT_REG_HALF_PRECISION = 0x00000100 +REG_A6XX_SP_PS_MRT = lambda i0: (0x0000a996 + 0x1*i0 ) +A6XX_SP_PS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff +A6XX_SP_PS_MRT_REG_COLOR_FORMAT__SHIFT = 0 +A6XX_SP_PS_MRT_REG_COLOR_SINT = 0x00000100 +A6XX_SP_PS_MRT_REG_COLOR_UINT = 0x00000200 +A6XX_SP_PS_MRT_REG_UNK10 = 0x00000400 +REG_A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL = 0x0000a99e +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_COUNT__MASK = 0x00000007 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_COUNT__SHIFT = 0 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_IJ_WRITE_DISABLE = 0x00000008 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_ENDOFQUAD = 0x00000010 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID__MASK = 0x00007fc0 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID__SHIFT = 6 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID4COORD__SHIFT = 16 +REG_A6XX_SP_PS_INITIAL_TEX_LOAD = lambda i0: (0x0000a99f + 0x1*i0 ) +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_SRC__MASK = 0x0000007f +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_SRC__SHIFT = 0 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_SAMP_ID__MASK = 0x00000780 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_SAMP_ID__SHIFT = 7 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_TEX_ID__MASK = 0x0000f800 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_TEX_ID__SHIFT = 11 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_DST__MASK = 0x003f0000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_DST__SHIFT = 16 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_WRMASK__MASK = 0x03c00000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_WRMASK__SHIFT = 22 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_HALF = 0x04000000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_UNK27 = 0x08000000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_BINDLESS = 0x10000000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_CMD__MASK = 0xe0000000 +A6XX_SP_PS_INITIAL_TEX_LOAD_CMD_CMD__SHIFT = 29 +REG_A7XX_SP_PS_INITIAL_TEX_LOAD = lambda i0: (0x0000a99f + 0x1*i0 ) +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_SRC__MASK = 0x0000007f +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_SRC__SHIFT = 0 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_SAMP_ID__MASK = 0x00000380 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_SAMP_ID__SHIFT = 7 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_TEX_ID__MASK = 0x00001c00 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_TEX_ID__SHIFT = 10 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_DST__MASK = 0x0007e000 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_DST__SHIFT = 13 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_WRMASK__MASK = 0x00780000 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_WRMASK__SHIFT = 19 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_HALF = 0x00800000 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_BINDLESS = 0x02000000 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_CMD__MASK = 0x3c000000 +A7XX_SP_PS_INITIAL_TEX_LOAD_CMD_CMD__SHIFT = 26 +REG_A6XX_SP_PS_INITIAL_TEX_INDEX = lambda i0: (0x0000a9a3 + 0x1*i0 ) +A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_SAMP_ID__MASK = 0x0000ffff +A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_SAMP_ID__SHIFT = 0 +A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_TEX_ID__MASK = 0xffff0000 +A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_TEX_ID__SHIFT = 16 +REG_A6XX_SP_PS_TSIZE = 0x0000a9a7 +REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 +REG_A6XX_SP_PS_PVT_MEM_STACK_OFFSET = 0x0000a9a9 +A6XX_SP_PS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_PS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_PS_UNKNOWN_A9AB = 0x0000a9ab +REG_A6XX_SP_CS_CNTL_0 = 0x0000a9b0 +A6XX_SP_CS_CNTL_0_THREADMODE__MASK = 0x00000001 +A6XX_SP_CS_CNTL_0_THREADMODE__SHIFT = 0 +A6XX_SP_CS_CNTL_0_HALFREGFOOTPRINT__MASK = 0x0000007e +A6XX_SP_CS_CNTL_0_HALFREGFOOTPRINT__SHIFT = 1 +A6XX_SP_CS_CNTL_0_FULLREGFOOTPRINT__MASK = 0x00001f80 +A6XX_SP_CS_CNTL_0_FULLREGFOOTPRINT__SHIFT = 7 +A6XX_SP_CS_CNTL_0_UNK13 = 0x00002000 +A6XX_SP_CS_CNTL_0_BRANCHSTACK__MASK = 0x000fc000 +A6XX_SP_CS_CNTL_0_BRANCHSTACK__SHIFT = 14 +A6XX_SP_CS_CNTL_0_THREADSIZE__MASK = 0x00100000 +A6XX_SP_CS_CNTL_0_THREADSIZE__SHIFT = 20 +A6XX_SP_CS_CNTL_0_UNK21 = 0x00200000 +A6XX_SP_CS_CNTL_0_UNK22 = 0x00400000 +A6XX_SP_CS_CNTL_0_EARLYPREAMBLE = 0x00800000 +A6XX_SP_CS_CNTL_0_MERGEDREGS = 0x80000000 +REG_A6XX_SP_CS_CNTL_1 = 0x0000a9b1 +A6XX_SP_CS_CNTL_1_SHARED_SIZE__MASK = 0x0000001f +A6XX_SP_CS_CNTL_1_SHARED_SIZE__SHIFT = 0 +A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE__MASK = 0x00000060 +A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE__SHIFT = 5 +REG_A6XX_SP_CS_BOOLEAN_CF_MASK = 0x0000a9b2 +REG_A6XX_SP_CS_PROGRAM_COUNTER_OFFSET = 0x0000a9b3 +REG_A6XX_SP_CS_BASE = 0x0000a9b4 +REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 +A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff +A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 +A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 +A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 +REG_A6XX_SP_CS_PVT_MEM_BASE = 0x0000a9b7 +REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 +A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff +A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 +A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 +REG_A6XX_SP_CS_TSIZE = 0x0000a9ba +REG_A6XX_SP_CS_CONFIG = 0x0000a9bb +A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_CS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_CS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_CS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_CS_INSTR_SIZE = 0x0000a9bc +REG_A6XX_SP_CS_PVT_MEM_STACK_OFFSET = 0x0000a9bd +A6XX_SP_CS_PVT_MEM_STACK_OFFSET_OFFSET__MASK = 0x0007ffff +A6XX_SP_CS_PVT_MEM_STACK_OFFSET_OFFSET__SHIFT = 0 +REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be +REG_A7XX_SP_CS_VGS_CNTL = 0x0000a9c5 +REG_A6XX_SP_CS_WIE_CNTL_0 = 0x0000a9c2 +A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID__MASK = 0x000000ff +A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID__SHIFT = 0 +A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 +A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID__SHIFT = 8 +A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 +A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 +A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID__MASK = 0xff000000 +A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID__SHIFT = 24 +REG_A6XX_SP_CS_WIE_CNTL_1 = 0x0000a9c3 +A6XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A6XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A6XX_SP_CS_WIE_CNTL_1_SINGLE_SP_CORE = 0x00000100 +A6XX_SP_CS_WIE_CNTL_1_THREADSIZE__MASK = 0x00000200 +A6XX_SP_CS_WIE_CNTL_1_THREADSIZE__SHIFT = 9 +A6XX_SP_CS_WIE_CNTL_1_THREADSIZE_SCALAR = 0x00000400 +REG_A7XX_SP_CS_WIE_CNTL_1 = 0x0000a9c3 +A7XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff +A7XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 +A7XX_SP_CS_WIE_CNTL_1_THREADSIZE__MASK = 0x00000100 +A7XX_SP_CS_WIE_CNTL_1_THREADSIZE__SHIFT = 8 +A7XX_SP_CS_WIE_CNTL_1_THREADSIZE_SCALAR = 0x00000200 +A7XX_SP_CS_WIE_CNTL_1_WORKITEMRASTORDER__MASK = 0x00008000 +A7XX_SP_CS_WIE_CNTL_1_WORKITEMRASTORDER__SHIFT = 15 +REG_A6XX_SP_PS_SAMPLER_BASE = 0x0000a9e0 +REG_A6XX_SP_CS_SAMPLER_BASE = 0x0000a9e2 +REG_A6XX_SP_PS_TEXMEMOBJ_BASE = 0x0000a9e4 +REG_A6XX_SP_CS_TEXMEMOBJ_BASE = 0x0000a9e6 +REG_A6XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A7XX_SP_CS_BINDLESS_BASE = lambda i0: (0x0000a9e8 + 0x2*i0 ) +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_SP_CS_UAV_BASE = 0x0000a9f2 +REG_A7XX_SP_CS_UAV_BASE = 0x0000a9f8 +REG_A6XX_SP_CS_USIZE = 0x0000aa00 +REG_A7XX_SP_PS_VGS_CNTL = 0x0000aa01 +REG_A7XX_SP_PS_OUTPUT_CONST_CNTL = 0x0000aa02 +A7XX_SP_PS_OUTPUT_CONST_CNTL_ENABLED = 0x00000001 +REG_A7XX_SP_PS_OUTPUT_CONST_MASK = 0x0000aa03 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT0__MASK = 0x0000000f +A7XX_SP_PS_OUTPUT_CONST_MASK_RT0__SHIFT = 0 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT1__MASK = 0x000000f0 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT1__SHIFT = 4 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT2__MASK = 0x00000f00 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT2__SHIFT = 8 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT3__MASK = 0x0000f000 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT3__SHIFT = 12 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT4__MASK = 0x000f0000 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT4__SHIFT = 16 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT5__MASK = 0x00f00000 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT5__SHIFT = 20 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT6__MASK = 0x0f000000 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT6__SHIFT = 24 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT7__MASK = 0xf0000000 +A7XX_SP_PS_OUTPUT_CONST_MASK_RT7__SHIFT = 28 +REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 +REG_A6XX_SP_MODE_CNTL = 0x0000ab00 +A6XX_SP_MODE_CNTL_CONSTANT_DEMOTION_ENABLE = 0x00000001 +A6XX_SP_MODE_CNTL_ISAMMODE__MASK = 0x00000006 +A6XX_SP_MODE_CNTL_ISAMMODE__SHIFT = 1 +A6XX_SP_MODE_CNTL_SHARED_CONSTS_ENABLE = 0x00000008 +REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 +REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 +REG_A6XX_SP_PS_CONFIG = 0x0000ab04 +A6XX_SP_PS_CONFIG_BINDLESS_TEX = 0x00000001 +A6XX_SP_PS_CONFIG_BINDLESS_SAMP = 0x00000002 +A6XX_SP_PS_CONFIG_BINDLESS_UAV = 0x00000004 +A6XX_SP_PS_CONFIG_BINDLESS_UBO = 0x00000008 +A6XX_SP_PS_CONFIG_ENABLED = 0x00000100 +A6XX_SP_PS_CONFIG_NTEX__MASK = 0x0001fe00 +A6XX_SP_PS_CONFIG_NTEX__SHIFT = 9 +A6XX_SP_PS_CONFIG_NSAMP__MASK = 0x003e0000 +A6XX_SP_PS_CONFIG_NSAMP__SHIFT = 17 +A6XX_SP_PS_CONFIG_NUAV__MASK = 0x1fc00000 +A6XX_SP_PS_CONFIG_NUAV__SHIFT = 22 +REG_A6XX_SP_PS_INSTR_SIZE = 0x0000ab05 +REG_A6XX_SP_GFX_BINDLESS_BASE = lambda i0: (0x0000ab10 + 0x2*i0 ) +A6XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A7XX_SP_GFX_BINDLESS_BASE = lambda i0: (0x0000ab0a + 0x2*i0 ) +A7XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A7XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A7XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A7XX_SP_GFX_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_SP_GFX_UAV_BASE = 0x0000ab1a +REG_A6XX_SP_GFX_USIZE = 0x0000ab20 +REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 +REG_A6XX_SP_A2D_OUTPUT_INFO = 0x0000acc0 +A6XX_SP_A2D_OUTPUT_INFO_HALF_PRECISION = 0x00000001 +A6XX_SP_A2D_OUTPUT_INFO_IFMT_TYPE__MASK = 0x00000006 +A6XX_SP_A2D_OUTPUT_INFO_IFMT_TYPE__SHIFT = 1 +A6XX_SP_A2D_OUTPUT_INFO_COLOR_FORMAT__MASK = 0x000007f8 +A6XX_SP_A2D_OUTPUT_INFO_COLOR_FORMAT__SHIFT = 3 +A6XX_SP_A2D_OUTPUT_INFO_SRGB = 0x00000800 +A6XX_SP_A2D_OUTPUT_INFO_MASK__MASK = 0x0000f000 +A6XX_SP_A2D_OUTPUT_INFO_MASK__SHIFT = 12 +REG_A7XX_SP_A2D_OUTPUT_INFO = 0x0000a9bf +A7XX_SP_A2D_OUTPUT_INFO_HALF_PRECISION = 0x00000001 +A7XX_SP_A2D_OUTPUT_INFO_IFMT_TYPE__MASK = 0x00000006 +A7XX_SP_A2D_OUTPUT_INFO_IFMT_TYPE__SHIFT = 1 +A7XX_SP_A2D_OUTPUT_INFO_COLOR_FORMAT__MASK = 0x000007f8 +A7XX_SP_A2D_OUTPUT_INFO_COLOR_FORMAT__SHIFT = 3 +A7XX_SP_A2D_OUTPUT_INFO_SRGB = 0x00000800 +A7XX_SP_A2D_OUTPUT_INFO_MASK__MASK = 0x0000f000 +A7XX_SP_A2D_OUTPUT_INFO_MASK__SHIFT = 12 +REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 +REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 +REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 +REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 +REG_A6XX_SP_NC_MODE_CNTL_2 = 0x0000ae04 +A6XX_SP_NC_MODE_CNTL_2_F16_NO_INF = 0x00000008 +REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 +REG_A7XX_SP_CHICKEN_BITS_1 = 0x0000ae08 +REG_A7XX_SP_CHICKEN_BITS_2 = 0x0000ae09 +REG_A7XX_SP_CHICKEN_BITS_3 = 0x0000ae0a +REG_A6XX_SP_PERFCTR_SHADER_MASK = 0x0000ae0f +A6XX_SP_PERFCTR_SHADER_MASK_VS = 0x00000001 +A6XX_SP_PERFCTR_SHADER_MASK_HS = 0x00000002 +A6XX_SP_PERFCTR_SHADER_MASK_DS = 0x00000004 +A6XX_SP_PERFCTR_SHADER_MASK_GS = 0x00000008 +A6XX_SP_PERFCTR_SHADER_MASK_FS = 0x00000010 +A6XX_SP_PERFCTR_SHADER_MASK_CS = 0x00000020 +REG_A6XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae10 + 0x1*i0 ) +REG_A7XX_SP_PERFCTR_HLSQ_SEL = lambda i0: (0x0000ae60 + 0x1*i0 ) +REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a +REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b +REG_A7XX_SP_HLSQ_DBG_ECO_CNTL = 0x0000ae6c +REG_A7XX_SP_READ_SEL = 0x0000ae6d +A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 +A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 +A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 +A7XX_SP_READ_SEL_PIPE__SHIFT = 16 +A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 +A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 +A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 +A7XX_SP_READ_SEL_USPTP__SHIFT = 4 +A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f +A7XX_SP_READ_SEL_SPTP__SHIFT = 0 +REG_A7XX_SP_DBG_CNTL = 0x0000ae71 +REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 +REG_A7XX_SP_PERFCTR_SP_SEL = lambda i0: (0x0000ae80 + 0x1*i0 ) +REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 +REG_A6XX_TPL1_CS_BORDER_COLOR_BASE = 0x0000b180 +REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 +REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 +REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 +REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 +REG_A6XX_TPL1_RAS_MSAA_CNTL = 0x0000b300 +A6XX_TPL1_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_TPL1_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_TPL1_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c +A6XX_TPL1_RAS_MSAA_CNTL_UNK2__SHIFT = 2 +REG_A6XX_TPL1_DEST_MSAA_CNTL = 0x0000b301 +A6XX_TPL1_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 +A6XX_TPL1_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 +A6XX_TPL1_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 +REG_A6XX_TPL1_GFX_BORDER_COLOR_BASE = 0x0000b302 +REG_A6XX_TPL1_MSAA_SAMPLE_POS_CNTL = 0x0000b304 +A6XX_TPL1_MSAA_SAMPLE_POS_CNTL_UNK0 = 0x00000001 +A6XX_TPL1_MSAA_SAMPLE_POS_CNTL_LOCATION_ENABLE = 0x00000002 +REG_A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0 = 0x0000b305 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__MASK = 0x0000000f +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X__SHIFT = 0 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y__SHIFT = 4 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_X__SHIFT = 8 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_1_Y__SHIFT = 12 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_X__SHIFT = 16 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_2_Y__SHIFT = 20 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_X__SHIFT = 24 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1 = 0x0000b306 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__MASK = 0x0000000f +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_X__SHIFT = 0 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__MASK = 0x000000f0 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_0_Y__SHIFT = 4 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__MASK = 0x00000f00 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_X__SHIFT = 8 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__MASK = 0x0000f000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_1_Y__SHIFT = 12 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__MASK = 0x000f0000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_X__SHIFT = 16 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__MASK = 0x00f00000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_2_Y__SHIFT = 20 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__MASK = 0x0f000000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_X__SHIFT = 24 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__MASK = 0xf0000000 +A6XX_TPL1_PROGRAMMABLE_MSAA_POS_1_SAMPLE_3_Y__SHIFT = 28 +REG_A6XX_TPL1_WINDOW_OFFSET = 0x0000b307 +A6XX_TPL1_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_TPL1_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_TPL1_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_TPL1_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_TPL1_MODE_CNTL = 0x0000b309 +A6XX_TPL1_MODE_CNTL_ISAMMODE__MASK = 0x00000003 +A6XX_TPL1_MODE_CNTL_ISAMMODE__SHIFT = 0 +A6XX_TPL1_MODE_CNTL_TEXCOORDROUNDMODE__MASK = 0x00000004 +A6XX_TPL1_MODE_CNTL_TEXCOORDROUNDMODE__SHIFT = 2 +A6XX_TPL1_MODE_CNTL_NEARESTMIPSNAP__MASK = 0x00000020 +A6XX_TPL1_MODE_CNTL_NEARESTMIPSNAP__SHIFT = 5 +A6XX_TPL1_MODE_CNTL_DESTDATATYPEOVERRIDE = 0x00000080 +REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_INFO = 0x0000b4c0 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT__MASK = 0x000000ff +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT__SHIFT = 0 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_TILE_MODE__MASK = 0x00000300 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_TILE_MODE__SHIFT = 8 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_SWAP__MASK = 0x00000c00 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_SWAP__SHIFT = 10 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_FLAGS = 0x00001000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SRGB = 0x00002000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES__MASK = 0x0000c000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES__SHIFT = 14 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_FILTER = 0x00010000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK17 = 0x00020000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES_AVERAGE = 0x00040000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK19 = 0x00080000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK20 = 0x00100000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK21 = 0x00200000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK22 = 0x00400000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK23__MASK = 0x07800000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK23__SHIFT = 23 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK28 = 0x10000000 +A6XX_TPL1_A2D_SRC_TEXTURE_INFO_MUTABLEEN = 0x20000000 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_SIZE = 0x0000b4c1 +A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_WIDTH__MASK = 0x00007fff +A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_WIDTH__SHIFT = 0 +A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_HEIGHT__MASK = 0x3fff8000 +A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_HEIGHT__SHIFT = 15 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_BASE = 0x0000b4c2 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_PITCH = 0x0000b4c4 +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_UNK0__MASK = 0x000001ff +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_UNK0__SHIFT = 0 +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_PITCH__MASK = 0x00fffe00 +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_PITCH__SHIFT = 9 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_INFO = 0x0000b2c0 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT__MASK = 0x000000ff +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT__SHIFT = 0 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_TILE_MODE__MASK = 0x00000300 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_TILE_MODE__SHIFT = 8 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_SWAP__MASK = 0x00000c00 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_SWAP__SHIFT = 10 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_FLAGS = 0x00001000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_SRGB = 0x00002000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES__MASK = 0x0000c000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES__SHIFT = 14 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_FILTER = 0x00010000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK17 = 0x00020000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES_AVERAGE = 0x00040000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK19 = 0x00080000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK20 = 0x00100000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK21 = 0x00200000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK22 = 0x00400000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK23__MASK = 0x07800000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK23__SHIFT = 23 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK28 = 0x10000000 +A7XX_TPL1_A2D_SRC_TEXTURE_INFO_MUTABLEEN = 0x20000000 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_SIZE = 0x0000b2c1 +A7XX_TPL1_A2D_SRC_TEXTURE_SIZE_WIDTH__MASK = 0x00007fff +A7XX_TPL1_A2D_SRC_TEXTURE_SIZE_WIDTH__SHIFT = 0 +A7XX_TPL1_A2D_SRC_TEXTURE_SIZE_HEIGHT__MASK = 0x3fff8000 +A7XX_TPL1_A2D_SRC_TEXTURE_SIZE_HEIGHT__SHIFT = 15 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_BASE = 0x0000b2c2 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_PITCH = 0x0000b2c4 +A7XX_TPL1_A2D_SRC_TEXTURE_PITCH_PITCH__MASK = 0x00fffff8 +A7XX_TPL1_A2D_SRC_TEXTURE_PITCH_PITCH__SHIFT = 3 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_BASE_1 = 0x0000b4c5 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_1 = 0x0000b4c7 +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_1__MASK = 0x00000fff +A6XX_TPL1_A2D_SRC_TEXTURE_PITCH_1__SHIFT = 0 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_BASE_2 = 0x0000b4c8 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_BASE_1 = 0x0000b2c5 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_PITCH_1 = 0x0000b2c7 +A7XX_TPL1_A2D_SRC_TEXTURE_PITCH_1__MASK = 0x00000fff +A7XX_TPL1_A2D_SRC_TEXTURE_PITCH_1__SHIFT = 0 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_BASE_2 = 0x0000b2c8 +REG_A6XX_TPL1_A2D_SRC_TEXTURE_FLAG_BASE = 0x0000b4ca +REG_A6XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH = 0x0000b4cc +A6XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH__MASK = 0x000000ff +A6XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH__SHIFT = 0 +REG_A7XX_TPL1_A2D_SRC_TEXTURE_FLAG_BASE = 0x0000b2ca +REG_A7XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH = 0x0000b2cc +A7XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH__MASK = 0x000000ff +A7XX_TPL1_A2D_SRC_TEXTURE_FLAG_PITCH__SHIFT = 0 +REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd +REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce +REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf +REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 +REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 +A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff +A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 +A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd +REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce +REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf +REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 +REG_A7XX_TPL1_A2D_WINDOW_OFFSET = 0x0000b2d1 +A7XX_TPL1_A2D_WINDOW_OFFSET_X__MASK = 0x00003fff +A7XX_TPL1_A2D_WINDOW_OFFSET_X__SHIFT = 0 +A7XX_TPL1_A2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A7XX_TPL1_A2D_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A7XX_TPL1_A2D_BLT_CNTL = 0x0000b2d2 +A7XX_TPL1_A2D_BLT_CNTL_RAW_COPY = 0x00000001 +A7XX_TPL1_A2D_BLT_CNTL_START_OFFSET_TEXELS__MASK = 0x003f0000 +A7XX_TPL1_A2D_BLT_CNTL_START_OFFSET_TEXELS__SHIFT = 16 +A7XX_TPL1_A2D_BLT_CNTL_TYPE__MASK = 0xe0000000 +A7XX_TPL1_A2D_BLT_CNTL_TYPE__SHIFT = 29 +REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 +A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff +A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 +A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 +A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 +REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 +REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 +REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 +A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT = 0x00040000 +REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 +A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 +A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 +A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 +A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 +A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 +A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 +A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 +A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 +REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b +REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b +REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c +REG_A6XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) +REG_A7XX_TPL1_PERFCTR_TP_SEL = lambda i0: (0x0000b610 + 0x1*i0 ) +REG_A6XX_SP_VS_CONST_CONFIG = 0x0000b800 +A6XX_SP_VS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_VS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_VS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_VS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_SP_HS_CONST_CONFIG = 0x0000b801 +A6XX_SP_HS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_HS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_HS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_HS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_SP_DS_CONST_CONFIG = 0x0000b802 +A6XX_SP_DS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_DS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_DS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_DS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_SP_GS_CONST_CONFIG = 0x0000b803 +A6XX_SP_GS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_GS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_GS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_GS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_VS_CONST_CONFIG = 0x0000a827 +A7XX_SP_VS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_VS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_VS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_VS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_HS_CONST_CONFIG = 0x0000a83f +A7XX_SP_HS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_HS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_HS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_HS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_DS_CONST_CONFIG = 0x0000a867 +A7XX_SP_DS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_DS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_DS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_DS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_GS_CONST_CONFIG = 0x0000a898 +A7XX_SP_GS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_GS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_GS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_GS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_RENDER_CNTL = 0x0000a9aa +A7XX_SP_RENDER_CNTL_FS_DISABLE = 0x00000001 +REG_A7XX_SP_DITHER_CNTL = 0x0000a9ac +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 +A7XX_SP_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 +REG_A7XX_SP_VRS_CONFIG = 0x0000a9ad +A7XX_SP_VRS_CONFIG_PIPELINE_FSR_ENABLE = 0x00000001 +A7XX_SP_VRS_CONFIG_ATTACHMENT_FSR_ENABLE = 0x00000002 +A7XX_SP_VRS_CONFIG_PRIMITIVE_FSR_ENABLE = 0x00000008 +REG_A7XX_SP_PS_CNTL_1 = 0x0000a9ae +A7XX_SP_PS_CNTL_1_SYSVAL_REGS_COUNT__MASK = 0x000000ff +A7XX_SP_PS_CNTL_1_SYSVAL_REGS_COUNT__SHIFT = 0 +A7XX_SP_PS_CNTL_1_UNK8 = 0x00000100 +A7XX_SP_PS_CNTL_1_UNK9 = 0x00000200 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 +REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 +REG_A6XX_SP_PS_WAVE_CNTL = 0x0000b980 +A6XX_SP_PS_WAVE_CNTL_THREADSIZE__MASK = 0x00000001 +A6XX_SP_PS_WAVE_CNTL_THREADSIZE__SHIFT = 0 +A6XX_SP_PS_WAVE_CNTL_VARYINGS = 0x00000002 +A6XX_SP_PS_WAVE_CNTL_UNK2__MASK = 0x00000ffc +A6XX_SP_PS_WAVE_CNTL_UNK2__SHIFT = 2 +REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 +REG_A6XX_SP_LB_PARAM_LIMIT = 0x0000b982 +A6XX_SP_LB_PARAM_LIMIT_PRIMALLOCTHRESHOLD__MASK = 0x00000007 +A6XX_SP_LB_PARAM_LIMIT_PRIMALLOCTHRESHOLD__SHIFT = 0 +REG_A6XX_SP_REG_PROG_ID_0 = 0x0000b983 +A6XX_SP_REG_PROG_ID_0_FACEREGID__MASK = 0x000000ff +A6XX_SP_REG_PROG_ID_0_FACEREGID__SHIFT = 0 +A6XX_SP_REG_PROG_ID_0_SAMPLEID__MASK = 0x0000ff00 +A6XX_SP_REG_PROG_ID_0_SAMPLEID__SHIFT = 8 +A6XX_SP_REG_PROG_ID_0_SAMPLEMASK__MASK = 0x00ff0000 +A6XX_SP_REG_PROG_ID_0_SAMPLEMASK__SHIFT = 16 +A6XX_SP_REG_PROG_ID_0_CENTERRHW__MASK = 0xff000000 +A6XX_SP_REG_PROG_ID_0_CENTERRHW__SHIFT = 24 +REG_A6XX_SP_REG_PROG_ID_1 = 0x0000b984 +A6XX_SP_REG_PROG_ID_1_IJ_PERSP_PIXEL__MASK = 0x000000ff +A6XX_SP_REG_PROG_ID_1_IJ_PERSP_PIXEL__SHIFT = 0 +A6XX_SP_REG_PROG_ID_1_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 +A6XX_SP_REG_PROG_ID_1_IJ_LINEAR_PIXEL__SHIFT = 8 +A6XX_SP_REG_PROG_ID_1_IJ_PERSP_CENTROID__MASK = 0x00ff0000 +A6XX_SP_REG_PROG_ID_1_IJ_PERSP_CENTROID__SHIFT = 16 +A6XX_SP_REG_PROG_ID_1_IJ_LINEAR_CENTROID__MASK = 0xff000000 +A6XX_SP_REG_PROG_ID_1_IJ_LINEAR_CENTROID__SHIFT = 24 +REG_A6XX_SP_REG_PROG_ID_2 = 0x0000b985 +A6XX_SP_REG_PROG_ID_2_IJ_PERSP_SAMPLE__MASK = 0x000000ff +A6XX_SP_REG_PROG_ID_2_IJ_PERSP_SAMPLE__SHIFT = 0 +A6XX_SP_REG_PROG_ID_2_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 +A6XX_SP_REG_PROG_ID_2_IJ_LINEAR_SAMPLE__SHIFT = 8 +A6XX_SP_REG_PROG_ID_2_XYCOORDREGID__MASK = 0x00ff0000 +A6XX_SP_REG_PROG_ID_2_XYCOORDREGID__SHIFT = 16 +A6XX_SP_REG_PROG_ID_2_ZWCOORDREGID__MASK = 0xff000000 +A6XX_SP_REG_PROG_ID_2_ZWCOORDREGID__SHIFT = 24 +REG_A6XX_SP_REG_PROG_ID_3 = 0x0000b986 +A6XX_SP_REG_PROG_ID_3_LINELENGTHREGID__MASK = 0x000000ff +A6XX_SP_REG_PROG_ID_3_LINELENGTHREGID__SHIFT = 0 +A6XX_SP_REG_PROG_ID_3_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 +A6XX_SP_REG_PROG_ID_3_FOVEATIONQUALITYREGID__SHIFT = 8 +REG_A6XX_SP_CS_CONST_CONFIG = 0x0000b987 +A6XX_SP_CS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_CS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_CS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_CS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_PS_WAVE_CNTL = 0x0000a9c6 +A7XX_SP_PS_WAVE_CNTL_THREADSIZE__MASK = 0x00000001 +A7XX_SP_PS_WAVE_CNTL_THREADSIZE__SHIFT = 0 +A7XX_SP_PS_WAVE_CNTL_VARYINGS = 0x00000002 +A7XX_SP_PS_WAVE_CNTL_UNK2__MASK = 0x00000ffc +A7XX_SP_PS_WAVE_CNTL_UNK2__SHIFT = 2 +REG_A7XX_SP_LB_PARAM_LIMIT = 0x0000a9c7 +A7XX_SP_LB_PARAM_LIMIT_PRIMALLOCTHRESHOLD__MASK = 0x00000007 +A7XX_SP_LB_PARAM_LIMIT_PRIMALLOCTHRESHOLD__SHIFT = 0 +REG_A7XX_SP_REG_PROG_ID_0 = 0x0000a9c8 +A7XX_SP_REG_PROG_ID_0_FACEREGID__MASK = 0x000000ff +A7XX_SP_REG_PROG_ID_0_FACEREGID__SHIFT = 0 +A7XX_SP_REG_PROG_ID_0_SAMPLEID__MASK = 0x0000ff00 +A7XX_SP_REG_PROG_ID_0_SAMPLEID__SHIFT = 8 +A7XX_SP_REG_PROG_ID_0_SAMPLEMASK__MASK = 0x00ff0000 +A7XX_SP_REG_PROG_ID_0_SAMPLEMASK__SHIFT = 16 +A7XX_SP_REG_PROG_ID_0_CENTERRHW__MASK = 0xff000000 +A7XX_SP_REG_PROG_ID_0_CENTERRHW__SHIFT = 24 +REG_A7XX_SP_REG_PROG_ID_1 = 0x0000a9c9 +A7XX_SP_REG_PROG_ID_1_IJ_PERSP_PIXEL__MASK = 0x000000ff +A7XX_SP_REG_PROG_ID_1_IJ_PERSP_PIXEL__SHIFT = 0 +A7XX_SP_REG_PROG_ID_1_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 +A7XX_SP_REG_PROG_ID_1_IJ_LINEAR_PIXEL__SHIFT = 8 +A7XX_SP_REG_PROG_ID_1_IJ_PERSP_CENTROID__MASK = 0x00ff0000 +A7XX_SP_REG_PROG_ID_1_IJ_PERSP_CENTROID__SHIFT = 16 +A7XX_SP_REG_PROG_ID_1_IJ_LINEAR_CENTROID__MASK = 0xff000000 +A7XX_SP_REG_PROG_ID_1_IJ_LINEAR_CENTROID__SHIFT = 24 +REG_A7XX_SP_REG_PROG_ID_2 = 0x0000a9ca +A7XX_SP_REG_PROG_ID_2_IJ_PERSP_SAMPLE__MASK = 0x000000ff +A7XX_SP_REG_PROG_ID_2_IJ_PERSP_SAMPLE__SHIFT = 0 +A7XX_SP_REG_PROG_ID_2_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 +A7XX_SP_REG_PROG_ID_2_IJ_LINEAR_SAMPLE__SHIFT = 8 +A7XX_SP_REG_PROG_ID_2_XYCOORDREGID__MASK = 0x00ff0000 +A7XX_SP_REG_PROG_ID_2_XYCOORDREGID__SHIFT = 16 +A7XX_SP_REG_PROG_ID_2_ZWCOORDREGID__MASK = 0xff000000 +A7XX_SP_REG_PROG_ID_2_ZWCOORDREGID__SHIFT = 24 +REG_A7XX_SP_REG_PROG_ID_3 = 0x0000a9cb +A7XX_SP_REG_PROG_ID_3_LINELENGTHREGID__MASK = 0x000000ff +A7XX_SP_REG_PROG_ID_3_LINELENGTHREGID__SHIFT = 0 +A7XX_SP_REG_PROG_ID_3_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 +A7XX_SP_REG_PROG_ID_3_FOVEATIONQUALITYREGID__SHIFT = 8 +REG_A7XX_SP_CS_CONST_CONFIG = 0x0000a9cd +A7XX_SP_CS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_CS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_CS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_CS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A6XX_SP_CS_NDRANGE_0 = 0x0000b990 +A6XX_SP_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 +A6XX_SP_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 +A6XX_SP_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc +A6XX_SP_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 +A6XX_SP_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 +A6XX_SP_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 +A6XX_SP_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 +A6XX_SP_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_SP_CS_NDRANGE_1 = 0x0000b991 +A6XX_SP_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 +REG_A6XX_SP_CS_NDRANGE_2 = 0x0000b992 +A6XX_SP_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 +REG_A6XX_SP_CS_NDRANGE_3 = 0x0000b993 +A6XX_SP_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 +REG_A6XX_SP_CS_NDRANGE_4 = 0x0000b994 +A6XX_SP_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 +REG_A6XX_SP_CS_NDRANGE_5 = 0x0000b995 +A6XX_SP_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 +REG_A6XX_SP_CS_NDRANGE_6 = 0x0000b996 +A6XX_SP_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff +A6XX_SP_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 +REG_A6XX_SP_CS_CONST_CONFIG_0 = 0x0000b997 +A6XX_SP_CS_CONST_CONFIG_0_WGIDCONSTID__MASK = 0x000000ff +A6XX_SP_CS_CONST_CONFIG_0_WGIDCONSTID__SHIFT = 0 +A6XX_SP_CS_CONST_CONFIG_0_WGSIZECONSTID__MASK = 0x0000ff00 +A6XX_SP_CS_CONST_CONFIG_0_WGSIZECONSTID__SHIFT = 8 +A6XX_SP_CS_CONST_CONFIG_0_WGOFFSETCONSTID__MASK = 0x00ff0000 +A6XX_SP_CS_CONST_CONFIG_0_WGOFFSETCONSTID__SHIFT = 16 +A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID__MASK = 0xff000000 +A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID__SHIFT = 24 +REG_A6XX_SP_CS_WGE_CNTL = 0x0000b998 +A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID__MASK = 0x000000ff +A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID__SHIFT = 0 +A6XX_SP_CS_WGE_CNTL_SINGLE_SP_CORE = 0x00000100 +A6XX_SP_CS_WGE_CNTL_THREADSIZE__MASK = 0x00000200 +A6XX_SP_CS_WGE_CNTL_THREADSIZE__SHIFT = 9 +A6XX_SP_CS_WGE_CNTL_THREADSIZE_SCALAR = 0x00000400 +REG_A6XX_SP_CS_KERNEL_GROUP_X = 0x0000b999 +REG_A6XX_SP_CS_KERNEL_GROUP_Y = 0x0000b99a +REG_A6XX_SP_CS_KERNEL_GROUP_Z = 0x0000b99b +REG_A7XX_SP_CS_NDRANGE_0 = 0x0000a9d4 +A7XX_SP_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 +A7XX_SP_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 +A7XX_SP_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc +A7XX_SP_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 +A7XX_SP_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 +A7XX_SP_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 +A7XX_SP_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 +A7XX_SP_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 +REG_A7XX_SP_CS_NDRANGE_1 = 0x0000a9d5 +A7XX_SP_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 +REG_A7XX_SP_CS_NDRANGE_2 = 0x0000a9d6 +A7XX_SP_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 +REG_A7XX_SP_CS_NDRANGE_3 = 0x0000a9d7 +A7XX_SP_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 +REG_A7XX_SP_CS_NDRANGE_4 = 0x0000a9d8 +A7XX_SP_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 +REG_A7XX_SP_CS_NDRANGE_5 = 0x0000a9d9 +A7XX_SP_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 +REG_A7XX_SP_CS_NDRANGE_6 = 0x0000a9da +A7XX_SP_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff +A7XX_SP_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 +REG_A7XX_SP_CS_KERNEL_GROUP_X = 0x0000a9dc +REG_A7XX_SP_CS_KERNEL_GROUP_Y = 0x0000a9dd +REG_A7XX_SP_CS_KERNEL_GROUP_Z = 0x0000a9de +REG_A7XX_SP_CS_WGE_CNTL = 0x0000a9db +A7XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID__MASK = 0x000000ff +A7XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID__SHIFT = 0 +A7XX_SP_CS_WGE_CNTL_THREADSIZE__MASK = 0x00000200 +A7XX_SP_CS_WGE_CNTL_THREADSIZE__SHIFT = 9 +A7XX_SP_CS_WGE_CNTL_WORKGROUPRASTORDERZFIRSTEN = 0x00000800 +A7XX_SP_CS_WGE_CNTL_WGTILEWIDTH__MASK = 0x03f00000 +A7XX_SP_CS_WGE_CNTL_WGTILEWIDTH__SHIFT = 20 +A7XX_SP_CS_WGE_CNTL_WGTILEHEIGHT__MASK = 0xfc000000 +A7XX_SP_CS_WGE_CNTL_WGTILEHEIGHT__SHIFT = 26 +REG_A7XX_SP_CS_NDRANGE_7 = 0x0000a9df +A7XX_SP_CS_NDRANGE_7_LOCALSIZEX__MASK = 0x00000ffc +A7XX_SP_CS_NDRANGE_7_LOCALSIZEX__SHIFT = 2 +A7XX_SP_CS_NDRANGE_7_LOCALSIZEY__MASK = 0x003ff000 +A7XX_SP_CS_NDRANGE_7_LOCALSIZEY__SHIFT = 12 +A7XX_SP_CS_NDRANGE_7_LOCALSIZEZ__MASK = 0xffc00000 +A7XX_SP_CS_NDRANGE_7_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 +REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 +REG_A6XX_HLSQ_CS_BINDLESS_BASE = lambda i0: (0x0000b9c0 + 0x2*i0 ) +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_HLSQ_CS_CTRL_REG1 = 0x0000b9d0 +A6XX_HLSQ_CS_CTRL_REG1_SHARED_SIZE__MASK = 0x0000001f +A6XX_HLSQ_CS_CTRL_REG1_SHARED_SIZE__SHIFT = 0 +A6XX_HLSQ_CS_CTRL_REG1_CONSTANTRAMMODE__MASK = 0x00000060 +A6XX_HLSQ_CS_CTRL_REG1_CONSTANTRAMMODE__SHIFT = 5 +REG_A6XX_SP_DRAW_INITIATOR = 0x0000bb00 +A6XX_SP_DRAW_INITIATOR_STATE_ID__MASK = 0x000000ff +A6XX_SP_DRAW_INITIATOR_STATE_ID__SHIFT = 0 +REG_A6XX_SP_KERNEL_INITIATOR = 0x0000bb01 +A6XX_SP_KERNEL_INITIATOR_STATE_ID__MASK = 0x000000ff +A6XX_SP_KERNEL_INITIATOR_STATE_ID__SHIFT = 0 +REG_A6XX_SP_EVENT_INITIATOR = 0x0000bb02 +A6XX_SP_EVENT_INITIATOR_STATE_ID__MASK = 0x00ff0000 +A6XX_SP_EVENT_INITIATOR_STATE_ID__SHIFT = 16 +A6XX_SP_EVENT_INITIATOR_EVENT__MASK = 0x0000007f +A6XX_SP_EVENT_INITIATOR_EVENT__SHIFT = 0 +REG_A6XX_SP_UPDATE_CNTL = 0x0000bb08 +A6XX_SP_UPDATE_CNTL_VS_STATE = 0x00000001 +A6XX_SP_UPDATE_CNTL_HS_STATE = 0x00000002 +A6XX_SP_UPDATE_CNTL_DS_STATE = 0x00000004 +A6XX_SP_UPDATE_CNTL_GS_STATE = 0x00000008 +A6XX_SP_UPDATE_CNTL_FS_STATE = 0x00000010 +A6XX_SP_UPDATE_CNTL_CS_STATE = 0x00000020 +A6XX_SP_UPDATE_CNTL_CS_UAV = 0x00000040 +A6XX_SP_UPDATE_CNTL_GFX_UAV = 0x00000080 +A6XX_SP_UPDATE_CNTL_CS_SHARED_CONST = 0x00080000 +A6XX_SP_UPDATE_CNTL_GFX_SHARED_CONST = 0x00000100 +A6XX_SP_UPDATE_CNTL_CS_BINDLESS__MASK = 0x00003e00 +A6XX_SP_UPDATE_CNTL_CS_BINDLESS__SHIFT = 9 +A6XX_SP_UPDATE_CNTL_GFX_BINDLESS__MASK = 0x0007c000 +A6XX_SP_UPDATE_CNTL_GFX_BINDLESS__SHIFT = 14 +REG_A7XX_SP_DRAW_INITIATOR = 0x0000ab1c +A7XX_SP_DRAW_INITIATOR_STATE_ID__MASK = 0x000000ff +A7XX_SP_DRAW_INITIATOR_STATE_ID__SHIFT = 0 +REG_A7XX_SP_KERNEL_INITIATOR = 0x0000ab1d +A7XX_SP_KERNEL_INITIATOR_STATE_ID__MASK = 0x000000ff +A7XX_SP_KERNEL_INITIATOR_STATE_ID__SHIFT = 0 +REG_A7XX_SP_EVENT_INITIATOR = 0x0000ab1e +A7XX_SP_EVENT_INITIATOR_STATE_ID__MASK = 0x00ff0000 +A7XX_SP_EVENT_INITIATOR_STATE_ID__SHIFT = 16 +A7XX_SP_EVENT_INITIATOR_EVENT__MASK = 0x0000007f +A7XX_SP_EVENT_INITIATOR_EVENT__SHIFT = 0 +REG_A7XX_SP_UPDATE_CNTL = 0x0000ab1f +A7XX_SP_UPDATE_CNTL_VS_STATE = 0x00000001 +A7XX_SP_UPDATE_CNTL_HS_STATE = 0x00000002 +A7XX_SP_UPDATE_CNTL_DS_STATE = 0x00000004 +A7XX_SP_UPDATE_CNTL_GS_STATE = 0x00000008 +A7XX_SP_UPDATE_CNTL_FS_STATE = 0x00000010 +A7XX_SP_UPDATE_CNTL_CS_STATE = 0x00000020 +A7XX_SP_UPDATE_CNTL_CS_UAV = 0x00000040 +A7XX_SP_UPDATE_CNTL_GFX_UAV = 0x00000080 +A7XX_SP_UPDATE_CNTL_CS_BINDLESS__MASK = 0x0001fe00 +A7XX_SP_UPDATE_CNTL_CS_BINDLESS__SHIFT = 9 +A7XX_SP_UPDATE_CNTL_GFX_BINDLESS__MASK = 0x01fe0000 +A7XX_SP_UPDATE_CNTL_GFX_BINDLESS__SHIFT = 17 +REG_A6XX_SP_PS_CONST_CONFIG = 0x0000bb10 +A6XX_SP_PS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A6XX_SP_PS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A6XX_SP_PS_CONST_CONFIG_ENABLED = 0x00000100 +A6XX_SP_PS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_PS_CONST_CONFIG = 0x0000ab03 +A7XX_SP_PS_CONST_CONFIG_CONSTLEN__MASK = 0x000000ff +A7XX_SP_PS_CONST_CONFIG_CONSTLEN__SHIFT = 0 +A7XX_SP_PS_CONST_CONFIG_ENABLED = 0x00000100 +A7XX_SP_PS_CONST_CONFIG_READ_IMM_SHARED_CONSTS = 0x00000200 +REG_A7XX_SP_SHARED_CONSTANT_GFX_0 = lambda i0: (0x0000ab40 + 0x1*i0 ) +REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 +A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 +REG_A6XX_HLSQ_BINDLESS_BASE = lambda i0: (0x0000bb20 + 0x2*i0 ) +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc +A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 +REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 +A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 +A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 +A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f +A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 +REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 +REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 +REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 +REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 +REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 +REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL = lambda i0: (0x0000be10 + 0x1*i0 ) +REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 +REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 +REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 +REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 +REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 +REG_A6XX_CP_EVENT_START = 0x0000d600 +A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff +A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 +REG_A6XX_CP_EVENT_END = 0x0000d601 +A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff +A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 +REG_A6XX_CP_2D_EVENT_START = 0x0000d700 +A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff +A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 +REG_A6XX_CP_2D_EVENT_END = 0x0000d701 +A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff +A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 +REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 +REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 +REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 +REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 +REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 +REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 +REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 +REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 +REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 +REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 +REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 +REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 +REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 +REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 +REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 +REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 +REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 +REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 +REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 +REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 +REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 +REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 +REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 +REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 +REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da +REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db +REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 +A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 +REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 +REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a +REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e +REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f +REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 +A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 +REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f +REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 +REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 +REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 +REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 +REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 +A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 +A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 +A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 +__struct__cast = lambda X: (struct_X) +REG_CP_LOAD_STATE_0 = 0x00000000 +CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff +CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 +CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 +CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 +CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE_1 = 0x00000001 +CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 +CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 +CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE4_0 = 0x00000000 +CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff +CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 +CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 +CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 +CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE4_1 = 0x00000001 +CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 +CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 +CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE4_2 = 0x00000002 +CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff +CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 +REG_CP_LOAD_STATE6_0 = 0x00000000 +CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff +CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 +CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 +CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 +CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 +CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 +CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 +CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 +CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 +CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 +REG_CP_LOAD_STATE6_1 = 0x00000001 +CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc +CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 +REG_CP_LOAD_STATE6_2 = 0x00000002 +CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff +CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 +REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 +REG_CP_DRAW_INDX_0 = 0x00000000 +CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff +CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 +REG_CP_DRAW_INDX_1 = 0x00000001 +CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 +CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 +CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 +CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 +CP_DRAW_INDX_1_NOT_EOP = 0x00001000 +CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 +CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 +CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 +CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 +REG_CP_DRAW_INDX_2 = 0x00000002 +CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_3 = 0x00000003 +CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff +CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 +REG_CP_DRAW_INDX_4 = 0x00000004 +CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff +CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 +REG_CP_DRAW_INDX_2_0 = 0x00000000 +CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff +CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 +REG_CP_DRAW_INDX_2_1 = 0x00000001 +CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 +CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 +CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 +CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 +CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 +CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 +CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 +CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 +CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 +REG_CP_DRAW_INDX_2_2 = 0x00000002 +CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 +CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 +CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 +CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 +CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 +CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 +CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 +CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 +CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 +CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 +REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 +CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 +CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 +CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 +A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 +A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 +REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 +A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 +CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 +REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 +CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff +CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 +A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f +A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 +A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 +A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 +A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 +A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 +A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 +A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 +A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 +A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 +A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 +A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 +REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 +A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff +A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 +A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 +A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 +REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 +A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f +A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 +A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 +A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 +A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 +A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 +A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 +A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 +A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 +A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 +A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 +A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 +REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 +A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 +A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 +REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 +A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff +A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 +A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 +A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 +REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 +A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 +A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 +A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff +A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 +REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f +A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 +A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 +A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 +A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 +A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 +A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 +A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 +A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 +A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 +A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f +A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 +A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 +A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 +REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 +REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 +REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 +REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 +REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 +REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a +REG_CP_DRAW_AUTO_0 = 0x00000000 +CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f +CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 +CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 +CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 +CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 +CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 +CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 +CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 +CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 +CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 +CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 +CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 +REG_CP_DRAW_AUTO_1 = 0x00000001 +CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff +CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 +REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 +REG_CP_DRAW_AUTO_4 = 0x00000004 +CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff +CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 +REG_CP_DRAW_AUTO_5 = 0x00000005 +CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff +CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 +REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 +CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 +REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 +CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 +REG_CP_DRAW_PRED_SET_0 = 0x00000000 +CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 +CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 +CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 +CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 +REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 +REG_CP_SET_DRAW_STATE_ = lambda i0: (0x00000000 + 0x3*i0 ) +CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff +CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 +CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 +CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 +CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 +CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 +CP_SET_DRAW_STATE__0_BINNING = 0x00100000 +CP_SET_DRAW_STATE__0_GMEM = 0x00200000 +CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 +CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 +CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 +CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff +CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 +CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff +CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 +REG_CP_SET_BIN_0 = 0x00000000 +REG_CP_SET_BIN_1 = 0x00000001 +CP_SET_BIN_1_X1__MASK = 0x0000ffff +CP_SET_BIN_1_X1__SHIFT = 0 +CP_SET_BIN_1_Y1__MASK = 0xffff0000 +CP_SET_BIN_1_Y1__SHIFT = 16 +REG_CP_SET_BIN_2 = 0x00000002 +CP_SET_BIN_2_X2__MASK = 0x0000ffff +CP_SET_BIN_2_X2__SHIFT = 0 +CP_SET_BIN_2_Y2__MASK = 0xffff0000 +CP_SET_BIN_2_Y2__SHIFT = 16 +REG_CP_SET_BIN_DATA_0 = 0x00000000 +CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff +CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 +REG_CP_SET_BIN_DATA_1 = 0x00000001 +CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff +CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 +REG_CP_SET_BIN_DATA5_0 = 0x00000000 +CP_SET_BIN_DATA5_0_VSC_MASK__MASK = 0x0000ffff +CP_SET_BIN_DATA5_0_VSC_MASK__SHIFT = 0 +CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 +CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 +CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 +CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 +CP_SET_BIN_DATA5_0_ABS_MASK__MASK = 0x10000000 +CP_SET_BIN_DATA5_0_ABS_MASK__SHIFT = 28 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_1 = 0x00000001 +NO_ABS_MASK_CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_2 = 0x00000002 +NO_ABS_MASK_CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_3 = 0x00000003 +NO_ABS_MASK_CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_4 = 0x00000004 +NO_ABS_MASK_CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_5 = 0x00000005 +NO_ABS_MASK_CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_6 = 0x00000006 +NO_ABS_MASK_CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_7 = 0x00000007 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_9 = 0x00000009 +REG_ABS_MASK_CP_SET_BIN_DATA5_ABS_MASK = 0x00000001 +REG_ABS_MASK_CP_SET_BIN_DATA5_2 = 0x00000002 +ABS_MASK_CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_LO__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_LO__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_3 = 0x00000003 +ABS_MASK_CP_SET_BIN_DATA5_3_BIN_DATA_ADDR_HI__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_3_BIN_DATA_ADDR_HI__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_4 = 0x00000004 +ABS_MASK_CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_LO__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_5 = 0x00000005 +ABS_MASK_CP_SET_BIN_DATA5_5_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_5_BIN_SIZE_ADDRESS_HI__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_6 = 0x00000006 +ABS_MASK_CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_LO__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_LO__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_7 = 0x00000007 +ABS_MASK_CP_SET_BIN_DATA5_7_BIN_PRIM_STRM_HI__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_7_BIN_PRIM_STRM_HI__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_8 = 0x00000008 +REG_ABS_MASK_CP_SET_BIN_DATA5_10 = 0x0000000a +REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_MASK__MASK = 0x0000ffff +CP_SET_BIN_DATA5_OFFSET_0_VSC_MASK__SHIFT = 0 +CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 +CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 +CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 +CP_SET_BIN_DATA5_OFFSET_0_ABS_MASK__MASK = 0x10000000 +CP_SET_BIN_DATA5_OFFSET_0_ABS_MASK__SHIFT = 28 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 +REG_NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff +NO_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_ABS_MASK = 0x00000001 +REG_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2_BIN_DATA_OFFSET__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_2_BIN_DATA_OFFSET__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3_BIN_SIZE_OFFSET__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_3_BIN_SIZE_OFFSET__SHIFT = 0 +REG_ABS_MASK_CP_SET_BIN_DATA5_OFFSET_4 = 0x00000004 +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_4_BIN_DATA2_OFFSET__MASK = 0xffffffff +ABS_MASK_CP_SET_BIN_DATA5_OFFSET_4_BIN_DATA2_OFFSET__SHIFT = 0 +REG_CP_REG_RMW_0 = 0x00000000 +CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff +CP_REG_RMW_0_DST_REG__SHIFT = 0 +CP_REG_RMW_0_DST_SCRATCH = 0x00080000 +CP_REG_RMW_0_SKIP_WAIT_FOR_ME = 0x00800000 +CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 +CP_REG_RMW_0_ROTATE__SHIFT = 24 +CP_REG_RMW_0_SRC1_ADD = 0x20000000 +CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 +CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 +REG_CP_REG_RMW_1 = 0x00000001 +CP_REG_RMW_1_SRC0__MASK = 0xffffffff +CP_REG_RMW_1_SRC0__SHIFT = 0 +REG_CP_REG_RMW_2 = 0x00000002 +CP_REG_RMW_2_SRC1__MASK = 0xffffffff +CP_REG_RMW_2_SRC1__SHIFT = 0 +REG_CP_REG_TO_MEM_0 = 0x00000000 +CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_0_REG__SHIFT = 0 +CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_0_64B = 0x40000000 +CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_1 = 0x00000001 +CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_2 = 0x00000002 +CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 +CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 +CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 +CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 +CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 +REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 +CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff +CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 +CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 +CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 +CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 +CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 +REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 +CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 +CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 +CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 +REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 +CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff +CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 +REG_CP_MEM_TO_REG_0 = 0x00000000 +CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff +CP_MEM_TO_REG_0_REG__SHIFT = 0 +CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 +CP_MEM_TO_REG_0_CNT__SHIFT = 19 +CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 +CP_MEM_TO_REG_0_UNK31 = 0x80000000 +REG_CP_MEM_TO_REG_1 = 0x00000001 +CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff +CP_MEM_TO_REG_1_SRC__SHIFT = 0 +REG_CP_MEM_TO_REG_2 = 0x00000002 +CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff +CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 +REG_CP_MEM_TO_MEM_0 = 0x00000000 +CP_MEM_TO_MEM_0_NEG_A = 0x00000001 +CP_MEM_TO_MEM_0_NEG_B = 0x00000002 +CP_MEM_TO_MEM_0_NEG_C = 0x00000004 +CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 +CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 +CP_MEM_TO_MEM_0_UNK31 = 0x80000000 +REG_CP_MEMCPY_0 = 0x00000000 +CP_MEMCPY_0_DWORDS__MASK = 0xffffffff +CP_MEMCPY_0_DWORDS__SHIFT = 0 +REG_CP_MEMCPY_1 = 0x00000001 +CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff +CP_MEMCPY_1_SRC_LO__SHIFT = 0 +REG_CP_MEMCPY_2 = 0x00000002 +CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff +CP_MEMCPY_2_SRC_HI__SHIFT = 0 +REG_CP_MEMCPY_3 = 0x00000003 +CP_MEMCPY_3_DST_LO__MASK = 0xffffffff +CP_MEMCPY_3_DST_LO__SHIFT = 0 +REG_CP_MEMCPY_4 = 0x00000004 +CP_MEMCPY_4_DST_HI__MASK = 0xffffffff +CP_MEMCPY_4_DST_HI__SHIFT = 0 +REG_CP_REG_TO_SCRATCH_0 = 0x00000000 +CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff +CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 +CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 +CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 +CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 +CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 +CP_REG_TO_SCRATCH_0_SKIP_WAIT_FOR_ME = 0x08000000 +REG_CP_SCRATCH_TO_REG_0 = 0x00000000 +CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff +CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 +CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 +CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 +CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 +CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 +CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 +REG_CP_SCRATCH_WRITE_0 = 0x00000000 +CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 +CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 +REG_CP_MEM_WRITE_0 = 0x00000000 +CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff +CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 +REG_CP_MEM_WRITE_1 = 0x00000001 +CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff +CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE_0 = 0x00000000 +CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 +CP_COND_WRITE_0_FUNCTION__SHIFT = 0 +CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 +CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 +REG_CP_COND_WRITE_1 = 0x00000001 +CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff +CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 +REG_CP_COND_WRITE_2 = 0x00000002 +CP_COND_WRITE_2_REF__MASK = 0xffffffff +CP_COND_WRITE_2_REF__SHIFT = 0 +REG_CP_COND_WRITE_3 = 0x00000003 +CP_COND_WRITE_3_MASK__MASK = 0xffffffff +CP_COND_WRITE_3_MASK__SHIFT = 0 +REG_CP_COND_WRITE_4 = 0x00000004 +CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff +CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 +REG_CP_COND_WRITE_5 = 0x00000005 +CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff +CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 +REG_CP_COND_WRITE5_0 = 0x00000000 +CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 +CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 +CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 +CP_COND_WRITE5_0_POLL__MASK = 0x00000030 +CP_COND_WRITE5_0_POLL__SHIFT = 4 +CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 +REG_CP_COND_WRITE5_1 = 0x00000001 +CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_COND_WRITE5_2 = 0x00000002 +CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE5_3 = 0x00000003 +CP_COND_WRITE5_3_REF__MASK = 0xffffffff +CP_COND_WRITE5_3_REF__SHIFT = 0 +REG_CP_COND_WRITE5_4 = 0x00000004 +CP_COND_WRITE5_4_MASK__MASK = 0xffffffff +CP_COND_WRITE5_4_MASK__SHIFT = 0 +REG_CP_COND_WRITE5_5 = 0x00000005 +CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff +CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 +REG_CP_COND_WRITE5_6 = 0x00000006 +CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff +CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 +REG_CP_COND_WRITE5_7 = 0x00000007 +CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff +CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_0 = 0x00000000 +CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff +CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_1 = 0x00000001 +CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_2 = 0x00000002 +CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_WAIT_MEM_GTE_3 = 0x00000003 +CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff +CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 +REG_CP_WAIT_REG_MEM_0 = 0x00000000 +CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 +CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 +CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 +CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 +CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 +CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 +REG_CP_WAIT_REG_MEM_1 = 0x00000001 +CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff +CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 +REG_CP_WAIT_REG_MEM_2 = 0x00000002 +CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff +CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 +REG_CP_WAIT_REG_MEM_3 = 0x00000003 +CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff +CP_WAIT_REG_MEM_3_REF__SHIFT = 0 +REG_CP_WAIT_REG_MEM_4 = 0x00000004 +CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff +CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 +REG_CP_WAIT_REG_MEM_5 = 0x00000005 +CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff +CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_0 = 0x00000000 +CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff +CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_1 = 0x00000001 +CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff +CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 +REG_CP_WAIT_TWO_REGS_2 = 0x00000002 +CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff +CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 +REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 +CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 +CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 +REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 +CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff +CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 +REG_CP_SET_RENDER_MODE_0 = 0x00000000 +CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff +CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 +REG_CP_SET_RENDER_MODE_1 = 0x00000001 +CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff +CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 +REG_CP_SET_RENDER_MODE_2 = 0x00000002 +CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff +CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 +REG_CP_SET_RENDER_MODE_3 = 0x00000003 +CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 +CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 +REG_CP_SET_RENDER_MODE_4 = 0x00000004 +REG_CP_SET_RENDER_MODE_5 = 0x00000005 +CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff +CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 +REG_CP_SET_RENDER_MODE_6 = 0x00000006 +CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff +CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 +REG_CP_SET_RENDER_MODE_7 = 0x00000007 +CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff +CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 +CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 +CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 +REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 +REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 +CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 +CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 +CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff +CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 +REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 +REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 +REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 +CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff +CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 +REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 +CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff +CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 +REG_CP_EVENT_WRITE_0 = 0x00000000 +CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff +CP_EVENT_WRITE_0_EVENT__SHIFT = 0 +CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 +CP_EVENT_WRITE_0_IRQ = 0x80000000 +REG_CP_EVENT_WRITE_1 = 0x00000001 +CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff +CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 +REG_CP_EVENT_WRITE_2 = 0x00000002 +CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff +CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 +REG_CP_EVENT_WRITE_3 = 0x00000003 +REG_CP_EVENT_WRITE7_0 = 0x00000000 +CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff +CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 +CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 +CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 +CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 +CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 +CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 +CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 +CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 +CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 +CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 +CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 +CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 +CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 +CP_EVENT_WRITE7_0_IRQ = 0x80000000 +REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 +REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 +EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 +REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 +EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff +EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 +EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 +EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 +REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 +EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff +EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 +REG_CP_BLIT_0 = 0x00000000 +CP_BLIT_0_OP__MASK = 0x0000000f +CP_BLIT_0_OP__SHIFT = 0 +REG_CP_BLIT_1 = 0x00000001 +CP_BLIT_1_SRC_X1__MASK = 0x00003fff +CP_BLIT_1_SRC_X1__SHIFT = 0 +CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 +CP_BLIT_1_SRC_Y1__SHIFT = 16 +REG_CP_BLIT_2 = 0x00000002 +CP_BLIT_2_SRC_X2__MASK = 0x00003fff +CP_BLIT_2_SRC_X2__SHIFT = 0 +CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 +CP_BLIT_2_SRC_Y2__SHIFT = 16 +REG_CP_BLIT_3 = 0x00000003 +CP_BLIT_3_DST_X1__MASK = 0x00003fff +CP_BLIT_3_DST_X1__SHIFT = 0 +CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 +CP_BLIT_3_DST_Y1__SHIFT = 16 +REG_CP_BLIT_4 = 0x00000004 +CP_BLIT_4_DST_X2__MASK = 0x00003fff +CP_BLIT_4_DST_X2__SHIFT = 0 +CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 +CP_BLIT_4_DST_Y2__SHIFT = 16 +REG_CP_EXEC_CS_0 = 0x00000000 +REG_CP_EXEC_CS_1 = 0x00000001 +CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff +CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 +REG_CP_EXEC_CS_2 = 0x00000002 +CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff +CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 +REG_CP_EXEC_CS_3 = 0x00000003 +CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff +CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 +REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 +REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 +A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff +A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 +REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 +A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 +REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 +A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff +A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 +REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 +A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff +A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 +REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 +A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 +REG_A6XX_CP_SET_MARKER_0 = 0x00000000 +A6XX_CP_SET_MARKER_0_MARKER_MODE__MASK = 0x00000100 +A6XX_CP_SET_MARKER_0_MARKER_MODE__SHIFT = 8 +A6XX_CP_SET_MARKER_0_MODE__MASK = 0x0000000f +A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 +A6XX_CP_SET_MARKER_0_USES_GMEM = 0x00000010 +A6XX_CP_SET_MARKER_0_IFPC_MODE__MASK = 0x00000001 +A6XX_CP_SET_MARKER_0_IFPC_MODE__SHIFT = 0 +A6XX_CP_SET_MARKER_0_SHADER_USES_RT = 0x00000200 +A6XX_CP_SET_MARKER_0_RT_WA_START = 0x00000400 +A6XX_CP_SET_MARKER_0_RT_WA_END = 0x00000800 +REG_A6XX_CP_SET_PSEUDO_REG_ = lambda i0: (0x00000000 + 0x3*i0 ) +A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff +A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 +A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff +A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 +A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff +A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 +REG_A6XX_CP_REG_TEST_0 = 0x00000000 +A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff +A6XX_CP_REG_TEST_0_REG__SHIFT = 0 +A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff +A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 +A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 +A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 +A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 +A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 +A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 +A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 +A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 +A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 +REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 +REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 +REG_CP_COND_REG_EXEC_0 = 0x00000000 +CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff +CP_COND_REG_EXEC_0_REG0__SHIFT = 0 +CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 +CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 +CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 +CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 +CP_COND_REG_EXEC_0_BINNING = 0x02000000 +CP_COND_REG_EXEC_0_GMEM = 0x04000000 +CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 +CP_COND_REG_EXEC_0_BV = 0x02000000 +CP_COND_REG_EXEC_0_BR = 0x04000000 +CP_COND_REG_EXEC_0_LPAC = 0x08000000 +CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 +CP_COND_REG_EXEC_0_MODE__SHIFT = 28 +REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 +PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 +REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff +REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 +REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 +REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 +RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 +REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff +REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 +REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 +THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff +THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 +REG_CP_COND_REG_EXEC_2 = 0x00000002 +CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff +CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 +REG_CP_COND_EXEC_0 = 0x00000000 +CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff +CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 +REG_CP_COND_EXEC_1 = 0x00000001 +CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff +CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 +REG_CP_COND_EXEC_2 = 0x00000002 +CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff +CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 +REG_CP_COND_EXEC_3 = 0x00000003 +CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff +CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 +REG_CP_COND_EXEC_4 = 0x00000004 +CP_COND_EXEC_4_REF__MASK = 0xffffffff +CP_COND_EXEC_4_REF__SHIFT = 0 +REG_CP_COND_EXEC_5 = 0x00000005 +CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff +CP_COND_EXEC_5_DWORDS__SHIFT = 0 +REG_CP_SET_AMBLE_0 = 0x00000000 +CP_SET_AMBLE_0_ADDR_LO__MASK = 0xffffffff +CP_SET_AMBLE_0_ADDR_LO__SHIFT = 0 +REG_CP_SET_AMBLE_1 = 0x00000001 +CP_SET_AMBLE_1_ADDR_HI__MASK = 0xffffffff +CP_SET_AMBLE_1_ADDR_HI__SHIFT = 0 +REG_CP_SET_AMBLE_2 = 0x00000002 +CP_SET_AMBLE_2_DWORDS__MASK = 0x000fffff +CP_SET_AMBLE_2_DWORDS__SHIFT = 0 +CP_SET_AMBLE_2_TYPE__MASK = 0x00300000 +CP_SET_AMBLE_2_TYPE__SHIFT = 20 +REG_CP_REG_WRITE_0 = 0x00000000 +CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f +CP_REG_WRITE_0_TRACKER__SHIFT = 0 +REG_CP_REG_WRITE_1 = 0x00000001 +REG_CP_REG_WRITE_2 = 0x00000002 +REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 +CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 +REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 +CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff +CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 +CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 +CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 +REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 +CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 +REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 +CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff +CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 +REG_CP_START_BIN_BIN_COUNT = 0x00000000 +REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 +REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 +REG_CP_START_BIN_BODY_DWORDS = 0x00000004 +REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 +CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 +CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 +CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 +CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 +REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 +REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 +REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 +REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 +REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 +CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f +CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 +REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 +CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff +CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 +REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 +CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff +CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 +CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 +CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 +REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 +CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f +CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 +CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f +CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 +CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff +CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 +REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 +CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff +CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 +REG_CP_THREAD_CONTROL_0 = 0x00000000 +CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 +CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 +CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 +CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 +REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 +REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 +CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff +CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 +CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 +CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 +REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 +CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff +CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 +REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 +CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 +CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 +CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER = 0x00000004 +CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS = 0x00000008 +REG_CP_SCOPE_CNTL_0 = 0x00000000 +CP_SCOPE_CNTL_0_DISABLE_PREEMPTION = 0x00000001 +CP_SCOPE_CNTL_0_SCOPE__MASK = 0xf0000000 +CP_SCOPE_CNTL_0_SCOPE__SHIFT = 28 +REG_A5XX_CP_INDIRECT_BUFFER_IB_BASE = 0x00000000 +REG_A5XX_CP_INDIRECT_BUFFER_2 = 0x00000002 +A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE__MASK = 0x000fffff +A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE__SHIFT = 0 +__struct__cast = lambda X: (struct_X) +__struct__cast = lambda X: (struct_X) +REG_A6XX_TEX_SAMP_0 = 0x00000000 +A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 +A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 +A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 +A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 +A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 +A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 +A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 +A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 +A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 +A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 +A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 +A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 +A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 +A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 +A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 +REG_A6XX_TEX_SAMP_1 = 0x00000001 +A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 +A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e +A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 +A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 +A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 +A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 +A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 +A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 +A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 +A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 +REG_A6XX_TEX_SAMP_2 = 0x00000002 +A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 +A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 +A6XX_TEX_SAMP_2_FASTBORDERCOLOR__MASK = 0x0000000c +A6XX_TEX_SAMP_2_FASTBORDERCOLOR__SHIFT = 2 +A6XX_TEX_SAMP_2_FASTBORDERCOLOREN = 0x00000010 +A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 +A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 +A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 +REG_A6XX_TEX_SAMP_3 = 0x00000003 +REG_A6XX_TEX_CONST_0 = 0x00000000 +A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 +A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 +A6XX_TEX_CONST_0_SRGB = 0x00000004 +A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 +A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 +A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 +A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 +A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 +A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 +A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 +A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 +A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 +A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 +A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 +A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 +A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 +A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 +A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 +A6XX_TEX_CONST_0_FMT__SHIFT = 22 +A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 +A6XX_TEX_CONST_0_SWAP__SHIFT = 30 +REG_A6XX_TEX_CONST_1 = 0x00000001 +A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff +A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 +A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 +A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 +A6XX_TEX_CONST_1_MUTABLEEN = 0x80000000 +REG_A6XX_TEX_CONST_2 = 0x00000002 +A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 +A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 +A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 +A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 +A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f +A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 +A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 +A6XX_TEX_CONST_2_PITCH__SHIFT = 7 +A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 +A6XX_TEX_CONST_2_TYPE__SHIFT = 29 +REG_A6XX_TEX_CONST_3 = 0x00000003 +A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff +A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 +A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 +A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 +A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 +A6XX_TEX_CONST_3_FLAG = 0x10000000 +REG_A6XX_TEX_CONST_4 = 0x00000004 +A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 +A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 +REG_A6XX_TEX_CONST_5 = 0x00000005 +A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff +A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 +A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 +A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 +REG_A6XX_TEX_CONST_6 = 0x00000006 +A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff +A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 +A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 +A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 +REG_A6XX_TEX_CONST_7 = 0x00000007 +A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 +A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 +REG_A6XX_TEX_CONST_8 = 0x00000008 +A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff +A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 +REG_A6XX_TEX_CONST_9 = 0x00000009 +A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff +A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 +REG_A6XX_TEX_CONST_10 = 0x0000000a +A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f +A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 +A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 +REG_A6XX_TEX_CONST_11 = 0x0000000b +REG_A6XX_TEX_CONST_12 = 0x0000000c +REG_A6XX_TEX_CONST_13 = 0x0000000d +REG_A6XX_TEX_CONST_14 = 0x0000000e +REG_A6XX_TEX_CONST_15 = 0x0000000f +REG_A6XX_UBO_0 = 0x00000000 +A6XX_UBO_0_BASE_LO__MASK = 0xffffffff +A6XX_UBO_0_BASE_LO__SHIFT = 0 +REG_A6XX_UBO_1 = 0x00000001 +A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff +A6XX_UBO_1_BASE_HI__SHIFT = 0 +A6XX_UBO_1_SIZE__MASK = 0xfffe0000 +A6XX_UBO_1_SIZE__SHIFT = 17 lvp_nir_options = gzip.decompress(base64.b64decode("H4sIAAAAAAAAA2NgZGRkYGAAkYxgCsQFsxigwgwQBoxmhCqFq2WEKwIrAEGIkQxoAEMALwCqVsCiGUwLMHA0QPn29nBJkswHANb8YpH4AAAA")) \ No newline at end of file diff --git a/tinygrad/runtime/ops_qcom.py b/tinygrad/runtime/ops_qcom.py index f8feb4ed12..4b944d97a7 100644 --- a/tinygrad/runtime/ops_qcom.py +++ b/tinygrad/runtime/ops_qcom.py @@ -6,7 +6,7 @@ from typing import Any, cast from tinygrad.device import BufferSpec, CompilerSet, CompilerPair from tinygrad.runtime.support.hcq import HCQBuffer, HWQueue, HCQProgram, HCQCompiled, HCQAllocatorBase, HCQSignal, HCQArgsState, BumpAllocator from tinygrad.runtime.support.hcq import FileIOInterface, MMIOInterface -from tinygrad.runtime.autogen import kgsl, adreno +from tinygrad.runtime.autogen import kgsl, mesa from tinygrad.runtime.ops_cl import CLCompiler, CLDevice from tinygrad.renderer.cstyle import QCOMRenderer from tinygrad.helpers import getenv, mv_address, to_mv, round_up, data64_le, prod, fromimport, cpu_profile, lo32, PROFILE, suppress_finalizing @@ -20,9 +20,9 @@ BUFTYPE_BUF, BUFTYPE_TEX, BUFTYPE_IBO = 0, 1, 2 def _qreg_exec(__reg, __val=0, **kwargs): for k, v in kwargs.items(): reg_name = f"{__reg[4:]}_{k.removeprefix('_').upper()}" - __val |= (getattr(adreno, reg_name) if v else 0) if type(v) is bool else (v << getattr(adreno, f'{reg_name}__SHIFT')) + __val |= (getattr(mesa, reg_name) if v else 0) if type(v) is bool else (v << getattr(mesa, f'{reg_name}__SHIFT')) return __val -qreg: Any = type("QREG", (object,), {name[4:].lower(): functools.partial(_qreg_exec, name) for name in adreno.__dict__.keys() if name[:4] == 'REG_'}) +qreg: Any = type("QREG", (object,), {name[4:].lower(): functools.partial(_qreg_exec, name) for name in mesa.__dict__.keys() if name[:4] == 'REG_'}) def next_power2(x): return 1 if x == 0 else 1 << (x - 1).bit_length() @@ -30,9 +30,9 @@ def parity(val: int): for i in range(4,1,-1): val ^= val >> (1 << i) return (~0x6996 >> (val & 0xf)) & 1 -def pkt7_hdr(opcode: int, cnt: int): return adreno.CP_TYPE7_PKT | cnt & 0x3FFF | parity(cnt) << 15 | (opcode & 0x7F) << 16 | parity(opcode) << 23 +def pkt7_hdr(opcode: int, cnt: int): return mesa.CP_TYPE7_PKT | cnt & 0x3FFF | parity(cnt) << 15 | (opcode & 0x7F) << 16 | parity(opcode) << 23 -def pkt4_hdr(reg: int, cnt: int): return adreno.CP_TYPE4_PKT | cnt & 0x7F | parity(cnt) << 7 | (reg & 0x3FFFF) << 8 | parity(reg) << 27 +def pkt4_hdr(reg: int, cnt: int): return mesa.CP_TYPE4_PKT | cnt & 0x7F | parity(cnt) << 7 | (reg & 0x3FFFF) << 8 | parity(reg) << 27 class QCOMCompiler(CLCompiler): def __init__(self, device:str=""): super().__init__(CLDevice(device), 'compile_qcom') @@ -61,19 +61,19 @@ class QCOMComputeQueue(HWQueue): def _cache_flush(self, write_back=True, invalidate=False, sync=True, memsync=False): # TODO: 7xx support. - if write_back: self.cmd(adreno.CP_EVENT_WRITE, adreno.CACHE_FLUSH_TS, *data64_le(self.dev.dummy_addr), 0) # dirty cache write-back. - if invalidate: self.cmd(adreno.CP_EVENT_WRITE, adreno.CACHE_INVALIDATE) # invalidate cache lines (following reads from RAM). - if memsync: self.cmd(adreno.CP_WAIT_MEM_WRITES) - if sync: self.cmd(adreno.CP_WAIT_FOR_IDLE) + if write_back: self.cmd(mesa.CP_EVENT_WRITE, mesa.CACHE_FLUSH_TS, *data64_le(self.dev.dummy_addr), 0) # dirty cache write-back. + if invalidate: self.cmd(mesa.CP_EVENT_WRITE, mesa.CACHE_INVALIDATE) # invalidate cache lines (following reads from RAM). + if memsync: self.cmd(mesa.CP_WAIT_MEM_WRITES) + if sync: self.cmd(mesa.CP_WAIT_FOR_IDLE) def memory_barrier(self): self._cache_flush(write_back=True, invalidate=True, sync=True, memsync=True) return self def signal(self, signal:QCOMSignal, value=0): - self.cmd(adreno.CP_WAIT_FOR_IDLE) + self.cmd(mesa.CP_WAIT_FOR_IDLE) if self.dev.gpu_id[:2] < (7, 3): - self.cmd(adreno.CP_EVENT_WRITE, qreg.cp_event_write_0(event=adreno.CACHE_FLUSH_TS), *data64_le(signal.value_addr), lo32(value)) + self.cmd(mesa.CP_EVENT_WRITE, qreg.cp_event_write_0(event=mesa.CACHE_FLUSH_TS), *data64_le(signal.value_addr), lo32(value)) self._cache_flush(write_back=True, invalidate=False, sync=False, memsync=False) else: # TODO: support devices starting with 8 Gen 1. Also, 700th series have convenient CP_GLOBAL_TIMESTAMP and CP_LOCAL_TIMESTAMP @@ -81,12 +81,12 @@ class QCOMComputeQueue(HWQueue): return self def timestamp(self, signal:QCOMSignal): - self.cmd(adreno.CP_WAIT_FOR_IDLE) - self.cmd(adreno.CP_REG_TO_MEM, qreg.cp_reg_to_mem_0(reg=adreno.REG_A6XX_CP_ALWAYS_ON_COUNTER, cnt=2, _64b=True),*data64_le(signal.timestamp_addr)) + self.cmd(mesa.CP_WAIT_FOR_IDLE) + self.cmd(mesa.CP_REG_TO_MEM, qreg.cp_reg_to_mem_0(reg=mesa.REG_A6XX_CP_ALWAYS_ON_COUNTER, cnt=2, _64b=True),*data64_le(signal.timestamp_addr)) return self def wait(self, signal:QCOMSignal, value=0): - self.cmd(adreno.CP_WAIT_REG_MEM, qreg.cp_wait_reg_mem_0(function=adreno.WRITE_GE, poll=adreno.POLL_MEMORY),*data64_le(signal.value_addr), + self.cmd(mesa.CP_WAIT_REG_MEM, qreg.cp_wait_reg_mem_0(function=mesa.WRITE_GE, poll=mesa.POLL_MEMORY),*data64_le(signal.value_addr), qreg.cp_wait_reg_mem_3(ref=value&0xFFFFFFFF), qreg.cp_wait_reg_mem_4(mask=0xFFFFFFFF), qreg.cp_wait_reg_mem_5(delay_loop_cycles=32)) return self @@ -115,62 +115,63 @@ class QCOMComputeQueue(HWQueue): def cast_int(x, ceil=False): return (math.ceil(x) if ceil else int(x)) if isinstance(x, float) else x global_size_mp = [cast_int(g*l) for g,l in zip(global_size, local_size)] - self.cmd(adreno.CP_SET_MARKER, qreg.a6xx_cp_set_marker_0(mode=adreno.RM6_COMPUTE)) - self.reg(adreno.REG_A6XX_HLSQ_INVALIDATE_CMD, qreg.a6xx_hlsq_invalidate_cmd(cs_state=True, cs_ibo=True)) - self.reg(adreno.REG_A6XX_HLSQ_INVALIDATE_CMD, 0x0) - self.reg(adreno.REG_A6XX_SP_CS_TEX_COUNT, qreg.a6xx_sp_cs_tex_count(0x80)) - self.reg(adreno.REG_A6XX_SP_CS_IBO_COUNT, qreg.a6xx_sp_cs_ibo_count(0x40)) - self.reg(adreno.REG_A6XX_SP_MODE_CONTROL, qreg.a6xx_sp_mode_control(isammode=adreno.ISAMMODE_CL)) - self.reg(adreno.REG_A6XX_SP_PERFCTR_ENABLE, qreg.a6xx_sp_perfctr_enable(cs=True)) - self.reg(adreno.REG_A6XX_SP_TP_MODE_CNTL, qreg.a6xx_sp_tp_mode_cntl(isammode=adreno.ISAMMODE_CL, unk3=2)) - self.reg(adreno.REG_A6XX_TPL1_DBG_ECO_CNTL, 0) - self.cmd(adreno.CP_WAIT_FOR_IDLE) + self.cmd(mesa.CP_SET_MARKER, qreg.a6xx_cp_set_marker_0(mode=mesa.RM6_COMPUTE)) + self.reg(mesa.REG_A6XX_SP_UPDATE_CNTL, qreg.a6xx_sp_update_cntl(cs_state=True, cs_uav=True)) + self.reg(mesa.REG_A6XX_SP_UPDATE_CNTL, 0x0) + self.reg(mesa.REG_A6XX_SP_CS_TSIZE, qreg.a6xx_sp_cs_tsize(0x80)) # is this right? mesa uses 1 + self.reg(mesa.REG_A6XX_SP_CS_USIZE, qreg.a6xx_sp_cs_usize(0x40)) # mesa also uses 1 + self.reg(mesa.REG_A6XX_SP_MODE_CNTL, qreg.a6xx_sp_mode_cntl(isammode=mesa.ISAMMODE_CL)) + self.reg(mesa.REG_A6XX_SP_PERFCTR_SHADER_MASK, qreg.a6xx_sp_perfctr_shader_mask(cs=True)) + self.reg(mesa.REG_A6XX_TPL1_MODE_CNTL, qreg.a6xx_tpl1_mode_cntl(isammode=mesa.ISAMMODE_CL)) + self.reg(mesa.REG_A6XX_TPL1_DBG_ECO_CNTL, 0) + self.cmd(mesa.CP_WAIT_FOR_IDLE) - self.reg(adreno.REG_A6XX_HLSQ_CS_NDRANGE_0, - qreg.a6xx_hlsq_cs_ndrange_0(kerneldim=3, localsizex=local_size[0] - 1, localsizey=local_size[1] - 1, localsizez=local_size[2] - 1), - global_size_mp[0], 0, global_size_mp[1], 0, global_size_mp[2], 0, 0xccc0cf, 0xfc | qreg.a6xx_hlsq_cs_cntl_1(threadsize=adreno.THREAD64), + self.reg(mesa.REG_A6XX_SP_CS_NDRANGE_0, + qreg.a6xx_sp_cs_ndrange_0(kerneldim=3, localsizex=local_size[0] - 1, localsizey=local_size[1] - 1, localsizez=local_size[2] - 1), + global_size_mp[0], 0, global_size_mp[1], 0, global_size_mp[2], 0, 0xccc0cf, 0xfc | qreg.a6xx_sp_cs_wge_cntl(threadsize=mesa.THREAD64), cast_int(global_size[0], ceil=True), cast_int(global_size[1], ceil=True), cast_int(global_size[2], ceil=True)) - self.reg(adreno.REG_A6XX_SP_CS_CTRL_REG0, - qreg.a6xx_sp_cs_ctrl_reg0(threadsize=adreno.THREAD64, halfregfootprint=prg.hregs, fullregfootprint=prg.fregs, branchstack=prg.brnchstck), - qreg.a6xx_sp_cs_unknown_a9b1(unk6=True, shared_size=prg.shared_size), 0, prg.prg_offset, *data64_le(prg.lib_gpu.va_addr), + self.reg(mesa.REG_A6XX_SP_CS_CNTL_0, + qreg.a6xx_sp_cs_cntl_0(threadsize=mesa.THREAD64, halfregfootprint=prg.hregs, fullregfootprint=prg.fregs, branchstack=prg.brnchstck), + qreg.a6xx_sp_cs_cntl_1(constantrammode=mesa.CONSTLEN_256, shared_size=prg.shared_size), # should this be CONSTLEN_512? + 0, prg.prg_offset, *data64_le(prg.lib_gpu.va_addr), qreg.a6xx_sp_cs_pvt_mem_param(memsizeperitem=prg.pvtmem_size_per_item), *data64_le(prg.dev._stack.va_addr), qreg.a6xx_sp_cs_pvt_mem_size(totalpvtmemsize=prg.pvtmem_size_total)) - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_CONSTANTS, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=1024 // 4), + self.cmd(mesa.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=mesa.ST_CONSTANTS, state_src=mesa.SS6_INDIRECT, + state_block=mesa.SB6_CS_SHADER, num_unit=1024 // 4), *data64_le(args_state.buf.va_addr)) - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_SHADER, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=round_up(prg.image_size, 128) // 128), + self.cmd(mesa.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=mesa.ST_SHADER, state_src=mesa.SS6_INDIRECT, + state_block=mesa.SB6_CS_SHADER, num_unit=round_up(prg.image_size, 128) // 128), *data64_le(prg.lib_gpu.va_addr)) - self.reg(adreno.REG_A6XX_HLSQ_CONTROL_2_REG, 0xfcfcfcfc, 0xfcfcfcfc, 0xfcfcfcfc, 0xfc, qreg.a6xx_hlsq_cs_cntl(constlen=1024 // 4, enabled=True)) + self.reg(mesa.REG_A6XX_SP_REG_PROG_ID_0, 0xfcfcfcfc, 0xfcfcfcfc, 0xfcfcfcfc, 0xfc, qreg.a6xx_sp_cs_const_config(constlen=1024 // 4, enabled=True)) - self.reg(adreno.REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET, qreg.a6xx_sp_cs_pvt_mem_hw_stack_offset(prg.hw_stack_offset)) - self.reg(adreno.REG_A6XX_SP_CS_INSTRLEN, qreg.a6xx_sp_cs_instrlen(prg.image_size // 4)) + self.reg(mesa.REG_A6XX_SP_CS_PVT_MEM_STACK_OFFSET, qreg.a6xx_sp_cs_pvt_mem_stack_offset(prg.hw_stack_offset)) + self.reg(mesa.REG_A6XX_SP_CS_INSTR_SIZE, qreg.a6xx_sp_cs_instr_size(prg.image_size // 4)) if args_state.prg.samp_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_SHADER, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_TEX, num_unit=args_state.prg.samp_cnt), + self.cmd(mesa.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=mesa.ST_SHADER, state_src=mesa.SS6_INDIRECT, + state_block=mesa.SB6_CS_TEX, num_unit=args_state.prg.samp_cnt), *data64_le(args_state.buf.va_addr + args_state.prg.samp_off)) - self.reg(adreno.REG_A6XX_SP_CS_TEX_SAMP, *data64_le(args_state.buf.va_addr + args_state.prg.samp_off)) - self.reg(adreno.REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, *data64_le(prg.dev.border_color_buf.va_addr)) + self.reg(mesa.REG_A6XX_SP_CS_SAMPLER_BASE, *data64_le(args_state.buf.va_addr + args_state.prg.samp_off)) + self.reg(mesa.REG_A6XX_TPL1_CS_BORDER_COLOR_BASE, *data64_le(prg.dev.border_color_buf.va_addr)) if args_state.prg.tex_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST_CONSTANTS, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_TEX, num_unit=min(16, args_state.prg.tex_cnt)), + self.cmd(mesa.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=mesa.ST_CONSTANTS, state_src=mesa.SS6_INDIRECT, + state_block=mesa.SB6_CS_TEX, num_unit=min(16, args_state.prg.tex_cnt)), *data64_le(args_state.buf.va_addr + args_state.prg.tex_off)) - self.reg(adreno.REG_A6XX_SP_CS_TEX_CONST, *data64_le(args_state.buf.va_addr + args_state.prg.tex_off)) + self.reg(mesa.REG_A6XX_SP_CS_TEXMEMOBJ_BASE, *data64_le(args_state.buf.va_addr + args_state.prg.tex_off)) if args_state.prg.ibo_cnt > 0: - self.cmd(adreno.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=adreno.ST6_IBO, state_src=adreno.SS6_INDIRECT, - state_block=adreno.SB6_CS_SHADER, num_unit=args_state.prg.ibo_cnt), + self.cmd(mesa.CP_LOAD_STATE6_FRAG, qreg.cp_load_state6_0(state_type=mesa.ST6_UAV, state_src=mesa.SS6_INDIRECT, + state_block=mesa.SB6_CS_SHADER, num_unit=args_state.prg.ibo_cnt), *data64_le(args_state.buf.va_addr + args_state.prg.ibo_off)) - self.reg(adreno.REG_A6XX_SP_CS_IBO, *data64_le(args_state.buf.va_addr + args_state.prg.ibo_off)) + self.reg(mesa.REG_A6XX_SP_CS_UAV_BASE, *data64_le(args_state.buf.va_addr + args_state.prg.ibo_off)) - self.reg(adreno.REG_A6XX_SP_CS_CONFIG, - qreg.a6xx_sp_cs_config(enabled=True, nsamp=args_state.prg.samp_cnt, ntex=args_state.prg.tex_cnt, nibo=args_state.prg.ibo_cnt)) - self.cmd(adreno.CP_RUN_OPENCL, 0) + self.reg(mesa.REG_A6XX_SP_CS_CONFIG, + qreg.a6xx_sp_cs_config(enabled=True, nsamp=args_state.prg.samp_cnt, ntex=args_state.prg.tex_cnt, nuav=args_state.prg.ibo_cnt)) + self.cmd(mesa.CP_RUN_OPENCL, 0) self._cache_flush(write_back=True, invalidate=False, sync=False, memsync=False) return self @@ -240,7 +241,7 @@ class QCOMProgram(HCQProgram): assert self.samp_cnt <= 1, "Up to one sampler supported" if self.samp_cnt: self.samp_cnt += 1 - self.samplers = [qreg.a6xx_tex_samp_0(wrap_s=(clamp_mode:=adreno.A6XX_TEX_CLAMP_TO_BORDER), wrap_t=clamp_mode, wrap_r=clamp_mode), + self.samplers = [qreg.a6xx_tex_samp_0(wrap_s=(clamp_mode:=mesa.A6XX_TEX_CLAMP_TO_BORDER), wrap_t=clamp_mode, wrap_r=clamp_mode), qreg.a6xx_tex_samp_1(unnorm_coords=True, cubemapseamlessfiltoff=True), 0, 0, 0, 0, 0, 0] # Collect kernel arguments (buffers) info. @@ -290,9 +291,9 @@ class QCOMAllocator(HCQAllocatorBase): buf = self.dev._gpu_map(options.external_ptr, size) if options.external_ptr else self.dev._gpu_alloc(size) if options.image is not None: - tex_fmt = adreno.FMT6_32_32_32_32_FLOAT if options.image.itemsize == 4 else adreno.FMT6_16_16_16_16_FLOAT + tex_fmt = mesa.FMT6_32_32_32_32_FLOAT if options.image.itemsize == 4 else mesa.FMT6_16_16_16_16_FLOAT desc = [qreg.a6xx_tex_const_0(0x8, swiz_x=0, swiz_y=1, swiz_z=2, swiz_w=3, fmt=tex_fmt), qreg.a6xx_tex_const_1(width=imgw, height=imgh), - qreg.a6xx_tex_const_2(type=adreno.A6XX_TEX_2D, pitch=pitch, pitchalign=pitchalign-6), 0, + qreg.a6xx_tex_const_2(type=mesa.A6XX_TEX_2D, pitch=pitch, pitchalign=pitchalign-6), 0, *data64_le(buf.va_addr), qreg.a6xx_tex_const_6(plane_pitch=0x400000), qreg.a6xx_tex_const_7(13)] buf.texture_info = QCOMTextureInfo(pitch, real_stride, desc, [desc[0] & (~0xffff), *desc[1:len(desc)]])