diff --git a/autogen_stubs.sh b/autogen_stubs.sh index 356b6687a4..50e56b448c 100755 --- a/autogen_stubs.sh +++ b/autogen_stubs.sh @@ -331,6 +331,12 @@ generate_am() { -o $BASE/am/mmhub_3_0_0.py fixup $BASE/am/mmhub_3_0_0.py + clang2py -k cdefstum \ + extra/amdpci/headers/mmhub_3_0_2_offset.h \ + extra/amdpci/headers/mmhub_3_0_2_sh_mask.h \ + -o $BASE/am/mmhub_3_0_2.py + fixup $BASE/am/mmhub_3_0_2.py + clang2py -k cdefstum \ extra/amdpci/headers/nbio_4_3_0_offset.h \ extra/amdpci/headers/nbio_4_3_0_sh_mask.h \ diff --git a/extra/amdpci/headers/mmhub_3_0_2_offset.h b/extra/amdpci/headers/mmhub_3_0_2_offset.h new file mode 100644 index 0000000000..13a881e53d --- /dev/null +++ b/extra/amdpci/headers/mmhub_3_0_2_offset.h @@ -0,0 +1,1425 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_2_OFFSET_HEADER +#define _mmhub_3_0_2_OFFSET_HEADER + + + +// addressBlock: mmhub_dagbdec +// base address: 0x68000 +#define regDAGB0_RDCLI0 0x0000 +#define regDAGB0_RDCLI0_BASE_IDX 0 +#define regDAGB0_RDCLI1 0x0001 +#define regDAGB0_RDCLI1_BASE_IDX 0 +#define regDAGB0_RDCLI2 0x0002 +#define regDAGB0_RDCLI2_BASE_IDX 0 +#define regDAGB0_RDCLI3 0x0003 +#define regDAGB0_RDCLI3_BASE_IDX 0 +#define regDAGB0_RDCLI4 0x0004 +#define regDAGB0_RDCLI4_BASE_IDX 0 +#define regDAGB0_RDCLI5 0x0005 +#define regDAGB0_RDCLI5_BASE_IDX 0 +#define regDAGB0_RDCLI6 0x0006 +#define regDAGB0_RDCLI6_BASE_IDX 0 +#define regDAGB0_RDCLI7 0x0007 +#define regDAGB0_RDCLI7_BASE_IDX 0 +#define regDAGB0_RDCLI8 0x0008 +#define regDAGB0_RDCLI8_BASE_IDX 0 +#define regDAGB0_RDCLI9 0x0009 +#define regDAGB0_RDCLI9_BASE_IDX 0 +#define regDAGB0_RDCLI10 0x000a +#define regDAGB0_RDCLI10_BASE_IDX 0 +#define regDAGB0_RDCLI11 0x000b +#define regDAGB0_RDCLI11_BASE_IDX 0 +#define regDAGB0_RDCLI12 0x000c +#define regDAGB0_RDCLI12_BASE_IDX 0 +#define regDAGB0_RDCLI13 0x000d +#define regDAGB0_RDCLI13_BASE_IDX 0 +#define regDAGB0_RDCLI14 0x000e +#define regDAGB0_RDCLI14_BASE_IDX 0 +#define regDAGB0_RDCLI15 0x000f +#define regDAGB0_RDCLI15_BASE_IDX 0 +#define regDAGB0_RDCLI16 0x0010 +#define regDAGB0_RDCLI16_BASE_IDX 0 +#define regDAGB0_RDCLI17 0x0011 +#define regDAGB0_RDCLI17_BASE_IDX 0 +#define regDAGB0_RDCLI18 0x0012 +#define regDAGB0_RDCLI18_BASE_IDX 0 +#define regDAGB0_RDCLI19 0x0013 +#define regDAGB0_RDCLI19_BASE_IDX 0 +#define regDAGB0_RDCLI20 0x0014 +#define regDAGB0_RDCLI20_BASE_IDX 0 +#define regDAGB0_RDCLI21 0x0015 +#define regDAGB0_RDCLI21_BASE_IDX 0 +#define regDAGB0_RDCLI22 0x0016 +#define regDAGB0_RDCLI22_BASE_IDX 0 +#define regDAGB0_RDCLI23 0x0017 +#define regDAGB0_RDCLI23_BASE_IDX 0 +#define regDAGB0_RD_CNTL 0x0018 +#define regDAGB0_RD_CNTL_BASE_IDX 0 +#define regDAGB0_RD_IO_CNTL 0x0019 +#define regDAGB0_RD_IO_CNTL_BASE_IDX 0 +#define regDAGB0_RD_GMI_CNTL 0x001a +#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB 0x001b +#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_RD_CGTT_CLK_CTRL 0x001c +#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001d +#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001e +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001f +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0020 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0021 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0022 +#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0023 +#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_RD_VC0_CNTL 0x0024 +#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC1_CNTL 0x0025 +#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC2_CNTL 0x0026 +#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC3_CNTL 0x0027 +#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC4_CNTL 0x0028 +#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_RD_VC5_CNTL 0x0029 +#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_RD_IO_VC_CNTL 0x002a +#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB0_RD_GMI_VC_CNTL 0x002b +#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB0_RD_CNTL_MISC 0x002c +#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_RD_TLB_CREDIT 0x002d +#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x002e +#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x002f +#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK_PENDING 0x0030 +#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GO_PENDING 0x0031 +#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0032 +#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_TLB_PENDING 0x0033 +#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OARB_PENDING 0x0034 +#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x0035 +#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK2DF_PENDING 0x0036 +#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_OSD_PENDING 0x0037 +#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x0038 +#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE 0x0039 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 0x003a +#define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_WRCLI0 0x003b +#define regDAGB0_WRCLI0_BASE_IDX 0 +#define regDAGB0_WRCLI1 0x003c +#define regDAGB0_WRCLI1_BASE_IDX 0 +#define regDAGB0_WRCLI2 0x003d +#define regDAGB0_WRCLI2_BASE_IDX 0 +#define regDAGB0_WRCLI3 0x003e +#define regDAGB0_WRCLI3_BASE_IDX 0 +#define regDAGB0_WRCLI4 0x003f +#define regDAGB0_WRCLI4_BASE_IDX 0 +#define regDAGB0_WRCLI5 0x0040 +#define regDAGB0_WRCLI5_BASE_IDX 0 +#define regDAGB0_WRCLI6 0x0041 +#define regDAGB0_WRCLI6_BASE_IDX 0 +#define regDAGB0_WRCLI7 0x0042 +#define regDAGB0_WRCLI7_BASE_IDX 0 +#define regDAGB0_WRCLI8 0x0043 +#define regDAGB0_WRCLI8_BASE_IDX 0 +#define regDAGB0_WRCLI9 0x0044 +#define regDAGB0_WRCLI9_BASE_IDX 0 +#define regDAGB0_WRCLI10 0x0045 +#define regDAGB0_WRCLI10_BASE_IDX 0 +#define regDAGB0_WRCLI11 0x0046 +#define regDAGB0_WRCLI11_BASE_IDX 0 +#define regDAGB0_WRCLI12 0x0047 +#define regDAGB0_WRCLI12_BASE_IDX 0 +#define regDAGB0_WRCLI13 0x0048 +#define regDAGB0_WRCLI13_BASE_IDX 0 +#define regDAGB0_WRCLI14 0x0049 +#define regDAGB0_WRCLI14_BASE_IDX 0 +#define regDAGB0_WRCLI15 0x004a +#define regDAGB0_WRCLI15_BASE_IDX 0 +#define regDAGB0_WRCLI16 0x004b +#define regDAGB0_WRCLI16_BASE_IDX 0 +#define regDAGB0_WRCLI17 0x004c +#define regDAGB0_WRCLI17_BASE_IDX 0 +#define regDAGB0_WRCLI18 0x004d +#define regDAGB0_WRCLI18_BASE_IDX 0 +#define regDAGB0_WRCLI19 0x004e +#define regDAGB0_WRCLI19_BASE_IDX 0 +#define regDAGB0_WRCLI20 0x004f +#define regDAGB0_WRCLI20_BASE_IDX 0 +#define regDAGB0_WRCLI21 0x0050 +#define regDAGB0_WRCLI21_BASE_IDX 0 +#define regDAGB0_WRCLI22 0x0051 +#define regDAGB0_WRCLI22_BASE_IDX 0 +#define regDAGB0_WRCLI23 0x0052 +#define regDAGB0_WRCLI23_BASE_IDX 0 +#define regDAGB0_WR_CNTL 0x0053 +#define regDAGB0_WR_CNTL_BASE_IDX 0 +#define regDAGB0_WR_IO_CNTL 0x0054 +#define regDAGB0_WR_IO_CNTL_BASE_IDX 0 +#define regDAGB0_WR_GMI_CNTL 0x0055 +#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB 0x0056 +#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 +#define regDAGB0_WR_CGTT_CLK_CTRL 0x0057 +#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0058 +#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0059 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x005a +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x005b +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x005c +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x005d +#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x005e +#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB 0x005f +#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0060 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0061 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0062 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0063 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0064 +#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0065 +#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB0_WR_VC0_CNTL 0x0066 +#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC1_CNTL 0x0067 +#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC2_CNTL 0x0068 +#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC3_CNTL 0x0069 +#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC4_CNTL 0x006a +#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 +#define regDAGB0_WR_VC5_CNTL 0x006b +#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 +#define regDAGB0_WR_IO_VC_CNTL 0x006c +#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB0_WR_GMI_VC_CNTL 0x006d +#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB0_WR_CNTL_MISC 0x006e +#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_WR_TLB_CREDIT 0x006f +#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_DATA_CREDIT 0x0070 +#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_MISC_CREDIT 0x0071 +#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0072 +#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0073 +#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK_PENDING 0x0074 +#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GO_PENDING 0x0075 +#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0076 +#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_TLB_PENDING 0x0077 +#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OARB_PENDING 0x0078 +#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0079 +#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK2DF_PENDING 0x007a +#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_OSD_PENDING 0x007b +#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x007c +#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x007d +#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x007e +#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x007f +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0080 +#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE 0x0081 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 0x0082 +#define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB0_DAGB_DLY 0x0083 +#define regDAGB0_DAGB_DLY_BASE_IDX 0 +#define regDAGB0_CNTL_MISC 0x0084 +#define regDAGB0_CNTL_MISC_BASE_IDX 0 +#define regDAGB0_CNTL_MISC2 0x0085 +#define regDAGB0_CNTL_MISC2_BASE_IDX 0 +#define regDAGB0_FIFO_EMPTY 0x0086 +#define regDAGB0_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB0_FIFO_FULL 0x0087 +#define regDAGB0_FIFO_FULL_BASE_IDX 0 +#define regDAGB0_RD_CREDITS_FULL 0x0088 +#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_WR_CREDITS_FULL 0x0089 +#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_LO 0x008a +#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_HI 0x008b +#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER0_CFG 0x008c +#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER1_CFG 0x008d +#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER2_CFG 0x008e +#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x008f +#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB0_L1TLB_REG_RW 0x0090 +#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB0_RESERVE1 0x0091 +#define regDAGB0_RESERVE1_BASE_IDX 0 +#define regDAGB0_RESERVE2 0x0092 +#define regDAGB0_RESERVE2_BASE_IDX 0 +#define regDAGB0_RESERVE3 0x0093 +#define regDAGB0_RESERVE3_BASE_IDX 0 +#define regDAGB0_RESERVE4 0x0094 +#define regDAGB0_RESERVE4_BASE_IDX 0 +#define regDAGB0_SDP_RD_BW_CNTL 0x0095 +#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 0 +#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x0096 +#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 +#define regDAGB0_SDP_RD_PRIORITY 0x0097 +#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 0 +#define regDAGB0_SDP_WR_PRIORITY 0x0098 +#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 0 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x0099 +#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x009a +#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB0_SDP_ENABLE 0x009b +#define regDAGB0_SDP_ENABLE_BASE_IDX 0 +#define regDAGB0_SDP_CREDITS 0x009c +#define regDAGB0_SDP_CREDITS_BASE_IDX 0 +#define regDAGB0_SDP_TAG_RESERVE0 0x009d +#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_TAG_RESERVE1 0x009e +#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_VCC_RESERVE0 0x009f +#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_VCC_RESERVE1 0x00a0 +#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_ERR_STATUS 0x00a1 +#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 0 +#define regDAGB0_SDP_REQ_CNTL 0x00a2 +#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 0 +#define regDAGB0_SDP_MISC_AON 0x00a3 +#define regDAGB0_SDP_MISC_AON_BASE_IDX 0 +#define regDAGB0_SDP_MISC 0x00a4 +#define regDAGB0_SDP_MISC_BASE_IDX 0 +#define regDAGB0_SDP_MISC2 0x00a5 +#define regDAGB0_SDP_MISC2_BASE_IDX 0 +#define regDAGB0_SDP_VCD_RESERVE0 0x00a7 +#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regDAGB0_SDP_VCD_RESERVE1 0x00a8 +#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regDAGB0_SDP_ARB_CNTL0 0x00a9 +#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 0 +#define regDAGB0_SDP_ARB_CNTL1 0x00aa +#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CNTL 0x00ab +#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_CLEAR 0x00ac +#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS0 0x00ad +#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS1 0x00ae +#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS2 0x00af +#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS3 0x00b0 +#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 +#define regDAGB0_FATAL_ERROR_STATUS4 0x00b1 +#define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 0 +#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00b6 +#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB0_SDP_LATENCY_SAMPLING 0x00b7 +#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 0 +#define regDAGB1_RDCLI0 0x00b8 +#define regDAGB1_RDCLI0_BASE_IDX 0 +#define regDAGB1_RDCLI1 0x00b9 +#define regDAGB1_RDCLI1_BASE_IDX 0 +#define regDAGB1_RDCLI2 0x00ba +#define regDAGB1_RDCLI2_BASE_IDX 0 +#define regDAGB1_RDCLI3 0x00bb +#define regDAGB1_RDCLI3_BASE_IDX 0 +#define regDAGB1_RDCLI4 0x00bc +#define regDAGB1_RDCLI4_BASE_IDX 0 +#define regDAGB1_RDCLI5 0x00bd +#define regDAGB1_RDCLI5_BASE_IDX 0 +#define regDAGB1_RDCLI6 0x00be +#define regDAGB1_RDCLI6_BASE_IDX 0 +#define regDAGB1_RDCLI7 0x00bf +#define regDAGB1_RDCLI7_BASE_IDX 0 +#define regDAGB1_RDCLI8 0x00c0 +#define regDAGB1_RDCLI8_BASE_IDX 0 +#define regDAGB1_RDCLI9 0x00c1 +#define regDAGB1_RDCLI9_BASE_IDX 0 +#define regDAGB1_RDCLI10 0x00c2 +#define regDAGB1_RDCLI10_BASE_IDX 0 +#define regDAGB1_RDCLI11 0x00c3 +#define regDAGB1_RDCLI11_BASE_IDX 0 +#define regDAGB1_RDCLI12 0x00c4 +#define regDAGB1_RDCLI12_BASE_IDX 0 +#define regDAGB1_RDCLI13 0x00c5 +#define regDAGB1_RDCLI13_BASE_IDX 0 +#define regDAGB1_RDCLI14 0x00c6 +#define regDAGB1_RDCLI14_BASE_IDX 0 +#define regDAGB1_RDCLI15 0x00c7 +#define regDAGB1_RDCLI15_BASE_IDX 0 +#define regDAGB1_RDCLI16 0x00c8 +#define regDAGB1_RDCLI16_BASE_IDX 0 +#define regDAGB1_RDCLI17 0x00c9 +#define regDAGB1_RDCLI17_BASE_IDX 0 +#define regDAGB1_RDCLI18 0x00ca +#define regDAGB1_RDCLI18_BASE_IDX 0 +#define regDAGB1_RDCLI19 0x00cb +#define regDAGB1_RDCLI19_BASE_IDX 0 +#define regDAGB1_RDCLI20 0x00cc +#define regDAGB1_RDCLI20_BASE_IDX 0 +#define regDAGB1_RDCLI21 0x00cd +#define regDAGB1_RDCLI21_BASE_IDX 0 +#define regDAGB1_RDCLI22 0x00ce +#define regDAGB1_RDCLI22_BASE_IDX 0 +#define regDAGB1_RDCLI23 0x00cf +#define regDAGB1_RDCLI23_BASE_IDX 0 +#define regDAGB1_RD_CNTL 0x00d0 +#define regDAGB1_RD_CNTL_BASE_IDX 0 +#define regDAGB1_RD_IO_CNTL 0x00d1 +#define regDAGB1_RD_IO_CNTL_BASE_IDX 0 +#define regDAGB1_RD_GMI_CNTL 0x00d2 +#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB 0x00d3 +#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 +#define regDAGB1_RD_CGTT_CLK_CTRL 0x00d4 +#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x00d5 +#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x00d6 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x00d7 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x00d8 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x00d9 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x00da +#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x00db +#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 +#define regDAGB1_RD_VC0_CNTL 0x00dc +#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC1_CNTL 0x00dd +#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC2_CNTL 0x00de +#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC3_CNTL 0x00df +#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC4_CNTL 0x00e0 +#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 +#define regDAGB1_RD_VC5_CNTL 0x00e1 +#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 +#define regDAGB1_RD_IO_VC_CNTL 0x00e2 +#define regDAGB1_RD_IO_VC_CNTL_BASE_IDX 0 +#define regDAGB1_RD_GMI_VC_CNTL 0x00e3 +#define regDAGB1_RD_GMI_VC_CNTL_BASE_IDX 0 +#define regDAGB1_RD_CNTL_MISC 0x00e4 +#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_RD_TLB_CREDIT 0x00e5 +#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00e6 +#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00e7 +#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK_PENDING 0x00e8 +#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GO_PENDING 0x00e9 +#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00ea +#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_TLB_PENDING 0x00eb +#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OARB_PENDING 0x00ec +#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK2ARB_PENDING 0x00ed +#define regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK2DF_PENDING 0x00ee +#define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_OSD_PENDING 0x00ef +#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_ASK_OSD_PENDING 0x00f0 +#define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 0 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE 0x00f1 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 0 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE 0x00f2 +#define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 0 +#define regDAGB1_DAGB_DLY 0x00f3 +#define regDAGB1_DAGB_DLY_BASE_IDX 0 +#define regDAGB1_CNTL_MISC 0x00f4 +#define regDAGB1_CNTL_MISC_BASE_IDX 0 +#define regDAGB1_CNTL_MISC2 0x00f5 +#define regDAGB1_CNTL_MISC2_BASE_IDX 0 +#define regDAGB1_FIFO_EMPTY 0x00f6 +#define regDAGB1_FIFO_EMPTY_BASE_IDX 0 +#define regDAGB1_FIFO_FULL 0x00f7 +#define regDAGB1_FIFO_FULL_BASE_IDX 0 +#define regDAGB1_RD_CREDITS_FULL 0x00f8 +#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_LO 0x00f9 +#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_HI 0x00fa +#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER0_CFG 0x00fb +#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER1_CFG 0x00fc +#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER2_CFG 0x00fd +#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fe +#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regDAGB1_L1TLB_REG_RW 0x00ff +#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 +#define regDAGB1_RESERVE1 0x0100 +#define regDAGB1_RESERVE1_BASE_IDX 0 +#define regDAGB1_RESERVE2 0x0101 +#define regDAGB1_RESERVE2_BASE_IDX 0 +#define regDAGB1_RESERVE3 0x0102 +#define regDAGB1_RESERVE3_BASE_IDX 0 +#define regDAGB1_RESERVE4 0x0103 +#define regDAGB1_RESERVE4_BASE_IDX 0 +#define regDAGB1_SDP_RD_BW_CNTL 0x0104 +#define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 0 +#define regDAGB1_SDP_PRIORITY_OVERRIDE 0x0105 +#define regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX 0 +#define regDAGB1_SDP_RD_PRIORITY 0x0106 +#define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 0 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x0107 +#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0 +#define regDAGB1_SDP_ENABLE 0x0108 +#define regDAGB1_SDP_ENABLE_BASE_IDX 0 +#define regDAGB1_SDP_CREDITS 0x0109 +#define regDAGB1_SDP_CREDITS_BASE_IDX 0 +#define regDAGB1_SDP_TAG_RESERVE0 0x010a +#define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regDAGB1_SDP_TAG_RESERVE1 0x010b +#define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regDAGB1_SDP_VCC_RESERVE0 0x010c +#define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regDAGB1_SDP_VCC_RESERVE1 0x010d +#define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regDAGB1_SDP_ERR_STATUS 0x010e +#define regDAGB1_SDP_ERR_STATUS_BASE_IDX 0 +#define regDAGB1_SDP_REQ_CNTL 0x010f +#define regDAGB1_SDP_REQ_CNTL_BASE_IDX 0 +#define regDAGB1_SDP_MISC_AON 0x0110 +#define regDAGB1_SDP_MISC_AON_BASE_IDX 0 +#define regDAGB1_SDP_MISC 0x0111 +#define regDAGB1_SDP_MISC_BASE_IDX 0 +#define regDAGB1_SDP_MISC2 0x0112 +#define regDAGB1_SDP_MISC2_BASE_IDX 0 +#define regDAGB1_SDP_ARB_CNTL0 0x0114 +#define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 0 +#define regDAGB1_SDP_ARB_CNTL1 0x0115 +#define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 0 +#define regDAGB1_SDP_CGTT_CLK_CTRL 0x0116 +#define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 0 +#define regDAGB1_SDP_LATENCY_SAMPLING 0x0117 +#define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 0 + + +// addressBlock: mmhub_pctldec +// base address: 0x68e00 +#define regPCTL_CTRL 0x0380 +#define regPCTL_CTRL_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 +#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 +#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 +#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 +#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 +#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 +#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 +#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 +#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 +#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a +#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b +#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c +#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d +#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 +#define regPCTL_UTCL2_MISC 0x038e +#define regPCTL_UTCL2_MISC_BASE_IDX 0 +#define regPCTL_SLICE0_MISC 0x038f +#define regPCTL_SLICE0_MISC_BASE_IDX 0 +#define regPCTL_SLICE1_MISC 0x0390 +#define regPCTL_SLICE1_MISC_BASE_IDX 0 +#define regPCTL_RENG_CTRL 0x0391 +#define regPCTL_RENG_CTRL_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_EXECUTE 0x0392 +#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_EXECUTE 0x0393 +#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_EXECUTE 0x0394 +#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 +#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 +#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 +#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 +#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 +#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 0 +#define regPCTL_SLICE1_RENG_RAM_DATA 0x039a +#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 +#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 +#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0 +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af +#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 +#define regPCTL_STATUS 0x03b0 +#define regPCTL_STATUS_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_LO 0x03b1 +#define regPCTL_PERFCOUNTER_LO_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_HI 0x03b2 +#define regPCTL_PERFCOUNTER_HI_BASE_IDX 0 +#define regPCTL_PERFCOUNTER0_CFG 0x03b3 +#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regPCTL_PERFCOUNTER1_CFG 0x03b4 +#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 +#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regPCTL_RESERVED_0 0x03b6 +#define regPCTL_RESERVED_0_BASE_IDX 0 +#define regPCTL_RESERVED_1 0x03b7 +#define regPCTL_RESERVED_1_BASE_IDX 0 +#define regPCTL_RESERVED_2 0x03b8 +#define regPCTL_RESERVED_2_BASE_IDX 0 +#define regPCTL_RESERVED_3 0x03b9 +#define regPCTL_RESERVED_3_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmvml1pfdec +// base address: 0x69600 +#define regMMMC_VM_MX_L1_TLB0_STATUS 0x0586 +#define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB1_STATUS 0x0587 +#define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB2_STATUS 0x0588 +#define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB3_STATUS 0x0589 +#define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB4_STATUS 0x058a +#define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB5_STATUS 0x058b +#define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmvml1pldec +// base address: 0x69670 +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c +#define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d +#define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e +#define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f +#define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_l1tlb_mmvml1prdec +// base address: 0x69690 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 +#define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 +#define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +// base address: 0x69a00 +#define regMMVM_L2_CNTL 0x0680 +#define regMMVM_L2_CNTL_BASE_IDX 0 +#define regMMVM_L2_CNTL2 0x0681 +#define regMMVM_L2_CNTL2_BASE_IDX 0 +#define regMMVM_L2_CNTL3 0x0682 +#define regMMVM_L2_CNTL3_BASE_IDX 0 +#define regMMVM_L2_STATUS 0x0683 +#define regMMVM_L2_STATUS_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0684 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_CNTL 0x0687 +#define regMMVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0688 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0689 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x068a +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068b +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_STATUS 0x068c +#define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068d +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068e +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068f +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0690 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0692 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0693 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0694 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0695 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0696 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0697 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regMMVM_L2_CNTL4 0x0698 +#define regMMVM_L2_CNTL4_BASE_IDX 0 +#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0699 +#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x069a +#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x069b +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regMMVM_L2_CACHE_PARITY_CNTL 0x069c +#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regMMVM_L2_CGTT_CLK_CTRL 0x069d +#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMVM_L2_CNTL5 0x069e +#define regMMVM_L2_CNTL5_BASE_IDX 0 +#define regMMVM_L2_GCR_CNTL 0x069f +#define regMMVM_L2_GCR_CNTL_BASE_IDX 0 +#define regMMVM_L2_CGTT_BUSY_CTRL 0x06a0 +#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x06a1 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x06a2 +#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x06a5 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x06a6 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x06a7 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x06a8 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 +#define regMMVM_L2_BANK_SELECT_MASKS 0x06a9 +#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x06aa +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x06ab +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x06ac +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x06ad +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x06ae +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +// base address: 0x69b00 +#define regMMVM_CONTEXT0_CNTL 0x06c0 +#define regMMVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT1_CNTL 0x06c1 +#define regMMVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT2_CNTL 0x06c2 +#define regMMVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT3_CNTL 0x06c3 +#define regMMVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT4_CNTL 0x06c4 +#define regMMVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT5_CNTL 0x06c5 +#define regMMVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT6_CNTL 0x06c6 +#define regMMVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT7_CNTL 0x06c7 +#define regMMVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT8_CNTL 0x06c8 +#define regMMVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT9_CNTL 0x06c9 +#define regMMVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT10_CNTL 0x06ca +#define regMMVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT11_CNTL 0x06cb +#define regMMVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT12_CNTL 0x06cc +#define regMMVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT13_CNTL 0x06cd +#define regMMVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT14_CNTL 0x06ce +#define regMMVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXT15_CNTL 0x06cf +#define regMMVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regMMVM_CONTEXTS_DISABLE 0x06d0 +#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_SEM 0x06d1 +#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_SEM 0x06d2 +#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_SEM 0x06d3 +#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_SEM 0x06d4 +#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_SEM 0x06d5 +#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_SEM 0x06d6 +#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_SEM 0x06d7 +#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_SEM 0x06d8 +#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_SEM 0x06d9 +#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_SEM 0x06da +#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_SEM 0x06db +#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_SEM 0x06dc +#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_SEM 0x06dd +#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_SEM 0x06de +#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_SEM 0x06df +#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_SEM 0x06e0 +#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_SEM 0x06e1 +#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_SEM 0x06e2 +#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_REQ 0x06e3 +#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_REQ 0x06e4 +#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_REQ 0x06e5 +#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_REQ 0x06e6 +#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_REQ 0x06e7 +#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_REQ 0x06e8 +#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_REQ 0x06e9 +#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_REQ 0x06ea +#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_REQ 0x06eb +#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_REQ 0x06ec +#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_REQ 0x06ed +#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_REQ 0x06ee +#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_REQ 0x06ef +#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_REQ 0x06f0 +#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_REQ 0x06f1 +#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_REQ 0x06f2 +#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_REQ 0x06f3 +#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_REQ 0x06f4 +#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ACK 0x06f5 +#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ACK 0x06f6 +#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ACK 0x06f7 +#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ACK 0x06f8 +#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ACK 0x06f9 +#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ACK 0x06fa +#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ACK 0x06fb +#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ACK 0x06fc +#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ACK 0x06fd +#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ACK 0x06fe +#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ACK 0x06ff +#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ACK 0x0700 +#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ACK 0x0701 +#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ACK 0x0702 +#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ACK 0x0703 +#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ACK 0x0704 +#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ACK 0x0705 +#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ACK 0x0706 +#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x078b +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x078c +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x078d +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x078e +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x078f +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0790 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0791 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0792 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0793 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0794 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0795 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0796 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0797 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0798 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0799 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x079a +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x079b +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +// base address: 0x69e90 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x07aa +#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x07ab +#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER0_CFG 0x07ad +#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER1_CFG 0x07ae +#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER2_CFG 0x07af +#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER3_CFG 0x07b0 +#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x07b1 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +// base address: 0x69ee0 +#define regMMMC_VM_L2_PERFCOUNTER_LO 0x07b8 +#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMMC_VM_L2_PERFCOUNTER_HI 0x07b9 +#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_LO 0x07ba +#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 0 +#define regMMUTCL2_PERFCOUNTER_HI 0x07bb +#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +// base address: 0x69f30 +#define regMMMC_VM_FB_SIZE_OFFSET_VF0 0x07cc +#define regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF1 0x07cd +#define regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF2 0x07ce +#define regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF3 0x07cf +#define regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 +#define regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 +#define regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 +#define regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 +#define regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 +#define regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 +#define regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 +#define regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 +#define regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 +#define regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF14 0x07da +#define regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 +#define regMMMC_VM_FB_SIZE_OFFSET_VF15 0x07db +#define regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +// base address: 0x6a140 +#define regMMMC_VM_FB_OFFSET 0x0857 +#define regMMMC_VM_FB_OFFSET_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0858 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0859 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regMMMC_VM_STEERING 0x085a +#define regMMMC_VM_STEERING_BASE_IDX 0 +#define regMMMC_MEM_POWER_LS 0x085c +#define regMMMC_MEM_POWER_LS_BASE_IDX 0 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x085d +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x085e +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x085f +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x0860 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_APT_CNTL 0x0861 +#define regMMMC_VM_APT_CNTL_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x0862 +#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x0863 +#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x0864 +#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0 +#define regMMUTCL2_CGTT_CLK_CTRL 0x0865 +#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 +#define regMMUTCL2_CGTT_BUSY_CTRL 0x0867 +#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regMMMC_VM_FB_NOALLOC_CNTL 0x0868 +#define regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX 0 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x0869 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x086b +#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +// base address: 0x6a1b0 +#define regMMMC_VM_FB_LOCATION_BASE 0x086c +#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define regMMMC_VM_FB_LOCATION_TOP 0x086d +#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 +#define regMMMC_VM_AGP_TOP 0x086e +#define regMMMC_VM_AGP_TOP_BASE_IDX 0 +#define regMMMC_VM_AGP_BOT 0x086f +#define regMMMC_VM_AGP_BOT_BASE_IDX 0 +#define regMMMC_VM_AGP_BASE 0x0870 +#define regMMMC_VM_AGP_BASE_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0871 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0872 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 +#define regMMMC_VM_MX_L1_TLB_CNTL 0x0873 +#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +// base address: 0x6a850 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0a14 +#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 0 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0a17 +#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 0 +#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0a1a +#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 0 +#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0a1b +#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 0 + +#endif diff --git a/extra/amdpci/headers/mmhub_3_0_2_sh_mask.h b/extra/amdpci/headers/mmhub_3_0_2_sh_mask.h new file mode 100644 index 0000000000..67e233353d --- /dev/null +++ b/extra/amdpci/headers/mmhub_3_0_2_sh_mask.h @@ -0,0 +1,7228 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_3_0_2_SH_MASK_HEADER +#define _mmhub_3_0_2_SH_MASK_HEADER + + +// addressBlock: mmhub_dagbdec +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI16 +#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI17 +#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI18 +#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI19 +#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI20 +#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI21 +#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI22 +#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI23 +#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L +#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L +//DAGB0_RD_IO_CNTL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_IO_VC_CNTL +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_GMI_VC_CNTL +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RD_RDRET_CREDIT_CNTL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB0_RD_RDRET_CREDIT_CNTL2 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2ARB_PENDING +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK2DF_PENDING +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_ASK_OSD_PENDING +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_NOALLOC_OVERRIDE +#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI16 +#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI17 +#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI18 +#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI19 +#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI20 +#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI21 +#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI22 +#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI23 +#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xc +#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT 0xd +#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT 0xe +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK 0x00001000L +#define DAGB0_WR_CNTL__UPDATE_FED_MASK 0x00002000L +#define DAGB0_WR_CNTL__UPDATE_NACK_MASK 0x00004000L +//DAGB0_WR_IO_CNTL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST2 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST2 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_IO_VC_CNTL +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_GMI_VC_CNTL +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x000007C0L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L +#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L +//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x1a +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1b +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1c +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x03F00000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x04000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x08000000L +#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x10000000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2ARB_PENDING +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK2DF_PENDING +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_ASK_OSD_PENDING +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_NOALLOC_OVERRIDE +#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb +#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x0001FFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x0000FFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0001FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_L1TLB_REG_RW +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x2 +#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_SDP_RD_BW_CNTL +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L +#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L +#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L +//DAGB0_SDP_PRIORITY_OVERRIDE +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L +#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L +//DAGB0_SDP_RD_PRIORITY +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_WR_PRIORITY +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT 0x0 +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT 0x4 +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT 0x8 +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT 0xc +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT 0x10 +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT 0x14 +#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK 0x00F00000L +//DAGB0_SDP_RD_CLI2SDP_VC_MAP +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_WR_CLI2SDP_VC_MAP +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB0_SDP_ENABLE +#define DAGB0_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB0_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB0_SDP_CREDITS +#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB0_SDP_TAG_RESERVE0 +#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB0_SDP_TAG_RESERVE1 +#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB0_SDP_VCC_RESERVE0 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCC_RESERVE1 +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB0_SDP_ERR_STATUS +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//DAGB0_SDP_REQ_CNTL +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//DAGB0_SDP_MISC_AON +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L +//DAGB0_SDP_MISC +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L +#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L +//DAGB0_SDP_MISC2 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 +#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L +//DAGB0_SDP_VCD_RESERVE0 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB0_SDP_VCD_RESERVE1 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x12 +#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x00040000L +//DAGB0_SDP_ARB_CNTL0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 +#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L +#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L +#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L +#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L +//DAGB0_SDP_ARB_CNTL1 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L +#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L +#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L +//DAGB0_FATAL_ERROR_CNTL +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL +//DAGB0_FATAL_ERROR_CLEAR +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L +//DAGB0_FATAL_ERROR_STATUS0 +#define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L +#define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL +#define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L +//DAGB0_FATAL_ERROR_STATUS1 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL +//DAGB0_FATAL_ERROR_STATUS2 +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x1c +#define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x1d +#define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x1e +#define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x1f +#define DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK 0x0000FFFFL +#define DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK 0x00FF0000L +#define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x0F000000L +#define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x10000000L +#define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x20000000L +#define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x40000000L +#define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x80000000L +//DAGB0_FATAL_ERROR_STATUS3 +#define DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT 0xd +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 +#define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 +#define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 +#define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT 0x18 +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT 0x19 +#define DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK 0x0000003FL +#define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L +#define DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK 0x0000E000L +#define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L +#define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L +#define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L +#define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L +#define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L +#define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L +#define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L +#define DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK 0x01000000L +#define DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK 0x02000000L +//DAGB0_FATAL_ERROR_STATUS4 +#define DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT 0x0 +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT 0x4 +#define DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT 0x5 +#define DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT 0x6 +#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT 0x7 +#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT 0x8 +#define DAGB0_FATAL_ERROR_STATUS4__PRI_MASK 0x0000000FL +#define DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK 0x00000010L +#define DAGB0_FATAL_ERROR_STATUS4__FULL_MASK 0x00000020L +#define DAGB0_FATAL_ERROR_STATUS4__DROP_MASK 0x00000040L +#define DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK 0x00000080L +#define DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK 0x00000100L +//DAGB0_SDP_CGTT_CLK_CTRL +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB0_SDP_LATENCY_SAMPLING +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//DAGB1_RDCLI0 +#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI1 +#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI2 +#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI3 +#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI4 +#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI5 +#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI6 +#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI7 +#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI8 +#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI9 +#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI10 +#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI11 +#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI12 +#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI13 +#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI14 +#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI15 +#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI16 +#define DAGB1_RDCLI16__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI16__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI16__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI16__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI16__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI16__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI16__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI16__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI16__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI16__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI16__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI16__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI17 +#define DAGB1_RDCLI17__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI17__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI17__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI17__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI17__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI17__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI17__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI17__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI17__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI17__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI17__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI17__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI18 +#define DAGB1_RDCLI18__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI18__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI18__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI18__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI18__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI18__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI18__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI18__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI18__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI18__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI18__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI18__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI19 +#define DAGB1_RDCLI19__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI19__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI19__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI19__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI19__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI19__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI19__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI19__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI19__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI19__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI19__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI19__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI20 +#define DAGB1_RDCLI20__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI20__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI20__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI20__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI20__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI20__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI20__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI20__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI20__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI20__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI20__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI20__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI21 +#define DAGB1_RDCLI21__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI21__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI21__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI21__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI21__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI21__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI21__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI21__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI21__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI21__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI21__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI21__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI22 +#define DAGB1_RDCLI22__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI22__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI22__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI22__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI22__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI22__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI22__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI22__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI22__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI22__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI22__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI22__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI23 +#define DAGB1_RDCLI23__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI23__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI23__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI23__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI23__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI23__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI23__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI23__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI23__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI23__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI23__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI23__MAX_OSD_MASK 0xFC000000L +//DAGB1_RD_CNTL +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x0 +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0x6 +#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0xc +#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT 0xf +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x0000003FL +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x00000FC0L +#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x00007000L +#define DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK 0x00008000L +//DAGB1_RD_IO_CNTL +#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB1_RD_GMI_CNTL +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT 0x0 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT 0x1 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT 0x9 +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT 0xa +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT 0xd +#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT 0x12 +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK 0x00000001L +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK 0x0000000EL +#define DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK 0x00000200L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK 0x00001C00L +#define DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK 0x0003E000L +#define DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK 0x001C0000L +//DAGB1_RD_ADDR_DAGB +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +#define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L +//DAGB1_RD_CGTT_CLK_CTRL +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST2 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER2 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L +//DAGB1_RD_VC0_CNTL +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC1_CNTL +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC2_CNTL +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC3_CNTL +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC4_CNTL +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC5_CNTL +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_IO_VC_CNTL +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_GMI_VC_CNTL +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_CNTL_MISC +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT 0x6 +#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT 0x9 +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK 0x000001C0L +#define DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK 0x00000200L +//DAGB1_RD_TLB_CREDIT +#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_RD_RDRET_CREDIT_CNTL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x5 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xa +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0xf +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x14 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT 0x19 +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x000003E0L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x00007C00L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x000F8000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x01F00000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK 0x3E000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L +#define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L +//DAGB1_RD_RDRET_CREDIT_CNTL2 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0000003FL +//DAGB1_RDCLI_ASK_PENDING +#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GO_PENDING +#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GBLSEND_PENDING +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_TLB_PENDING +#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OARB_PENDING +#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK2ARB_PENDING +#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK2DF_PENDING +#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OSD_PENDING +#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_ASK_OSD_PENDING +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_NOALLOC_OVERRIDE +#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT 0x0 +#define DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE +#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT 0x0 +#define DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK 0xFFFFFFFFL +//DAGB1_DAGB_DLY +#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB1_CNTL_MISC +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x0 +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x0000003FL +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0x6 +#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT 0x7 +#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT 0x8 +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x9 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0xa +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0xb +#define DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK 0x00000001L +#define DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK 0x00000010L +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000020L +#define DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000040L +#define DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK 0x00000080L +#define DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK 0x00000100L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000200L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000400L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000800L +//DAGB1_FIFO_EMPTY +#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x0000007FL +//DAGB1_FIFO_FULL +#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB1_FIFO_FULL__FULL_MASK 0x0000007FL +//DAGB1_RD_CREDITS_FULL +#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0000007FL +//DAGB1_PERFCOUNTER_LO +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB1_PERFCOUNTER_HI +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB1_PERFCOUNTER0_CFG +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER1_CFG +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER2_CFG +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER_RSLT_CNTL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB1_L1TLB_REG_RW +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 +#define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x2 +#define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L +#define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L +#define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0x3FFFFFFCL +//DAGB1_RESERVE1 +#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE2 +#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE3 +#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE4 +#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_SDP_RD_BW_CNTL +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT 0x0 +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT 0x1 +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT 0x9 +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT 0xa +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT 0xd +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK 0x00000001L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK 0x000001FEL +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK 0x00000200L +#define DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK 0x00001C00L +#define DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK 0x0007E000L +//DAGB1_SDP_PRIORITY_OVERRIDE +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT 0x0 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT 0x4 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT 0x9 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT 0xa +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT 0xb +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT 0xc +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT 0xd +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT 0xe +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT 0x10 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT 0x14 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT 0x19 +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT 0x1a +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT 0x1b +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT 0x1c +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT 0x1d +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT 0x1e +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK 0x0000000FL +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK 0x000001F0L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK 0x00000200L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK 0x00000400L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK 0x00000800L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK 0x00001000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK 0x00002000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK 0x00004000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK 0x000F0000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK 0x01F00000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK 0x02000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK 0x04000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK 0x08000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK 0x10000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK 0x20000000L +#define DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK 0x40000000L +//DAGB1_SDP_RD_PRIORITY +#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT 0x0 +#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT 0x4 +#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT 0x8 +#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT 0xc +#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT 0x10 +#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT 0x14 +#define DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK 0x0000000FL +#define DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK 0x000000F0L +#define DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK 0x00000F00L +#define DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK 0x0000F000L +#define DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK 0x000F0000L +#define DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK 0x00F00000L +//DAGB1_SDP_RD_CLI2SDP_VC_MAP +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT 0x0 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT 0x3 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT 0x6 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT 0x9 +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT 0xc +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT 0xf +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK 0x00000007L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK 0x00000038L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK 0x000001C0L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK 0x00000E00L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK 0x00007000L +#define DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK 0x00038000L +//DAGB1_SDP_ENABLE +#define DAGB1_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define DAGB1_SDP_ENABLE__ENABLE_MASK 0x00000001L +//DAGB1_SDP_CREDITS +#define DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define DAGB1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x01FF0000L +//DAGB1_SDP_TAG_RESERVE0 +#define DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//DAGB1_SDP_TAG_RESERVE1 +#define DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define DAGB1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define DAGB1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define DAGB1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define DAGB1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//DAGB1_SDP_VCC_RESERVE0 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//DAGB1_SDP_VCC_RESERVE1 +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//DAGB1_SDP_ERR_STATUS +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 +#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +#define DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L +#define DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L +#define DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L +#define DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L +//DAGB1_SDP_REQ_CNTL +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L +#define DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L +//DAGB1_SDP_MISC_AON +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L +#define DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L +//DAGB1_SDP_MISC +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x0 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x1 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x2 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x3 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0x4 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0x5 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0x6 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0x7 +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x8 +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x9 +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xb +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xd +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xf +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT 0x14 +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT 0x15 +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000001L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000002L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000004L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000008L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000010L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000020L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00000040L +#define DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00000080L +#define DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000100L +#define DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000600L +#define DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00001800L +#define DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00006000L +#define DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000F8000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK 0x00100000L +#define DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK 0x00200000L +//DAGB1_SDP_MISC2 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT 0x0 +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT 0x1 +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT 0x2 +#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT 0x3 +#define DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK 0x00000001L +#define DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK 0x00000002L +#define DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK 0x00000004L +#define DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK 0x00000008L +//DAGB1_SDP_ARB_CNTL0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT 0x1 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT 0x2 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT 0x3 +#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT 0x4 +#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT 0x5 +#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT 0x6 +#define DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT 0x7 +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK 0x00000001L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK 0x00000002L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK 0x00000004L +#define DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK 0x00000008L +#define DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK 0x00000010L +#define DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK 0x00000020L +#define DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK 0x00000040L +#define DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK 0x00000080L +//DAGB1_SDP_ARB_CNTL1 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT 0x0 +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT 0x8 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT 0x10 +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT 0x18 +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK 0x00007F00L +#define DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK 0x007F0000L +#define DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK 0x7F000000L +//DAGB1_SDP_CGTT_CLK_CTRL +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//DAGB1_SDP_LATENCY_SAMPLING +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L + + +// addressBlock: mmhub_pctldec +//PCTL_CTRL +#define PCTL_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT 0x4 +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT 0x5 +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x7 +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xe +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x13 +#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT 0x14 +#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT 0x15 +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT 0x16 +#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT 0x1b +#define PCTL_CTRL__Z9_PWRDOWN__SHIFT 0x1c +#define PCTL_CTRL__Z9_PWRUP__SHIFT 0x1d +#define PCTL_CTRL__SNR_DISABLE__SHIFT 0x1e +#define PCTL_CTRL__WRACK_GUARD__SHIFT 0x1f +#define PCTL_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK 0x00000010L +#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK 0x00000060L +#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00003F80L +#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0007C000L +#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00080000L +#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK 0x00100000L +#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK 0x00200000L +#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK 0x07C00000L +#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK 0x08000000L +#define PCTL_CTRL__Z9_PWRDOWN_MASK 0x10000000L +#define PCTL_CTRL__Z9_PWRUP_MASK 0x20000000L +#define PCTL_CTRL__SNR_DISABLE_MASK 0x40000000L +#define PCTL_CTRL__WRACK_GUARD_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_IB +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL_PG_IGNORE_DEEPSLEEP +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL_PG_IGNORE_DEEPSLEEP_IB +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL_SLICE0_CFG_DAGB_WRBUSY +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DAGB_RDBUSY +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE0_CFG_DS_ALLOW +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE0_CFG_DS_ALLOW_IB +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DAGB_WRBUSY +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DAGB_RDBUSY +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL_SLICE1_CFG_DS_ALLOW +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL_SLICE1_CFG_DS_ALLOW_IB +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL_UTCL2_MISC +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000007FFL +#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +//PCTL_SLICE0_MISC +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT 0x1e +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT 0x1f +#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK 0x40000000L +#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK 0x80000000L +//PCTL_SLICE1_MISC +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT 0x0 +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT 0x13 +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT 0x14 +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT 0x1a +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT 0x1e +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT 0x1f +#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x000003FFL +#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK 0x00080000L +#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK 0x03F00000L +#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK 0x3C000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK 0x40000000L +#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK 0x80000000L +//PCTL_RENG_CTRL +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +//PCTL_UTCL2_RENG_EXECUTE +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL_SLICE0_RENG_EXECUTE +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_SLICE1_RENG_EXECUTE +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL_UTCL2_RENG_RAM_INDEX +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL_UTCL2_RENG_RAM_DATA +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE0_RENG_RAM_INDEX +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE0_RENG_RAM_DATA +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_SLICE1_RENG_RAM_INDEX +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL_SLICE1_RENG_RAM_DATA +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL +#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L +//PCTL_STATUS +#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT 0x0 +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT 0x1 +#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT 0x2 +#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT 0x3 +#define PCTL_STATUS__MMHUB_IDLE__SHIFT 0x4 +#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT 0x5 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT 0x7 +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT 0xf +#define PCTL_STATUS__MMHUB_POWER__SHIFT 0x10 +#define PCTL_STATUS__RENG_RAM_STALE__SHIFT 0x11 +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT 0x12 +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT 0x13 +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT 0x14 +#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK 0x00000001L +#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK 0x00000002L +#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK 0x00000004L +#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK 0x00000008L +#define PCTL_STATUS__MMHUB_IDLE_MASK 0x00000010L +#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK 0x00000060L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK 0x00007F80L +#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK 0x00008000L +#define PCTL_STATUS__MMHUB_POWER_MASK 0x00010000L +#define PCTL_STATUS__RENG_RAM_STALE_MASK 0x00020000L +#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK 0x00040000L +#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK 0x00080000L +#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK 0x00100000L +//PCTL_PERFCOUNTER_LO +#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//PCTL_PERFCOUNTER_HI +#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//PCTL_PERFCOUNTER0_CFG +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER1_CFG +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//PCTL_PERFCOUNTER_RSLT_CNTL +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//PCTL_RESERVED_0 +#define PCTL_RESERVED_0__WORD__SHIFT 0x0 +#define PCTL_RESERVED_0__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_0__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_0__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_0__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_0__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_0__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_0__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_0__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_0__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_0__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_0__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_0__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_0__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_0__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_0__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_0__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_0__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_0__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_0__BIT0_MASK 0x80000000L +//PCTL_RESERVED_1 +#define PCTL_RESERVED_1__WORD__SHIFT 0x0 +#define PCTL_RESERVED_1__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_1__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_1__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_1__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_1__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_1__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_1__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_1__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_1__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_1__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_1__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_1__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_1__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_1__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_1__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_1__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_1__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_1__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_1__BIT0_MASK 0x80000000L +//PCTL_RESERVED_2 +#define PCTL_RESERVED_2__WORD__SHIFT 0x0 +#define PCTL_RESERVED_2__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_2__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_2__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_2__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_2__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_2__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_2__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_2__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_2__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_2__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_2__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_2__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_2__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_2__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_2__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_2__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_2__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_2__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_2__BIT0_MASK 0x80000000L +//PCTL_RESERVED_3 +#define PCTL_RESERVED_3__WORD__SHIFT 0x0 +#define PCTL_RESERVED_3__BYTE__SHIFT 0x10 +#define PCTL_RESERVED_3__BIT7__SHIFT 0x18 +#define PCTL_RESERVED_3__BIT6__SHIFT 0x19 +#define PCTL_RESERVED_3__BIT5__SHIFT 0x1a +#define PCTL_RESERVED_3__BIT4__SHIFT 0x1b +#define PCTL_RESERVED_3__BIT3__SHIFT 0x1c +#define PCTL_RESERVED_3__BIT2__SHIFT 0x1d +#define PCTL_RESERVED_3__BIT1__SHIFT 0x1e +#define PCTL_RESERVED_3__BIT0__SHIFT 0x1f +#define PCTL_RESERVED_3__WORD_MASK 0x0000FFFFL +#define PCTL_RESERVED_3__BYTE_MASK 0x00FF0000L +#define PCTL_RESERVED_3__BIT7_MASK 0x01000000L +#define PCTL_RESERVED_3__BIT6_MASK 0x02000000L +#define PCTL_RESERVED_3__BIT5_MASK 0x04000000L +#define PCTL_RESERVED_3__BIT4_MASK 0x08000000L +#define PCTL_RESERVED_3__BIT3_MASK 0x10000000L +#define PCTL_RESERVED_3__BIT2_MASK 0x20000000L +#define PCTL_RESERVED_3__BIT1_MASK 0x40000000L +#define PCTL_RESERVED_3__BIT0_MASK 0x80000000L + + +// addressBlock: mmhub_l1tlb_mmvml1pfdec +//MMMC_VM_MX_L1_TLB0_STATUS +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MMMC_VM_MX_L1_TLB1_STATUS +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MMMC_VM_MX_L1_TLB2_STATUS +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MMMC_VM_MX_L1_TLB3_STATUS +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MMMC_VM_MX_L1_TLB4_STATUS +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//MMMC_VM_MX_L1_TLB5_STATUS +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L + + +// addressBlock: mmhub_l1tlb_mmvml1pldec +//MMMC_VM_MX_L1_PERFCOUNTER0_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER1_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER2_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER3_CFG +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_mmvml1prdec +//MMMC_VM_MX_L1_PERFCOUNTER_LO +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_MX_L1_PERFCOUNTER_HI +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +//MMVM_L2_CNTL +#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//MMVM_L2_CNTL2 +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_CNTL3 +#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_STATUS +#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//MMVM_DUMMY_PAGE_FAULT_CNTL +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_INVALIDATE_CNTL +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//MMVM_L2_PROTECTION_FAULT_CNTL +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//MMVM_L2_PROTECTION_FAULT_CNTL2 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_STATUS +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d +#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L +//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//MMVM_L2_CNTL4 +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//MMVM_L2_MM_GROUP_RT_CLASSES +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID2 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_CACHE_PARITY_CNTL +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//MMVM_L2_CGTT_CLK_CTRL +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMVM_L2_CNTL5 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L +//MMVM_L2_GCR_CNTL +#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//MMVM_L2_CGTT_BUSY_CTRL +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMVM_L2_PTE_CACHE_DUMP_CNTL +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//MMVM_L2_PTE_CACHE_DUMP_READ +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_MASKS +#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +//MMVM_CONTEXT0_CNTL +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT1_CNTL +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT2_CNTL +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT3_CNTL +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT4_CNTL +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT5_CNTL +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT6_CNTL +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT7_CNTL +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT8_CNTL +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT9_CNTL +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT10_CNTL +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT11_CNTL +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT12_CNTL +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT13_CNTL +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT14_CNTL +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXT15_CNTL +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L +//MMVM_CONTEXTS_DISABLE +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_INVALIDATE_ENG0_SEM +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG1_SEM +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG2_SEM +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG3_SEM +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG4_SEM +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG5_SEM +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG6_SEM +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG7_SEM +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG8_SEM +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG9_SEM +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG10_SEM +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG11_SEM +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG12_SEM +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG13_SEM +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG14_SEM +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG15_SEM +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG16_SEM +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG17_SEM +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG0_REQ +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG1_REQ +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG2_REQ +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG3_REQ +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG4_REQ +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG5_REQ +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG6_REQ +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG7_REQ +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG8_REQ +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG9_REQ +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG10_REQ +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG11_REQ +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG12_REQ +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG13_REQ +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG14_REQ +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG15_REQ +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG16_REQ +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG17_REQ +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +//MMVM_INVALIDATE_ENG0_ACK +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG1_ACK +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG2_ACK +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG3_ACK +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG4_ACK +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG5_ACK +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG6_ACK +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG7_ACK +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG8_ACK +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG9_ACK +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG10_ACK +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG11_ACK +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG12_ACK +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG13_ACK +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG14_ACK +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG15_ACK +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG16_ACK +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG17_ACK +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +//MMMC_VM_L2_PERFCOUNTER0_CFG +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER1_CFG +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER2_CFG +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER3_CFG +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER4_CFG +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER5_CFG +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER6_CFG +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER7_CFG +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMUTCL2_PERFCOUNTER0_CFG +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER1_CFG +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER2_CFG +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER3_CFG +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER_RSLT_CNTL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +//MMMC_VM_L2_PERFCOUNTER_LO +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_L2_PERFCOUNTER_HI +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMUTCL2_PERFCOUNTER_LO +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMUTCL2_PERFCOUNTER_HI +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +//MMMC_VM_FB_SIZE_OFFSET_VF0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF1 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF2 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF3 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF4 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF5 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF6 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF7 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF8 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF9 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF11 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF12 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF13 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF14 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//MMMC_VM_FB_SIZE_OFFSET_VF15 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +//MMMC_VM_FB_OFFSET +#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//MMMC_VM_STEERING +#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MMMC_MEM_POWER_LS +#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_APT_CNTL +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +//MMMC_VM_LOCAL_FB_ADDRESS_START +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_END +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//MMUTCL2_CGTT_CLK_CTRL +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x1FFFE000L +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMUTCL2_CGTT_BUSY_CTRL +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMMC_VM_FB_NOALLOC_CNTL +#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 +#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x2 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x3 +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x4 +#define MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L +#define MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000004L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000008L +#define MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000010L +//MMUTCL2_HARVEST_BYPASS_GROUPS +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//MMUTCL2_GROUP_RET_FAULT_STATUS +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +//MMMC_VM_FB_LOCATION_BASE +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//MMMC_VM_FB_LOCATION_TOP +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_TOP +#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BOT +#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//MMMC_VM_AGP_BASE +#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//MMMC_VM_MX_L1_TLB_CNTL +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +//MMUTCL2_TRANSLATION_BYPASS_BY_VMID +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L +//MMUTC_TRANSLATION_FAULT_CNTL0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//MMUTC_TRANSLATION_FAULT_CNTL1 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L +#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L + +#endif diff --git a/tinygrad/runtime/autogen/am/mmhub_3_0_2.py b/tinygrad/runtime/autogen/am/mmhub_3_0_2.py new file mode 100644 index 0000000000..f6cf4d86f7 --- /dev/null +++ b/tinygrad/runtime/autogen/am/mmhub_3_0_2.py @@ -0,0 +1,14973 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_mmhub_3_0_2_OFFSET_HEADER = True # macro +regDAGB0_RDCLI0 = 0x0000 # macro +regDAGB0_RDCLI0_BASE_IDX = 0 # macro +regDAGB0_RDCLI1 = 0x0001 # macro +regDAGB0_RDCLI1_BASE_IDX = 0 # macro +regDAGB0_RDCLI2 = 0x0002 # macro +regDAGB0_RDCLI2_BASE_IDX = 0 # macro +regDAGB0_RDCLI3 = 0x0003 # macro +regDAGB0_RDCLI3_BASE_IDX = 0 # macro +regDAGB0_RDCLI4 = 0x0004 # macro +regDAGB0_RDCLI4_BASE_IDX = 0 # macro +regDAGB0_RDCLI5 = 0x0005 # macro +regDAGB0_RDCLI5_BASE_IDX = 0 # macro +regDAGB0_RDCLI6 = 0x0006 # macro +regDAGB0_RDCLI6_BASE_IDX = 0 # macro +regDAGB0_RDCLI7 = 0x0007 # macro +regDAGB0_RDCLI7_BASE_IDX = 0 # macro +regDAGB0_RDCLI8 = 0x0008 # macro +regDAGB0_RDCLI8_BASE_IDX = 0 # macro +regDAGB0_RDCLI9 = 0x0009 # macro +regDAGB0_RDCLI9_BASE_IDX = 0 # macro +regDAGB0_RDCLI10 = 0x000a # macro +regDAGB0_RDCLI10_BASE_IDX = 0 # macro +regDAGB0_RDCLI11 = 0x000b # macro +regDAGB0_RDCLI11_BASE_IDX = 0 # macro +regDAGB0_RDCLI12 = 0x000c # macro +regDAGB0_RDCLI12_BASE_IDX = 0 # macro +regDAGB0_RDCLI13 = 0x000d # macro +regDAGB0_RDCLI13_BASE_IDX = 0 # macro +regDAGB0_RDCLI14 = 0x000e # macro +regDAGB0_RDCLI14_BASE_IDX = 0 # macro +regDAGB0_RDCLI15 = 0x000f # macro +regDAGB0_RDCLI15_BASE_IDX = 0 # macro +regDAGB0_RDCLI16 = 0x0010 # macro +regDAGB0_RDCLI16_BASE_IDX = 0 # macro +regDAGB0_RDCLI17 = 0x0011 # macro +regDAGB0_RDCLI17_BASE_IDX = 0 # macro +regDAGB0_RDCLI18 = 0x0012 # macro +regDAGB0_RDCLI18_BASE_IDX = 0 # macro +regDAGB0_RDCLI19 = 0x0013 # macro +regDAGB0_RDCLI19_BASE_IDX = 0 # macro +regDAGB0_RDCLI20 = 0x0014 # macro +regDAGB0_RDCLI20_BASE_IDX = 0 # macro +regDAGB0_RDCLI21 = 0x0015 # macro +regDAGB0_RDCLI21_BASE_IDX = 0 # macro +regDAGB0_RDCLI22 = 0x0016 # macro +regDAGB0_RDCLI22_BASE_IDX = 0 # macro +regDAGB0_RDCLI23 = 0x0017 # macro +regDAGB0_RDCLI23_BASE_IDX = 0 # macro +regDAGB0_RD_CNTL = 0x0018 # macro +regDAGB0_RD_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_IO_CNTL = 0x0019 # macro +regDAGB0_RD_IO_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_GMI_CNTL = 0x001a # macro +regDAGB0_RD_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB = 0x001b # macro +regDAGB0_RD_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB0_RD_CGTT_CLK_CTRL = 0x001c # macro +regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_RD_CGTT_CLK_CTRL = 0x001d # macro +regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST0 = 0x001e # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 = 0x001f # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST1 = 0x0020 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 = 0x0021 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST2 = 0x0022 # macro +regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 = 0x0023 # macro +regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_RD_VC0_CNTL = 0x0024 # macro +regDAGB0_RD_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC1_CNTL = 0x0025 # macro +regDAGB0_RD_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC2_CNTL = 0x0026 # macro +regDAGB0_RD_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC3_CNTL = 0x0027 # macro +regDAGB0_RD_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC4_CNTL = 0x0028 # macro +regDAGB0_RD_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_VC5_CNTL = 0x0029 # macro +regDAGB0_RD_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_IO_VC_CNTL = 0x002a # macro +regDAGB0_RD_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_GMI_VC_CNTL = 0x002b # macro +regDAGB0_RD_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_CNTL_MISC = 0x002c # macro +regDAGB0_RD_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_RD_TLB_CREDIT = 0x002d # macro +regDAGB0_RD_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB0_RD_RDRET_CREDIT_CNTL = 0x002e # macro +regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX = 0 # macro +regDAGB0_RD_RDRET_CREDIT_CNTL2 = 0x002f # macro +regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK_PENDING = 0x0030 # macro +regDAGB0_RDCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_GO_PENDING = 0x0031 # macro +regDAGB0_RDCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_GBLSEND_PENDING = 0x0032 # macro +regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_TLB_PENDING = 0x0033 # macro +regDAGB0_RDCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_OARB_PENDING = 0x0034 # macro +regDAGB0_RDCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK2ARB_PENDING = 0x0035 # macro +regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK2DF_PENDING = 0x0036 # macro +regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_OSD_PENDING = 0x0037 # macro +regDAGB0_RDCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_ASK_OSD_PENDING = 0x0038 # macro +regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE = 0x0039 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE = 0x003a # macro +regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_WRCLI0 = 0x003b # macro +regDAGB0_WRCLI0_BASE_IDX = 0 # macro +regDAGB0_WRCLI1 = 0x003c # macro +regDAGB0_WRCLI1_BASE_IDX = 0 # macro +regDAGB0_WRCLI2 = 0x003d # macro +regDAGB0_WRCLI2_BASE_IDX = 0 # macro +regDAGB0_WRCLI3 = 0x003e # macro +regDAGB0_WRCLI3_BASE_IDX = 0 # macro +regDAGB0_WRCLI4 = 0x003f # macro +regDAGB0_WRCLI4_BASE_IDX = 0 # macro +regDAGB0_WRCLI5 = 0x0040 # macro +regDAGB0_WRCLI5_BASE_IDX = 0 # macro +regDAGB0_WRCLI6 = 0x0041 # macro +regDAGB0_WRCLI6_BASE_IDX = 0 # macro +regDAGB0_WRCLI7 = 0x0042 # macro +regDAGB0_WRCLI7_BASE_IDX = 0 # macro +regDAGB0_WRCLI8 = 0x0043 # macro +regDAGB0_WRCLI8_BASE_IDX = 0 # macro +regDAGB0_WRCLI9 = 0x0044 # macro +regDAGB0_WRCLI9_BASE_IDX = 0 # macro +regDAGB0_WRCLI10 = 0x0045 # macro +regDAGB0_WRCLI10_BASE_IDX = 0 # macro +regDAGB0_WRCLI11 = 0x0046 # macro +regDAGB0_WRCLI11_BASE_IDX = 0 # macro +regDAGB0_WRCLI12 = 0x0047 # macro +regDAGB0_WRCLI12_BASE_IDX = 0 # macro +regDAGB0_WRCLI13 = 0x0048 # macro +regDAGB0_WRCLI13_BASE_IDX = 0 # macro +regDAGB0_WRCLI14 = 0x0049 # macro +regDAGB0_WRCLI14_BASE_IDX = 0 # macro +regDAGB0_WRCLI15 = 0x004a # macro +regDAGB0_WRCLI15_BASE_IDX = 0 # macro +regDAGB0_WRCLI16 = 0x004b # macro +regDAGB0_WRCLI16_BASE_IDX = 0 # macro +regDAGB0_WRCLI17 = 0x004c # macro +regDAGB0_WRCLI17_BASE_IDX = 0 # macro +regDAGB0_WRCLI18 = 0x004d # macro +regDAGB0_WRCLI18_BASE_IDX = 0 # macro +regDAGB0_WRCLI19 = 0x004e # macro +regDAGB0_WRCLI19_BASE_IDX = 0 # macro +regDAGB0_WRCLI20 = 0x004f # macro +regDAGB0_WRCLI20_BASE_IDX = 0 # macro +regDAGB0_WRCLI21 = 0x0050 # macro +regDAGB0_WRCLI21_BASE_IDX = 0 # macro +regDAGB0_WRCLI22 = 0x0051 # macro +regDAGB0_WRCLI22_BASE_IDX = 0 # macro +regDAGB0_WRCLI23 = 0x0052 # macro +regDAGB0_WRCLI23_BASE_IDX = 0 # macro +regDAGB0_WR_CNTL = 0x0053 # macro +regDAGB0_WR_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_IO_CNTL = 0x0054 # macro +regDAGB0_WR_IO_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_GMI_CNTL = 0x0055 # macro +regDAGB0_WR_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB = 0x0056 # macro +regDAGB0_WR_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB0_WR_CGTT_CLK_CTRL = 0x0057 # macro +regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_WR_CGTT_CLK_CTRL = 0x0058 # macro +regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST0 = 0x0059 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 = 0x005a # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST1 = 0x005b # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 = 0x005c # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST2 = 0x005d # macro +regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 = 0x005e # macro +regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB = 0x005f # macro +regDAGB0_WR_DATA_DAGB_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST0 = 0x0060 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 = 0x0061 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST1 = 0x0062 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 = 0x0063 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST2 = 0x0064 # macro +regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 = 0x0065 # macro +regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB0_WR_VC0_CNTL = 0x0066 # macro +regDAGB0_WR_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC1_CNTL = 0x0067 # macro +regDAGB0_WR_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC2_CNTL = 0x0068 # macro +regDAGB0_WR_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC3_CNTL = 0x0069 # macro +regDAGB0_WR_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC4_CNTL = 0x006a # macro +regDAGB0_WR_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_VC5_CNTL = 0x006b # macro +regDAGB0_WR_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_IO_VC_CNTL = 0x006c # macro +regDAGB0_WR_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_GMI_VC_CNTL = 0x006d # macro +regDAGB0_WR_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB0_WR_CNTL_MISC = 0x006e # macro +regDAGB0_WR_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_WR_TLB_CREDIT = 0x006f # macro +regDAGB0_WR_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_CREDIT = 0x0070 # macro +regDAGB0_WR_DATA_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_MISC_CREDIT = 0x0071 # macro +regDAGB0_WR_MISC_CREDIT_BASE_IDX = 0 # macro +regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 = 0x0072 # macro +regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX = 0 # macro +regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 = 0x0073 # macro +regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK_PENDING = 0x0074 # macro +regDAGB0_WRCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GO_PENDING = 0x0075 # macro +regDAGB0_WRCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GBLSEND_PENDING = 0x0076 # macro +regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_TLB_PENDING = 0x0077 # macro +regDAGB0_WRCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_OARB_PENDING = 0x0078 # macro +regDAGB0_WRCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK2ARB_PENDING = 0x0079 # macro +regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK2DF_PENDING = 0x007a # macro +regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_OSD_PENDING = 0x007b # macro +regDAGB0_WRCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_ASK_OSD_PENDING = 0x007c # macro +regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_DBUS_ASK_PENDING = 0x007d # macro +regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_DBUS_GO_PENDING = 0x007e # macro +regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE = 0x007f # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE = 0x0080 # macro +regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE = 0x0081 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE = 0x0082 # macro +regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB0_DAGB_DLY = 0x0083 # macro +regDAGB0_DAGB_DLY_BASE_IDX = 0 # macro +regDAGB0_CNTL_MISC = 0x0084 # macro +regDAGB0_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB0_CNTL_MISC2 = 0x0085 # macro +regDAGB0_CNTL_MISC2_BASE_IDX = 0 # macro +regDAGB0_FIFO_EMPTY = 0x0086 # macro +regDAGB0_FIFO_EMPTY_BASE_IDX = 0 # macro +regDAGB0_FIFO_FULL = 0x0087 # macro +regDAGB0_FIFO_FULL_BASE_IDX = 0 # macro +regDAGB0_RD_CREDITS_FULL = 0x0088 # macro +regDAGB0_RD_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB0_WR_CREDITS_FULL = 0x0089 # macro +regDAGB0_WR_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_LO = 0x008a # macro +regDAGB0_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_HI = 0x008b # macro +regDAGB0_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER0_CFG = 0x008c # macro +regDAGB0_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER1_CFG = 0x008d # macro +regDAGB0_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER2_CFG = 0x008e # macro +regDAGB0_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regDAGB0_PERFCOUNTER_RSLT_CNTL = 0x008f # macro +regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regDAGB0_L1TLB_REG_RW = 0x0090 # macro +regDAGB0_L1TLB_REG_RW_BASE_IDX = 0 # macro +regDAGB0_RESERVE1 = 0x0091 # macro +regDAGB0_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_RESERVE2 = 0x0092 # macro +regDAGB0_RESERVE2_BASE_IDX = 0 # macro +regDAGB0_RESERVE3 = 0x0093 # macro +regDAGB0_RESERVE3_BASE_IDX = 0 # macro +regDAGB0_RESERVE4 = 0x0094 # macro +regDAGB0_RESERVE4_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_BW_CNTL = 0x0095 # macro +regDAGB0_SDP_RD_BW_CNTL_BASE_IDX = 0 # macro +regDAGB0_SDP_PRIORITY_OVERRIDE = 0x0096 # macro +regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_PRIORITY = 0x0097 # macro +regDAGB0_SDP_RD_PRIORITY_BASE_IDX = 0 # macro +regDAGB0_SDP_WR_PRIORITY = 0x0098 # macro +regDAGB0_SDP_WR_PRIORITY_BASE_IDX = 0 # macro +regDAGB0_SDP_RD_CLI2SDP_VC_MAP = 0x0099 # macro +regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB0_SDP_WR_CLI2SDP_VC_MAP = 0x009a # macro +regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB0_SDP_ENABLE = 0x009b # macro +regDAGB0_SDP_ENABLE_BASE_IDX = 0 # macro +regDAGB0_SDP_CREDITS = 0x009c # macro +regDAGB0_SDP_CREDITS_BASE_IDX = 0 # macro +regDAGB0_SDP_TAG_RESERVE0 = 0x009d # macro +regDAGB0_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_TAG_RESERVE1 = 0x009e # macro +regDAGB0_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_VCC_RESERVE0 = 0x009f # macro +regDAGB0_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_VCC_RESERVE1 = 0x00a0 # macro +regDAGB0_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_ERR_STATUS = 0x00a1 # macro +regDAGB0_SDP_ERR_STATUS_BASE_IDX = 0 # macro +regDAGB0_SDP_REQ_CNTL = 0x00a2 # macro +regDAGB0_SDP_REQ_CNTL_BASE_IDX = 0 # macro +regDAGB0_SDP_MISC_AON = 0x00a3 # macro +regDAGB0_SDP_MISC_AON_BASE_IDX = 0 # macro +regDAGB0_SDP_MISC = 0x00a4 # macro +regDAGB0_SDP_MISC_BASE_IDX = 0 # macro +regDAGB0_SDP_MISC2 = 0x00a5 # macro +regDAGB0_SDP_MISC2_BASE_IDX = 0 # macro +regDAGB0_SDP_VCD_RESERVE0 = 0x00a7 # macro +regDAGB0_SDP_VCD_RESERVE0_BASE_IDX = 0 # macro +regDAGB0_SDP_VCD_RESERVE1 = 0x00a8 # macro +regDAGB0_SDP_VCD_RESERVE1_BASE_IDX = 0 # macro +regDAGB0_SDP_ARB_CNTL0 = 0x00a9 # macro +regDAGB0_SDP_ARB_CNTL0_BASE_IDX = 0 # macro +regDAGB0_SDP_ARB_CNTL1 = 0x00aa # macro +regDAGB0_SDP_ARB_CNTL1_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_CNTL = 0x00ab # macro +regDAGB0_FATAL_ERROR_CNTL_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_CLEAR = 0x00ac # macro +regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS0 = 0x00ad # macro +regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS1 = 0x00ae # macro +regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS2 = 0x00af # macro +regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS3 = 0x00b0 # macro +regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX = 0 # macro +regDAGB0_FATAL_ERROR_STATUS4 = 0x00b1 # macro +regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX = 0 # macro +regDAGB0_SDP_CGTT_CLK_CTRL = 0x00b6 # macro +regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB0_SDP_LATENCY_SAMPLING = 0x00b7 # macro +regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regDAGB1_RDCLI0 = 0x00b8 # macro +regDAGB1_RDCLI0_BASE_IDX = 0 # macro +regDAGB1_RDCLI1 = 0x00b9 # macro +regDAGB1_RDCLI1_BASE_IDX = 0 # macro +regDAGB1_RDCLI2 = 0x00ba # macro +regDAGB1_RDCLI2_BASE_IDX = 0 # macro +regDAGB1_RDCLI3 = 0x00bb # macro +regDAGB1_RDCLI3_BASE_IDX = 0 # macro +regDAGB1_RDCLI4 = 0x00bc # macro +regDAGB1_RDCLI4_BASE_IDX = 0 # macro +regDAGB1_RDCLI5 = 0x00bd # macro +regDAGB1_RDCLI5_BASE_IDX = 0 # macro +regDAGB1_RDCLI6 = 0x00be # macro +regDAGB1_RDCLI6_BASE_IDX = 0 # macro +regDAGB1_RDCLI7 = 0x00bf # macro +regDAGB1_RDCLI7_BASE_IDX = 0 # macro +regDAGB1_RDCLI8 = 0x00c0 # macro +regDAGB1_RDCLI8_BASE_IDX = 0 # macro +regDAGB1_RDCLI9 = 0x00c1 # macro +regDAGB1_RDCLI9_BASE_IDX = 0 # macro +regDAGB1_RDCLI10 = 0x00c2 # macro +regDAGB1_RDCLI10_BASE_IDX = 0 # macro +regDAGB1_RDCLI11 = 0x00c3 # macro +regDAGB1_RDCLI11_BASE_IDX = 0 # macro +regDAGB1_RDCLI12 = 0x00c4 # macro +regDAGB1_RDCLI12_BASE_IDX = 0 # macro +regDAGB1_RDCLI13 = 0x00c5 # macro +regDAGB1_RDCLI13_BASE_IDX = 0 # macro +regDAGB1_RDCLI14 = 0x00c6 # macro +regDAGB1_RDCLI14_BASE_IDX = 0 # macro +regDAGB1_RDCLI15 = 0x00c7 # macro +regDAGB1_RDCLI15_BASE_IDX = 0 # macro +regDAGB1_RDCLI16 = 0x00c8 # macro +regDAGB1_RDCLI16_BASE_IDX = 0 # macro +regDAGB1_RDCLI17 = 0x00c9 # macro +regDAGB1_RDCLI17_BASE_IDX = 0 # macro +regDAGB1_RDCLI18 = 0x00ca # macro +regDAGB1_RDCLI18_BASE_IDX = 0 # macro +regDAGB1_RDCLI19 = 0x00cb # macro +regDAGB1_RDCLI19_BASE_IDX = 0 # macro +regDAGB1_RDCLI20 = 0x00cc # macro +regDAGB1_RDCLI20_BASE_IDX = 0 # macro +regDAGB1_RDCLI21 = 0x00cd # macro +regDAGB1_RDCLI21_BASE_IDX = 0 # macro +regDAGB1_RDCLI22 = 0x00ce # macro +regDAGB1_RDCLI22_BASE_IDX = 0 # macro +regDAGB1_RDCLI23 = 0x00cf # macro +regDAGB1_RDCLI23_BASE_IDX = 0 # macro +regDAGB1_RD_CNTL = 0x00d0 # macro +regDAGB1_RD_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_IO_CNTL = 0x00d1 # macro +regDAGB1_RD_IO_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_GMI_CNTL = 0x00d2 # macro +regDAGB1_RD_GMI_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB = 0x00d3 # macro +regDAGB1_RD_ADDR_DAGB_BASE_IDX = 0 # macro +regDAGB1_RD_CGTT_CLK_CTRL = 0x00d4 # macro +regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_L1TLB_RD_CGTT_CLK_CTRL = 0x00d5 # macro +regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST0 = 0x00d6 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 = 0x00d7 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST1 = 0x00d8 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 = 0x00d9 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST2 = 0x00da # macro +regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX = 0 # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 = 0x00db # macro +regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX = 0 # macro +regDAGB1_RD_VC0_CNTL = 0x00dc # macro +regDAGB1_RD_VC0_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC1_CNTL = 0x00dd # macro +regDAGB1_RD_VC1_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC2_CNTL = 0x00de # macro +regDAGB1_RD_VC2_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC3_CNTL = 0x00df # macro +regDAGB1_RD_VC3_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC4_CNTL = 0x00e0 # macro +regDAGB1_RD_VC4_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_VC5_CNTL = 0x00e1 # macro +regDAGB1_RD_VC5_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_IO_VC_CNTL = 0x00e2 # macro +regDAGB1_RD_IO_VC_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_GMI_VC_CNTL = 0x00e3 # macro +regDAGB1_RD_GMI_VC_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_CNTL_MISC = 0x00e4 # macro +regDAGB1_RD_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB1_RD_TLB_CREDIT = 0x00e5 # macro +regDAGB1_RD_TLB_CREDIT_BASE_IDX = 0 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL = 0x00e6 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX = 0 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL2 = 0x00e7 # macro +regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK_PENDING = 0x00e8 # macro +regDAGB1_RDCLI_ASK_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_GO_PENDING = 0x00e9 # macro +regDAGB1_RDCLI_GO_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_GBLSEND_PENDING = 0x00ea # macro +regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_TLB_PENDING = 0x00eb # macro +regDAGB1_RDCLI_TLB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_OARB_PENDING = 0x00ec # macro +regDAGB1_RDCLI_OARB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK2ARB_PENDING = 0x00ed # macro +regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK2DF_PENDING = 0x00ee # macro +regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_OSD_PENDING = 0x00ef # macro +regDAGB1_RDCLI_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_ASK_OSD_PENDING = 0x00f0 # macro +regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX = 0 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE = 0x00f1 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX = 0 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE = 0x00f2 # macro +regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX = 0 # macro +regDAGB1_DAGB_DLY = 0x00f3 # macro +regDAGB1_DAGB_DLY_BASE_IDX = 0 # macro +regDAGB1_CNTL_MISC = 0x00f4 # macro +regDAGB1_CNTL_MISC_BASE_IDX = 0 # macro +regDAGB1_CNTL_MISC2 = 0x00f5 # macro +regDAGB1_CNTL_MISC2_BASE_IDX = 0 # macro +regDAGB1_FIFO_EMPTY = 0x00f6 # macro +regDAGB1_FIFO_EMPTY_BASE_IDX = 0 # macro +regDAGB1_FIFO_FULL = 0x00f7 # macro +regDAGB1_FIFO_FULL_BASE_IDX = 0 # macro +regDAGB1_RD_CREDITS_FULL = 0x00f8 # macro +regDAGB1_RD_CREDITS_FULL_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_LO = 0x00f9 # macro +regDAGB1_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_HI = 0x00fa # macro +regDAGB1_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER0_CFG = 0x00fb # macro +regDAGB1_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER1_CFG = 0x00fc # macro +regDAGB1_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER2_CFG = 0x00fd # macro +regDAGB1_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regDAGB1_PERFCOUNTER_RSLT_CNTL = 0x00fe # macro +regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regDAGB1_L1TLB_REG_RW = 0x00ff # macro +regDAGB1_L1TLB_REG_RW_BASE_IDX = 0 # macro +regDAGB1_RESERVE1 = 0x0100 # macro +regDAGB1_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_RESERVE2 = 0x0101 # macro +regDAGB1_RESERVE2_BASE_IDX = 0 # macro +regDAGB1_RESERVE3 = 0x0102 # macro +regDAGB1_RESERVE3_BASE_IDX = 0 # macro +regDAGB1_RESERVE4 = 0x0103 # macro +regDAGB1_RESERVE4_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_BW_CNTL = 0x0104 # macro +regDAGB1_SDP_RD_BW_CNTL_BASE_IDX = 0 # macro +regDAGB1_SDP_PRIORITY_OVERRIDE = 0x0105 # macro +regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_PRIORITY = 0x0106 # macro +regDAGB1_SDP_RD_PRIORITY_BASE_IDX = 0 # macro +regDAGB1_SDP_RD_CLI2SDP_VC_MAP = 0x0107 # macro +regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX = 0 # macro +regDAGB1_SDP_ENABLE = 0x0108 # macro +regDAGB1_SDP_ENABLE_BASE_IDX = 0 # macro +regDAGB1_SDP_CREDITS = 0x0109 # macro +regDAGB1_SDP_CREDITS_BASE_IDX = 0 # macro +regDAGB1_SDP_TAG_RESERVE0 = 0x010a # macro +regDAGB1_SDP_TAG_RESERVE0_BASE_IDX = 0 # macro +regDAGB1_SDP_TAG_RESERVE1 = 0x010b # macro +regDAGB1_SDP_TAG_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_SDP_VCC_RESERVE0 = 0x010c # macro +regDAGB1_SDP_VCC_RESERVE0_BASE_IDX = 0 # macro +regDAGB1_SDP_VCC_RESERVE1 = 0x010d # macro +regDAGB1_SDP_VCC_RESERVE1_BASE_IDX = 0 # macro +regDAGB1_SDP_ERR_STATUS = 0x010e # macro +regDAGB1_SDP_ERR_STATUS_BASE_IDX = 0 # macro +regDAGB1_SDP_REQ_CNTL = 0x010f # macro +regDAGB1_SDP_REQ_CNTL_BASE_IDX = 0 # macro +regDAGB1_SDP_MISC_AON = 0x0110 # macro +regDAGB1_SDP_MISC_AON_BASE_IDX = 0 # macro +regDAGB1_SDP_MISC = 0x0111 # macro +regDAGB1_SDP_MISC_BASE_IDX = 0 # macro +regDAGB1_SDP_MISC2 = 0x0112 # macro +regDAGB1_SDP_MISC2_BASE_IDX = 0 # macro +regDAGB1_SDP_ARB_CNTL0 = 0x0114 # macro +regDAGB1_SDP_ARB_CNTL0_BASE_IDX = 0 # macro +regDAGB1_SDP_ARB_CNTL1 = 0x0115 # macro +regDAGB1_SDP_ARB_CNTL1_BASE_IDX = 0 # macro +regDAGB1_SDP_CGTT_CLK_CTRL = 0x0116 # macro +regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regDAGB1_SDP_LATENCY_SAMPLING = 0x0117 # macro +regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX = 0 # macro +regPCTL_CTRL = 0x0380 # macro +regPCTL_CTRL_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_IB = 0x0381 # macro +regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE = 0x0382 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX = 0 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB = 0x0383 # macro +regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX = 0 # macro +regPCTL_PG_IGNORE_DEEPSLEEP = 0x0384 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX = 0 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_IB = 0x0385 # macro +regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DAGB_WRBUSY = 0x0386 # macro +regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DAGB_RDBUSY = 0x0387 # macro +regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DS_ALLOW = 0x0388 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX = 0 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_IB = 0x0389 # macro +regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DAGB_WRBUSY = 0x038a # macro +regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DAGB_RDBUSY = 0x038b # macro +regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DS_ALLOW = 0x038c # macro +regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX = 0 # macro +regPCTL_SLICE1_CFG_DS_ALLOW_IB = 0x038d # macro +regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX = 0 # macro +regPCTL_UTCL2_MISC = 0x038e # macro +regPCTL_UTCL2_MISC_BASE_IDX = 0 # macro +regPCTL_SLICE0_MISC = 0x038f # macro +regPCTL_SLICE0_MISC_BASE_IDX = 0 # macro +regPCTL_SLICE1_MISC = 0x0390 # macro +regPCTL_SLICE1_MISC_BASE_IDX = 0 # macro +regPCTL_RENG_CTRL = 0x0391 # macro +regPCTL_RENG_CTRL_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_EXECUTE = 0x0392 # macro +regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_EXECUTE = 0x0393 # macro +regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_EXECUTE = 0x0394 # macro +regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_RAM_INDEX = 0x0395 # macro +regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_UTCL2_RENG_RAM_DATA = 0x0396 # macro +regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_RAM_INDEX = 0x0397 # macro +regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_SLICE0_RENG_RAM_DATA = 0x0398 # macro +regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_RAM_INDEX = 0x0399 # macro +regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX = 0 # macro +regPCTL_SLICE1_RENG_RAM_DATA = 0x039a # macro +regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 = 0x039b # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 = 0x039c # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 = 0x039d # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 = 0x039e # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 = 0x039f # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03a0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03a1 # macro +regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 = 0x03a2 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 = 0x03a3 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 = 0x03a4 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 = 0x03a5 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 = 0x03a6 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03a7 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03a8 # macro +regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 = 0x03a9 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 = 0x03aa # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 = 0x03ab # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 = 0x03ac # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 = 0x03ad # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 = 0x03ae # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX = 0 # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 = 0x03af # macro +regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX = 0 # macro +regPCTL_STATUS = 0x03b0 # macro +regPCTL_STATUS_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_LO = 0x03b1 # macro +regPCTL_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_HI = 0x03b2 # macro +regPCTL_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER0_CFG = 0x03b3 # macro +regPCTL_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER1_CFG = 0x03b4 # macro +regPCTL_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regPCTL_PERFCOUNTER_RSLT_CNTL = 0x03b5 # macro +regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regPCTL_RESERVED_0 = 0x03b6 # macro +regPCTL_RESERVED_0_BASE_IDX = 0 # macro +regPCTL_RESERVED_1 = 0x03b7 # macro +regPCTL_RESERVED_1_BASE_IDX = 0 # macro +regPCTL_RESERVED_2 = 0x03b8 # macro +regPCTL_RESERVED_2_BASE_IDX = 0 # macro +regPCTL_RESERVED_3 = 0x03b9 # macro +regPCTL_RESERVED_3_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB0_STATUS = 0x0586 # macro +regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB1_STATUS = 0x0587 # macro +regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB2_STATUS = 0x0588 # macro +regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB3_STATUS = 0x0589 # macro +regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB4_STATUS = 0x058a # macro +regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB5_STATUS = 0x058b # macro +regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER0_CFG = 0x059c # macro +regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER1_CFG = 0x059d # macro +regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER2_CFG = 0x059e # macro +regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER3_CFG = 0x059f # macro +regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL = 0x05a0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_LO = 0x05a4 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_HI = 0x05a5 # macro +regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMMVM_L2_CNTL = 0x0680 # macro +regMMVM_L2_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CNTL2 = 0x0681 # macro +regMMVM_L2_CNTL2_BASE_IDX = 0 # macro +regMMVM_L2_CNTL3 = 0x0682 # macro +regMMVM_L2_CNTL3_BASE_IDX = 0 # macro +regMMVM_L2_STATUS = 0x0683 # macro +regMMVM_L2_STATUS_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_CNTL = 0x0684 # macro +regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x0685 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x0686 # macro +regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_CNTL = 0x0687 # macro +regMMVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL = 0x0688 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL2 = 0x0689 # macro +regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x068a # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x068b # macro +regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_STATUS = 0x068c # macro +regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x068d # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x068e # macro +regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x068f # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x0690 # macro +regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x0692 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x0693 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x0694 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x0695 # macro +regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x0696 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x0697 # macro +regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro +regMMVM_L2_CNTL4 = 0x0698 # macro +regMMVM_L2_CNTL4_BASE_IDX = 0 # macro +regMMVM_L2_MM_GROUP_RT_CLASSES = 0x0699 # macro +regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID = 0x069a # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID2 = 0x069b # macro +regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro +regMMVM_L2_CACHE_PARITY_CNTL = 0x069c # macro +regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CGTT_CLK_CTRL = 0x069d # macro +regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMMVM_L2_CNTL5 = 0x069e # macro +regMMVM_L2_CNTL5_BASE_IDX = 0 # macro +regMMVM_L2_GCR_CNTL = 0x069f # macro +regMMVM_L2_GCR_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_CGTT_BUSY_CTRL = 0x06a0 # macro +regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regMMVM_L2_PTE_CACHE_DUMP_CNTL = 0x06a1 # macro +regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro +regMMVM_L2_PTE_CACHE_DUMP_READ = 0x06a2 # macro +regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x06a5 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x06a6 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x06a7 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x06a8 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 0 # macro +regMMVM_L2_BANK_SELECT_MASKS = 0x06a9 # macro +regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC = 0x06aa # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC = 0x06ab # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX = 0 # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC = 0x06ac # macro +regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX = 0 # macro +regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT = 0x06ad # macro +regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX = 0 # macro +regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ = 0x06ae # macro +regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_CNTL = 0x06c0 # macro +regMMVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_CNTL = 0x06c1 # macro +regMMVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_CNTL = 0x06c2 # macro +regMMVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_CNTL = 0x06c3 # macro +regMMVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_CNTL = 0x06c4 # macro +regMMVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_CNTL = 0x06c5 # macro +regMMVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_CNTL = 0x06c6 # macro +regMMVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_CNTL = 0x06c7 # macro +regMMVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_CNTL = 0x06c8 # macro +regMMVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_CNTL = 0x06c9 # macro +regMMVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_CNTL = 0x06ca # macro +regMMVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_CNTL = 0x06cb # macro +regMMVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_CNTL = 0x06cc # macro +regMMVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_CNTL = 0x06cd # macro +regMMVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_CNTL = 0x06ce # macro +regMMVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_CNTL = 0x06cf # macro +regMMVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro +regMMVM_CONTEXTS_DISABLE = 0x06d0 # macro +regMMVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_SEM = 0x06d1 # macro +regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_SEM = 0x06d2 # macro +regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_SEM = 0x06d3 # macro +regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_SEM = 0x06d4 # macro +regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_SEM = 0x06d5 # macro +regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_SEM = 0x06d6 # macro +regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_SEM = 0x06d7 # macro +regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_SEM = 0x06d8 # macro +regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_SEM = 0x06d9 # macro +regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_SEM = 0x06da # macro +regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_SEM = 0x06db # macro +regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_SEM = 0x06dc # macro +regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_SEM = 0x06dd # macro +regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_SEM = 0x06de # macro +regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_SEM = 0x06df # macro +regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_SEM = 0x06e0 # macro +regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_SEM = 0x06e1 # macro +regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_SEM = 0x06e2 # macro +regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_REQ = 0x06e3 # macro +regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_REQ = 0x06e4 # macro +regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_REQ = 0x06e5 # macro +regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_REQ = 0x06e6 # macro +regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_REQ = 0x06e7 # macro +regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_REQ = 0x06e8 # macro +regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_REQ = 0x06e9 # macro +regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_REQ = 0x06ea # macro +regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_REQ = 0x06eb # macro +regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_REQ = 0x06ec # macro +regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_REQ = 0x06ed # macro +regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_REQ = 0x06ee # macro +regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_REQ = 0x06ef # macro +regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_REQ = 0x06f0 # macro +regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_REQ = 0x06f1 # macro +regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_REQ = 0x06f2 # macro +regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_REQ = 0x06f3 # macro +regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_REQ = 0x06f4 # macro +regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ACK = 0x06f5 # macro +regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ACK = 0x06f6 # macro +regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ACK = 0x06f7 # macro +regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ACK = 0x06f8 # macro +regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ACK = 0x06f9 # macro +regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ACK = 0x06fa # macro +regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ACK = 0x06fb # macro +regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ACK = 0x06fc # macro +regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ACK = 0x06fd # macro +regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ACK = 0x06fe # macro +regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ACK = 0x06ff # macro +regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ACK = 0x0700 # macro +regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ACK = 0x0701 # macro +regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ACK = 0x0702 # macro +regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ACK = 0x0703 # macro +regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ACK = 0x0704 # macro +regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ACK = 0x0705 # macro +regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ACK = 0x0706 # macro +regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x0707 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x0708 # macro +regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x0709 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x070a # macro +regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x070b # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x070c # macro +regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x070d # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x070e # macro +regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x070f # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x0710 # macro +regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x0711 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x0712 # macro +regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x0713 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x0714 # macro +regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x0715 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x0716 # macro +regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x0717 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x0718 # macro +regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x0719 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x071a # macro +regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x071b # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x071c # macro +regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x071d # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x071e # macro +regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x071f # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x0720 # macro +regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x0721 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x0722 # macro +regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x0723 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x0724 # macro +regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x0725 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x0726 # macro +regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x0727 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x0728 # macro +regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x0729 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x072a # macro +regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x072b # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x072c # macro +regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x072d # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x072e # macro +regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x072f # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x0730 # macro +regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x0731 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x0732 # macro +regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x0733 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x0734 # macro +regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x0735 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x0736 # macro +regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x0737 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x0738 # macro +regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x0739 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x073a # macro +regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x073b # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x073c # macro +regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x073d # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x073e # macro +regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x073f # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x0740 # macro +regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x0741 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x0742 # macro +regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x0743 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x0744 # macro +regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x0745 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x0746 # macro +regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x0747 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x0748 # macro +regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x0749 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x074a # macro +regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x074b # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x074c # macro +regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x074d # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x074e # macro +regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x074f # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x0750 # macro +regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x0751 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x0752 # macro +regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x0753 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x0754 # macro +regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x0755 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x0756 # macro +regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x0757 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x0758 # macro +regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x0759 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x075a # macro +regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x075b # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x075c # macro +regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x075d # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x075e # macro +regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x075f # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x0760 # macro +regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x0761 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x0762 # macro +regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x0763 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x0764 # macro +regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x0765 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x0766 # macro +regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x0767 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x0768 # macro +regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x0769 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x076a # macro +regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x076b # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x076c # macro +regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x076d # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x076e # macro +regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x076f # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x0770 # macro +regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x0771 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x0772 # macro +regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x0773 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x0774 # macro +regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x0775 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x0776 # macro +regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x0777 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x0778 # macro +regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x0779 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x077a # macro +regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x077b # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x077c # macro +regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x077d # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x077e # macro +regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x077f # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x0780 # macro +regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x0781 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x0782 # macro +regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x0783 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x0784 # macro +regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x0785 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x0786 # macro +regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x0787 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x0788 # macro +regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x0789 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x078a # macro +regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x078b # macro +regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x078c # macro +regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x078d # macro +regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x078e # macro +regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x078f # macro +regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0790 # macro +regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0791 # macro +regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0792 # macro +regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0793 # macro +regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0794 # macro +regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0795 # macro +regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0796 # macro +regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0797 # macro +regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0798 # macro +regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x0799 # macro +regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x079a # macro +regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x079b # macro +regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER0_CFG = 0x07a4 # macro +regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER1_CFG = 0x07a5 # macro +regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER2_CFG = 0x07a6 # macro +regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER3_CFG = 0x07a7 # macro +regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER4_CFG = 0x07a8 # macro +regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER5_CFG = 0x07a9 # macro +regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER6_CFG = 0x07aa # macro +regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER7_CFG = 0x07ab # macro +regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x07ac # macro +regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER0_CFG = 0x07ad # macro +regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER1_CFG = 0x07ae # macro +regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER2_CFG = 0x07af # macro +regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER3_CFG = 0x07b0 # macro +regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_RSLT_CNTL = 0x07b1 # macro +regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_LO = 0x07b8 # macro +regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMMC_VM_L2_PERFCOUNTER_HI = 0x07b9 # macro +regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_LO = 0x07ba # macro +regMMUTCL2_PERFCOUNTER_LO_BASE_IDX = 0 # macro +regMMUTCL2_PERFCOUNTER_HI = 0x07bb # macro +regMMUTCL2_PERFCOUNTER_HI_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF0 = 0x07cc # macro +regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF1 = 0x07cd # macro +regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF2 = 0x07ce # macro +regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF3 = 0x07cf # macro +regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF4 = 0x07d0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF5 = 0x07d1 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF6 = 0x07d2 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF7 = 0x07d3 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF8 = 0x07d4 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF9 = 0x07d5 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF10 = 0x07d6 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF11 = 0x07d7 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF12 = 0x07d8 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF13 = 0x07d9 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF14 = 0x07da # macro +regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 0 # macro +regMMMC_VM_FB_SIZE_OFFSET_VF15 = 0x07db # macro +regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 0 # macro +regMMMC_VM_FB_OFFSET = 0x0857 # macro +regMMMC_VM_FB_OFFSET_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x0858 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x0859 # macro +regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro +regMMMC_VM_STEERING = 0x085a # macro +regMMMC_VM_STEERING_BASE_IDX = 0 # macro +regMMMC_MEM_POWER_LS = 0x085c # macro +regMMMC_MEM_POWER_LS_BASE_IDX = 0 # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x085d # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x085e # macro +regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START = 0x085f # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END = 0x0860 # macro +regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_APT_CNTL = 0x0861 # macro +regMMMC_VM_APT_CNTL_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_START = 0x0862 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_END = 0x0863 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX = 0 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL = 0x0864 # macro +regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_CGTT_CLK_CTRL = 0x0865 # macro +regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX = 0 # macro +regMMUTCL2_CGTT_BUSY_CTRL = 0x0867 # macro +regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX = 0 # macro +regMMMC_VM_FB_NOALLOC_CNTL = 0x0868 # macro +regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_HARVEST_BYPASS_GROUPS = 0x0869 # macro +regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro +regMMUTCL2_GROUP_RET_FAULT_STATUS = 0x086b # macro +regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX = 0 # macro +regMMMC_VM_FB_LOCATION_BASE = 0x086c # macro +regMMMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +regMMMC_VM_FB_LOCATION_TOP = 0x086d # macro +regMMMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro +regMMMC_VM_AGP_TOP = 0x086e # macro +regMMMC_VM_AGP_TOP_BASE_IDX = 0 # macro +regMMMC_VM_AGP_BOT = 0x086f # macro +regMMMC_VM_AGP_BOT_BASE_IDX = 0 # macro +regMMMC_VM_AGP_BASE = 0x0870 # macro +regMMMC_VM_AGP_BASE_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0871 # macro +regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro +regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x0872 # macro +regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro +regMMMC_VM_MX_L1_TLB_CNTL = 0x0873 # macro +regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro +regMMUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x0a14 # macro +regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 0 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL = 0x0a17 # macro +regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX = 0 # macro +regMMUTC_TRANSLATION_FAULT_CNTL0 = 0x0a1a # macro +regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX = 0 # macro +regMMUTC_TRANSLATION_FAULT_CNTL1 = 0x0a1b # macro +regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX = 0 # macro +_mmhub_3_0_2_SH_MASK_HEADER = True # macro +DAGB0_RDCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RDCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_RDCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_RDCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_RDCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_RDCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_RDCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_RDCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_RDCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_RDCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_RDCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_RDCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_RDCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_RDCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_RDCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT = 0xc # macro +DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xf # macro +DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB0_RD_CNTL__SHARE_VC_NUM_MASK = 0x00007000 # macro +DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00008000 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_RD_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_RD_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT = 0x6 # macro +DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT = 0x9 # macro +DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK = 0x000001C0 # macro +DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK = 0x00000200 # macro +DAGB0_RD_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB0_RD_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB0_RD_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB0_RD_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB0_RD_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB0_RD_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB0_RD_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB0_RD_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB0_RD_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB0_RD_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB0_RD_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB0_RD_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT = 0x14 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT = 0x19 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT = 0x1e # macro +DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT = 0x1f # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK = 0x01F00000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK = 0x3E000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK = 0x40000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK = 0x80000000 # macro +DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WRCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB0_WRCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB0_WRCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB0_WRCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB0_WRCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB0_WRCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB0_WRCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB0_WRCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB0_WRCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB0_WRCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB0_WRCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB0_WRCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB0_WRCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB0_WRCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xc # macro +DAGB0_WR_CNTL__UPDATE_FED__SHIFT = 0xd # macro +DAGB0_WR_CNTL__UPDATE_NACK__SHIFT = 0xe # macro +DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00001000 # macro +DAGB0_WR_CNTL__UPDATE_FED_MASK = 0x00002000 # macro +DAGB0_WR_CNTL__UPDATE_NACK_MASK = 0x00004000 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_WR_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB0_WR_DATA_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB0_WR_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT = 0x6 # macro +DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB0_WR_CNTL_MISC__HDP_CID_MASK = 0x000007C0 # macro +DAGB0_WR_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB0_WR_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB0_WR_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB0_WR_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB0_WR_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB0_WR_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB0_WR_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB0_WR_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB0_WR_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB0_WR_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB0_WR_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB0_WR_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT = 0x0 # macro +DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT = 0x8 # macro +DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT = 0x10 # macro +DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT = 0x18 # macro +DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK = 0x000000FF # macro +DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK = 0x0000FF00 # macro +DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK = 0x00FF0000 # macro +DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK = 0xFF000000 # macro +DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT = 0x6 # macro +DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK = 0x0000003F # macro +DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK = 0x000001C0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT = 0x14 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT = 0x19 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT = 0x1a # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT = 0x1b # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK = 0x01F00000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK = 0x02000000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK = 0x04000000 # macro +DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK = 0x08000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT = 0xa # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT = 0xf # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT = 0x14 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT = 0x1a # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT = 0x1b # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT = 0x1c # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK = 0x03F00000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK = 0x04000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK = 0x08000000 # macro +DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK = 0x10000000 # macro +DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB0_DAGB_DLY__DLY__SHIFT = 0x0 # macro +DAGB0_DAGB_DLY__CLI__SHIFT = 0x8 # macro +DAGB0_DAGB_DLY__POS__SHIFT = 0x10 # macro +DAGB0_DAGB_DLY__DLY_MASK = 0x000000FF # macro +DAGB0_DAGB_DLY__CLI_MASK = 0x0000FF00 # macro +DAGB0_DAGB_DLY__POS_MASK = 0x000F0000 # macro +DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT = 0x0 # macro +DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK = 0x0000003F # macro +DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT = 0x0 # macro +DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT = 0x1 # macro +DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT = 0x2 # macro +DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT = 0x3 # macro +DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT = 0x4 # macro +DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT = 0x5 # macro +DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT = 0x6 # macro +DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT = 0x7 # macro +DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT = 0x8 # macro +DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT = 0x9 # macro +DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT = 0xa # macro +DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT = 0xb # macro +DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK = 0x00000001 # macro +DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK = 0x00000002 # macro +DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK = 0x00000004 # macro +DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK = 0x00000008 # macro +DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK = 0x00000010 # macro +DAGB0_CNTL_MISC2__SWAP_CTL_MASK = 0x00000020 # macro +DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK = 0x00000040 # macro +DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK = 0x00000080 # macro +DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK = 0x00000100 # macro +DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK = 0x00000200 # macro +DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK = 0x00000400 # macro +DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK = 0x00000800 # macro +DAGB0_FIFO_EMPTY__EMPTY__SHIFT = 0x0 # macro +DAGB0_FIFO_EMPTY__EMPTY_MASK = 0x0001FFFF # macro +DAGB0_FIFO_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_FIFO_FULL__FULL_MASK = 0x0000FFFF # macro +DAGB0_RD_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_RD_CREDITS_FULL__FULL_MASK = 0x0000007F # macro +DAGB0_WR_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB0_WR_CREDITS_FULL__FULL_MASK = 0x0001FFFF # macro +DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x00000003 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT = 0x0 # macro +DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT = 0x1 # macro +DAGB0_L1TLB_REG_RW__RESERVE__SHIFT = 0x2 # macro +DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK = 0x00000001 # macro +DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK = 0x00000002 # macro +DAGB0_L1TLB_REG_RW__RESERVE_MASK = 0x3FFFFFFC # macro +DAGB0_RESERVE1__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE1__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE2__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE2__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE3__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE3__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_RESERVE4__RESERVE__SHIFT = 0x0 # macro +DAGB0_RESERVE4__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT = 0x1 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT = 0x9 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT = 0xa # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT = 0xd # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK = 0x000001FE # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK = 0x00000200 # macro +DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK = 0x00001C00 # macro +DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK = 0x0007E000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT = 0x9 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT = 0xa # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT = 0xb # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT = 0xc # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT = 0xd # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT = 0xe # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT = 0x14 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT = 0x19 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT = 0x1a # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT = 0x1b # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT = 0x1c # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT = 0x1d # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT = 0x1e # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK = 0x00000200 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK = 0x00000400 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK = 0x00000800 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK = 0x00001000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK = 0x00002000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK = 0x00004000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK = 0x01F00000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK = 0x02000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK = 0x04000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK = 0x08000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK = 0x10000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK = 0x20000000 # macro +DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK = 0x40000000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB0_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +DAGB0_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +DAGB0_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x01FF0000 # macro +DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +DAGB0_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +DAGB0_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +DAGB0_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +DAGB0_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +DAGB0_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +DAGB0_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +DAGB0_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +DAGB0_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT = 0x12 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK = 0x00040000 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT = 0x4 # macro +DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x5 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT = 0x6 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT = 0x8 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT = 0xa # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK = 0x00000010 # macro +DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000020 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK = 0x000000C0 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK = 0x00000300 # macro +DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK = 0x00000C00 # macro +DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT = 0x0 # macro +DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT = 0x2 # macro +DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK = 0x00000003 # macro +DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK = 0x00000004 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x0 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x1 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x2 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x3 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0x4 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0x5 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0x6 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0x7 # macro +DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0x8 # macro +DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0x9 # macro +DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0xb # macro +DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0xd # macro +DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0xf # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT = 0x14 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT = 0x15 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000001 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000002 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000004 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000008 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000010 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000020 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00000040 # macro +DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00000080 # macro +DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00000100 # macro +DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00000600 # macro +DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00001800 # macro +DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00006000 # macro +DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x000F8000 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK = 0x00100000 # macro +DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK = 0x00200000 # macro +DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT = 0x0 # macro +DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT = 0x1 # macro +DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT = 0x2 # macro +DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT = 0x3 # macro +DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK = 0x00000001 # macro +DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK = 0x00000002 # macro +DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK = 0x00000004 # macro +DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK = 0x00000008 # macro +DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x12 # macro +DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK = 0x00040000 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT = 0x0 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT = 0x1 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT = 0x2 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT = 0x3 # macro +DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT = 0x4 # macro +DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT = 0x5 # macro +DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT = 0x6 # macro +DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT = 0x7 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK = 0x00000001 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK = 0x00000002 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK = 0x00000004 # macro +DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK = 0x00000008 # macro +DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK = 0x00000010 # macro +DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK = 0x00000020 # macro +DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK = 0x00000040 # macro +DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK = 0x00000080 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT = 0x0 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT = 0x8 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT = 0x10 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT = 0x18 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK = 0x0000007F # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK = 0x00007F00 # macro +DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK = 0x007F0000 # macro +DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK = 0x7F000000 # macro +DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK = 0x000003FF # macro +DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK = 0x00000001 # macro +DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT = 0x1 # macro +DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS0__VALID_MASK = 0x00000001 # macro +DAGB0_FATAL_ERROR_STATUS0__CID_MASK = 0x0000003E # macro +DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK = 0xFFFFFFC0 # macro +DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK = 0x0001FFFF # macro +DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT = 0x10 # macro +DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT = 0x18 # macro +DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT = 0x1c # macro +DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT = 0x1d # macro +DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT = 0x1e # macro +DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT = 0x1f # macro +DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK = 0x0000FFFF # macro +DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK = 0x00FF0000 # macro +DAGB0_FATAL_ERROR_STATUS2__VFID_MASK = 0x0F000000 # macro +DAGB0_FATAL_ERROR_STATUS2__VF_MASK = 0x10000000 # macro +DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK = 0x20000000 # macro +DAGB0_FATAL_ERROR_STATUS2__IO_MASK = 0x40000000 # macro +DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK = 0x80000000 # macro +DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT = 0xd # macro +DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT = 0x10 # macro +DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT = 0x11 # macro +DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT = 0x12 # macro +DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT = 0x13 # macro +DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT = 0x14 # macro +DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT = 0x16 # macro +DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT = 0x17 # macro +DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT = 0x18 # macro +DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT = 0x19 # macro +DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK = 0x0000003F # macro +DAGB0_FATAL_ERROR_STATUS3__OP_MASK = 0x00001FC0 # macro +DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK = 0x0000E000 # macro +DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK = 0x00010000 # macro +DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK = 0x00020000 # macro +DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK = 0x00040000 # macro +DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK = 0x00080000 # macro +DAGB0_FATAL_ERROR_STATUS3__NACK_MASK = 0x00300000 # macro +DAGB0_FATAL_ERROR_STATUS3__RO_MASK = 0x00400000 # macro +DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK = 0x00800000 # macro +DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK = 0x01000000 # macro +DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK = 0x02000000 # macro +DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT = 0x0 # macro +DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT = 0x4 # macro +DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT = 0x5 # macro +DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT = 0x6 # macro +DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT = 0x7 # macro +DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT = 0x8 # macro +DAGB0_FATAL_ERROR_STATUS4__PRI_MASK = 0x0000000F # macro +DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK = 0x00000010 # macro +DAGB0_FATAL_ERROR_STATUS4__FULL_MASK = 0x00000020 # macro +DAGB0_FATAL_ERROR_STATUS4__DROP_MASK = 0x00000040 # macro +DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK = 0x00000080 # macro +DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK = 0x00000100 # macro +DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +DAGB1_RDCLI0__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI0__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI0__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI0__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI0__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI0__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI0__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI0__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI0__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI0__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI0__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI0__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI0__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI0__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI1__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI1__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI1__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI1__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI1__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI1__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI1__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI1__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI1__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI1__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI1__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI1__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI1__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI1__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI2__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI2__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI2__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI2__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI2__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI2__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI2__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI2__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI2__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI2__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI2__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI2__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI2__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI2__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI3__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI3__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI3__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI3__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI3__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI3__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI3__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI3__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI3__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI3__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI3__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI3__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI3__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI3__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI4__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI4__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI4__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI4__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI4__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI4__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI4__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI4__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI4__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI4__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI4__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI4__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI4__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI4__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI5__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI5__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI5__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI5__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI5__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI5__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI5__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI5__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI5__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI5__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI5__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI5__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI5__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI5__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI6__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI6__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI6__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI6__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI6__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI6__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI6__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI6__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI6__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI6__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI6__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI6__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI6__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI6__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI7__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI7__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI7__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI7__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI7__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI7__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI7__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI7__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI7__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI7__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI7__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI7__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI7__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI7__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI8__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI8__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI8__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI8__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI8__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI8__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI8__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI8__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI8__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI8__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI8__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI8__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI8__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI8__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI9__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI9__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI9__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI9__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI9__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI9__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI9__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI9__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI9__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI9__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI9__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI9__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI9__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI9__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI10__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI10__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI10__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI10__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI10__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI10__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI10__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI10__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI10__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI10__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI10__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI10__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI10__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI10__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI11__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI11__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI11__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI11__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI11__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI11__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI11__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI11__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI11__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI11__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI11__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI11__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI11__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI11__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI12__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI12__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI12__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI12__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI12__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI12__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI12__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI12__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI12__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI12__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI12__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI12__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI12__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI12__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI13__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI13__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI13__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI13__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI13__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI13__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI13__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI13__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI13__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI13__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI13__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI13__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI13__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI13__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI14__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI14__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI14__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI14__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI14__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI14__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI14__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI14__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI14__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI14__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI14__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI14__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI14__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI14__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI15__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI15__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI15__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI15__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI15__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI15__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI15__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI15__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI15__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI15__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI15__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI15__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI15__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI15__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI16__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI16__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI16__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI16__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI16__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI16__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI16__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI16__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI16__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI16__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI16__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI16__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI16__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI16__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI17__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI17__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI17__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI17__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI17__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI17__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI17__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI17__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI17__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI17__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI17__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI17__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI17__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI17__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI18__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI18__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI18__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI18__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI18__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI18__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI18__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI18__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI18__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI18__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI18__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI18__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI18__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI18__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI19__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI19__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI19__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI19__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI19__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI19__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI19__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI19__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI19__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI19__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI19__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI19__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI19__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI19__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI20__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI20__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI20__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI20__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI20__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI20__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI20__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI20__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI20__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI20__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI20__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI20__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI20__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI20__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI21__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI21__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI21__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI21__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI21__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI21__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI21__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI21__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI21__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI21__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI21__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI21__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI21__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI21__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI22__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI22__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI22__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI22__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI22__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI22__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI22__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI22__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI22__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI22__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI22__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI22__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI22__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI22__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RDCLI23__VIRT_CHAN__SHIFT = 0x0 # macro +DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT = 0x3 # macro +DAGB1_RDCLI23__URG_HIGH__SHIFT = 0x4 # macro +DAGB1_RDCLI23__URG_LOW__SHIFT = 0x8 # macro +DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT = 0xc # macro +DAGB1_RDCLI23__MAX_BW__SHIFT = 0xd # macro +DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT = 0x15 # macro +DAGB1_RDCLI23__MIN_BW__SHIFT = 0x16 # macro +DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT = 0x19 # macro +DAGB1_RDCLI23__MAX_OSD__SHIFT = 0x1a # macro +DAGB1_RDCLI23__VIRT_CHAN_MASK = 0x00000007 # macro +DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK = 0x00000008 # macro +DAGB1_RDCLI23__URG_HIGH_MASK = 0x000000F0 # macro +DAGB1_RDCLI23__URG_LOW_MASK = 0x00000F00 # macro +DAGB1_RDCLI23__MAX_BW_ENABLE_MASK = 0x00001000 # macro +DAGB1_RDCLI23__MAX_BW_MASK = 0x001FE000 # macro +DAGB1_RDCLI23__MIN_BW_ENABLE_MASK = 0x00200000 # macro +DAGB1_RDCLI23__MIN_BW_MASK = 0x01C00000 # macro +DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK = 0x02000000 # macro +DAGB1_RDCLI23__MAX_OSD_MASK = 0xFC000000 # macro +DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT = 0x0 # macro +DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT = 0x6 # macro +DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT = 0xc # macro +DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT = 0xf # macro +DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK = 0x0000003F # macro +DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK = 0x00000FC0 # macro +DAGB1_RD_CNTL__SHARE_VC_NUM_MASK = 0x00007000 # macro +DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK = 0x00008000 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT = 0x1 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT = 0x9 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT = 0xa # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT = 0xd # macro +DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT = 0x12 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK = 0x0000000E # macro +DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK = 0x00000200 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK = 0x00001C00 # macro +DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK = 0x0003E000 # macro +DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK = 0x001C0000 # macro +DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT = 0x3 # macro +DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT = 0x6 # macro +DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT = 0x7 # macro +DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT = 0xd # macro +DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK = 0x00000007 # macro +DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK = 0x00000038 # macro +DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK = 0x00000040 # macro +DAGB1_RD_ADDR_DAGB__WHOAMI_MASK = 0x00001F80 # macro +DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK = 0x00002000 # macro +DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK = 0xF0000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT = 0x0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT = 0x4 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT = 0x8 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT = 0xc # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT = 0x10 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT = 0x14 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT = 0x18 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT = 0x1c # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK = 0x0000000F # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK = 0x000000F0 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK = 0x00000F00 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK = 0x0000F000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK = 0x000F0000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK = 0x00F00000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK = 0x0F000000 # macro +DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK = 0xF0000000 # macro +DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC0_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC0_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC0_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC1_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC1_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC1_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC2_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC2_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC2_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC3_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC3_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC3_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC4_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC4_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC4_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT = 0xb # macro +DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK = 0x00000800 # macro +DAGB1_RD_VC5_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_VC5_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_VC5_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT = 0xc # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT = 0x14 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT = 0x15 # macro +DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT = 0x18 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT = 0x19 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK = 0x000FF000 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK = 0x00100000 # macro +DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK = 0x00E00000 # macro +DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK = 0x01000000 # macro +DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK = 0xFE000000 # macro +DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT = 0x6 # macro +DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT = 0x9 # macro +DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK = 0x0000003F # macro +DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK = 0x000001C0 # macro +DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK = 0x00000200 # macro +DAGB1_RD_TLB_CREDIT__TLB0__SHIFT = 0x0 # macro +DAGB1_RD_TLB_CREDIT__TLB1__SHIFT = 0x5 # macro +DAGB1_RD_TLB_CREDIT__TLB2__SHIFT = 0xa # macro +DAGB1_RD_TLB_CREDIT__TLB3__SHIFT = 0xf # macro +DAGB1_RD_TLB_CREDIT__TLB4__SHIFT = 0x14 # macro +DAGB1_RD_TLB_CREDIT__TLB5__SHIFT = 0x19 # macro +DAGB1_RD_TLB_CREDIT__TLB0_MASK = 0x0000001F # macro +DAGB1_RD_TLB_CREDIT__TLB1_MASK = 0x000003E0 # macro +DAGB1_RD_TLB_CREDIT__TLB2_MASK = 0x00007C00 # macro +DAGB1_RD_TLB_CREDIT__TLB3_MASK = 0x000F8000 # macro +DAGB1_RD_TLB_CREDIT__TLB4_MASK = 0x01F00000 # macro +DAGB1_RD_TLB_CREDIT__TLB5_MASK = 0x3E000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT = 0x5 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT = 0xa # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT = 0xf # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT = 0x14 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT = 0x19 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT = 0x1e # macro +DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT = 0x1f # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK = 0x0000001F # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK = 0x000003E0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK = 0x00007C00 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK = 0x000F8000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK = 0x01F00000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK = 0x3E000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK = 0x40000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK = 0x80000000 # macro +DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT = 0x0 # macro +DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK = 0x0000003F # macro +DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_GO_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_TLB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_OARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT = 0x0 # macro +DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT = 0x0 # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK = 0xFFFFFFFF # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT = 0x0 # macro +DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK = 0xFFFFFFFF # macro +DAGB1_DAGB_DLY__DLY__SHIFT = 0x0 # macro +DAGB1_DAGB_DLY__CLI__SHIFT = 0x8 # macro +DAGB1_DAGB_DLY__POS__SHIFT = 0x10 # macro +DAGB1_DAGB_DLY__DLY_MASK = 0x000000FF # macro +DAGB1_DAGB_DLY__CLI_MASK = 0x0000FF00 # macro +DAGB1_DAGB_DLY__POS_MASK = 0x000F0000 # macro +DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT = 0x0 # macro +DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK = 0x0000003F # macro +DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT = 0x0 # macro +DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT = 0x1 # macro +DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT = 0x2 # macro +DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT = 0x3 # macro +DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT = 0x4 # macro +DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT = 0x5 # macro +DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT = 0x6 # macro +DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT = 0x7 # macro +DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT = 0x8 # macro +DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT = 0x9 # macro +DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT = 0xa # macro +DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT = 0xb # macro +DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK = 0x00000001 # macro +DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK = 0x00000002 # macro +DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK = 0x00000004 # macro +DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK = 0x00000008 # macro +DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK = 0x00000010 # macro +DAGB1_CNTL_MISC2__SWAP_CTL_MASK = 0x00000020 # macro +DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK = 0x00000040 # macro +DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK = 0x00000080 # macro +DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK = 0x00000100 # macro +DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK = 0x00000200 # macro +DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK = 0x00000400 # macro +DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK = 0x00000800 # macro +DAGB1_FIFO_EMPTY__EMPTY__SHIFT = 0x0 # macro +DAGB1_FIFO_EMPTY__EMPTY_MASK = 0x0000007F # macro +DAGB1_FIFO_FULL__FULL__SHIFT = 0x0 # macro +DAGB1_FIFO_FULL__FULL_MASK = 0x0000007F # macro +DAGB1_RD_CREDITS_FULL__FULL__SHIFT = 0x0 # macro +DAGB1_RD_CREDITS_FULL__FULL_MASK = 0x0000007F # macro +DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x00000003 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT = 0x0 # macro +DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT = 0x1 # macro +DAGB1_L1TLB_REG_RW__RESERVE__SHIFT = 0x2 # macro +DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK = 0x00000001 # macro +DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK = 0x00000002 # macro +DAGB1_L1TLB_REG_RW__RESERVE_MASK = 0x3FFFFFFC # macro +DAGB1_RESERVE1__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE1__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE2__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE2__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE3__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE3__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_RESERVE4__RESERVE__SHIFT = 0x0 # macro +DAGB1_RESERVE4__RESERVE_MASK = 0xFFFFFFFF # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT = 0x0 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT = 0x1 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT = 0x9 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT = 0xa # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT = 0xd # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK = 0x00000001 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK = 0x000001FE # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK = 0x00000200 # macro +DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK = 0x00001C00 # macro +DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK = 0x0007E000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT = 0x0 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT = 0x4 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT = 0x9 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT = 0xa # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT = 0xb # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT = 0xc # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT = 0xd # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT = 0xe # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT = 0x10 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT = 0x14 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT = 0x19 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT = 0x1a # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT = 0x1b # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT = 0x1c # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT = 0x1d # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT = 0x1e # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK = 0x0000000F # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK = 0x000001F0 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK = 0x00000200 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK = 0x00000400 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK = 0x00000800 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK = 0x00001000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK = 0x00002000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK = 0x00004000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK = 0x000F0000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK = 0x01F00000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK = 0x02000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK = 0x04000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK = 0x08000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK = 0x10000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK = 0x20000000 # macro +DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK = 0x40000000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT = 0x0 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT = 0x4 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT = 0x8 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT = 0xc # macro +DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT = 0x10 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT = 0x14 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK = 0x0000000F # macro +DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK = 0x000000F0 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK = 0x00000F00 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK = 0x0000F000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK = 0x000F0000 # macro +DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK = 0x00F00000 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT = 0x0 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT = 0x3 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT = 0x6 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT = 0x9 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT = 0xc # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT = 0xf # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK = 0x00000007 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK = 0x00000038 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK = 0x000001C0 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK = 0x00000E00 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK = 0x00007000 # macro +DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK = 0x00038000 # macro +DAGB1_SDP_ENABLE__ENABLE__SHIFT = 0x0 # macro +DAGB1_SDP_ENABLE__ENABLE_MASK = 0x00000001 # macro +DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT = 0x0 # macro +DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT = 0x8 # macro +DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT = 0x10 # macro +DAGB1_SDP_CREDITS__TAG_LIMIT_MASK = 0x000000FF # macro +DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK = 0x00007F00 # macro +DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK = 0x01FF0000 # macro +DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT = 0x0 # macro +DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT = 0x8 # macro +DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT = 0x10 # macro +DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT = 0x18 # macro +DAGB1_SDP_TAG_RESERVE0__VC0_MASK = 0x000000FF # macro +DAGB1_SDP_TAG_RESERVE0__VC1_MASK = 0x0000FF00 # macro +DAGB1_SDP_TAG_RESERVE0__VC2_MASK = 0x00FF0000 # macro +DAGB1_SDP_TAG_RESERVE0__VC3_MASK = 0xFF000000 # macro +DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT = 0x0 # macro +DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT = 0x8 # macro +DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT = 0x10 # macro +DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT = 0x18 # macro +DAGB1_SDP_TAG_RESERVE1__VC4_MASK = 0x000000FF # macro +DAGB1_SDP_TAG_RESERVE1__VC5_MASK = 0x0000FF00 # macro +DAGB1_SDP_TAG_RESERVE1__VC6_MASK = 0x00FF0000 # macro +DAGB1_SDP_TAG_RESERVE1__VC7_MASK = 0xFF000000 # macro +DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT = 0x0 # macro +DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT = 0x6 # macro +DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT = 0xc # macro +DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT = 0x12 # macro +DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT = 0x18 # macro +DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK = 0x0000003F # macro +DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK = 0x00000FC0 # macro +DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK = 0x0003F000 # macro +DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK = 0x00FC0000 # macro +DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK = 0x3F000000 # macro +DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT = 0x0 # macro +DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT = 0x6 # macro +DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT = 0xc # macro +DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT = 0x1f # macro +DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK = 0x0000003F # macro +DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK = 0x00000FC0 # macro +DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK = 0x0003F000 # macro +DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK = 0x80000000 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT = 0x0 # macro +DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT = 0x4 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT = 0x8 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT = 0xa # macro +DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT = 0xb # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT = 0xc # macro +DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT = 0xd # macro +DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT = 0xe # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT = 0xf # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT = 0x10 # macro +DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT = 0x11 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT = 0x12 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK = 0x0000000F # macro +DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK = 0x000000F0 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK = 0x00000300 # macro +DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK = 0x00000400 # macro +DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK = 0x00000800 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK = 0x00001000 # macro +DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK = 0x00002000 # macro +DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK = 0x00004000 # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK = 0x00008000 # macro +DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK = 0x00010000 # macro +DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK = 0x00020000 # macro +DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK = 0x00040000 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT = 0x0 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT = 0x1 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT = 0x2 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT = 0x3 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT = 0x4 # macro +DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT = 0x5 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT = 0x6 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT = 0x8 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT = 0xa # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK = 0x00000001 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK = 0x00000002 # macro +DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK = 0x00000004 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK = 0x00000008 # macro +DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK = 0x00000010 # macro +DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK = 0x00000020 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK = 0x000000C0 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK = 0x00000300 # macro +DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK = 0x00000C00 # macro +DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT = 0x0 # macro +DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT = 0x2 # macro +DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK = 0x00000003 # macro +DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK = 0x00000004 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT = 0x0 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT = 0x1 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT = 0x2 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT = 0x3 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT = 0x4 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT = 0x5 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT = 0x6 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT = 0x7 # macro +DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT = 0x8 # macro +DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT = 0x9 # macro +DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT = 0xb # macro +DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT = 0xd # macro +DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT = 0xf # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT = 0x14 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT = 0x15 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK = 0x00000001 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK = 0x00000002 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK = 0x00000004 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK = 0x00000008 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK = 0x00000010 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK = 0x00000020 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK = 0x00000040 # macro +DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK = 0x00000080 # macro +DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK = 0x00000100 # macro +DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK = 0x00000600 # macro +DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK = 0x00001800 # macro +DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK = 0x00006000 # macro +DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK = 0x000F8000 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK = 0x00100000 # macro +DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK = 0x00200000 # macro +DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT = 0x0 # macro +DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT = 0x1 # macro +DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT = 0x2 # macro +DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT = 0x3 # macro +DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK = 0x00000001 # macro +DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK = 0x00000002 # macro +DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK = 0x00000004 # macro +DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK = 0x00000008 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT = 0x0 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT = 0x1 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT = 0x2 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT = 0x3 # macro +DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT = 0x4 # macro +DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT = 0x5 # macro +DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT = 0x6 # macro +DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT = 0x7 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK = 0x00000001 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK = 0x00000002 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK = 0x00000004 # macro +DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK = 0x00000008 # macro +DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK = 0x00000010 # macro +DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK = 0x00000020 # macro +DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK = 0x00000040 # macro +DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK = 0x00000080 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT = 0x0 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT = 0x8 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT = 0x10 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT = 0x18 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK = 0x0000007F # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK = 0x00007F00 # macro +DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK = 0x007F0000 # macro +DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK = 0x7F000000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT = 0x0 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT = 0x1 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT = 0x2 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT = 0x3 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT = 0x4 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT = 0x5 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT = 0x6 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT = 0x7 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT = 0x8 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT = 0x9 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT = 0xa # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT = 0xb # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT = 0xc # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT = 0xd # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT = 0xe # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT = 0x16 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK = 0x00000001 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK = 0x00000002 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK = 0x00000004 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK = 0x00000008 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK = 0x00000010 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK = 0x00000020 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK = 0x00000040 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK = 0x00000080 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK = 0x00000100 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK = 0x00000200 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK = 0x00000400 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK = 0x00000800 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK = 0x00001000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK = 0x00002000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK = 0x003FC000 # macro +DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK = 0x3FC00000 # macro +PCTL_CTRL__PG_ENABLE__SHIFT = 0x0 # macro +PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT = 0x1 # macro +PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT = 0x4 # macro +PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT = 0x5 # macro +PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT = 0x7 # macro +PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT = 0xe # macro +PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT = 0x13 # macro +PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT = 0x14 # macro +PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT = 0x15 # macro +PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT = 0x16 # macro +PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT = 0x1b # macro +PCTL_CTRL__Z9_PWRDOWN__SHIFT = 0x1c # macro +PCTL_CTRL__Z9_PWRUP__SHIFT = 0x1d # macro +PCTL_CTRL__SNR_DISABLE__SHIFT = 0x1e # macro +PCTL_CTRL__WRACK_GUARD__SHIFT = 0x1f # macro +PCTL_CTRL__PG_ENABLE_MASK = 0x00000001 # macro +PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK = 0x0000000E # macro +PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK = 0x00000010 # macro +PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK = 0x00000060 # macro +PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK = 0x00003F80 # macro +PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK = 0x0007C000 # macro +PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK = 0x00080000 # macro +PCTL_CTRL__UTCL2_LEGACY_MODE_MASK = 0x00100000 # macro +PCTL_CTRL__SDP_DISCONNECT_MODE_MASK = 0x00200000 # macro +PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK = 0x07C00000 # macro +PCTL_CTRL__ZSC_TIMER_ENABLE_MASK = 0x08000000 # macro +PCTL_CTRL__Z9_PWRDOWN_MASK = 0x10000000 # macro +PCTL_CTRL__Z9_PWRUP_MASK = 0x20000000 # macro +PCTL_CTRL__SNR_DISABLE_MASK = 0x40000000 # macro +PCTL_CTRL__WRACK_GUARD_MASK = 0x80000000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT = 0x1f # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK = 0x00010000 # macro +PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK = 0x80000000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT = 0x11 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK = 0x00010000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK = 0x00020000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT = 0x0 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT = 0x1 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT = 0x2 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT = 0x3 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT = 0x4 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT = 0x5 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT = 0x6 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT = 0x7 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT = 0x8 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT = 0x9 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT = 0xa # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT = 0xb # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT = 0xc # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT = 0xd # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT = 0xe # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT = 0xf # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT = 0x10 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK = 0x00000001 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK = 0x00000002 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK = 0x00000004 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK = 0x00000008 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK = 0x00000010 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK = 0x00000020 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK = 0x00000040 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK = 0x00000080 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK = 0x00000100 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK = 0x00000200 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK = 0x00000400 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK = 0x00000800 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK = 0x00001000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK = 0x00002000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK = 0x00004000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK = 0x00008000 # macro +PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT = 0x0 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT = 0x1 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT = 0x2 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT = 0x3 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT = 0x4 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT = 0x5 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT = 0x6 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT = 0x7 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT = 0x8 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT = 0x9 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT = 0xa # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT = 0xb # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT = 0xc # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT = 0xd # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT = 0xe # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT = 0xf # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT = 0x10 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT = 0x11 # macro +PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT = 0x12 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK = 0x00000001 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK = 0x00000002 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK = 0x00000004 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK = 0x00000008 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK = 0x00000010 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK = 0x00000020 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK = 0x00000040 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK = 0x00000080 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK = 0x00000100 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK = 0x00000200 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK = 0x00000400 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK = 0x00000800 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK = 0x00001000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK = 0x00002000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK = 0x00004000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK = 0x00008000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK = 0x00020000 # macro +PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK = 0x00040000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT = 0x0 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT = 0x1 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT = 0x2 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT = 0x3 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT = 0x4 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT = 0x5 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT = 0x6 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT = 0x7 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT = 0x8 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT = 0x9 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT = 0xa # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT = 0xb # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT = 0xc # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT = 0xd # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT = 0xe # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT = 0xf # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT = 0x10 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT = 0x11 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK = 0x00000001 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK = 0x00000002 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK = 0x00000004 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK = 0x00000008 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK = 0x00000010 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK = 0x00000020 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK = 0x00000040 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK = 0x00000080 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK = 0x00000100 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK = 0x00000200 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK = 0x00000400 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK = 0x00000800 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK = 0x00001000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK = 0x00002000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK = 0x00004000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK = 0x00008000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK = 0x00010000 # macro +PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK = 0x00020000 # macro +PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT = 0x1 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT = 0x2 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT = 0x3 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT = 0x4 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT = 0x5 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT = 0x6 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT = 0x7 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT = 0x8 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT = 0x9 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT = 0xa # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT = 0xb # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT = 0xc # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT = 0xd # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT = 0xe # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT = 0xf # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT = 0x10 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK = 0x00000001 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK = 0x00000002 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK = 0x00000004 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK = 0x00000008 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK = 0x00000010 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK = 0x00000020 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK = 0x00000040 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK = 0x00000080 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK = 0x00000100 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK = 0x00000200 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK = 0x00000400 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK = 0x00000800 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK = 0x00001000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK = 0x00002000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK = 0x00004000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK = 0x00008000 # macro +PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK = 0x00010000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT = 0x0 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT = 0x1 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT = 0x2 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT = 0x3 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT = 0x4 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT = 0x5 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT = 0x6 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT = 0x7 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT = 0x8 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT = 0x9 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT = 0xa # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT = 0xb # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT = 0xc # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT = 0xd # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT = 0xe # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT = 0xf # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT = 0x10 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK = 0x00000001 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK = 0x00000002 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK = 0x00000004 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK = 0x00000008 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK = 0x00000010 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK = 0x00000020 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK = 0x00000040 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK = 0x00000080 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK = 0x00000100 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK = 0x00000200 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK = 0x00000400 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK = 0x00000800 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK = 0x00001000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK = 0x00002000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK = 0x00004000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK = 0x00008000 # macro +PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK = 0x00010000 # macro +PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT = 0x1 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT = 0x2 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT = 0x3 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT = 0x4 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT = 0x5 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT = 0x6 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT = 0x7 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT = 0x8 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT = 0x9 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT = 0xa # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT = 0xb # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT = 0xc # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT = 0xd # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT = 0xe # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT = 0xf # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT = 0x10 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK = 0x00000001 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK = 0x00000002 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK = 0x00000004 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK = 0x00000008 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK = 0x00000010 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK = 0x00000020 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK = 0x00000040 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK = 0x00000080 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK = 0x00000100 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK = 0x00000200 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK = 0x00000400 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK = 0x00000800 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK = 0x00001000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK = 0x00002000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK = 0x00004000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK = 0x00008000 # macro +PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK = 0x00010000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT = 0x0 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT = 0x1 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT = 0x2 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT = 0x3 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT = 0x4 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT = 0x5 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT = 0x6 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT = 0x7 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT = 0x8 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT = 0x9 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT = 0xa # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT = 0xb # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT = 0xc # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT = 0xd # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT = 0xe # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT = 0xf # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT = 0x10 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK = 0x00000001 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK = 0x00000002 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK = 0x00000004 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK = 0x00000008 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK = 0x00000010 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK = 0x00000020 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK = 0x00000040 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK = 0x00000080 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK = 0x00000100 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK = 0x00000200 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK = 0x00000400 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK = 0x00000800 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK = 0x00001000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK = 0x00002000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK = 0x00004000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK = 0x00008000 # macro +PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK = 0x00010000 # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT = 0x0 # macro +PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xb # macro +PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xc # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xf # macro +PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0x10 # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK = 0x000007FF # macro +PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000800 # macro +PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00007000 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00008000 # macro +PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00010000 # macro +PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT = 0x0 # macro +PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xa # macro +PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xb # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xe # macro +PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0xf # macro +PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT = 0x10 # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT = 0x1e # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT = 0x1f # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK = 0x000003FF # macro +PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000400 # macro +PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00003800 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00004000 # macro +PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00008000 # macro +PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK = 0x00010000 # macro +PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK = 0x40000000 # macro +PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK = 0x80000000 # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT = 0x0 # macro +PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT = 0xa # macro +PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT = 0xb # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT = 0xe # macro +PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT = 0xf # macro +PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT = 0x10 # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT = 0x11 # macro +PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT = 0x12 # macro +PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT = 0x13 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT = 0x14 # macro +PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT = 0x1a # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT = 0x1e # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT = 0x1f # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK = 0x000003FF # macro +PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK = 0x00000400 # macro +PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK = 0x00003800 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK = 0x00004000 # macro +PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK = 0x00008000 # macro +PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK = 0x00010000 # macro +PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK = 0x00020000 # macro +PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK = 0x00040000 # macro +PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK = 0x00080000 # macro +PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK = 0x03F00000 # macro +PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK = 0x3C000000 # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK = 0x40000000 # macro +PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK = 0x80000000 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xd # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00001FFC # macro +PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x00FFE000 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xc # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00000FFC # macro +PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x003FF000 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT = 0x1 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT = 0x2 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT = 0xc # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK = 0x00000001 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK = 0x00000002 # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK = 0x00000FFC # macro +PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK = 0x003FF000 # macro +PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000007FF # macro +PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000003FF # macro +PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK = 0x000003FF # macro +PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT = 0x0 # macro +PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK = 0xFFFFFFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK = 0xFFFF0000 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT = 0x0 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT = 0x10 # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK = 0x0000FFFF # macro +PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK = 0xFFFF0000 # macro +PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT = 0x0 # macro +PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT = 0x1 # macro +PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT = 0x2 # macro +PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT = 0x3 # macro +PCTL_STATUS__MMHUB_IDLE__SHIFT = 0x4 # macro +PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT = 0x5 # macro +PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT = 0x7 # macro +PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT = 0xf # macro +PCTL_STATUS__MMHUB_POWER__SHIFT = 0x10 # macro +PCTL_STATUS__RENG_RAM_STALE__SHIFT = 0x11 # macro +PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT = 0x12 # macro +PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT = 0x13 # macro +PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT = 0x14 # macro +PCTL_STATUS__MMHUB_CONFIG_DONE_MASK = 0x00000001 # macro +PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK = 0x00000002 # macro +PCTL_STATUS__MMHUB_FENCE_REQ_MASK = 0x00000004 # macro +PCTL_STATUS__MMHUB_FENCE_ACK_MASK = 0x00000008 # macro +PCTL_STATUS__MMHUB_IDLE_MASK = 0x00000010 # macro +PCTL_STATUS__PGFSM_CMD_STATUS_MASK = 0x00000060 # macro +PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK = 0x00007F80 # macro +PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK = 0x00008000 # macro +PCTL_STATUS__MMHUB_POWER_MASK = 0x00010000 # macro +PCTL_STATUS__RENG_RAM_STALE_MASK = 0x00020000 # macro +PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK = 0x00040000 # macro +PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK = 0x00080000 # macro +PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK = 0x00100000 # macro +PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +PCTL_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +PCTL_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +PCTL_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +PCTL_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +PCTL_RESERVED_0__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_0__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_0__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_0__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_0__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_0__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_0__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_0__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_0__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_0__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_0__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_0__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_0__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_0__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_0__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_0__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_0__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_0__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_0__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_0__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_1__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_1__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_1__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_1__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_1__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_1__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_1__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_1__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_1__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_1__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_1__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_1__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_1__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_1__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_1__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_1__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_1__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_1__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_1__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_1__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_2__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_2__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_2__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_2__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_2__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_2__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_2__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_2__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_2__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_2__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_2__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_2__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_2__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_2__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_2__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_2__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_2__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_2__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_2__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_2__BIT0_MASK = 0x80000000 # macro +PCTL_RESERVED_3__WORD__SHIFT = 0x0 # macro +PCTL_RESERVED_3__BYTE__SHIFT = 0x10 # macro +PCTL_RESERVED_3__BIT7__SHIFT = 0x18 # macro +PCTL_RESERVED_3__BIT6__SHIFT = 0x19 # macro +PCTL_RESERVED_3__BIT5__SHIFT = 0x1a # macro +PCTL_RESERVED_3__BIT4__SHIFT = 0x1b # macro +PCTL_RESERVED_3__BIT3__SHIFT = 0x1c # macro +PCTL_RESERVED_3__BIT2__SHIFT = 0x1d # macro +PCTL_RESERVED_3__BIT1__SHIFT = 0x1e # macro +PCTL_RESERVED_3__BIT0__SHIFT = 0x1f # macro +PCTL_RESERVED_3__WORD_MASK = 0x0000FFFF # macro +PCTL_RESERVED_3__BYTE_MASK = 0x00FF0000 # macro +PCTL_RESERVED_3__BIT7_MASK = 0x01000000 # macro +PCTL_RESERVED_3__BIT6_MASK = 0x02000000 # macro +PCTL_RESERVED_3__BIT5_MASK = 0x04000000 # macro +PCTL_RESERVED_3__BIT4_MASK = 0x08000000 # macro +PCTL_RESERVED_3__BIT3_MASK = 0x10000000 # macro +PCTL_RESERVED_3__BIT2_MASK = 0x20000000 # macro +PCTL_RESERVED_3__BIT1_MASK = 0x40000000 # macro +PCTL_RESERVED_3__BIT0_MASK = 0x80000000 # macro +MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT = 0x1 # macro +MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK = 0x00000002 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT = 0x0 # macro +MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT = 0x1 # macro +MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT = 0x2 # macro +MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT = 0x4 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT = 0x8 # macro +MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0x9 # macro +MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT = 0xa # macro +MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT = 0xb # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT = 0xc # macro +MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT = 0xf # macro +MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT = 0x12 # macro +MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT = 0x13 # macro +MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT = 0x15 # macro +MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT = 0x1a # macro +MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK = 0x00000001 # macro +MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK = 0x00000002 # macro +MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK = 0x0000000C # macro +MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK = 0x00000030 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK = 0x00000100 # macro +MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000200 # macro +MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK = 0x00000400 # macro +MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK = 0x00000800 # macro +MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK = 0x00007000 # macro +MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK = 0x00038000 # macro +MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK = 0x00040000 # macro +MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK = 0x00180000 # macro +MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK = 0x03E00000 # macro +MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK = 0x0C000000 # macro +MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT = 0x0 # macro +MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT = 0x1 # macro +MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT = 0x15 # macro +MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT = 0x16 # macro +MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT = 0x17 # macro +MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT = 0x1a # macro +MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT = 0x1c # macro +MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK = 0x00000001 # macro +MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK = 0x00000002 # macro +MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK = 0x00200000 # macro +MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK = 0x00400000 # macro +MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK = 0x03800000 # macro +MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK = 0x0C000000 # macro +MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK = 0x70000000 # macro +MMVM_L2_CNTL3__BANK_SELECT__SHIFT = 0x0 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT = 0x6 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT = 0x8 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0xf # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT = 0x14 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT = 0x15 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT = 0x18 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT = 0x1c # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT = 0x1d # macro +MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT = 0x1e # macro +MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT = 0x1f # macro +MMVM_L2_CNTL3__BANK_SELECT_MASK = 0x0000003F # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK = 0x000000C0 # macro +MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK = 0x00001F00 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000F8000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK = 0x00100000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK = 0x00E00000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK = 0x0F000000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK = 0x10000000 # macro +MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK = 0x20000000 # macro +MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK = 0x40000000 # macro +MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK = 0x80000000 # macro +MMVM_L2_STATUS__L2_BUSY__SHIFT = 0x0 # macro +MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT = 0x1 # macro +MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x11 # macro +MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT = 0x12 # macro +MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT = 0x13 # macro +MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT = 0x14 # macro +MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT = 0x15 # macro +MMVM_L2_STATUS__L2_BUSY_MASK = 0x00000001 # macro +MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK = 0x0001FFFE # macro +MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK = 0x00020000 # macro +MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK = 0x00040000 # macro +MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK = 0x00080000 # macro +MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK = 0x00100000 # macro +MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK = 0x00200000 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT = 0x1 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT = 0x2 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK = 0x00000001 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK = 0x00000002 # macro +MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK = 0x000000FC # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT = 0x0 # macro +MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT = 0x8 # macro +MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK = 0x000000FF # macro +MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK = 0x0000FF00 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT = 0x1 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x2 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x3 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x4 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x5 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x6 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x7 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x8 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x9 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xb # macro +MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0xd # macro +MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x1d # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT = 0x1e # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT = 0x1f # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x00000001 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK = 0x00000002 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000004 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000008 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000010 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000020 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000040 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000080 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000100 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000200 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000800 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x1FFFE000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0x20000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK = 0x40000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK = 0x80000000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT = 0x10 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT = 0x11 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT = 0x12 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT = 0x13 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x0000FFFF # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK = 0x00010000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK = 0x00020000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK = 0x00040000 # macro +MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK = 0x00080000 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT = 0x1 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT = 0x4 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT = 0x8 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT = 0x9 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT = 0x12 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT = 0x13 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT = 0x14 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT = 0x18 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT = 0x19 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT = 0x1d # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK = 0x00000001 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK = 0x0000000E # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK = 0x000000F0 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK = 0x00000100 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK = 0x0003FE00 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK = 0x00040000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK = 0x00080000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK = 0x00F00000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK = 0x01000000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK = 0x1E000000 # macro +MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK = 0x20000000 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT = 0x0 # macro +MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK = 0xFFFFFFFF # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK = 0x0000000F # macro +MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT = 0x0 # macro +MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT = 0x6 # macro +MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT = 0x7 # macro +MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x8 # macro +MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT = 0x12 # macro +MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT = 0x1c # macro +MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT = 0x1d # macro +MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT = 0x1e # macro +MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT = 0x1f # macro +MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK = 0x0000003F # macro +MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK = 0x00000040 # macro +MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK = 0x00000080 # macro +MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0003FF00 # macro +MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK = 0x0FFC0000 # macro +MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK = 0x10000000 # macro +MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK = 0x20000000 # macro +MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK = 0x40000000 # macro +MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK = 0x80000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT = 0x0 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT = 0x1 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT = 0x2 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT = 0x3 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT = 0x4 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT = 0x5 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT = 0x6 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT = 0x7 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT = 0x8 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT = 0x9 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT = 0xa # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT = 0xb # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT = 0xc # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT = 0xd # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT = 0xe # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT = 0xf # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT = 0x10 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT = 0x11 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT = 0x12 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT = 0x13 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT = 0x14 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT = 0x15 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT = 0x16 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT = 0x17 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT = 0x18 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT = 0x19 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT = 0x1a # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT = 0x1b # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT = 0x1c # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT = 0x1d # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT = 0x1e # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT = 0x1f # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK = 0x00000001 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK = 0x00000002 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK = 0x00000004 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK = 0x00000008 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK = 0x00000010 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK = 0x00000020 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK = 0x00000040 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK = 0x00000080 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK = 0x00000100 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK = 0x00000200 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK = 0x00000400 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK = 0x00000800 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK = 0x00001000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK = 0x00002000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK = 0x00004000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK = 0x00008000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK = 0x00010000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK = 0x00020000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK = 0x00040000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK = 0x00080000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK = 0x00100000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK = 0x00200000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK = 0x00400000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK = 0x00800000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK = 0x01000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK = 0x02000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK = 0x04000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK = 0x08000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK = 0x10000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK = 0x20000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK = 0x40000000 # macro +MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK = 0x80000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT = 0x14 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK = 0x00100000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT = 0xa # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT = 0x14 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT = 0x18 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT = 0x19 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT = 0x1a # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK = 0x000001FF # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK = 0x0007FC00 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK = 0x00100000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK = 0x01000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK = 0x02000000 # macro +MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK = 0x7C000000 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT = 0x0 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT = 0x1 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT = 0x2 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT = 0x3 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT = 0x4 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT = 0x5 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT = 0x6 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT = 0x9 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT = 0xc # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK = 0x00000001 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK = 0x00000002 # macro +MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK = 0x00000004 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK = 0x00000008 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK = 0x00000010 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK = 0x00000020 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK = 0x000001C0 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK = 0x00000E00 # macro +MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK = 0x0000F000 # macro +MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT = 0x5 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT = 0xe # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT = 0xf # macro +MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT = 0x10 # macro +MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT = 0x11 # macro +MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK = 0x00003FE0 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK = 0x00004000 # macro +MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK = 0x00008000 # macro +MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK = 0x00010000 # macro +MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK = 0x00020000 # macro +MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT = 0x0 # macro +MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT = 0x1 # macro +MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK = 0x00000001 # macro +MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK = 0x000003FE # macro +MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT = 0x0 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT = 0x1 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT = 0x4 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT = 0x8 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT = 0xc # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT = 0x10 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK = 0x00000001 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK = 0x00000002 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK = 0x000000F0 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK = 0x00000F00 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK = 0x0000F000 # macro +MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK = 0xFFFF0000 # macro +MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT = 0x0 # macro +MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK = 0xFFFFFFFF # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK = 0xFFFFFFFF # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT = 0x4 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT = 0x8 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT = 0xc # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT = 0xd # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT = 0xf # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT = 0x10 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT = 0x11 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT = 0x12 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT = 0x1e # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK = 0x0000000F # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK = 0x000000F0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK = 0x00000F00 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK = 0x00001000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK = 0x00006000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK = 0x00008000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK = 0x00010000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK = 0x00020000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK = 0x07FC0000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK = 0x40000000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK = 0xFFFFFFFF # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT = 0x4 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT = 0x7 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT = 0xd # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT = 0xe # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT = 0xf # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT = 0x10 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT = 0x11 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT = 0x12 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT = 0x15 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT = 0x16 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT = 0x18 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT = 0x1f # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK = 0x0000000F # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK = 0x00000070 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK = 0x00001F80 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK = 0x00002000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK = 0x00004000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK = 0x00008000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK = 0x00010000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK = 0x00020000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK = 0x001C0000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK = 0x00200000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK = 0x00C00000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK = 0x01000000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK = 0x80000000 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT = 0x0 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT = 0x4 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT = 0x8 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT = 0xc # macro +MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK = 0x0000000F # macro +MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK = 0x000000F0 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK = 0x00000F00 # macro +MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK = 0x0000F000 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK = 0x00000400 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK = 0x00000400 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT = 0x0 # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT = 0xa # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK = 0x000003FF # macro +MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK = 0x00000400 # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT = 0x0 # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT = 0xa # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK = 0x000003FF # macro +MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK = 0x00000400 # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT = 0x0 # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT = 0xa # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK = 0x000003FF # macro +MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK = 0x00000400 # macro +MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT = 0x0 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT = 0x1 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT = 0x3 # macro +MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT = 0x7 # macro +MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT = 0x8 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x9 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xa # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xb # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xc # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xd # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0xe # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0xf # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x10 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x11 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x12 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x13 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x14 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x15 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x16 # macro +MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT = 0x17 # macro +MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT = 0x18 # macro +MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK = 0x00000001 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK = 0x00000006 # macro +MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK = 0x00000078 # macro +MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK = 0x00000080 # macro +MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK = 0x00000100 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000200 # macro +MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00000400 # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00000800 # macro +MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00001000 # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00002000 # macro +MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00004000 # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00008000 # macro +MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00010000 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00020000 # macro +MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00040000 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00080000 # macro +MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00100000 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00200000 # macro +MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x00400000 # macro +MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK = 0x00800000 # macro +MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK = 0x01000000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT = 0x0 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT = 0x1 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT = 0x2 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT = 0x3 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT = 0x4 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT = 0x5 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT = 0x6 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT = 0x7 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT = 0x8 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT = 0x9 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT = 0xa # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT = 0xb # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT = 0xc # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT = 0xd # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT = 0xe # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT = 0xf # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK = 0x00000001 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK = 0x00000002 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK = 0x00000004 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK = 0x00000008 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK = 0x00000010 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK = 0x00000020 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK = 0x00000040 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK = 0x00000080 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK = 0x00000100 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK = 0x00000200 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK = 0x00000400 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK = 0x00000800 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK = 0x00001000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK = 0x00002000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK = 0x00004000 # macro +MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK = 0x00008000 # macro +MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT = 0x13 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT = 0x14 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT = 0x15 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT = 0x16 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT = 0x17 # macro +MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT = 0x18 # macro +MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT = 0x19 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT = 0x1a # macro +MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK = 0x00070000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK = 0x00080000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK = 0x00100000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK = 0x00200000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK = 0x00400000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK = 0x00800000 # macro +MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK = 0x01000000 # macro +MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK = 0x02000000 # macro +MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK = 0x04000000 # macro +MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT = 0x10 # macro +MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK = 0x0000FFFF # macro +MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK = 0x00010000 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT = 0x1 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK = 0x00000001 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK = 0xFFFFFFFE # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT = 0x0 # macro +MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK = 0x0000001F # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK = 0xFFFFFFFF # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT = 0x0 # macro +MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK = 0x0000000F # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT = 0x0 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT = 0x5 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT = 0xa # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK = 0x0000001F # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK = 0x000003E0 # macro +MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK = 0x0000FC00 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT = 0x1c # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT = 0x1d # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK = 0x10000000 # macro +MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK = 0x20000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT = 0x1c # macro +MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT = 0x1d # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK = 0x000000FF # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK = 0x0F000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK = 0x10000000 # macro +MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK = 0x20000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT = 0x8 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT = 0x10 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT = 0x18 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT = 0x19 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT = 0x1a # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK = 0x0000000F # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK = 0x0000FF00 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK = 0x00FF0000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK = 0x01000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK = 0x02000000 # macro +MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK = 0x04000000 # macro +MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK = 0xFFFFFFFF # macro +MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT = 0x0 # macro +MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT = 0x10 # macro +MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK = 0x0000FFFF # macro +MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT = 0x0 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT = 0x10 # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK = 0x0000FFFF # macro +MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK = 0xFFFF0000 # macro +MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT = 0x0 # macro +MMMC_VM_FB_OFFSET__FB_OFFSET_MASK = 0x00FFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK = 0xFFFFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK = 0x0000000F # macro +MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT = 0x0 # macro +MMMC_VM_STEERING__DEFAULT_STEERING_MASK = 0x00000003 # macro +MMMC_MEM_POWER_LS__LS_SETUP__SHIFT = 0x0 # macro +MMMC_MEM_POWER_LS__LS_HOLD__SHIFT = 0x6 # macro +MMMC_MEM_POWER_LS__LS_SETUP_MASK = 0x0000003F # macro +MMMC_MEM_POWER_LS__LS_HOLD_MASK = 0x00000FC0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT = 0x0 # macro +MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT = 0x1 # macro +MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT = 0x2 # macro +MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT = 0x4 # macro +MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT = 0x5 # macro +MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT = 0x6 # macro +MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK = 0x00000001 # macro +MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK = 0x00000002 # macro +MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK = 0x0000000C # macro +MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK = 0x00000010 # macro +MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK = 0x00000020 # macro +MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK = 0x000000C0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK = 0x000FFFFF # macro +MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT = 0x0 # macro +MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK = 0x00000001 # macro +MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT = 0x0 # macro +MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT = 0x5 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT = 0xd # macro +MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT = 0x1e # macro +MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT = 0x1f # macro +MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK = 0x0000001F # macro +MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK = 0x00001FE0 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK = 0x1FFFE000 # macro +MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK = 0x40000000 # macro +MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK = 0x80000000 # macro +MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT = 0x0 # macro +MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT = 0x5 # macro +MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK = 0x0000001F # macro +MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK = 0x00000020 # macro +MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT = 0x0 # macro +MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT = 0x1 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT = 0x2 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT = 0x3 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT = 0x4 # macro +MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK = 0x00000001 # macro +MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK = 0x00000002 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK = 0x00000004 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK = 0x00000008 # macro +MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK = 0x00000010 # macro +MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT = 0x0 # macro +MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK = 0xFFFFFFFF # macro +MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT = 0x0 # macro +MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK = 0xFFFFFFFF # macro +MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT = 0x0 # macro +MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK = 0x00FFFFFF # macro +MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT = 0x0 # macro +MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_TOP__AGP_TOP__SHIFT = 0x0 # macro +MMMC_VM_AGP_TOP__AGP_TOP_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_BOT__AGP_BOT__SHIFT = 0x0 # macro +MMMC_VM_AGP_BOT__AGP_BOT_MASK = 0x00FFFFFF # macro +MMMC_VM_AGP_BASE__AGP_BASE__SHIFT = 0x0 # macro +MMMC_VM_AGP_BASE__AGP_BASE_MASK = 0x00FFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT = 0x0 # macro +MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK = 0x3FFFFFFF # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT = 0x0 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT = 0x3 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT = 0x5 # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT = 0x6 # macro +MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT = 0x7 # macro +MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT = 0xb # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK = 0x00000001 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK = 0x00000018 # macro +MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK = 0x00000020 # macro +MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK = 0x00000040 # macro +MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK = 0x00000780 # macro +MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK = 0x00003800 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT = 0x0 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT = 0x10 # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK = 0x0000FFFF # macro +MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK = 0xFFFF0000 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT = 0x0 # macro +MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK = 0x00000001 # macro +MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT = 0x0 # macro +MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK = 0xFFFFFFFF # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT = 0x0 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT = 0x4 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT = 0x5 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT = 0x6 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK = 0x0000000F # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK = 0x00000010 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK = 0x00000020 # macro +MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK = 0x00000040 # macro +__all__ = \ + ['DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK', + 'DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK', + 'DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK', + 'DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT', + 'DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK', + 'DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT', + 'DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK', + 'DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT', + 'DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__SWAP_CTL_MASK', + 'DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT', + 'DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK', + 'DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT', + 'DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK', + 'DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT', + 'DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK', + 'DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT', + 'DAGB0_DAGB_DLY__CLI_MASK', 'DAGB0_DAGB_DLY__CLI__SHIFT', + 'DAGB0_DAGB_DLY__DLY_MASK', 'DAGB0_DAGB_DLY__DLY__SHIFT', + 'DAGB0_DAGB_DLY__POS_MASK', 'DAGB0_DAGB_DLY__POS__SHIFT', + 'DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK', + 'DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT', + 'DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK', + 'DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__CID_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS0__VALID_MASK', + 'DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK', + 'DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__CLI_TAG_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__CLI_TAG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__IO_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SDP_TAG_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SDP_TAG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__VFID_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS2__VF_MASK', + 'DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__EXT_FATAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__INT_FATAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__INT_FATAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__NACK_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__OP_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__RO_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__SECLEVEL_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__SECLEVEL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__UNITID_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__UNITID__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK', + 'DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__CHAIN_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__CHAIN__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__DROP_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__DROP__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__FULL_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__FULL__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__NOALLOC_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__NOALLOC__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__PRI_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__PRI__SHIFT', + 'DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE_MASK', + 'DAGB0_FATAL_ERROR_STATUS4__WADDR_PHASE__SHIFT', + 'DAGB0_FIFO_EMPTY__EMPTY_MASK', 'DAGB0_FIFO_EMPTY__EMPTY__SHIFT', + 'DAGB0_FIFO_FULL__FULL_MASK', 'DAGB0_FIFO_FULL__FULL__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK', + 'DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT', + 'DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK', + 'DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT', + 'DAGB0_L1TLB_REG_RW__RESERVE_MASK', + 'DAGB0_L1TLB_REG_RW__RESERVE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK', + 'DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK', + 'DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI0__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI0__MAX_BW_MASK', + 'DAGB0_RDCLI0__MAX_BW__SHIFT', 'DAGB0_RDCLI0__MAX_OSD_MASK', + 'DAGB0_RDCLI0__MAX_OSD__SHIFT', + 'DAGB0_RDCLI0__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI0__MIN_BW_MASK', + 'DAGB0_RDCLI0__MIN_BW__SHIFT', + 'DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI0__URG_HIGH_MASK', 'DAGB0_RDCLI0__URG_HIGH__SHIFT', + 'DAGB0_RDCLI0__URG_LOW_MASK', 'DAGB0_RDCLI0__URG_LOW__SHIFT', + 'DAGB0_RDCLI0__VIRT_CHAN_MASK', 'DAGB0_RDCLI0__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI10__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI10__MAX_BW_MASK', 'DAGB0_RDCLI10__MAX_BW__SHIFT', + 'DAGB0_RDCLI10__MAX_OSD_MASK', 'DAGB0_RDCLI10__MAX_OSD__SHIFT', + 'DAGB0_RDCLI10__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI10__MIN_BW_MASK', 'DAGB0_RDCLI10__MIN_BW__SHIFT', + 'DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI10__URG_HIGH_MASK', 'DAGB0_RDCLI10__URG_HIGH__SHIFT', + 'DAGB0_RDCLI10__URG_LOW_MASK', 'DAGB0_RDCLI10__URG_LOW__SHIFT', + 'DAGB0_RDCLI10__VIRT_CHAN_MASK', + 'DAGB0_RDCLI10__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI11__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI11__MAX_BW_MASK', 'DAGB0_RDCLI11__MAX_BW__SHIFT', + 'DAGB0_RDCLI11__MAX_OSD_MASK', 'DAGB0_RDCLI11__MAX_OSD__SHIFT', + 'DAGB0_RDCLI11__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI11__MIN_BW_MASK', 'DAGB0_RDCLI11__MIN_BW__SHIFT', + 'DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI11__URG_HIGH_MASK', 'DAGB0_RDCLI11__URG_HIGH__SHIFT', + 'DAGB0_RDCLI11__URG_LOW_MASK', 'DAGB0_RDCLI11__URG_LOW__SHIFT', + 'DAGB0_RDCLI11__VIRT_CHAN_MASK', + 'DAGB0_RDCLI11__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI12__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI12__MAX_BW_MASK', 'DAGB0_RDCLI12__MAX_BW__SHIFT', + 'DAGB0_RDCLI12__MAX_OSD_MASK', 'DAGB0_RDCLI12__MAX_OSD__SHIFT', + 'DAGB0_RDCLI12__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI12__MIN_BW_MASK', 'DAGB0_RDCLI12__MIN_BW__SHIFT', + 'DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI12__URG_HIGH_MASK', 'DAGB0_RDCLI12__URG_HIGH__SHIFT', + 'DAGB0_RDCLI12__URG_LOW_MASK', 'DAGB0_RDCLI12__URG_LOW__SHIFT', + 'DAGB0_RDCLI12__VIRT_CHAN_MASK', + 'DAGB0_RDCLI12__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI13__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI13__MAX_BW_MASK', 'DAGB0_RDCLI13__MAX_BW__SHIFT', + 'DAGB0_RDCLI13__MAX_OSD_MASK', 'DAGB0_RDCLI13__MAX_OSD__SHIFT', + 'DAGB0_RDCLI13__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI13__MIN_BW_MASK', 'DAGB0_RDCLI13__MIN_BW__SHIFT', + 'DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI13__URG_HIGH_MASK', 'DAGB0_RDCLI13__URG_HIGH__SHIFT', + 'DAGB0_RDCLI13__URG_LOW_MASK', 'DAGB0_RDCLI13__URG_LOW__SHIFT', + 'DAGB0_RDCLI13__VIRT_CHAN_MASK', + 'DAGB0_RDCLI13__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI14__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI14__MAX_BW_MASK', 'DAGB0_RDCLI14__MAX_BW__SHIFT', + 'DAGB0_RDCLI14__MAX_OSD_MASK', 'DAGB0_RDCLI14__MAX_OSD__SHIFT', + 'DAGB0_RDCLI14__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI14__MIN_BW_MASK', 'DAGB0_RDCLI14__MIN_BW__SHIFT', + 'DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI14__URG_HIGH_MASK', 'DAGB0_RDCLI14__URG_HIGH__SHIFT', + 'DAGB0_RDCLI14__URG_LOW_MASK', 'DAGB0_RDCLI14__URG_LOW__SHIFT', + 'DAGB0_RDCLI14__VIRT_CHAN_MASK', + 'DAGB0_RDCLI14__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI15__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI15__MAX_BW_MASK', 'DAGB0_RDCLI15__MAX_BW__SHIFT', + 'DAGB0_RDCLI15__MAX_OSD_MASK', 'DAGB0_RDCLI15__MAX_OSD__SHIFT', + 'DAGB0_RDCLI15__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI15__MIN_BW_MASK', 'DAGB0_RDCLI15__MIN_BW__SHIFT', + 'DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI15__URG_HIGH_MASK', 'DAGB0_RDCLI15__URG_HIGH__SHIFT', + 'DAGB0_RDCLI15__URG_LOW_MASK', 'DAGB0_RDCLI15__URG_LOW__SHIFT', + 'DAGB0_RDCLI15__VIRT_CHAN_MASK', + 'DAGB0_RDCLI15__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI16__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI16__MAX_BW_MASK', 'DAGB0_RDCLI16__MAX_BW__SHIFT', + 'DAGB0_RDCLI16__MAX_OSD_MASK', 'DAGB0_RDCLI16__MAX_OSD__SHIFT', + 'DAGB0_RDCLI16__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI16__MIN_BW_MASK', 'DAGB0_RDCLI16__MIN_BW__SHIFT', + 'DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI16__URG_HIGH_MASK', 'DAGB0_RDCLI16__URG_HIGH__SHIFT', + 'DAGB0_RDCLI16__URG_LOW_MASK', 'DAGB0_RDCLI16__URG_LOW__SHIFT', + 'DAGB0_RDCLI16__VIRT_CHAN_MASK', + 'DAGB0_RDCLI16__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI17__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI17__MAX_BW_MASK', 'DAGB0_RDCLI17__MAX_BW__SHIFT', + 'DAGB0_RDCLI17__MAX_OSD_MASK', 'DAGB0_RDCLI17__MAX_OSD__SHIFT', + 'DAGB0_RDCLI17__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI17__MIN_BW_MASK', 'DAGB0_RDCLI17__MIN_BW__SHIFT', + 'DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI17__URG_HIGH_MASK', 'DAGB0_RDCLI17__URG_HIGH__SHIFT', + 'DAGB0_RDCLI17__URG_LOW_MASK', 'DAGB0_RDCLI17__URG_LOW__SHIFT', + 'DAGB0_RDCLI17__VIRT_CHAN_MASK', + 'DAGB0_RDCLI17__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI18__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI18__MAX_BW_MASK', 'DAGB0_RDCLI18__MAX_BW__SHIFT', + 'DAGB0_RDCLI18__MAX_OSD_MASK', 'DAGB0_RDCLI18__MAX_OSD__SHIFT', + 'DAGB0_RDCLI18__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI18__MIN_BW_MASK', 'DAGB0_RDCLI18__MIN_BW__SHIFT', + 'DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI18__URG_HIGH_MASK', 'DAGB0_RDCLI18__URG_HIGH__SHIFT', + 'DAGB0_RDCLI18__URG_LOW_MASK', 'DAGB0_RDCLI18__URG_LOW__SHIFT', + 'DAGB0_RDCLI18__VIRT_CHAN_MASK', + 'DAGB0_RDCLI18__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI19__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI19__MAX_BW_MASK', 'DAGB0_RDCLI19__MAX_BW__SHIFT', + 'DAGB0_RDCLI19__MAX_OSD_MASK', 'DAGB0_RDCLI19__MAX_OSD__SHIFT', + 'DAGB0_RDCLI19__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI19__MIN_BW_MASK', 'DAGB0_RDCLI19__MIN_BW__SHIFT', + 'DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI19__URG_HIGH_MASK', 'DAGB0_RDCLI19__URG_HIGH__SHIFT', + 'DAGB0_RDCLI19__URG_LOW_MASK', 'DAGB0_RDCLI19__URG_LOW__SHIFT', + 'DAGB0_RDCLI19__VIRT_CHAN_MASK', + 'DAGB0_RDCLI19__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI1__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI1__MAX_BW_MASK', + 'DAGB0_RDCLI1__MAX_BW__SHIFT', 'DAGB0_RDCLI1__MAX_OSD_MASK', + 'DAGB0_RDCLI1__MAX_OSD__SHIFT', + 'DAGB0_RDCLI1__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI1__MIN_BW_MASK', + 'DAGB0_RDCLI1__MIN_BW__SHIFT', + 'DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI1__URG_HIGH_MASK', 'DAGB0_RDCLI1__URG_HIGH__SHIFT', + 'DAGB0_RDCLI1__URG_LOW_MASK', 'DAGB0_RDCLI1__URG_LOW__SHIFT', + 'DAGB0_RDCLI1__VIRT_CHAN_MASK', 'DAGB0_RDCLI1__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI20__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI20__MAX_BW_MASK', 'DAGB0_RDCLI20__MAX_BW__SHIFT', + 'DAGB0_RDCLI20__MAX_OSD_MASK', 'DAGB0_RDCLI20__MAX_OSD__SHIFT', + 'DAGB0_RDCLI20__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI20__MIN_BW_MASK', 'DAGB0_RDCLI20__MIN_BW__SHIFT', + 'DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI20__URG_HIGH_MASK', 'DAGB0_RDCLI20__URG_HIGH__SHIFT', + 'DAGB0_RDCLI20__URG_LOW_MASK', 'DAGB0_RDCLI20__URG_LOW__SHIFT', + 'DAGB0_RDCLI20__VIRT_CHAN_MASK', + 'DAGB0_RDCLI20__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI21__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI21__MAX_BW_MASK', 'DAGB0_RDCLI21__MAX_BW__SHIFT', + 'DAGB0_RDCLI21__MAX_OSD_MASK', 'DAGB0_RDCLI21__MAX_OSD__SHIFT', + 'DAGB0_RDCLI21__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI21__MIN_BW_MASK', 'DAGB0_RDCLI21__MIN_BW__SHIFT', + 'DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI21__URG_HIGH_MASK', 'DAGB0_RDCLI21__URG_HIGH__SHIFT', + 'DAGB0_RDCLI21__URG_LOW_MASK', 'DAGB0_RDCLI21__URG_LOW__SHIFT', + 'DAGB0_RDCLI21__VIRT_CHAN_MASK', + 'DAGB0_RDCLI21__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI22__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI22__MAX_BW_MASK', 'DAGB0_RDCLI22__MAX_BW__SHIFT', + 'DAGB0_RDCLI22__MAX_OSD_MASK', 'DAGB0_RDCLI22__MAX_OSD__SHIFT', + 'DAGB0_RDCLI22__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI22__MIN_BW_MASK', 'DAGB0_RDCLI22__MIN_BW__SHIFT', + 'DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI22__URG_HIGH_MASK', 'DAGB0_RDCLI22__URG_HIGH__SHIFT', + 'DAGB0_RDCLI22__URG_LOW_MASK', 'DAGB0_RDCLI22__URG_LOW__SHIFT', + 'DAGB0_RDCLI22__VIRT_CHAN_MASK', + 'DAGB0_RDCLI22__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI23__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI23__MAX_BW_MASK', 'DAGB0_RDCLI23__MAX_BW__SHIFT', + 'DAGB0_RDCLI23__MAX_OSD_MASK', 'DAGB0_RDCLI23__MAX_OSD__SHIFT', + 'DAGB0_RDCLI23__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RDCLI23__MIN_BW_MASK', 'DAGB0_RDCLI23__MIN_BW__SHIFT', + 'DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI23__URG_HIGH_MASK', 'DAGB0_RDCLI23__URG_HIGH__SHIFT', + 'DAGB0_RDCLI23__URG_LOW_MASK', 'DAGB0_RDCLI23__URG_LOW__SHIFT', + 'DAGB0_RDCLI23__VIRT_CHAN_MASK', + 'DAGB0_RDCLI23__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI2__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI2__MAX_BW_MASK', + 'DAGB0_RDCLI2__MAX_BW__SHIFT', 'DAGB0_RDCLI2__MAX_OSD_MASK', + 'DAGB0_RDCLI2__MAX_OSD__SHIFT', + 'DAGB0_RDCLI2__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI2__MIN_BW_MASK', + 'DAGB0_RDCLI2__MIN_BW__SHIFT', + 'DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI2__URG_HIGH_MASK', 'DAGB0_RDCLI2__URG_HIGH__SHIFT', + 'DAGB0_RDCLI2__URG_LOW_MASK', 'DAGB0_RDCLI2__URG_LOW__SHIFT', + 'DAGB0_RDCLI2__VIRT_CHAN_MASK', 'DAGB0_RDCLI2__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI3__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI3__MAX_BW_MASK', + 'DAGB0_RDCLI3__MAX_BW__SHIFT', 'DAGB0_RDCLI3__MAX_OSD_MASK', + 'DAGB0_RDCLI3__MAX_OSD__SHIFT', + 'DAGB0_RDCLI3__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI3__MIN_BW_MASK', + 'DAGB0_RDCLI3__MIN_BW__SHIFT', + 'DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI3__URG_HIGH_MASK', 'DAGB0_RDCLI3__URG_HIGH__SHIFT', + 'DAGB0_RDCLI3__URG_LOW_MASK', 'DAGB0_RDCLI3__URG_LOW__SHIFT', + 'DAGB0_RDCLI3__VIRT_CHAN_MASK', 'DAGB0_RDCLI3__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI4__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI4__MAX_BW_MASK', + 'DAGB0_RDCLI4__MAX_BW__SHIFT', 'DAGB0_RDCLI4__MAX_OSD_MASK', + 'DAGB0_RDCLI4__MAX_OSD__SHIFT', + 'DAGB0_RDCLI4__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI4__MIN_BW_MASK', + 'DAGB0_RDCLI4__MIN_BW__SHIFT', + 'DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI4__URG_HIGH_MASK', 'DAGB0_RDCLI4__URG_HIGH__SHIFT', + 'DAGB0_RDCLI4__URG_LOW_MASK', 'DAGB0_RDCLI4__URG_LOW__SHIFT', + 'DAGB0_RDCLI4__VIRT_CHAN_MASK', 'DAGB0_RDCLI4__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI5__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI5__MAX_BW_MASK', + 'DAGB0_RDCLI5__MAX_BW__SHIFT', 'DAGB0_RDCLI5__MAX_OSD_MASK', + 'DAGB0_RDCLI5__MAX_OSD__SHIFT', + 'DAGB0_RDCLI5__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI5__MIN_BW_MASK', + 'DAGB0_RDCLI5__MIN_BW__SHIFT', + 'DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI5__URG_HIGH_MASK', 'DAGB0_RDCLI5__URG_HIGH__SHIFT', + 'DAGB0_RDCLI5__URG_LOW_MASK', 'DAGB0_RDCLI5__URG_LOW__SHIFT', + 'DAGB0_RDCLI5__VIRT_CHAN_MASK', 'DAGB0_RDCLI5__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI6__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI6__MAX_BW_MASK', + 'DAGB0_RDCLI6__MAX_BW__SHIFT', 'DAGB0_RDCLI6__MAX_OSD_MASK', + 'DAGB0_RDCLI6__MAX_OSD__SHIFT', + 'DAGB0_RDCLI6__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI6__MIN_BW_MASK', + 'DAGB0_RDCLI6__MIN_BW__SHIFT', + 'DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI6__URG_HIGH_MASK', 'DAGB0_RDCLI6__URG_HIGH__SHIFT', + 'DAGB0_RDCLI6__URG_LOW_MASK', 'DAGB0_RDCLI6__URG_LOW__SHIFT', + 'DAGB0_RDCLI6__VIRT_CHAN_MASK', 'DAGB0_RDCLI6__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI7__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI7__MAX_BW_MASK', + 'DAGB0_RDCLI7__MAX_BW__SHIFT', 'DAGB0_RDCLI7__MAX_OSD_MASK', + 'DAGB0_RDCLI7__MAX_OSD__SHIFT', + 'DAGB0_RDCLI7__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI7__MIN_BW_MASK', + 'DAGB0_RDCLI7__MIN_BW__SHIFT', + 'DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI7__URG_HIGH_MASK', 'DAGB0_RDCLI7__URG_HIGH__SHIFT', + 'DAGB0_RDCLI7__URG_LOW_MASK', 'DAGB0_RDCLI7__URG_LOW__SHIFT', + 'DAGB0_RDCLI7__VIRT_CHAN_MASK', 'DAGB0_RDCLI7__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI8__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI8__MAX_BW_MASK', + 'DAGB0_RDCLI8__MAX_BW__SHIFT', 'DAGB0_RDCLI8__MAX_OSD_MASK', + 'DAGB0_RDCLI8__MAX_OSD__SHIFT', + 'DAGB0_RDCLI8__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI8__MIN_BW_MASK', + 'DAGB0_RDCLI8__MIN_BW__SHIFT', + 'DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI8__URG_HIGH_MASK', 'DAGB0_RDCLI8__URG_HIGH__SHIFT', + 'DAGB0_RDCLI8__URG_LOW_MASK', 'DAGB0_RDCLI8__URG_LOW__SHIFT', + 'DAGB0_RDCLI8__VIRT_CHAN_MASK', 'DAGB0_RDCLI8__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_RDCLI9__MAX_BW_ENABLE_MASK', + 'DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB0_RDCLI9__MAX_BW_MASK', + 'DAGB0_RDCLI9__MAX_BW__SHIFT', 'DAGB0_RDCLI9__MAX_OSD_MASK', + 'DAGB0_RDCLI9__MAX_OSD__SHIFT', + 'DAGB0_RDCLI9__MIN_BW_ENABLE_MASK', + 'DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB0_RDCLI9__MIN_BW_MASK', + 'DAGB0_RDCLI9__MIN_BW__SHIFT', + 'DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RDCLI9__URG_HIGH_MASK', 'DAGB0_RDCLI9__URG_HIGH__SHIFT', + 'DAGB0_RDCLI9__URG_LOW_MASK', 'DAGB0_RDCLI9__URG_LOW__SHIFT', + 'DAGB0_RDCLI9__VIRT_CHAN_MASK', 'DAGB0_RDCLI9__VIRT_CHAN__SHIFT', + 'DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_ASK_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_GO_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB0_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_RDCLI_OARB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_OSD_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_RDCLI_TLB_PENDING__BUSY_MASK', + 'DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB0_RD_ADDR_DAGB__WHOAMI_MASK', + 'DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK', + 'DAGB0_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT', + 'DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK', + 'DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT', + 'DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB0_RD_CNTL__SHARE_VC_NUM_MASK', + 'DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT', + 'DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB0_RD_CREDITS_FULL__FULL_MASK', + 'DAGB0_RD_CREDITS_FULL__FULL__SHIFT', + 'DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK', + 'DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB0_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB0__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB1_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB1__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB2_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB2__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB3_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB3__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB4_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB4__SHIFT', + 'DAGB0_RD_TLB_CREDIT__TLB5_MASK', + 'DAGB0_RD_TLB_CREDIT__TLB5__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC0_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC1_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC2_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC3_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC4_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_BW_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB0_RD_VC5_CNTL__MAX_OSD_MASK', + 'DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__MIN_BW_MASK', + 'DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_RESERVE1__RESERVE_MASK', 'DAGB0_RESERVE1__RESERVE__SHIFT', + 'DAGB0_RESERVE2__RESERVE_MASK', 'DAGB0_RESERVE2__RESERVE__SHIFT', + 'DAGB0_RESERVE3__RESERVE_MASK', 'DAGB0_RESERVE3__RESERVE__SHIFT', + 'DAGB0_RESERVE4__RESERVE_MASK', 'DAGB0_RESERVE4__RESERVE__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK', + 'DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK', + 'DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK', + 'DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK', + 'DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT', + 'DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK', + 'DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK', + 'DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK', + 'DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'DAGB0_SDP_CREDITS__TAG_LIMIT_MASK', + 'DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'DAGB0_SDP_ENABLE__ENABLE_MASK', + 'DAGB0_SDP_ENABLE__ENABLE__SHIFT', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK', + 'DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT', + 'DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK', + 'DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT', + 'DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK', + 'DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT', + 'DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK', + 'DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT', + 'DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK', + 'DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT', + 'DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK', + 'DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT', + 'DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK', + 'DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK', + 'DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK', + 'DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK', + 'DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT', + 'DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK', + 'DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT', + 'DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC0_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC1_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC2_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT', + 'DAGB0_SDP_TAG_RESERVE0__VC3_MASK', + 'DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC4_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC5_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC6_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT', + 'DAGB0_SDP_TAG_RESERVE1__VC7_MASK', + 'DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK', + 'DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT', + 'DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK', + 'DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT', + 'DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI0__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI0__MAX_BW_MASK', + 'DAGB0_WRCLI0__MAX_BW__SHIFT', 'DAGB0_WRCLI0__MAX_OSD_MASK', + 'DAGB0_WRCLI0__MAX_OSD__SHIFT', + 'DAGB0_WRCLI0__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI0__MIN_BW_MASK', + 'DAGB0_WRCLI0__MIN_BW__SHIFT', + 'DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI0__URG_HIGH_MASK', 'DAGB0_WRCLI0__URG_HIGH__SHIFT', + 'DAGB0_WRCLI0__URG_LOW_MASK', 'DAGB0_WRCLI0__URG_LOW__SHIFT', + 'DAGB0_WRCLI0__VIRT_CHAN_MASK', 'DAGB0_WRCLI0__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI10__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI10__MAX_BW_MASK', 'DAGB0_WRCLI10__MAX_BW__SHIFT', + 'DAGB0_WRCLI10__MAX_OSD_MASK', 'DAGB0_WRCLI10__MAX_OSD__SHIFT', + 'DAGB0_WRCLI10__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI10__MIN_BW_MASK', 'DAGB0_WRCLI10__MIN_BW__SHIFT', + 'DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI10__URG_HIGH_MASK', 'DAGB0_WRCLI10__URG_HIGH__SHIFT', + 'DAGB0_WRCLI10__URG_LOW_MASK', 'DAGB0_WRCLI10__URG_LOW__SHIFT', + 'DAGB0_WRCLI10__VIRT_CHAN_MASK', + 'DAGB0_WRCLI10__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI11__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI11__MAX_BW_MASK', 'DAGB0_WRCLI11__MAX_BW__SHIFT', + 'DAGB0_WRCLI11__MAX_OSD_MASK', 'DAGB0_WRCLI11__MAX_OSD__SHIFT', + 'DAGB0_WRCLI11__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI11__MIN_BW_MASK', 'DAGB0_WRCLI11__MIN_BW__SHIFT', + 'DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI11__URG_HIGH_MASK', 'DAGB0_WRCLI11__URG_HIGH__SHIFT', + 'DAGB0_WRCLI11__URG_LOW_MASK', 'DAGB0_WRCLI11__URG_LOW__SHIFT', + 'DAGB0_WRCLI11__VIRT_CHAN_MASK', + 'DAGB0_WRCLI11__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI12__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI12__MAX_BW_MASK', 'DAGB0_WRCLI12__MAX_BW__SHIFT', + 'DAGB0_WRCLI12__MAX_OSD_MASK', 'DAGB0_WRCLI12__MAX_OSD__SHIFT', + 'DAGB0_WRCLI12__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI12__MIN_BW_MASK', 'DAGB0_WRCLI12__MIN_BW__SHIFT', + 'DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI12__URG_HIGH_MASK', 'DAGB0_WRCLI12__URG_HIGH__SHIFT', + 'DAGB0_WRCLI12__URG_LOW_MASK', 'DAGB0_WRCLI12__URG_LOW__SHIFT', + 'DAGB0_WRCLI12__VIRT_CHAN_MASK', + 'DAGB0_WRCLI12__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI13__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI13__MAX_BW_MASK', 'DAGB0_WRCLI13__MAX_BW__SHIFT', + 'DAGB0_WRCLI13__MAX_OSD_MASK', 'DAGB0_WRCLI13__MAX_OSD__SHIFT', + 'DAGB0_WRCLI13__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI13__MIN_BW_MASK', 'DAGB0_WRCLI13__MIN_BW__SHIFT', + 'DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI13__URG_HIGH_MASK', 'DAGB0_WRCLI13__URG_HIGH__SHIFT', + 'DAGB0_WRCLI13__URG_LOW_MASK', 'DAGB0_WRCLI13__URG_LOW__SHIFT', + 'DAGB0_WRCLI13__VIRT_CHAN_MASK', + 'DAGB0_WRCLI13__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI14__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI14__MAX_BW_MASK', 'DAGB0_WRCLI14__MAX_BW__SHIFT', + 'DAGB0_WRCLI14__MAX_OSD_MASK', 'DAGB0_WRCLI14__MAX_OSD__SHIFT', + 'DAGB0_WRCLI14__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI14__MIN_BW_MASK', 'DAGB0_WRCLI14__MIN_BW__SHIFT', + 'DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI14__URG_HIGH_MASK', 'DAGB0_WRCLI14__URG_HIGH__SHIFT', + 'DAGB0_WRCLI14__URG_LOW_MASK', 'DAGB0_WRCLI14__URG_LOW__SHIFT', + 'DAGB0_WRCLI14__VIRT_CHAN_MASK', + 'DAGB0_WRCLI14__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI15__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI15__MAX_BW_MASK', 'DAGB0_WRCLI15__MAX_BW__SHIFT', + 'DAGB0_WRCLI15__MAX_OSD_MASK', 'DAGB0_WRCLI15__MAX_OSD__SHIFT', + 'DAGB0_WRCLI15__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI15__MIN_BW_MASK', 'DAGB0_WRCLI15__MIN_BW__SHIFT', + 'DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI15__URG_HIGH_MASK', 'DAGB0_WRCLI15__URG_HIGH__SHIFT', + 'DAGB0_WRCLI15__URG_LOW_MASK', 'DAGB0_WRCLI15__URG_LOW__SHIFT', + 'DAGB0_WRCLI15__VIRT_CHAN_MASK', + 'DAGB0_WRCLI15__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI16__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI16__MAX_BW_MASK', 'DAGB0_WRCLI16__MAX_BW__SHIFT', + 'DAGB0_WRCLI16__MAX_OSD_MASK', 'DAGB0_WRCLI16__MAX_OSD__SHIFT', + 'DAGB0_WRCLI16__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI16__MIN_BW_MASK', 'DAGB0_WRCLI16__MIN_BW__SHIFT', + 'DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI16__URG_HIGH_MASK', 'DAGB0_WRCLI16__URG_HIGH__SHIFT', + 'DAGB0_WRCLI16__URG_LOW_MASK', 'DAGB0_WRCLI16__URG_LOW__SHIFT', + 'DAGB0_WRCLI16__VIRT_CHAN_MASK', + 'DAGB0_WRCLI16__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI17__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI17__MAX_BW_MASK', 'DAGB0_WRCLI17__MAX_BW__SHIFT', + 'DAGB0_WRCLI17__MAX_OSD_MASK', 'DAGB0_WRCLI17__MAX_OSD__SHIFT', + 'DAGB0_WRCLI17__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI17__MIN_BW_MASK', 'DAGB0_WRCLI17__MIN_BW__SHIFT', + 'DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI17__URG_HIGH_MASK', 'DAGB0_WRCLI17__URG_HIGH__SHIFT', + 'DAGB0_WRCLI17__URG_LOW_MASK', 'DAGB0_WRCLI17__URG_LOW__SHIFT', + 'DAGB0_WRCLI17__VIRT_CHAN_MASK', + 'DAGB0_WRCLI17__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI18__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI18__MAX_BW_MASK', 'DAGB0_WRCLI18__MAX_BW__SHIFT', + 'DAGB0_WRCLI18__MAX_OSD_MASK', 'DAGB0_WRCLI18__MAX_OSD__SHIFT', + 'DAGB0_WRCLI18__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI18__MIN_BW_MASK', 'DAGB0_WRCLI18__MIN_BW__SHIFT', + 'DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI18__URG_HIGH_MASK', 'DAGB0_WRCLI18__URG_HIGH__SHIFT', + 'DAGB0_WRCLI18__URG_LOW_MASK', 'DAGB0_WRCLI18__URG_LOW__SHIFT', + 'DAGB0_WRCLI18__VIRT_CHAN_MASK', + 'DAGB0_WRCLI18__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI19__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI19__MAX_BW_MASK', 'DAGB0_WRCLI19__MAX_BW__SHIFT', + 'DAGB0_WRCLI19__MAX_OSD_MASK', 'DAGB0_WRCLI19__MAX_OSD__SHIFT', + 'DAGB0_WRCLI19__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI19__MIN_BW_MASK', 'DAGB0_WRCLI19__MIN_BW__SHIFT', + 'DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI19__URG_HIGH_MASK', 'DAGB0_WRCLI19__URG_HIGH__SHIFT', + 'DAGB0_WRCLI19__URG_LOW_MASK', 'DAGB0_WRCLI19__URG_LOW__SHIFT', + 'DAGB0_WRCLI19__VIRT_CHAN_MASK', + 'DAGB0_WRCLI19__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI1__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI1__MAX_BW_MASK', + 'DAGB0_WRCLI1__MAX_BW__SHIFT', 'DAGB0_WRCLI1__MAX_OSD_MASK', + 'DAGB0_WRCLI1__MAX_OSD__SHIFT', + 'DAGB0_WRCLI1__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI1__MIN_BW_MASK', + 'DAGB0_WRCLI1__MIN_BW__SHIFT', + 'DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI1__URG_HIGH_MASK', 'DAGB0_WRCLI1__URG_HIGH__SHIFT', + 'DAGB0_WRCLI1__URG_LOW_MASK', 'DAGB0_WRCLI1__URG_LOW__SHIFT', + 'DAGB0_WRCLI1__VIRT_CHAN_MASK', 'DAGB0_WRCLI1__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI20__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI20__MAX_BW_MASK', 'DAGB0_WRCLI20__MAX_BW__SHIFT', + 'DAGB0_WRCLI20__MAX_OSD_MASK', 'DAGB0_WRCLI20__MAX_OSD__SHIFT', + 'DAGB0_WRCLI20__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI20__MIN_BW_MASK', 'DAGB0_WRCLI20__MIN_BW__SHIFT', + 'DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI20__URG_HIGH_MASK', 'DAGB0_WRCLI20__URG_HIGH__SHIFT', + 'DAGB0_WRCLI20__URG_LOW_MASK', 'DAGB0_WRCLI20__URG_LOW__SHIFT', + 'DAGB0_WRCLI20__VIRT_CHAN_MASK', + 'DAGB0_WRCLI20__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI21__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI21__MAX_BW_MASK', 'DAGB0_WRCLI21__MAX_BW__SHIFT', + 'DAGB0_WRCLI21__MAX_OSD_MASK', 'DAGB0_WRCLI21__MAX_OSD__SHIFT', + 'DAGB0_WRCLI21__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI21__MIN_BW_MASK', 'DAGB0_WRCLI21__MIN_BW__SHIFT', + 'DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI21__URG_HIGH_MASK', 'DAGB0_WRCLI21__URG_HIGH__SHIFT', + 'DAGB0_WRCLI21__URG_LOW_MASK', 'DAGB0_WRCLI21__URG_LOW__SHIFT', + 'DAGB0_WRCLI21__VIRT_CHAN_MASK', + 'DAGB0_WRCLI21__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI22__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI22__MAX_BW_MASK', 'DAGB0_WRCLI22__MAX_BW__SHIFT', + 'DAGB0_WRCLI22__MAX_OSD_MASK', 'DAGB0_WRCLI22__MAX_OSD__SHIFT', + 'DAGB0_WRCLI22__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI22__MIN_BW_MASK', 'DAGB0_WRCLI22__MIN_BW__SHIFT', + 'DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI22__URG_HIGH_MASK', 'DAGB0_WRCLI22__URG_HIGH__SHIFT', + 'DAGB0_WRCLI22__URG_LOW_MASK', 'DAGB0_WRCLI22__URG_LOW__SHIFT', + 'DAGB0_WRCLI22__VIRT_CHAN_MASK', + 'DAGB0_WRCLI22__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI23__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI23__MAX_BW_MASK', 'DAGB0_WRCLI23__MAX_BW__SHIFT', + 'DAGB0_WRCLI23__MAX_OSD_MASK', 'DAGB0_WRCLI23__MAX_OSD__SHIFT', + 'DAGB0_WRCLI23__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WRCLI23__MIN_BW_MASK', 'DAGB0_WRCLI23__MIN_BW__SHIFT', + 'DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI23__URG_HIGH_MASK', 'DAGB0_WRCLI23__URG_HIGH__SHIFT', + 'DAGB0_WRCLI23__URG_LOW_MASK', 'DAGB0_WRCLI23__URG_LOW__SHIFT', + 'DAGB0_WRCLI23__VIRT_CHAN_MASK', + 'DAGB0_WRCLI23__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI2__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI2__MAX_BW_MASK', + 'DAGB0_WRCLI2__MAX_BW__SHIFT', 'DAGB0_WRCLI2__MAX_OSD_MASK', + 'DAGB0_WRCLI2__MAX_OSD__SHIFT', + 'DAGB0_WRCLI2__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI2__MIN_BW_MASK', + 'DAGB0_WRCLI2__MIN_BW__SHIFT', + 'DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI2__URG_HIGH_MASK', 'DAGB0_WRCLI2__URG_HIGH__SHIFT', + 'DAGB0_WRCLI2__URG_LOW_MASK', 'DAGB0_WRCLI2__URG_LOW__SHIFT', + 'DAGB0_WRCLI2__VIRT_CHAN_MASK', 'DAGB0_WRCLI2__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI3__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI3__MAX_BW_MASK', + 'DAGB0_WRCLI3__MAX_BW__SHIFT', 'DAGB0_WRCLI3__MAX_OSD_MASK', + 'DAGB0_WRCLI3__MAX_OSD__SHIFT', + 'DAGB0_WRCLI3__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI3__MIN_BW_MASK', + 'DAGB0_WRCLI3__MIN_BW__SHIFT', + 'DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI3__URG_HIGH_MASK', 'DAGB0_WRCLI3__URG_HIGH__SHIFT', + 'DAGB0_WRCLI3__URG_LOW_MASK', 'DAGB0_WRCLI3__URG_LOW__SHIFT', + 'DAGB0_WRCLI3__VIRT_CHAN_MASK', 'DAGB0_WRCLI3__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI4__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI4__MAX_BW_MASK', + 'DAGB0_WRCLI4__MAX_BW__SHIFT', 'DAGB0_WRCLI4__MAX_OSD_MASK', + 'DAGB0_WRCLI4__MAX_OSD__SHIFT', + 'DAGB0_WRCLI4__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI4__MIN_BW_MASK', + 'DAGB0_WRCLI4__MIN_BW__SHIFT', + 'DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI4__URG_HIGH_MASK', 'DAGB0_WRCLI4__URG_HIGH__SHIFT', + 'DAGB0_WRCLI4__URG_LOW_MASK', 'DAGB0_WRCLI4__URG_LOW__SHIFT', + 'DAGB0_WRCLI4__VIRT_CHAN_MASK', 'DAGB0_WRCLI4__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI5__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI5__MAX_BW_MASK', + 'DAGB0_WRCLI5__MAX_BW__SHIFT', 'DAGB0_WRCLI5__MAX_OSD_MASK', + 'DAGB0_WRCLI5__MAX_OSD__SHIFT', + 'DAGB0_WRCLI5__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI5__MIN_BW_MASK', + 'DAGB0_WRCLI5__MIN_BW__SHIFT', + 'DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI5__URG_HIGH_MASK', 'DAGB0_WRCLI5__URG_HIGH__SHIFT', + 'DAGB0_WRCLI5__URG_LOW_MASK', 'DAGB0_WRCLI5__URG_LOW__SHIFT', + 'DAGB0_WRCLI5__VIRT_CHAN_MASK', 'DAGB0_WRCLI5__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI6__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI6__MAX_BW_MASK', + 'DAGB0_WRCLI6__MAX_BW__SHIFT', 'DAGB0_WRCLI6__MAX_OSD_MASK', + 'DAGB0_WRCLI6__MAX_OSD__SHIFT', + 'DAGB0_WRCLI6__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI6__MIN_BW_MASK', + 'DAGB0_WRCLI6__MIN_BW__SHIFT', + 'DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI6__URG_HIGH_MASK', 'DAGB0_WRCLI6__URG_HIGH__SHIFT', + 'DAGB0_WRCLI6__URG_LOW_MASK', 'DAGB0_WRCLI6__URG_LOW__SHIFT', + 'DAGB0_WRCLI6__VIRT_CHAN_MASK', 'DAGB0_WRCLI6__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI7__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI7__MAX_BW_MASK', + 'DAGB0_WRCLI7__MAX_BW__SHIFT', 'DAGB0_WRCLI7__MAX_OSD_MASK', + 'DAGB0_WRCLI7__MAX_OSD__SHIFT', + 'DAGB0_WRCLI7__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI7__MIN_BW_MASK', + 'DAGB0_WRCLI7__MIN_BW__SHIFT', + 'DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI7__URG_HIGH_MASK', 'DAGB0_WRCLI7__URG_HIGH__SHIFT', + 'DAGB0_WRCLI7__URG_LOW_MASK', 'DAGB0_WRCLI7__URG_LOW__SHIFT', + 'DAGB0_WRCLI7__VIRT_CHAN_MASK', 'DAGB0_WRCLI7__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI8__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI8__MAX_BW_MASK', + 'DAGB0_WRCLI8__MAX_BW__SHIFT', 'DAGB0_WRCLI8__MAX_OSD_MASK', + 'DAGB0_WRCLI8__MAX_OSD__SHIFT', + 'DAGB0_WRCLI8__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI8__MIN_BW_MASK', + 'DAGB0_WRCLI8__MIN_BW__SHIFT', + 'DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI8__URG_HIGH_MASK', 'DAGB0_WRCLI8__URG_HIGH__SHIFT', + 'DAGB0_WRCLI8__URG_LOW_MASK', 'DAGB0_WRCLI8__URG_LOW__SHIFT', + 'DAGB0_WRCLI8__VIRT_CHAN_MASK', 'DAGB0_WRCLI8__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB0_WRCLI9__MAX_BW_ENABLE_MASK', + 'DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB0_WRCLI9__MAX_BW_MASK', + 'DAGB0_WRCLI9__MAX_BW__SHIFT', 'DAGB0_WRCLI9__MAX_OSD_MASK', + 'DAGB0_WRCLI9__MAX_OSD__SHIFT', + 'DAGB0_WRCLI9__MIN_BW_ENABLE_MASK', + 'DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB0_WRCLI9__MIN_BW_MASK', + 'DAGB0_WRCLI9__MIN_BW__SHIFT', + 'DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WRCLI9__URG_HIGH_MASK', 'DAGB0_WRCLI9__URG_HIGH__SHIFT', + 'DAGB0_WRCLI9__URG_LOW_MASK', 'DAGB0_WRCLI9__URG_LOW__SHIFT', + 'DAGB0_WRCLI9__VIRT_CHAN_MASK', 'DAGB0_WRCLI9__VIRT_CHAN__SHIFT', + 'DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_ASK_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GO_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK', + 'DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB0_WRCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB0_WRCLI_OARB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_OSD_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB0_WRCLI_TLB_PENDING__BUSY_MASK', + 'DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB0_WR_ADDR_DAGB__WHOAMI_MASK', + 'DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK', + 'DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB0_WR_CNTL_MISC__HDP_CID_MASK', + 'DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT', + 'DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB0_WR_CNTL__UPDATE_FED_MASK', + 'DAGB0_WR_CNTL__UPDATE_FED__SHIFT', + 'DAGB0_WR_CNTL__UPDATE_NACK_MASK', + 'DAGB0_WR_CNTL__UPDATE_NACK__SHIFT', + 'DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB0_WR_CREDITS_FULL__FULL_MASK', + 'DAGB0_WR_CREDITS_FULL__FULL__SHIFT', + 'DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK', + 'DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK', + 'DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB0_WR_DATA_DAGB__WHOAMI_MASK', + 'DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK', + 'DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT', + 'DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK', + 'DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT', + 'DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK', + 'DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB0_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB0__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB1_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB1__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB2_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB2__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB3_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB3__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB4_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB4__SHIFT', + 'DAGB0_WR_TLB_CREDIT__TLB5_MASK', + 'DAGB0_WR_TLB_CREDIT__TLB5__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC0_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC1_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC2_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC3_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC4_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_BW_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB0_WR_VC5_CNTL__MAX_OSD_MASK', + 'DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__MIN_BW_MASK', + 'DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK', + 'DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK', + 'DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT', + 'DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK', + 'DAGB1_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT', + 'DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK', + 'DAGB1_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT', + 'DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK', + 'DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT', + 'DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__SWAP_CTL_MASK', + 'DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT', + 'DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK', + 'DAGB1_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT', + 'DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK', + 'DAGB1_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT', + 'DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK', + 'DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT', + 'DAGB1_DAGB_DLY__CLI_MASK', 'DAGB1_DAGB_DLY__CLI__SHIFT', + 'DAGB1_DAGB_DLY__DLY_MASK', 'DAGB1_DAGB_DLY__DLY__SHIFT', + 'DAGB1_DAGB_DLY__POS_MASK', 'DAGB1_DAGB_DLY__POS__SHIFT', + 'DAGB1_FIFO_EMPTY__EMPTY_MASK', 'DAGB1_FIFO_EMPTY__EMPTY__SHIFT', + 'DAGB1_FIFO_FULL__FULL_MASK', 'DAGB1_FIFO_FULL__FULL__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK', + 'DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT', + 'DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK', + 'DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT', + 'DAGB1_L1TLB_REG_RW__RESERVE_MASK', + 'DAGB1_L1TLB_REG_RW__RESERVE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK', + 'DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK', + 'DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI0__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI0__MAX_BW_MASK', + 'DAGB1_RDCLI0__MAX_BW__SHIFT', 'DAGB1_RDCLI0__MAX_OSD_MASK', + 'DAGB1_RDCLI0__MAX_OSD__SHIFT', + 'DAGB1_RDCLI0__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI0__MIN_BW_MASK', + 'DAGB1_RDCLI0__MIN_BW__SHIFT', + 'DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI0__URG_HIGH_MASK', 'DAGB1_RDCLI0__URG_HIGH__SHIFT', + 'DAGB1_RDCLI0__URG_LOW_MASK', 'DAGB1_RDCLI0__URG_LOW__SHIFT', + 'DAGB1_RDCLI0__VIRT_CHAN_MASK', 'DAGB1_RDCLI0__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI10__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI10__MAX_BW_MASK', 'DAGB1_RDCLI10__MAX_BW__SHIFT', + 'DAGB1_RDCLI10__MAX_OSD_MASK', 'DAGB1_RDCLI10__MAX_OSD__SHIFT', + 'DAGB1_RDCLI10__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI10__MIN_BW_MASK', 'DAGB1_RDCLI10__MIN_BW__SHIFT', + 'DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI10__URG_HIGH_MASK', 'DAGB1_RDCLI10__URG_HIGH__SHIFT', + 'DAGB1_RDCLI10__URG_LOW_MASK', 'DAGB1_RDCLI10__URG_LOW__SHIFT', + 'DAGB1_RDCLI10__VIRT_CHAN_MASK', + 'DAGB1_RDCLI10__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI11__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI11__MAX_BW_MASK', 'DAGB1_RDCLI11__MAX_BW__SHIFT', + 'DAGB1_RDCLI11__MAX_OSD_MASK', 'DAGB1_RDCLI11__MAX_OSD__SHIFT', + 'DAGB1_RDCLI11__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI11__MIN_BW_MASK', 'DAGB1_RDCLI11__MIN_BW__SHIFT', + 'DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI11__URG_HIGH_MASK', 'DAGB1_RDCLI11__URG_HIGH__SHIFT', + 'DAGB1_RDCLI11__URG_LOW_MASK', 'DAGB1_RDCLI11__URG_LOW__SHIFT', + 'DAGB1_RDCLI11__VIRT_CHAN_MASK', + 'DAGB1_RDCLI11__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI12__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI12__MAX_BW_MASK', 'DAGB1_RDCLI12__MAX_BW__SHIFT', + 'DAGB1_RDCLI12__MAX_OSD_MASK', 'DAGB1_RDCLI12__MAX_OSD__SHIFT', + 'DAGB1_RDCLI12__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI12__MIN_BW_MASK', 'DAGB1_RDCLI12__MIN_BW__SHIFT', + 'DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI12__URG_HIGH_MASK', 'DAGB1_RDCLI12__URG_HIGH__SHIFT', + 'DAGB1_RDCLI12__URG_LOW_MASK', 'DAGB1_RDCLI12__URG_LOW__SHIFT', + 'DAGB1_RDCLI12__VIRT_CHAN_MASK', + 'DAGB1_RDCLI12__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI13__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI13__MAX_BW_MASK', 'DAGB1_RDCLI13__MAX_BW__SHIFT', + 'DAGB1_RDCLI13__MAX_OSD_MASK', 'DAGB1_RDCLI13__MAX_OSD__SHIFT', + 'DAGB1_RDCLI13__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI13__MIN_BW_MASK', 'DAGB1_RDCLI13__MIN_BW__SHIFT', + 'DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI13__URG_HIGH_MASK', 'DAGB1_RDCLI13__URG_HIGH__SHIFT', + 'DAGB1_RDCLI13__URG_LOW_MASK', 'DAGB1_RDCLI13__URG_LOW__SHIFT', + 'DAGB1_RDCLI13__VIRT_CHAN_MASK', + 'DAGB1_RDCLI13__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI14__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI14__MAX_BW_MASK', 'DAGB1_RDCLI14__MAX_BW__SHIFT', + 'DAGB1_RDCLI14__MAX_OSD_MASK', 'DAGB1_RDCLI14__MAX_OSD__SHIFT', + 'DAGB1_RDCLI14__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI14__MIN_BW_MASK', 'DAGB1_RDCLI14__MIN_BW__SHIFT', + 'DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI14__URG_HIGH_MASK', 'DAGB1_RDCLI14__URG_HIGH__SHIFT', + 'DAGB1_RDCLI14__URG_LOW_MASK', 'DAGB1_RDCLI14__URG_LOW__SHIFT', + 'DAGB1_RDCLI14__VIRT_CHAN_MASK', + 'DAGB1_RDCLI14__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI15__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI15__MAX_BW_MASK', 'DAGB1_RDCLI15__MAX_BW__SHIFT', + 'DAGB1_RDCLI15__MAX_OSD_MASK', 'DAGB1_RDCLI15__MAX_OSD__SHIFT', + 'DAGB1_RDCLI15__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI15__MIN_BW_MASK', 'DAGB1_RDCLI15__MIN_BW__SHIFT', + 'DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI15__URG_HIGH_MASK', 'DAGB1_RDCLI15__URG_HIGH__SHIFT', + 'DAGB1_RDCLI15__URG_LOW_MASK', 'DAGB1_RDCLI15__URG_LOW__SHIFT', + 'DAGB1_RDCLI15__VIRT_CHAN_MASK', + 'DAGB1_RDCLI15__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI16__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI16__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI16__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI16__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI16__MAX_BW_MASK', 'DAGB1_RDCLI16__MAX_BW__SHIFT', + 'DAGB1_RDCLI16__MAX_OSD_MASK', 'DAGB1_RDCLI16__MAX_OSD__SHIFT', + 'DAGB1_RDCLI16__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI16__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI16__MIN_BW_MASK', 'DAGB1_RDCLI16__MIN_BW__SHIFT', + 'DAGB1_RDCLI16__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI16__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI16__URG_HIGH_MASK', 'DAGB1_RDCLI16__URG_HIGH__SHIFT', + 'DAGB1_RDCLI16__URG_LOW_MASK', 'DAGB1_RDCLI16__URG_LOW__SHIFT', + 'DAGB1_RDCLI16__VIRT_CHAN_MASK', + 'DAGB1_RDCLI16__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI17__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI17__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI17__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI17__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI17__MAX_BW_MASK', 'DAGB1_RDCLI17__MAX_BW__SHIFT', + 'DAGB1_RDCLI17__MAX_OSD_MASK', 'DAGB1_RDCLI17__MAX_OSD__SHIFT', + 'DAGB1_RDCLI17__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI17__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI17__MIN_BW_MASK', 'DAGB1_RDCLI17__MIN_BW__SHIFT', + 'DAGB1_RDCLI17__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI17__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI17__URG_HIGH_MASK', 'DAGB1_RDCLI17__URG_HIGH__SHIFT', + 'DAGB1_RDCLI17__URG_LOW_MASK', 'DAGB1_RDCLI17__URG_LOW__SHIFT', + 'DAGB1_RDCLI17__VIRT_CHAN_MASK', + 'DAGB1_RDCLI17__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI18__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI18__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI18__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI18__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI18__MAX_BW_MASK', 'DAGB1_RDCLI18__MAX_BW__SHIFT', + 'DAGB1_RDCLI18__MAX_OSD_MASK', 'DAGB1_RDCLI18__MAX_OSD__SHIFT', + 'DAGB1_RDCLI18__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI18__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI18__MIN_BW_MASK', 'DAGB1_RDCLI18__MIN_BW__SHIFT', + 'DAGB1_RDCLI18__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI18__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI18__URG_HIGH_MASK', 'DAGB1_RDCLI18__URG_HIGH__SHIFT', + 'DAGB1_RDCLI18__URG_LOW_MASK', 'DAGB1_RDCLI18__URG_LOW__SHIFT', + 'DAGB1_RDCLI18__VIRT_CHAN_MASK', + 'DAGB1_RDCLI18__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI19__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI19__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI19__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI19__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI19__MAX_BW_MASK', 'DAGB1_RDCLI19__MAX_BW__SHIFT', + 'DAGB1_RDCLI19__MAX_OSD_MASK', 'DAGB1_RDCLI19__MAX_OSD__SHIFT', + 'DAGB1_RDCLI19__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI19__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI19__MIN_BW_MASK', 'DAGB1_RDCLI19__MIN_BW__SHIFT', + 'DAGB1_RDCLI19__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI19__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI19__URG_HIGH_MASK', 'DAGB1_RDCLI19__URG_HIGH__SHIFT', + 'DAGB1_RDCLI19__URG_LOW_MASK', 'DAGB1_RDCLI19__URG_LOW__SHIFT', + 'DAGB1_RDCLI19__VIRT_CHAN_MASK', + 'DAGB1_RDCLI19__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI1__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI1__MAX_BW_MASK', + 'DAGB1_RDCLI1__MAX_BW__SHIFT', 'DAGB1_RDCLI1__MAX_OSD_MASK', + 'DAGB1_RDCLI1__MAX_OSD__SHIFT', + 'DAGB1_RDCLI1__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI1__MIN_BW_MASK', + 'DAGB1_RDCLI1__MIN_BW__SHIFT', + 'DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI1__URG_HIGH_MASK', 'DAGB1_RDCLI1__URG_HIGH__SHIFT', + 'DAGB1_RDCLI1__URG_LOW_MASK', 'DAGB1_RDCLI1__URG_LOW__SHIFT', + 'DAGB1_RDCLI1__VIRT_CHAN_MASK', 'DAGB1_RDCLI1__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI20__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI20__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI20__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI20__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI20__MAX_BW_MASK', 'DAGB1_RDCLI20__MAX_BW__SHIFT', + 'DAGB1_RDCLI20__MAX_OSD_MASK', 'DAGB1_RDCLI20__MAX_OSD__SHIFT', + 'DAGB1_RDCLI20__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI20__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI20__MIN_BW_MASK', 'DAGB1_RDCLI20__MIN_BW__SHIFT', + 'DAGB1_RDCLI20__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI20__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI20__URG_HIGH_MASK', 'DAGB1_RDCLI20__URG_HIGH__SHIFT', + 'DAGB1_RDCLI20__URG_LOW_MASK', 'DAGB1_RDCLI20__URG_LOW__SHIFT', + 'DAGB1_RDCLI20__VIRT_CHAN_MASK', + 'DAGB1_RDCLI20__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI21__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI21__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI21__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI21__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI21__MAX_BW_MASK', 'DAGB1_RDCLI21__MAX_BW__SHIFT', + 'DAGB1_RDCLI21__MAX_OSD_MASK', 'DAGB1_RDCLI21__MAX_OSD__SHIFT', + 'DAGB1_RDCLI21__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI21__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI21__MIN_BW_MASK', 'DAGB1_RDCLI21__MIN_BW__SHIFT', + 'DAGB1_RDCLI21__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI21__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI21__URG_HIGH_MASK', 'DAGB1_RDCLI21__URG_HIGH__SHIFT', + 'DAGB1_RDCLI21__URG_LOW_MASK', 'DAGB1_RDCLI21__URG_LOW__SHIFT', + 'DAGB1_RDCLI21__VIRT_CHAN_MASK', + 'DAGB1_RDCLI21__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI22__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI22__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI22__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI22__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI22__MAX_BW_MASK', 'DAGB1_RDCLI22__MAX_BW__SHIFT', + 'DAGB1_RDCLI22__MAX_OSD_MASK', 'DAGB1_RDCLI22__MAX_OSD__SHIFT', + 'DAGB1_RDCLI22__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI22__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI22__MIN_BW_MASK', 'DAGB1_RDCLI22__MIN_BW__SHIFT', + 'DAGB1_RDCLI22__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI22__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI22__URG_HIGH_MASK', 'DAGB1_RDCLI22__URG_HIGH__SHIFT', + 'DAGB1_RDCLI22__URG_LOW_MASK', 'DAGB1_RDCLI22__URG_LOW__SHIFT', + 'DAGB1_RDCLI22__VIRT_CHAN_MASK', + 'DAGB1_RDCLI22__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI23__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI23__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI23__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI23__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI23__MAX_BW_MASK', 'DAGB1_RDCLI23__MAX_BW__SHIFT', + 'DAGB1_RDCLI23__MAX_OSD_MASK', 'DAGB1_RDCLI23__MAX_OSD__SHIFT', + 'DAGB1_RDCLI23__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI23__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RDCLI23__MIN_BW_MASK', 'DAGB1_RDCLI23__MIN_BW__SHIFT', + 'DAGB1_RDCLI23__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI23__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI23__URG_HIGH_MASK', 'DAGB1_RDCLI23__URG_HIGH__SHIFT', + 'DAGB1_RDCLI23__URG_LOW_MASK', 'DAGB1_RDCLI23__URG_LOW__SHIFT', + 'DAGB1_RDCLI23__VIRT_CHAN_MASK', + 'DAGB1_RDCLI23__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI2__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI2__MAX_BW_MASK', + 'DAGB1_RDCLI2__MAX_BW__SHIFT', 'DAGB1_RDCLI2__MAX_OSD_MASK', + 'DAGB1_RDCLI2__MAX_OSD__SHIFT', + 'DAGB1_RDCLI2__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI2__MIN_BW_MASK', + 'DAGB1_RDCLI2__MIN_BW__SHIFT', + 'DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI2__URG_HIGH_MASK', 'DAGB1_RDCLI2__URG_HIGH__SHIFT', + 'DAGB1_RDCLI2__URG_LOW_MASK', 'DAGB1_RDCLI2__URG_LOW__SHIFT', + 'DAGB1_RDCLI2__VIRT_CHAN_MASK', 'DAGB1_RDCLI2__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI3__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI3__MAX_BW_MASK', + 'DAGB1_RDCLI3__MAX_BW__SHIFT', 'DAGB1_RDCLI3__MAX_OSD_MASK', + 'DAGB1_RDCLI3__MAX_OSD__SHIFT', + 'DAGB1_RDCLI3__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI3__MIN_BW_MASK', + 'DAGB1_RDCLI3__MIN_BW__SHIFT', + 'DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI3__URG_HIGH_MASK', 'DAGB1_RDCLI3__URG_HIGH__SHIFT', + 'DAGB1_RDCLI3__URG_LOW_MASK', 'DAGB1_RDCLI3__URG_LOW__SHIFT', + 'DAGB1_RDCLI3__VIRT_CHAN_MASK', 'DAGB1_RDCLI3__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI4__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI4__MAX_BW_MASK', + 'DAGB1_RDCLI4__MAX_BW__SHIFT', 'DAGB1_RDCLI4__MAX_OSD_MASK', + 'DAGB1_RDCLI4__MAX_OSD__SHIFT', + 'DAGB1_RDCLI4__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI4__MIN_BW_MASK', + 'DAGB1_RDCLI4__MIN_BW__SHIFT', + 'DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI4__URG_HIGH_MASK', 'DAGB1_RDCLI4__URG_HIGH__SHIFT', + 'DAGB1_RDCLI4__URG_LOW_MASK', 'DAGB1_RDCLI4__URG_LOW__SHIFT', + 'DAGB1_RDCLI4__VIRT_CHAN_MASK', 'DAGB1_RDCLI4__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI5__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI5__MAX_BW_MASK', + 'DAGB1_RDCLI5__MAX_BW__SHIFT', 'DAGB1_RDCLI5__MAX_OSD_MASK', + 'DAGB1_RDCLI5__MAX_OSD__SHIFT', + 'DAGB1_RDCLI5__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI5__MIN_BW_MASK', + 'DAGB1_RDCLI5__MIN_BW__SHIFT', + 'DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI5__URG_HIGH_MASK', 'DAGB1_RDCLI5__URG_HIGH__SHIFT', + 'DAGB1_RDCLI5__URG_LOW_MASK', 'DAGB1_RDCLI5__URG_LOW__SHIFT', + 'DAGB1_RDCLI5__VIRT_CHAN_MASK', 'DAGB1_RDCLI5__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI6__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI6__MAX_BW_MASK', + 'DAGB1_RDCLI6__MAX_BW__SHIFT', 'DAGB1_RDCLI6__MAX_OSD_MASK', + 'DAGB1_RDCLI6__MAX_OSD__SHIFT', + 'DAGB1_RDCLI6__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI6__MIN_BW_MASK', + 'DAGB1_RDCLI6__MIN_BW__SHIFT', + 'DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI6__URG_HIGH_MASK', 'DAGB1_RDCLI6__URG_HIGH__SHIFT', + 'DAGB1_RDCLI6__URG_LOW_MASK', 'DAGB1_RDCLI6__URG_LOW__SHIFT', + 'DAGB1_RDCLI6__VIRT_CHAN_MASK', 'DAGB1_RDCLI6__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI7__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI7__MAX_BW_MASK', + 'DAGB1_RDCLI7__MAX_BW__SHIFT', 'DAGB1_RDCLI7__MAX_OSD_MASK', + 'DAGB1_RDCLI7__MAX_OSD__SHIFT', + 'DAGB1_RDCLI7__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI7__MIN_BW_MASK', + 'DAGB1_RDCLI7__MIN_BW__SHIFT', + 'DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI7__URG_HIGH_MASK', 'DAGB1_RDCLI7__URG_HIGH__SHIFT', + 'DAGB1_RDCLI7__URG_LOW_MASK', 'DAGB1_RDCLI7__URG_LOW__SHIFT', + 'DAGB1_RDCLI7__VIRT_CHAN_MASK', 'DAGB1_RDCLI7__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI8__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI8__MAX_BW_MASK', + 'DAGB1_RDCLI8__MAX_BW__SHIFT', 'DAGB1_RDCLI8__MAX_OSD_MASK', + 'DAGB1_RDCLI8__MAX_OSD__SHIFT', + 'DAGB1_RDCLI8__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI8__MIN_BW_MASK', + 'DAGB1_RDCLI8__MIN_BW__SHIFT', + 'DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI8__URG_HIGH_MASK', 'DAGB1_RDCLI8__URG_HIGH__SHIFT', + 'DAGB1_RDCLI8__URG_LOW_MASK', 'DAGB1_RDCLI8__URG_LOW__SHIFT', + 'DAGB1_RDCLI8__VIRT_CHAN_MASK', 'DAGB1_RDCLI8__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK', + 'DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT', + 'DAGB1_RDCLI9__MAX_BW_ENABLE_MASK', + 'DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT', 'DAGB1_RDCLI9__MAX_BW_MASK', + 'DAGB1_RDCLI9__MAX_BW__SHIFT', 'DAGB1_RDCLI9__MAX_OSD_MASK', + 'DAGB1_RDCLI9__MAX_OSD__SHIFT', + 'DAGB1_RDCLI9__MIN_BW_ENABLE_MASK', + 'DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT', 'DAGB1_RDCLI9__MIN_BW_MASK', + 'DAGB1_RDCLI9__MIN_BW__SHIFT', + 'DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RDCLI9__URG_HIGH_MASK', 'DAGB1_RDCLI9__URG_HIGH__SHIFT', + 'DAGB1_RDCLI9__URG_LOW_MASK', 'DAGB1_RDCLI9__URG_LOW__SHIFT', + 'DAGB1_RDCLI9__VIRT_CHAN_MASK', 'DAGB1_RDCLI9__VIRT_CHAN__SHIFT', + 'DAGB1_RDCLI_ASK2ARB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK2DF_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK2DF_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK_OSD_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_ASK_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_GO_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE_MASK', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE__VALUE__SHIFT', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE_MASK', + 'DAGB1_RDCLI_NOALLOC_OVERRIDE__ENABLE__SHIFT', + 'DAGB1_RDCLI_OARB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_OSD_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT', + 'DAGB1_RDCLI_TLB_PENDING__BUSY_MASK', + 'DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK', + 'DAGB1_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK', + 'DAGB1_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT', + 'DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK', + 'DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT', + 'DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK', + 'DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT', + 'DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK', + 'DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT', + 'DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK', + 'DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT', + 'DAGB1_RD_ADDR_DAGB__WHOAMI_MASK', + 'DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE_MASK', + 'DAGB1_RD_CNTL_MISC__RDRET_CC_LEGACY_MODE__SHIFT', + 'DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK', + 'DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT', + 'DAGB1_RD_CNTL_MISC__UTCL2_VCI_MASK', + 'DAGB1_RD_CNTL_MISC__UTCL2_VCI__SHIFT', + 'DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK', + 'DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT', + 'DAGB1_RD_CNTL__SHARE_VC_NUM_MASK', + 'DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT', + 'DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK', + 'DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT', + 'DAGB1_RD_CNTL__VC_ROUNDROBIN_EN_MASK', + 'DAGB1_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT', + 'DAGB1_RD_CREDITS_FULL__FULL_MASK', + 'DAGB1_RD_CREDITS_FULL__FULL__SHIFT', + 'DAGB1_RD_GMI_CNTL__COMMON_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW_MASK', + 'DAGB1_RD_GMI_VC_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__COMMON_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__COMMON_PRIORITY__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_IO_VC_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW_MASK', + 'DAGB1_RD_IO_VC_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC5_CREDIT__SHIFT', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK', + 'DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB0_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB0__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB1_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB1__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB2_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB2__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB3_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB3__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB4_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB4__SHIFT', + 'DAGB1_RD_TLB_CREDIT__TLB5_MASK', + 'DAGB1_RD_TLB_CREDIT__TLB5__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC0_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC1_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC2_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC3_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC4_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_BW_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT', + 'DAGB1_RD_VC5_CNTL__MAX_OSD_MASK', + 'DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT', + 'DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__MIN_BW_MASK', + 'DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT', + 'DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK', + 'DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT', + 'DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK', + 'DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT', + 'DAGB1_RESERVE1__RESERVE_MASK', 'DAGB1_RESERVE1__RESERVE__SHIFT', + 'DAGB1_RESERVE2__RESERVE_MASK', 'DAGB1_RESERVE2__RESERVE__SHIFT', + 'DAGB1_RESERVE3__RESERVE_MASK', 'DAGB1_RESERVE3__RESERVE__SHIFT', + 'DAGB1_RESERVE4__RESERVE_MASK', 'DAGB1_RESERVE4__RESERVE__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__DED_MODE_MASK', + 'DAGB1_SDP_ARB_CNTL0__DED_MODE__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK', + 'DAGB1_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK', + 'DAGB1_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK', + 'DAGB1_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT', + 'DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK', + 'DAGB1_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK', + 'DAGB1_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK', + 'DAGB1_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'DAGB1_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'DAGB1_SDP_CREDITS__RD_RESP_CREDITS_MASK', + 'DAGB1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT', + 'DAGB1_SDP_CREDITS__TAG_LIMIT_MASK', + 'DAGB1_SDP_CREDITS__TAG_LIMIT__SHIFT', + 'DAGB1_SDP_CREDITS__WR_RESP_CREDITS_MASK', + 'DAGB1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT', + 'DAGB1_SDP_ENABLE__ENABLE_MASK', + 'DAGB1_SDP_ENABLE__ENABLE__SHIFT', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__FUE_FLAG_MASK', + 'DAGB1_SDP_ERR_STATUS__FUE_FLAG__SHIFT', + 'DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK', + 'DAGB1_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK', + 'DAGB1_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT', + 'DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK', + 'DAGB1_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT', + 'DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK', + 'DAGB1_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK', + 'DAGB1_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT', + 'DAGB1_SDP_MISC2__BLOCK_REQUESTS_MASK', + 'DAGB1_SDP_MISC2__BLOCK_REQUESTS__SHIFT', + 'DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK', + 'DAGB1_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT', + 'DAGB1_SDP_MISC2__REQUESTS_BLOCKED_MASK', + 'DAGB1_SDP_MISC2__REQUESTS_BLOCKED__SHIFT', + 'DAGB1_SDP_MISC2__RRET_SWAP_MODE_MASK', + 'DAGB1_SDP_MISC2__RRET_SWAP_MODE__SHIFT', + 'DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK', + 'DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT', + 'DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK', + 'DAGB1_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK', + 'DAGB1_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT', + 'DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA_MASK', + 'DAGB1_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK', + 'DAGB1_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK', + 'DAGB1_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK', + 'DAGB1_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT', + 'DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK', + 'DAGB1_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK', + 'DAGB1_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK', + 'DAGB1_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MAX_BW__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW_MASK', + 'DAGB1_SDP_RD_BW_CNTL__MIN_BW__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK', + 'DAGB1_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT', + 'DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK', + 'DAGB1_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT', + 'DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK', + 'DAGB1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK', + 'DAGB1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC0_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC0__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC1_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC1__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC2_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC2__SHIFT', + 'DAGB1_SDP_TAG_RESERVE0__VC3_MASK', + 'DAGB1_SDP_TAG_RESERVE0__VC3__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC4_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC4__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC5_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC5__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC6_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC6__SHIFT', + 'DAGB1_SDP_TAG_RESERVE1__VC7_MASK', + 'DAGB1_SDP_TAG_RESERVE1__VC7__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK', + 'DAGB1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT', + 'DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK', + 'DAGB1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT', + 'MMMC_MEM_POWER_LS__LS_HOLD_MASK', + 'MMMC_MEM_POWER_LS__LS_HOLD__SHIFT', + 'MMMC_MEM_POWER_LS__LS_SETUP_MASK', + 'MMMC_MEM_POWER_LS__LS_SETUP__SHIFT', + 'MMMC_VM_AGP_BASE__AGP_BASE_MASK', + 'MMMC_VM_AGP_BASE__AGP_BASE__SHIFT', + 'MMMC_VM_AGP_BOT__AGP_BOT_MASK', + 'MMMC_VM_AGP_BOT__AGP_BOT__SHIFT', + 'MMMC_VM_AGP_TOP__AGP_TOP_MASK', + 'MMMC_VM_AGP_TOP__AGP_TOP__SHIFT', + 'MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK', + 'MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT', + 'MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK', + 'MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT', + 'MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK', + 'MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT', + 'MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK', + 'MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT', + 'MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK', + 'MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT', + 'MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK', + 'MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK', + 'MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT', + 'MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK', + 'MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK', + 'MMMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT', + 'MMMC_VM_FB_OFFSET__FB_OFFSET_MASK', + 'MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK', + 'MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK', + 'MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT', + 'MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK', + 'MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK', + 'MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK', + 'MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK', + 'MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT', + 'MMMC_VM_STEERING__DEFAULT_STEERING_MASK', + 'MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK', + 'MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK', + 'MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT', + 'MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK', + 'MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT', + 'MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK', + 'MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT', + 'MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK', + 'MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT', + 'MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK', + 'MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK', + 'MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT', + 'MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK', + 'MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK', + 'MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK', + 'MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK', + 'MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK', + 'MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK', + 'MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK', + 'MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK', + 'MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK', + 'MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK', + 'MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK', + 'MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK', + 'MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT', + 'MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK', + 'MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT', + 'MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK', + 'MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT', + 'MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK', + 'MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT', + 'MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK', + 'MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT', + 'MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK', + 'MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT', + 'MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK', + 'MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT', + 'MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK', + 'MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK', + 'MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK', + 'MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT', + 'MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK', + 'MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT', + 'MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK', + 'MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT', + 'MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK', + 'MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT', + 'MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK', + 'MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT', + 'MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK', + 'MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT', + 'MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK', + 'MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT', + 'MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK', + 'MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT', + 'MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__BANK_SELECT_MASK', + 'MMVM_L2_CNTL3__BANK_SELECT__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK', + 'MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT', + 'MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK', + 'MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT', + 'MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK', + 'MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT', + 'MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK', + 'MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK', + 'MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT', + 'MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK', + 'MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT', + 'MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK', + 'MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT', + 'MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK', + 'MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT', + 'MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK', + 'MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT', + 'MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK', + 'MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT', + 'MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK', + 'MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK', + 'MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK', + 'MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT', + 'MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK', + 'MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT', + 'MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK', + 'MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT', + 'MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK', + 'MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK', + 'MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK', + 'MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT', + 'MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK', + 'MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK', + 'MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK', + 'MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT', + 'MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK', + 'MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT', + 'MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK', + 'MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK', + 'MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK', + 'MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT', + 'MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK', + 'MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT', + 'MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK', + 'MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK', + 'MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK', + 'MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK', + 'MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK', + 'MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK', + 'MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK', + 'MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK', + 'MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT', + 'MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK', + 'MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT', + 'MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK', + 'MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT', + 'MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK', + 'MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT', + 'MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK', + 'MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT', + 'MMVM_L2_STATUS__L2_BUSY_MASK', 'MMVM_L2_STATUS__L2_BUSY__SHIFT', + 'PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK', + 'PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT', + 'PCTL_CTRL__PG_ENABLE_MASK', 'PCTL_CTRL__PG_ENABLE__SHIFT', + 'PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK', + 'PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT', + 'PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK', + 'PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT', + 'PCTL_CTRL__SDP_DISCONNECT_MODE_MASK', + 'PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT', + 'PCTL_CTRL__SNR_DISABLE_MASK', 'PCTL_CTRL__SNR_DISABLE__SHIFT', + 'PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK', + 'PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT', + 'PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK', + 'PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT', + 'PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK', + 'PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT', + 'PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK', + 'PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT', + 'PCTL_CTRL__UTCL2_LEGACY_MODE_MASK', + 'PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT', + 'PCTL_CTRL__WRACK_GUARD_MASK', 'PCTL_CTRL__WRACK_GUARD__SHIFT', + 'PCTL_CTRL__Z9_PWRDOWN_MASK', 'PCTL_CTRL__Z9_PWRDOWN__SHIFT', + 'PCTL_CTRL__Z9_PWRUP_MASK', 'PCTL_CTRL__Z9_PWRUP__SHIFT', + 'PCTL_CTRL__ZSC_TIMER_ENABLE_MASK', + 'PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK', + 'PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK', + 'PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__CLEAR_MASK', + 'PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__ENABLE_MASK', + 'PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK', + 'PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__CLEAR_MASK', + 'PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__ENABLE_MASK', + 'PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK', + 'PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT', + 'PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK', + 'PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT', + 'PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK', + 'PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT', + 'PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK', + 'PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK', + 'PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK', + 'PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_RESERVED_0__BIT0_MASK', 'PCTL_RESERVED_0__BIT0__SHIFT', + 'PCTL_RESERVED_0__BIT1_MASK', 'PCTL_RESERVED_0__BIT1__SHIFT', + 'PCTL_RESERVED_0__BIT2_MASK', 'PCTL_RESERVED_0__BIT2__SHIFT', + 'PCTL_RESERVED_0__BIT3_MASK', 'PCTL_RESERVED_0__BIT3__SHIFT', + 'PCTL_RESERVED_0__BIT4_MASK', 'PCTL_RESERVED_0__BIT4__SHIFT', + 'PCTL_RESERVED_0__BIT5_MASK', 'PCTL_RESERVED_0__BIT5__SHIFT', + 'PCTL_RESERVED_0__BIT6_MASK', 'PCTL_RESERVED_0__BIT6__SHIFT', + 'PCTL_RESERVED_0__BIT7_MASK', 'PCTL_RESERVED_0__BIT7__SHIFT', + 'PCTL_RESERVED_0__BYTE_MASK', 'PCTL_RESERVED_0__BYTE__SHIFT', + 'PCTL_RESERVED_0__WORD_MASK', 'PCTL_RESERVED_0__WORD__SHIFT', + 'PCTL_RESERVED_1__BIT0_MASK', 'PCTL_RESERVED_1__BIT0__SHIFT', + 'PCTL_RESERVED_1__BIT1_MASK', 'PCTL_RESERVED_1__BIT1__SHIFT', + 'PCTL_RESERVED_1__BIT2_MASK', 'PCTL_RESERVED_1__BIT2__SHIFT', + 'PCTL_RESERVED_1__BIT3_MASK', 'PCTL_RESERVED_1__BIT3__SHIFT', + 'PCTL_RESERVED_1__BIT4_MASK', 'PCTL_RESERVED_1__BIT4__SHIFT', + 'PCTL_RESERVED_1__BIT5_MASK', 'PCTL_RESERVED_1__BIT5__SHIFT', + 'PCTL_RESERVED_1__BIT6_MASK', 'PCTL_RESERVED_1__BIT6__SHIFT', + 'PCTL_RESERVED_1__BIT7_MASK', 'PCTL_RESERVED_1__BIT7__SHIFT', + 'PCTL_RESERVED_1__BYTE_MASK', 'PCTL_RESERVED_1__BYTE__SHIFT', + 'PCTL_RESERVED_1__WORD_MASK', 'PCTL_RESERVED_1__WORD__SHIFT', + 'PCTL_RESERVED_2__BIT0_MASK', 'PCTL_RESERVED_2__BIT0__SHIFT', + 'PCTL_RESERVED_2__BIT1_MASK', 'PCTL_RESERVED_2__BIT1__SHIFT', + 'PCTL_RESERVED_2__BIT2_MASK', 'PCTL_RESERVED_2__BIT2__SHIFT', + 'PCTL_RESERVED_2__BIT3_MASK', 'PCTL_RESERVED_2__BIT3__SHIFT', + 'PCTL_RESERVED_2__BIT4_MASK', 'PCTL_RESERVED_2__BIT4__SHIFT', + 'PCTL_RESERVED_2__BIT5_MASK', 'PCTL_RESERVED_2__BIT5__SHIFT', + 'PCTL_RESERVED_2__BIT6_MASK', 'PCTL_RESERVED_2__BIT6__SHIFT', + 'PCTL_RESERVED_2__BIT7_MASK', 'PCTL_RESERVED_2__BIT7__SHIFT', + 'PCTL_RESERVED_2__BYTE_MASK', 'PCTL_RESERVED_2__BYTE__SHIFT', + 'PCTL_RESERVED_2__WORD_MASK', 'PCTL_RESERVED_2__WORD__SHIFT', + 'PCTL_RESERVED_3__BIT0_MASK', 'PCTL_RESERVED_3__BIT0__SHIFT', + 'PCTL_RESERVED_3__BIT1_MASK', 'PCTL_RESERVED_3__BIT1__SHIFT', + 'PCTL_RESERVED_3__BIT2_MASK', 'PCTL_RESERVED_3__BIT2__SHIFT', + 'PCTL_RESERVED_3__BIT3_MASK', 'PCTL_RESERVED_3__BIT3__SHIFT', + 'PCTL_RESERVED_3__BIT4_MASK', 'PCTL_RESERVED_3__BIT4__SHIFT', + 'PCTL_RESERVED_3__BIT5_MASK', 'PCTL_RESERVED_3__BIT5__SHIFT', + 'PCTL_RESERVED_3__BIT6_MASK', 'PCTL_RESERVED_3__BIT6__SHIFT', + 'PCTL_RESERVED_3__BIT7_MASK', 'PCTL_RESERVED_3__BIT7__SHIFT', + 'PCTL_RESERVED_3__BYTE_MASK', 'PCTL_RESERVED_3__BYTE__SHIFT', + 'PCTL_RESERVED_3__WORD_MASK', 'PCTL_RESERVED_3__WORD__SHIFT', + 'PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK', + 'PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT', + 'PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK', + 'PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK', + 'PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT', + 'PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK', + 'PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK', + 'PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT', + 'PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK', + 'PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK', + 'PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT', + 'PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_STATUS__MMHUB_CONFIG_DONE_MASK', + 'PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT', + 'PCTL_STATUS__MMHUB_FENCE_ACK_MASK', + 'PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT', + 'PCTL_STATUS__MMHUB_FENCE_REQ_MASK', + 'PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT', + 'PCTL_STATUS__MMHUB_IDLE_MASK', 'PCTL_STATUS__MMHUB_IDLE__SHIFT', + 'PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK', + 'PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT', + 'PCTL_STATUS__MMHUB_POWER_MASK', + 'PCTL_STATUS__MMHUB_POWER__SHIFT', + 'PCTL_STATUS__PGFSM_CMD_STATUS_MASK', + 'PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT', + 'PCTL_STATUS__RENG_RAM_STALE_MASK', + 'PCTL_STATUS__RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK', + 'PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT', + 'PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK', + 'PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT', + 'PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT', + 'PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK', + 'PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT', + 'PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK', + 'PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT', + 'PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK', + 'PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT', + 'PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK', + 'PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT', + 'PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK', + 'PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT', + 'PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK', + 'PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT', + 'PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT', + 'PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK', + 'PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT', + 'PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK', + 'PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK', + 'PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT', + '_mmhub_3_0_2_OFFSET_HEADER', '_mmhub_3_0_2_SH_MASK_HEADER', + 'regDAGB0_CNTL_MISC', 'regDAGB0_CNTL_MISC2', + 'regDAGB0_CNTL_MISC2_BASE_IDX', 'regDAGB0_CNTL_MISC_BASE_IDX', + 'regDAGB0_DAGB_DLY', 'regDAGB0_DAGB_DLY_BASE_IDX', + 'regDAGB0_FATAL_ERROR_CLEAR', + 'regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX', + 'regDAGB0_FATAL_ERROR_CNTL', 'regDAGB0_FATAL_ERROR_CNTL_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS0', + 'regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS1', + 'regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS2', + 'regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS3', + 'regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX', + 'regDAGB0_FATAL_ERROR_STATUS4', + 'regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX', 'regDAGB0_FIFO_EMPTY', + 'regDAGB0_FIFO_EMPTY_BASE_IDX', 'regDAGB0_FIFO_FULL', + 'regDAGB0_FIFO_FULL_BASE_IDX', 'regDAGB0_L1TLB_RD_CGTT_CLK_CTRL', + 'regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_L1TLB_REG_RW', 'regDAGB0_L1TLB_REG_RW_BASE_IDX', + 'regDAGB0_L1TLB_WR_CGTT_CLK_CTRL', + 'regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_PERFCOUNTER0_CFG', 'regDAGB0_PERFCOUNTER0_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER1_CFG', 'regDAGB0_PERFCOUNTER1_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER2_CFG', 'regDAGB0_PERFCOUNTER2_CFG_BASE_IDX', + 'regDAGB0_PERFCOUNTER_HI', 'regDAGB0_PERFCOUNTER_HI_BASE_IDX', + 'regDAGB0_PERFCOUNTER_LO', 'regDAGB0_PERFCOUNTER_LO_BASE_IDX', + 'regDAGB0_PERFCOUNTER_RSLT_CNTL', + 'regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regDAGB0_RDCLI0', + 'regDAGB0_RDCLI0_BASE_IDX', 'regDAGB0_RDCLI1', 'regDAGB0_RDCLI10', + 'regDAGB0_RDCLI10_BASE_IDX', 'regDAGB0_RDCLI11', + 'regDAGB0_RDCLI11_BASE_IDX', 'regDAGB0_RDCLI12', + 'regDAGB0_RDCLI12_BASE_IDX', 'regDAGB0_RDCLI13', + 'regDAGB0_RDCLI13_BASE_IDX', 'regDAGB0_RDCLI14', + 'regDAGB0_RDCLI14_BASE_IDX', 'regDAGB0_RDCLI15', + 'regDAGB0_RDCLI15_BASE_IDX', 'regDAGB0_RDCLI16', + 'regDAGB0_RDCLI16_BASE_IDX', 'regDAGB0_RDCLI17', + 'regDAGB0_RDCLI17_BASE_IDX', 'regDAGB0_RDCLI18', + 'regDAGB0_RDCLI18_BASE_IDX', 'regDAGB0_RDCLI19', + 'regDAGB0_RDCLI19_BASE_IDX', 'regDAGB0_RDCLI1_BASE_IDX', + 'regDAGB0_RDCLI2', 'regDAGB0_RDCLI20', + 'regDAGB0_RDCLI20_BASE_IDX', 'regDAGB0_RDCLI21', + 'regDAGB0_RDCLI21_BASE_IDX', 'regDAGB0_RDCLI22', + 'regDAGB0_RDCLI22_BASE_IDX', 'regDAGB0_RDCLI23', + 'regDAGB0_RDCLI23_BASE_IDX', 'regDAGB0_RDCLI2_BASE_IDX', + 'regDAGB0_RDCLI3', 'regDAGB0_RDCLI3_BASE_IDX', 'regDAGB0_RDCLI4', + 'regDAGB0_RDCLI4_BASE_IDX', 'regDAGB0_RDCLI5', + 'regDAGB0_RDCLI5_BASE_IDX', 'regDAGB0_RDCLI6', + 'regDAGB0_RDCLI6_BASE_IDX', 'regDAGB0_RDCLI7', + 'regDAGB0_RDCLI7_BASE_IDX', 'regDAGB0_RDCLI8', + 'regDAGB0_RDCLI8_BASE_IDX', 'regDAGB0_RDCLI9', + 'regDAGB0_RDCLI9_BASE_IDX', 'regDAGB0_RDCLI_ASK2ARB_PENDING', + 'regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK2DF_PENDING', + 'regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK_OSD_PENDING', + 'regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_ASK_PENDING', + 'regDAGB0_RDCLI_ASK_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_GBLSEND_PENDING', + 'regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_GO_PENDING', 'regDAGB0_RDCLI_GO_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_RDCLI_OARB_PENDING', + 'regDAGB0_RDCLI_OARB_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_OSD_PENDING', + 'regDAGB0_RDCLI_OSD_PENDING_BASE_IDX', + 'regDAGB0_RDCLI_TLB_PENDING', + 'regDAGB0_RDCLI_TLB_PENDING_BASE_IDX', 'regDAGB0_RD_ADDR_DAGB', + 'regDAGB0_RD_ADDR_DAGB_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST0', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST1', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST2', + 'regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_RD_CGTT_CLK_CTRL', 'regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_RD_CNTL', 'regDAGB0_RD_CNTL_BASE_IDX', + 'regDAGB0_RD_CNTL_MISC', 'regDAGB0_RD_CNTL_MISC_BASE_IDX', + 'regDAGB0_RD_CREDITS_FULL', 'regDAGB0_RD_CREDITS_FULL_BASE_IDX', + 'regDAGB0_RD_GMI_CNTL', 'regDAGB0_RD_GMI_CNTL_BASE_IDX', + 'regDAGB0_RD_GMI_VC_CNTL', 'regDAGB0_RD_GMI_VC_CNTL_BASE_IDX', + 'regDAGB0_RD_IO_CNTL', 'regDAGB0_RD_IO_CNTL_BASE_IDX', + 'regDAGB0_RD_IO_VC_CNTL', 'regDAGB0_RD_IO_VC_CNTL_BASE_IDX', + 'regDAGB0_RD_RDRET_CREDIT_CNTL', 'regDAGB0_RD_RDRET_CREDIT_CNTL2', + 'regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX', + 'regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX', + 'regDAGB0_RD_TLB_CREDIT', 'regDAGB0_RD_TLB_CREDIT_BASE_IDX', + 'regDAGB0_RD_VC0_CNTL', 'regDAGB0_RD_VC0_CNTL_BASE_IDX', + 'regDAGB0_RD_VC1_CNTL', 'regDAGB0_RD_VC1_CNTL_BASE_IDX', + 'regDAGB0_RD_VC2_CNTL', 'regDAGB0_RD_VC2_CNTL_BASE_IDX', + 'regDAGB0_RD_VC3_CNTL', 'regDAGB0_RD_VC3_CNTL_BASE_IDX', + 'regDAGB0_RD_VC4_CNTL', 'regDAGB0_RD_VC4_CNTL_BASE_IDX', + 'regDAGB0_RD_VC5_CNTL', 'regDAGB0_RD_VC5_CNTL_BASE_IDX', + 'regDAGB0_RESERVE1', 'regDAGB0_RESERVE1_BASE_IDX', + 'regDAGB0_RESERVE2', 'regDAGB0_RESERVE2_BASE_IDX', + 'regDAGB0_RESERVE3', 'regDAGB0_RESERVE3_BASE_IDX', + 'regDAGB0_RESERVE4', 'regDAGB0_RESERVE4_BASE_IDX', + 'regDAGB0_SDP_ARB_CNTL0', 'regDAGB0_SDP_ARB_CNTL0_BASE_IDX', + 'regDAGB0_SDP_ARB_CNTL1', 'regDAGB0_SDP_ARB_CNTL1_BASE_IDX', + 'regDAGB0_SDP_CGTT_CLK_CTRL', + 'regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX', 'regDAGB0_SDP_CREDITS', + 'regDAGB0_SDP_CREDITS_BASE_IDX', 'regDAGB0_SDP_ENABLE', + 'regDAGB0_SDP_ENABLE_BASE_IDX', 'regDAGB0_SDP_ERR_STATUS', + 'regDAGB0_SDP_ERR_STATUS_BASE_IDX', + 'regDAGB0_SDP_LATENCY_SAMPLING', + 'regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX', 'regDAGB0_SDP_MISC', + 'regDAGB0_SDP_MISC2', 'regDAGB0_SDP_MISC2_BASE_IDX', + 'regDAGB0_SDP_MISC_AON', 'regDAGB0_SDP_MISC_AON_BASE_IDX', + 'regDAGB0_SDP_MISC_BASE_IDX', 'regDAGB0_SDP_PRIORITY_OVERRIDE', + 'regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX', + 'regDAGB0_SDP_RD_BW_CNTL', 'regDAGB0_SDP_RD_BW_CNTL_BASE_IDX', + 'regDAGB0_SDP_RD_CLI2SDP_VC_MAP', + 'regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB0_SDP_RD_PRIORITY', 'regDAGB0_SDP_RD_PRIORITY_BASE_IDX', + 'regDAGB0_SDP_REQ_CNTL', 'regDAGB0_SDP_REQ_CNTL_BASE_IDX', + 'regDAGB0_SDP_TAG_RESERVE0', 'regDAGB0_SDP_TAG_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_TAG_RESERVE1', 'regDAGB0_SDP_TAG_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_VCC_RESERVE0', 'regDAGB0_SDP_VCC_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_VCC_RESERVE1', 'regDAGB0_SDP_VCC_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_VCD_RESERVE0', 'regDAGB0_SDP_VCD_RESERVE0_BASE_IDX', + 'regDAGB0_SDP_VCD_RESERVE1', 'regDAGB0_SDP_VCD_RESERVE1_BASE_IDX', + 'regDAGB0_SDP_WR_CLI2SDP_VC_MAP', + 'regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB0_SDP_WR_PRIORITY', 'regDAGB0_SDP_WR_PRIORITY_BASE_IDX', + 'regDAGB0_WRCLI0', 'regDAGB0_WRCLI0_BASE_IDX', 'regDAGB0_WRCLI1', + 'regDAGB0_WRCLI10', 'regDAGB0_WRCLI10_BASE_IDX', + 'regDAGB0_WRCLI11', 'regDAGB0_WRCLI11_BASE_IDX', + 'regDAGB0_WRCLI12', 'regDAGB0_WRCLI12_BASE_IDX', + 'regDAGB0_WRCLI13', 'regDAGB0_WRCLI13_BASE_IDX', + 'regDAGB0_WRCLI14', 'regDAGB0_WRCLI14_BASE_IDX', + 'regDAGB0_WRCLI15', 'regDAGB0_WRCLI15_BASE_IDX', + 'regDAGB0_WRCLI16', 'regDAGB0_WRCLI16_BASE_IDX', + 'regDAGB0_WRCLI17', 'regDAGB0_WRCLI17_BASE_IDX', + 'regDAGB0_WRCLI18', 'regDAGB0_WRCLI18_BASE_IDX', + 'regDAGB0_WRCLI19', 'regDAGB0_WRCLI19_BASE_IDX', + 'regDAGB0_WRCLI1_BASE_IDX', 'regDAGB0_WRCLI2', 'regDAGB0_WRCLI20', + 'regDAGB0_WRCLI20_BASE_IDX', 'regDAGB0_WRCLI21', + 'regDAGB0_WRCLI21_BASE_IDX', 'regDAGB0_WRCLI22', + 'regDAGB0_WRCLI22_BASE_IDX', 'regDAGB0_WRCLI23', + 'regDAGB0_WRCLI23_BASE_IDX', 'regDAGB0_WRCLI2_BASE_IDX', + 'regDAGB0_WRCLI3', 'regDAGB0_WRCLI3_BASE_IDX', 'regDAGB0_WRCLI4', + 'regDAGB0_WRCLI4_BASE_IDX', 'regDAGB0_WRCLI5', + 'regDAGB0_WRCLI5_BASE_IDX', 'regDAGB0_WRCLI6', + 'regDAGB0_WRCLI6_BASE_IDX', 'regDAGB0_WRCLI7', + 'regDAGB0_WRCLI7_BASE_IDX', 'regDAGB0_WRCLI8', + 'regDAGB0_WRCLI8_BASE_IDX', 'regDAGB0_WRCLI9', + 'regDAGB0_WRCLI9_BASE_IDX', 'regDAGB0_WRCLI_ASK2ARB_PENDING', + 'regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK2DF_PENDING', + 'regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK_OSD_PENDING', + 'regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_ASK_PENDING', + 'regDAGB0_WRCLI_ASK_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_DBUS_ASK_PENDING', + 'regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_DBUS_GO_PENDING', + 'regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GBLSEND_PENDING', + 'regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GO_PENDING', 'regDAGB0_WRCLI_GO_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE', + 'regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB0_WRCLI_OARB_PENDING', + 'regDAGB0_WRCLI_OARB_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_OSD_PENDING', + 'regDAGB0_WRCLI_OSD_PENDING_BASE_IDX', + 'regDAGB0_WRCLI_TLB_PENDING', + 'regDAGB0_WRCLI_TLB_PENDING_BASE_IDX', 'regDAGB0_WR_ADDR_DAGB', + 'regDAGB0_WR_ADDR_DAGB_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST0', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST1', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST2', + 'regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1', + 'regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX', + 'regDAGB0_WR_CGTT_CLK_CTRL', 'regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB0_WR_CNTL', 'regDAGB0_WR_CNTL_BASE_IDX', + 'regDAGB0_WR_CNTL_MISC', 'regDAGB0_WR_CNTL_MISC_BASE_IDX', + 'regDAGB0_WR_CREDITS_FULL', 'regDAGB0_WR_CREDITS_FULL_BASE_IDX', + 'regDAGB0_WR_DATA_CREDIT', 'regDAGB0_WR_DATA_CREDIT_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB', 'regDAGB0_WR_DATA_DAGB_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER0', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER1', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER2', + 'regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST0', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST1', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST2', + 'regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1', + 'regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX', + 'regDAGB0_WR_GMI_CNTL', 'regDAGB0_WR_GMI_CNTL_BASE_IDX', + 'regDAGB0_WR_GMI_VC_CNTL', 'regDAGB0_WR_GMI_VC_CNTL_BASE_IDX', + 'regDAGB0_WR_IO_CNTL', 'regDAGB0_WR_IO_CNTL_BASE_IDX', + 'regDAGB0_WR_IO_VC_CNTL', 'regDAGB0_WR_IO_VC_CNTL_BASE_IDX', + 'regDAGB0_WR_MISC_CREDIT', 'regDAGB0_WR_MISC_CREDIT_BASE_IDX', + 'regDAGB0_WR_TLB_CREDIT', 'regDAGB0_WR_TLB_CREDIT_BASE_IDX', + 'regDAGB0_WR_VC0_CNTL', 'regDAGB0_WR_VC0_CNTL_BASE_IDX', + 'regDAGB0_WR_VC1_CNTL', 'regDAGB0_WR_VC1_CNTL_BASE_IDX', + 'regDAGB0_WR_VC2_CNTL', 'regDAGB0_WR_VC2_CNTL_BASE_IDX', + 'regDAGB0_WR_VC3_CNTL', 'regDAGB0_WR_VC3_CNTL_BASE_IDX', + 'regDAGB0_WR_VC4_CNTL', 'regDAGB0_WR_VC4_CNTL_BASE_IDX', + 'regDAGB0_WR_VC5_CNTL', 'regDAGB0_WR_VC5_CNTL_BASE_IDX', + 'regDAGB1_CNTL_MISC', 'regDAGB1_CNTL_MISC2', + 'regDAGB1_CNTL_MISC2_BASE_IDX', 'regDAGB1_CNTL_MISC_BASE_IDX', + 'regDAGB1_DAGB_DLY', 'regDAGB1_DAGB_DLY_BASE_IDX', + 'regDAGB1_FIFO_EMPTY', 'regDAGB1_FIFO_EMPTY_BASE_IDX', + 'regDAGB1_FIFO_FULL', 'regDAGB1_FIFO_FULL_BASE_IDX', + 'regDAGB1_L1TLB_RD_CGTT_CLK_CTRL', + 'regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB1_L1TLB_REG_RW', 'regDAGB1_L1TLB_REG_RW_BASE_IDX', + 'regDAGB1_PERFCOUNTER0_CFG', 'regDAGB1_PERFCOUNTER0_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER1_CFG', 'regDAGB1_PERFCOUNTER1_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER2_CFG', 'regDAGB1_PERFCOUNTER2_CFG_BASE_IDX', + 'regDAGB1_PERFCOUNTER_HI', 'regDAGB1_PERFCOUNTER_HI_BASE_IDX', + 'regDAGB1_PERFCOUNTER_LO', 'regDAGB1_PERFCOUNTER_LO_BASE_IDX', + 'regDAGB1_PERFCOUNTER_RSLT_CNTL', + 'regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'regDAGB1_RDCLI0', + 'regDAGB1_RDCLI0_BASE_IDX', 'regDAGB1_RDCLI1', 'regDAGB1_RDCLI10', + 'regDAGB1_RDCLI10_BASE_IDX', 'regDAGB1_RDCLI11', + 'regDAGB1_RDCLI11_BASE_IDX', 'regDAGB1_RDCLI12', + 'regDAGB1_RDCLI12_BASE_IDX', 'regDAGB1_RDCLI13', + 'regDAGB1_RDCLI13_BASE_IDX', 'regDAGB1_RDCLI14', + 'regDAGB1_RDCLI14_BASE_IDX', 'regDAGB1_RDCLI15', + 'regDAGB1_RDCLI15_BASE_IDX', 'regDAGB1_RDCLI16', + 'regDAGB1_RDCLI16_BASE_IDX', 'regDAGB1_RDCLI17', + 'regDAGB1_RDCLI17_BASE_IDX', 'regDAGB1_RDCLI18', + 'regDAGB1_RDCLI18_BASE_IDX', 'regDAGB1_RDCLI19', + 'regDAGB1_RDCLI19_BASE_IDX', 'regDAGB1_RDCLI1_BASE_IDX', + 'regDAGB1_RDCLI2', 'regDAGB1_RDCLI20', + 'regDAGB1_RDCLI20_BASE_IDX', 'regDAGB1_RDCLI21', + 'regDAGB1_RDCLI21_BASE_IDX', 'regDAGB1_RDCLI22', + 'regDAGB1_RDCLI22_BASE_IDX', 'regDAGB1_RDCLI23', + 'regDAGB1_RDCLI23_BASE_IDX', 'regDAGB1_RDCLI2_BASE_IDX', + 'regDAGB1_RDCLI3', 'regDAGB1_RDCLI3_BASE_IDX', 'regDAGB1_RDCLI4', + 'regDAGB1_RDCLI4_BASE_IDX', 'regDAGB1_RDCLI5', + 'regDAGB1_RDCLI5_BASE_IDX', 'regDAGB1_RDCLI6', + 'regDAGB1_RDCLI6_BASE_IDX', 'regDAGB1_RDCLI7', + 'regDAGB1_RDCLI7_BASE_IDX', 'regDAGB1_RDCLI8', + 'regDAGB1_RDCLI8_BASE_IDX', 'regDAGB1_RDCLI9', + 'regDAGB1_RDCLI9_BASE_IDX', 'regDAGB1_RDCLI_ASK2ARB_PENDING', + 'regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK2DF_PENDING', + 'regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK_OSD_PENDING', + 'regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_ASK_PENDING', + 'regDAGB1_RDCLI_ASK_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_GBLSEND_PENDING', + 'regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_GO_PENDING', 'regDAGB1_RDCLI_GO_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE', + 'regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX', + 'regDAGB1_RDCLI_OARB_PENDING', + 'regDAGB1_RDCLI_OARB_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_OSD_PENDING', + 'regDAGB1_RDCLI_OSD_PENDING_BASE_IDX', + 'regDAGB1_RDCLI_TLB_PENDING', + 'regDAGB1_RDCLI_TLB_PENDING_BASE_IDX', 'regDAGB1_RD_ADDR_DAGB', + 'regDAGB1_RD_ADDR_DAGB_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2', + 'regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST0', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST1', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST2', + 'regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX', + 'regDAGB1_RD_CGTT_CLK_CTRL', 'regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX', + 'regDAGB1_RD_CNTL', 'regDAGB1_RD_CNTL_BASE_IDX', + 'regDAGB1_RD_CNTL_MISC', 'regDAGB1_RD_CNTL_MISC_BASE_IDX', + 'regDAGB1_RD_CREDITS_FULL', 'regDAGB1_RD_CREDITS_FULL_BASE_IDX', + 'regDAGB1_RD_GMI_CNTL', 'regDAGB1_RD_GMI_CNTL_BASE_IDX', + 'regDAGB1_RD_GMI_VC_CNTL', 'regDAGB1_RD_GMI_VC_CNTL_BASE_IDX', + 'regDAGB1_RD_IO_CNTL', 'regDAGB1_RD_IO_CNTL_BASE_IDX', + 'regDAGB1_RD_IO_VC_CNTL', 'regDAGB1_RD_IO_VC_CNTL_BASE_IDX', + 'regDAGB1_RD_RDRET_CREDIT_CNTL', 'regDAGB1_RD_RDRET_CREDIT_CNTL2', + 'regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX', + 'regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX', + 'regDAGB1_RD_TLB_CREDIT', 'regDAGB1_RD_TLB_CREDIT_BASE_IDX', + 'regDAGB1_RD_VC0_CNTL', 'regDAGB1_RD_VC0_CNTL_BASE_IDX', + 'regDAGB1_RD_VC1_CNTL', 'regDAGB1_RD_VC1_CNTL_BASE_IDX', + 'regDAGB1_RD_VC2_CNTL', 'regDAGB1_RD_VC2_CNTL_BASE_IDX', + 'regDAGB1_RD_VC3_CNTL', 'regDAGB1_RD_VC3_CNTL_BASE_IDX', + 'regDAGB1_RD_VC4_CNTL', 'regDAGB1_RD_VC4_CNTL_BASE_IDX', + 'regDAGB1_RD_VC5_CNTL', 'regDAGB1_RD_VC5_CNTL_BASE_IDX', + 'regDAGB1_RESERVE1', 'regDAGB1_RESERVE1_BASE_IDX', + 'regDAGB1_RESERVE2', 'regDAGB1_RESERVE2_BASE_IDX', + 'regDAGB1_RESERVE3', 'regDAGB1_RESERVE3_BASE_IDX', + 'regDAGB1_RESERVE4', 'regDAGB1_RESERVE4_BASE_IDX', + 'regDAGB1_SDP_ARB_CNTL0', 'regDAGB1_SDP_ARB_CNTL0_BASE_IDX', + 'regDAGB1_SDP_ARB_CNTL1', 'regDAGB1_SDP_ARB_CNTL1_BASE_IDX', + 'regDAGB1_SDP_CGTT_CLK_CTRL', + 'regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX', 'regDAGB1_SDP_CREDITS', + 'regDAGB1_SDP_CREDITS_BASE_IDX', 'regDAGB1_SDP_ENABLE', + 'regDAGB1_SDP_ENABLE_BASE_IDX', 'regDAGB1_SDP_ERR_STATUS', + 'regDAGB1_SDP_ERR_STATUS_BASE_IDX', + 'regDAGB1_SDP_LATENCY_SAMPLING', + 'regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX', 'regDAGB1_SDP_MISC', + 'regDAGB1_SDP_MISC2', 'regDAGB1_SDP_MISC2_BASE_IDX', + 'regDAGB1_SDP_MISC_AON', 'regDAGB1_SDP_MISC_AON_BASE_IDX', + 'regDAGB1_SDP_MISC_BASE_IDX', 'regDAGB1_SDP_PRIORITY_OVERRIDE', + 'regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX', + 'regDAGB1_SDP_RD_BW_CNTL', 'regDAGB1_SDP_RD_BW_CNTL_BASE_IDX', + 'regDAGB1_SDP_RD_CLI2SDP_VC_MAP', + 'regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX', + 'regDAGB1_SDP_RD_PRIORITY', 'regDAGB1_SDP_RD_PRIORITY_BASE_IDX', + 'regDAGB1_SDP_REQ_CNTL', 'regDAGB1_SDP_REQ_CNTL_BASE_IDX', + 'regDAGB1_SDP_TAG_RESERVE0', 'regDAGB1_SDP_TAG_RESERVE0_BASE_IDX', + 'regDAGB1_SDP_TAG_RESERVE1', 'regDAGB1_SDP_TAG_RESERVE1_BASE_IDX', + 'regDAGB1_SDP_VCC_RESERVE0', 'regDAGB1_SDP_VCC_RESERVE0_BASE_IDX', + 'regDAGB1_SDP_VCC_RESERVE1', 'regDAGB1_SDP_VCC_RESERVE1_BASE_IDX', + 'regMMMC_MEM_POWER_LS', 'regMMMC_MEM_POWER_LS_BASE_IDX', + 'regMMMC_VM_AGP_BASE', 'regMMMC_VM_AGP_BASE_BASE_IDX', + 'regMMMC_VM_AGP_BOT', 'regMMMC_VM_AGP_BOT_BASE_IDX', + 'regMMMC_VM_AGP_TOP', 'regMMMC_VM_AGP_TOP_BASE_IDX', + 'regMMMC_VM_APT_CNTL', 'regMMMC_VM_APT_CNTL_BASE_IDX', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START', + 'regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_FB_LOCATION_BASE', + 'regMMMC_VM_FB_LOCATION_BASE_BASE_IDX', + 'regMMMC_VM_FB_LOCATION_TOP', + 'regMMMC_VM_FB_LOCATION_TOP_BASE_IDX', + 'regMMMC_VM_FB_NOALLOC_CNTL', + 'regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX', 'regMMMC_VM_FB_OFFSET', + 'regMMMC_VM_FB_OFFSET_BASE_IDX', 'regMMMC_VM_FB_SIZE_OFFSET_VF0', + 'regMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF1', 'regMMMC_VM_FB_SIZE_OFFSET_VF10', + 'regMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF11', + 'regMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF12', + 'regMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF13', + 'regMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF14', + 'regMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF15', + 'regMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF2', + 'regMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF3', + 'regMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF4', + 'regMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF5', + 'regMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF6', + 'regMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF7', + 'regMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF8', + 'regMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', + 'regMMMC_VM_FB_SIZE_OFFSET_VF9', + 'regMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER0_CFG', + 'regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER1_CFG', + 'regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER2_CFG', + 'regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER3_CFG', + 'regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER4_CFG', + 'regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER5_CFG', + 'regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER6_CFG', + 'regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER7_CFG', + 'regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_HI', + 'regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_LO', + 'regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', + 'regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL', + 'regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_END', + 'regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL', + 'regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX', + 'regMMMC_VM_LOCAL_FB_ADDRESS_START', + 'regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START', + 'regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER0_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER1_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER2_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER3_CFG', + 'regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_HI', + 'regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_LO', + 'regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX', + 'regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL', + 'regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB0_STATUS', + 'regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB1_STATUS', + 'regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB2_STATUS', + 'regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB3_STATUS', + 'regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB4_STATUS', + 'regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB5_STATUS', + 'regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX', + 'regMMMC_VM_MX_L1_TLB_CNTL', 'regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX', + 'regMMMC_VM_STEERING', 'regMMMC_VM_STEERING_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', + 'regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR', + 'regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', + 'regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR', + 'regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', + 'regMMUTCL2_CGTT_BUSY_CTRL', 'regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX', + 'regMMUTCL2_CGTT_CLK_CTRL', 'regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC', + 'regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX', + 'regMMUTCL2_GROUP_RET_FAULT_STATUS', + 'regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX', + 'regMMUTCL2_HARVEST_BYPASS_GROUPS', + 'regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER0_CFG', + 'regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER1_CFG', + 'regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER2_CFG', + 'regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER3_CFG', + 'regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_HI', 'regMMUTCL2_PERFCOUNTER_HI_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_LO', 'regMMUTCL2_PERFCOUNTER_LO_BASE_IDX', + 'regMMUTCL2_PERFCOUNTER_RSLT_CNTL', + 'regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regMMUTCL2_TRANSLATION_BYPASS_BY_VMID', + 'regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', + 'regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', + 'regMMUTC_TRANSLATION_FAULT_CNTL0', + 'regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX', + 'regMMUTC_TRANSLATION_FAULT_CNTL1', + 'regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX', + 'regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT', + 'regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX', + 'regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ', + 'regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX', + 'regMMVM_CONTEXT0_CNTL', 'regMMVM_CONTEXT0_CNTL_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_CNTL', 'regMMVM_CONTEXT10_CNTL_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_CNTL', 'regMMVM_CONTEXT11_CNTL_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_CNTL', 'regMMVM_CONTEXT12_CNTL_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_CNTL', 'regMMVM_CONTEXT13_CNTL_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_CNTL', 'regMMVM_CONTEXT14_CNTL_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_CNTL', 'regMMVM_CONTEXT15_CNTL_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_CNTL', 'regMMVM_CONTEXT1_CNTL_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_CNTL', 'regMMVM_CONTEXT2_CNTL_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_CNTL', 'regMMVM_CONTEXT3_CNTL_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_CNTL', 'regMMVM_CONTEXT4_CNTL_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_CNTL', 'regMMVM_CONTEXT5_CNTL_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_CNTL', 'regMMVM_CONTEXT6_CNTL_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_CNTL', 'regMMVM_CONTEXT7_CNTL_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_CNTL', 'regMMVM_CONTEXT8_CNTL_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_CNTL', 'regMMVM_CONTEXT9_CNTL_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', + 'regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'regMMVM_CONTEXTS_DISABLE', 'regMMVM_CONTEXTS_DISABLE_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32', + 'regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_DUMMY_PAGE_FAULT_CNTL', + 'regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', + 'regMMVM_INVALIDATE_CNTL', 'regMMVM_INVALIDATE_CNTL_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ACK', + 'regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_REQ', + 'regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG0_SEM', + 'regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ACK', + 'regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_REQ', + 'regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG10_SEM', + 'regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ACK', + 'regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_REQ', + 'regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG11_SEM', + 'regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ACK', + 'regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_REQ', + 'regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG12_SEM', + 'regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ACK', + 'regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_REQ', + 'regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG13_SEM', + 'regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ACK', + 'regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_REQ', + 'regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG14_SEM', + 'regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ACK', + 'regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_REQ', + 'regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG15_SEM', + 'regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ACK', + 'regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_REQ', + 'regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG16_SEM', + 'regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ACK', + 'regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_REQ', + 'regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG17_SEM', + 'regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ACK', + 'regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_REQ', + 'regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG1_SEM', + 'regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ACK', + 'regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_REQ', + 'regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG2_SEM', + 'regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ACK', + 'regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_REQ', + 'regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG3_SEM', + 'regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ACK', + 'regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_REQ', + 'regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG4_SEM', + 'regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ACK', + 'regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_REQ', + 'regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG5_SEM', + 'regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ACK', + 'regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_REQ', + 'regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG6_SEM', + 'regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ACK', + 'regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_REQ', + 'regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG7_SEM', + 'regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ACK', + 'regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_REQ', + 'regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG8_SEM', + 'regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ACK', + 'regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', + 'regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_REQ', + 'regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX', + 'regMMVM_INVALIDATE_ENG9_SEM', + 'regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_MASKS', + 'regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID2', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', + 'regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', + 'regMMVM_L2_CACHE_PARITY_CNTL', + 'regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX', + 'regMMVM_L2_CGTT_BUSY_CTRL', 'regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX', + 'regMMVM_L2_CGTT_CLK_CTRL', 'regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX', + 'regMMVM_L2_CNTL', 'regMMVM_L2_CNTL2', + 'regMMVM_L2_CNTL2_BASE_IDX', 'regMMVM_L2_CNTL3', + 'regMMVM_L2_CNTL3_BASE_IDX', 'regMMVM_L2_CNTL4', + 'regMMVM_L2_CNTL4_BASE_IDX', 'regMMVM_L2_CNTL5', + 'regMMVM_L2_CNTL5_BASE_IDX', 'regMMVM_L2_CNTL_BASE_IDX', + 'regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', + 'regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', + 'regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', + 'regMMVM_L2_GCR_CNTL', 'regMMVM_L2_GCR_CNTL_BASE_IDX', + 'regMMVM_L2_MM_GROUP_RT_CLASSES', + 'regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_HI32', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_LO32', + 'regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_CNTL', + 'regMMVM_L2_PROTECTION_FAULT_CNTL2', + 'regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', + 'regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL3', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL4', + 'regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', + 'regMMVM_L2_PROTECTION_FAULT_STATUS', + 'regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', + 'regMMVM_L2_PTE_CACHE_DUMP_CNTL', + 'regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', + 'regMMVM_L2_PTE_CACHE_DUMP_READ', + 'regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'regMMVM_L2_STATUS', + 'regMMVM_L2_STATUS_BASE_IDX', 'regPCTL_CTRL', + 'regPCTL_CTRL_BASE_IDX', 'regPCTL_MMHUB_DEEPSLEEP_IB', + 'regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB', + 'regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX', + 'regPCTL_PERFCOUNTER0_CFG', 'regPCTL_PERFCOUNTER0_CFG_BASE_IDX', + 'regPCTL_PERFCOUNTER1_CFG', 'regPCTL_PERFCOUNTER1_CFG_BASE_IDX', + 'regPCTL_PERFCOUNTER_HI', 'regPCTL_PERFCOUNTER_HI_BASE_IDX', + 'regPCTL_PERFCOUNTER_LO', 'regPCTL_PERFCOUNTER_LO_BASE_IDX', + 'regPCTL_PERFCOUNTER_RSLT_CNTL', + 'regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'regPCTL_PG_IGNORE_DEEPSLEEP', + 'regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX', + 'regPCTL_PG_IGNORE_DEEPSLEEP_IB', + 'regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX', 'regPCTL_RENG_CTRL', + 'regPCTL_RENG_CTRL_BASE_IDX', 'regPCTL_RESERVED_0', + 'regPCTL_RESERVED_0_BASE_IDX', 'regPCTL_RESERVED_1', + 'regPCTL_RESERVED_1_BASE_IDX', 'regPCTL_RESERVED_2', + 'regPCTL_RESERVED_2_BASE_IDX', 'regPCTL_RESERVED_3', + 'regPCTL_RESERVED_3_BASE_IDX', 'regPCTL_SLICE0_CFG_DAGB_RDBUSY', + 'regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX', + 'regPCTL_SLICE0_CFG_DAGB_WRBUSY', + 'regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX', + 'regPCTL_SLICE0_CFG_DS_ALLOW', + 'regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX', + 'regPCTL_SLICE0_CFG_DS_ALLOW_IB', + 'regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX', 'regPCTL_SLICE0_MISC', + 'regPCTL_SLICE0_MISC_BASE_IDX', 'regPCTL_SLICE0_RENG_EXECUTE', + 'regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX', + 'regPCTL_SLICE0_RENG_RAM_DATA', + 'regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_SLICE0_RENG_RAM_INDEX', + 'regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX', + 'regPCTL_SLICE1_CFG_DAGB_RDBUSY', + 'regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX', + 'regPCTL_SLICE1_CFG_DAGB_WRBUSY', + 'regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX', + 'regPCTL_SLICE1_CFG_DS_ALLOW', + 'regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX', + 'regPCTL_SLICE1_CFG_DS_ALLOW_IB', + 'regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX', 'regPCTL_SLICE1_MISC', + 'regPCTL_SLICE1_MISC_BASE_IDX', 'regPCTL_SLICE1_RENG_EXECUTE', + 'regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX', + 'regPCTL_SLICE1_RENG_RAM_DATA', + 'regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_SLICE1_RENG_RAM_INDEX', + 'regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX', + 'regPCTL_STATUS', 'regPCTL_STATUS_BASE_IDX', 'regPCTL_UTCL2_MISC', + 'regPCTL_UTCL2_MISC_BASE_IDX', 'regPCTL_UTCL2_RENG_EXECUTE', + 'regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX', + 'regPCTL_UTCL2_RENG_RAM_DATA', + 'regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX', + 'regPCTL_UTCL2_RENG_RAM_INDEX', + 'regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4', + 'regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX'] diff --git a/tinygrad/runtime/ops_amd.py b/tinygrad/runtime/ops_amd.py index ac6b7b1708..f88b1d2eb3 100644 --- a/tinygrad/runtime/ops_amd.py +++ b/tinygrad/runtime/ops_amd.py @@ -426,6 +426,7 @@ class KFDIface: class AMAllocationMeta: owner:AMDDevice; mapped_devs:list[AMDDevice]; mapping:AMMapping # noqa: E702 class PCIIface: + supported_devs:list[int] = [0x744c, 0x7480] vfio:bool = getenv("VFIO", 1) and HWInterface.exists("/dev/vfio/vfio") vfio_fd:HWInterface gpus:list[Any] = [] @@ -437,7 +438,7 @@ class PCIIface: libpciaccess.pci_system_init() pci_iter = libpciaccess.pci_id_match_iterator_create(None) while pcidev:=libpciaccess.pci_device_next(pci_iter): - if pcidev.contents.vendor_id == 0x1002 and pcidev.contents.device_id == 0x744c: PCIIface.gpus.append(pcidev.contents) + if pcidev.contents.vendor_id == 0x1002 and pcidev.contents.device_id in PCIIface.supported_devs: PCIIface.gpus.append(pcidev.contents) # TODO: visible_devices should be handled layer above this? visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('HIP_VISIBLE_DEVICES', ''))).split(',') if x.strip()] diff --git a/tinygrad/runtime/support/am/amdev.py b/tinygrad/runtime/support/am/amdev.py index b06a2abcae..39859e5101 100644 --- a/tinygrad/runtime/support/am/amdev.py +++ b/tinygrad/runtime/support/am/amdev.py @@ -1,7 +1,7 @@ from __future__ import annotations import ctypes, collections, time, dataclasses, pathlib, fcntl, os from tinygrad.helpers import to_mv, mv_address, getenv, round_up, DEBUG, temp -from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0 +from tinygrad.runtime.autogen.am import am, mp_11_0, gc_11_0_0 from tinygrad.runtime.support.allocator import TLSFAllocator from tinygrad.runtime.support.am.ip import AM_SOC21, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA @@ -371,8 +371,16 @@ class AMDev: gc_info = am.struct_gc_info_v1_0.from_address(gc_addr:=ctypes.addressof(bhdr) + bhdr.table_list[am.GC].offset) self.gc_info = getattr(am, f"struct_gc_info_v{gc_info.header.version_major}_{gc_info.header.version_minor}").from_address(gc_addr) + def _ip_module(self, prefix:str, hwip): + version = [self.ip_versions[hwip]//10000, (self.ip_versions[hwip]//100)%100, self.ip_versions[hwip]%100] + for ver in [version, version[:2]+[0], version[:1]+[0, 0]]: + try: return __import__(f"tinygrad.runtime.autogen.am.{prefix}_{ver[0]}_{ver[1]}_{ver[2]}", fromlist=[f"{prefix}_{ver[0]}_{ver[1]}_{ver[2]}"]) + except ImportError: pass + assert False, f"am {self.devfmt}: failed to load {prefix} module with version {version}" + def _build_regs(self): - mods = [("MP0", mp_13_0_0), ("MP1", mp_11_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)] + mods = [("MP0", self._ip_module("mp", am.MP0_HWIP)), ("NBIO", self._ip_module("nbio", am.NBIO_HWIP)), ("GC", self._ip_module("gc", am.GC_HWIP)), + ("MP1", mp_11_0), ("MMHUB", self._ip_module("mmhub", am.MMHUB_HWIP)), ("OSSSYS", self._ip_module("osssys", am.OSSSYS_HWIP))] for base, module in mods: rpref = "mm" if base == "MP1" else "reg" # MP1 regs starts with mm reg_names: set[str] = set(k[len(rpref):] for k in module.__dict__.keys() if k.startswith(rpref) and not k.endswith("_BASE_IDX")) diff --git a/tinygrad/runtime/support/am/ip.py b/tinygrad/runtime/support/am/ip.py index 03fe61cb52..a7afb678b2 100644 --- a/tinygrad/runtime/support/am/ip.py +++ b/tinygrad/runtime/support/am/ip.py @@ -18,7 +18,7 @@ class AM_GMC(AM_IP): super().__init__(adev) # Memory controller aperture - self.mc_base = self.adev.regMMMC_VM_FB_LOCATION_BASE.read() << 24 + self.mc_base = (self.adev.regMMMC_VM_FB_LOCATION_BASE.read() & 0xFFFFFF) << 24 self.mc_end = self.mc_base + self.adev.mm.vram_size - 1 # VM aperture