From b2a54f4f41efa4bb45133161b66f3efb1252f921 Mon Sep 17 00:00:00 2001 From: Christopher Milan Date: Wed, 12 Nov 2025 13:47:28 -0500 Subject: [PATCH] fix am generations --- tinygrad/runtime/autogen/am/__init__.py | 11 +- tinygrad/runtime/autogen/am/am.py | 1160 +++++++++++++++++++- tinygrad/runtime/autogen/am/pm4_nv.py | 538 +++++++-- tinygrad/runtime/autogen/am/pm4_soc15.py | 538 +++++++-- tinygrad/runtime/autogen/am/smu_v13_0_0.py | 713 ++++++++++-- tinygrad/runtime/autogen/am/smu_v14_0_2.py | 966 ++++++++++++++-- 6 files changed, 3638 insertions(+), 288 deletions(-) diff --git a/tinygrad/runtime/autogen/am/__init__.py b/tinygrad/runtime/autogen/am/__init__.py index e2c90c213b..5d41282105 100644 --- a/tinygrad/runtime/autogen/am/__init__.py +++ b/tinygrad/runtime/autogen/am/__init__.py @@ -1,14 +1,15 @@ from tinygrad.runtime.autogen import load, root am_src="https://github.com/ROCm/ROCK-Kernel-Driver/archive/ceb12c04e2b5b53ec0779362831f5ee40c4921e4.tar.gz" +args=["-include", "stdint.h"] AMD="{}/drivers/gpu/drm/amd" def __getattr__(nm): match nm: case "am": return load("am/am", [], [root/f"extra/amdpci/headers/{s}.h" for s in ["v11_structs", "v12_structs", "amdgpu_vm", "discovery", - "amdgpu_ucode", "psp_gfx_if", "amdgpu_psp", "amdgpu_irq", "amdgpu_doorbell"]]+[f"{AMD}/include/soc15_ih_clientid.h"], tarball=am_src) - case "pm4_soc15": return load("am/pm4_soc15", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], tarball=am_src) - case "pm4_nv": return load("am/pm4_nv", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], tarball=am_src) + "amdgpu_ucode", "psp_gfx_if", "amdgpu_psp", "amdgpu_irq", "amdgpu_doorbell"]]+[f"{AMD}/include/soc15_ih_clientid.h"], args=args, tarball=am_src) + case "pm4_soc15": return load("am/pm4_soc15", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], args=args, tarball=am_src) + case "pm4_nv": return load("am/pm4_nv", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], args=args, tarball=am_src) case "sdma_4_0_0": return load("am/sdma_4_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/vega10_sdma_pkt_open.h"], args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src), case "sdma_5_0_0": return load("am/sdma_5_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/navi10_sdma_pkt_open.h"], @@ -16,7 +17,7 @@ def __getattr__(nm): case "sdma_6_0_0": return load("am/sdma_6_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}//amdgpu/sdma_v6_0_0_pkt_open.h"], args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src), case "smu_v13_0_0": return load("am/smu_v13_0_0",[],[f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_0_ppsmc","smu13_driver_if_v13_0_0"]] - +[root/"extra/amdpci/headers/amdgpu_smu.h"], tarball=am_src), + +[root/"extra/amdpci/headers/amdgpu_smu.h"], args=args, tarball=am_src), case "smu_v14_0_2": return load("am/smu_v14_0_2", [], [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v14_0_0_pmfw", "smu_v14_0_2_ppsmc", - "smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], tarball=am_src) + "smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=args, tarball=am_src) case _: raise AttributeError(f"no such autogen: {nm}") diff --git a/tinygrad/runtime/autogen/am/am.py b/tinygrad/runtime/autogen/am/am.py index 7038b769e3..93e6cfa836 100644 --- a/tinygrad/runtime/autogen/am/am.py +++ b/tinygrad/runtime/autogen/am/am.py @@ -1164,8 +1164,1167 @@ struct_v11_compute_mqd._fields_ = [ ('gws_63_val', ctypes.c_uint32), ] class struct_v12_gfx_mqd(Struct): pass +uint32_t = ctypes.c_uint32 +struct_v12_gfx_mqd._fields_ = [ + ('shadow_base_lo', uint32_t), + ('shadow_base_hi', uint32_t), + ('reserved_2', uint32_t), + ('reserved_3', uint32_t), + ('fw_work_area_base_lo', uint32_t), + ('fw_work_area_base_hi', uint32_t), + ('shadow_initialized', uint32_t), + ('ib_vmid', uint32_t), + ('reserved_8', uint32_t), + ('reserved_9', uint32_t), + ('reserved_10', uint32_t), + ('reserved_11', uint32_t), + ('reserved_12', uint32_t), + ('reserved_13', uint32_t), + ('reserved_14', uint32_t), + ('reserved_15', uint32_t), + ('reserved_16', uint32_t), + ('reserved_17', uint32_t), + ('reserved_18', uint32_t), + ('reserved_19', uint32_t), + ('reserved_20', uint32_t), + ('reserved_21', uint32_t), + ('reserved_22', uint32_t), + ('reserved_23', uint32_t), + ('reserved_24', uint32_t), + ('reserved_25', uint32_t), + ('reserved_26', uint32_t), + ('reserved_27', uint32_t), + ('reserved_28', uint32_t), + ('reserved_29', uint32_t), + ('reserved_30', uint32_t), + ('reserved_31', uint32_t), + ('reserved_32', uint32_t), + ('reserved_33', uint32_t), + ('reserved_34', uint32_t), + ('reserved_35', uint32_t), + ('reserved_36', uint32_t), + ('reserved_37', uint32_t), + ('reserved_38', uint32_t), + ('reserved_39', uint32_t), + ('reserved_40', uint32_t), + ('reserved_41', uint32_t), + ('reserved_42', uint32_t), + ('reserved_43', uint32_t), + ('reserved_44', uint32_t), + ('reserved_45', uint32_t), + ('reserved_46', uint32_t), + ('reserved_47', uint32_t), + ('reserved_48', uint32_t), + ('reserved_49', uint32_t), + ('reserved_50', uint32_t), + ('reserved_51', uint32_t), + ('reserved_52', uint32_t), + ('reserved_53', uint32_t), + ('reserved_54', uint32_t), + ('reserved_55', uint32_t), + ('reserved_56', uint32_t), + ('reserved_57', uint32_t), + ('reserved_58', uint32_t), + ('reserved_59', uint32_t), + ('reserved_60', uint32_t), + ('reserved_61', uint32_t), + ('reserved_62', uint32_t), + ('reserved_63', uint32_t), + ('reserved_64', uint32_t), + ('reserved_65', uint32_t), + ('reserved_66', uint32_t), + ('reserved_67', uint32_t), + ('reserved_68', uint32_t), + ('reserved_69', uint32_t), + ('reserved_70', uint32_t), + ('reserved_71', uint32_t), + ('reserved_72', uint32_t), + ('reserved_73', uint32_t), + ('reserved_74', uint32_t), + ('reserved_75', uint32_t), + ('reserved_76', uint32_t), + ('reserved_77', uint32_t), + ('reserved_78', uint32_t), + ('reserved_79', uint32_t), + ('reserved_80', uint32_t), + ('reserved_81', uint32_t), + ('reserved_82', uint32_t), + ('reserved_83', uint32_t), + ('checksum_lo', uint32_t), + ('checksum_hi', uint32_t), + ('cp_mqd_query_time_lo', uint32_t), + ('cp_mqd_query_time_hi', uint32_t), + ('reserved_88', uint32_t), + ('reserved_89', uint32_t), + ('reserved_90', uint32_t), + ('reserved_91', uint32_t), + ('cp_mqd_query_wave_count', uint32_t), + ('cp_mqd_query_gfx_hqd_rptr', uint32_t), + ('cp_mqd_query_gfx_hqd_wptr', uint32_t), + ('cp_mqd_query_gfx_hqd_offset', uint32_t), + ('reserved_96', uint32_t), + ('reserved_97', uint32_t), + ('reserved_98', uint32_t), + ('reserved_99', uint32_t), + ('reserved_100', uint32_t), + ('reserved_101', uint32_t), + ('reserved_102', uint32_t), + ('reserved_103', uint32_t), + ('task_shader_control_buf_addr_lo', uint32_t), + ('task_shader_control_buf_addr_hi', uint32_t), + ('task_shader_read_rptr_lo', uint32_t), + ('task_shader_read_rptr_hi', uint32_t), + ('task_shader_num_entries', uint32_t), + ('task_shader_num_entries_bits', uint32_t), + ('task_shader_ring_buffer_addr_lo', uint32_t), + ('task_shader_ring_buffer_addr_hi', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('reserved_114', uint32_t), + ('reserved_115', uint32_t), + ('reserved_116', uint32_t), + ('reserved_117', uint32_t), + ('reserved_118', uint32_t), + ('reserved_119', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('reserved_124', uint32_t), + ('reserved_125', uint32_t), + ('reserved_126', uint32_t), + ('reserved_127', uint32_t), + ('cp_mqd_base_addr', uint32_t), + ('cp_mqd_base_addr_hi', uint32_t), + ('cp_gfx_hqd_active', uint32_t), + ('cp_gfx_hqd_vmid', uint32_t), + ('reserved_132', uint32_t), + ('reserved_133', uint32_t), + ('cp_gfx_hqd_queue_priority', uint32_t), + ('cp_gfx_hqd_quantum', uint32_t), + ('cp_gfx_hqd_base', uint32_t), + ('cp_gfx_hqd_base_hi', uint32_t), + ('cp_gfx_hqd_rptr', uint32_t), + ('cp_gfx_hqd_rptr_addr', uint32_t), + ('cp_gfx_hqd_rptr_addr_hi', uint32_t), + ('cp_rb_wptr_poll_addr_lo', uint32_t), + ('cp_rb_wptr_poll_addr_hi', uint32_t), + ('cp_rb_doorbell_control', uint32_t), + ('cp_gfx_hqd_offset', uint32_t), + ('cp_gfx_hqd_cntl', uint32_t), + ('reserved_146', uint32_t), + ('reserved_147', uint32_t), + ('cp_gfx_hqd_csmd_rptr', uint32_t), + ('cp_gfx_hqd_wptr', uint32_t), + ('cp_gfx_hqd_wptr_hi', uint32_t), + ('reserved_151', uint32_t), + ('reserved_152', uint32_t), + ('reserved_153', uint32_t), + ('reserved_154', uint32_t), + ('reserved_155', uint32_t), + ('cp_gfx_hqd_mapped', uint32_t), + ('cp_gfx_hqd_que_mgr_control', uint32_t), + ('reserved_158', uint32_t), + ('reserved_159', uint32_t), + ('cp_gfx_hqd_hq_status0', uint32_t), + ('cp_gfx_hqd_hq_control0', uint32_t), + ('cp_gfx_mqd_control', uint32_t), + ('reserved_163', uint32_t), + ('reserved_164', uint32_t), + ('reserved_165', uint32_t), + ('reserved_166', uint32_t), + ('reserved_167', uint32_t), + ('reserved_168', uint32_t), + ('reserved_169', uint32_t), + ('reserved_170', uint32_t), + ('reserved_171', uint32_t), + ('reserved_172', uint32_t), + ('reserved_173', uint32_t), + ('reserved_174', uint32_t), + ('reserved_175', uint32_t), + ('reserved_176', uint32_t), + ('reserved_177', uint32_t), + ('reserved_178', uint32_t), + ('reserved_179', uint32_t), + ('reserved_180', uint32_t), + ('reserved_181', uint32_t), + ('reserved_182', uint32_t), + ('reserved_183', uint32_t), + ('reserved_184', uint32_t), + ('reserved_185', uint32_t), + ('reserved_186', uint32_t), + ('reserved_187', uint32_t), + ('reserved_188', uint32_t), + ('reserved_189', uint32_t), + ('reserved_190', uint32_t), + ('reserved_191', uint32_t), + ('reserved_192', uint32_t), + ('reserved_193', uint32_t), + ('reserved_194', uint32_t), + ('reserved_195', uint32_t), + ('reserved_196', uint32_t), + ('reserved_197', uint32_t), + ('reserved_198', uint32_t), + ('reserved_199', uint32_t), + ('reserved_200', uint32_t), + ('reserved_201', uint32_t), + ('reserved_202', uint32_t), + ('reserved_203', uint32_t), + ('reserved_204', uint32_t), + ('reserved_205', uint32_t), + ('reserved_206', uint32_t), + ('reserved_207', uint32_t), + ('reserved_208', uint32_t), + ('reserved_209', uint32_t), + ('reserved_210', uint32_t), + ('reserved_211', uint32_t), + ('reserved_212', uint32_t), + ('reserved_213', uint32_t), + ('reserved_214', uint32_t), + ('reserved_215', uint32_t), + ('reserved_216', uint32_t), + ('reserved_217', uint32_t), + ('reserved_218', uint32_t), + ('reserved_219', uint32_t), + ('reserved_220', uint32_t), + ('reserved_221', uint32_t), + ('reserved_222', uint32_t), + ('reserved_223', uint32_t), + ('reserved_224', uint32_t), + ('reserved_225', uint32_t), + ('reserved_226', uint32_t), + ('reserved_227', uint32_t), + ('reserved_228', uint32_t), + ('reserved_229', uint32_t), + ('reserved_230', uint32_t), + ('reserved_231', uint32_t), + ('reserved_232', uint32_t), + ('reserved_233', uint32_t), + ('reserved_234', uint32_t), + ('reserved_235', uint32_t), + ('reserved_236', uint32_t), + ('reserved_237', uint32_t), + ('reserved_238', uint32_t), + ('reserved_239', uint32_t), + ('reserved_240', uint32_t), + ('reserved_241', uint32_t), + ('reserved_242', uint32_t), + ('reserved_243', uint32_t), + ('reserved_244', uint32_t), + ('reserved_245', uint32_t), + ('reserved_246', uint32_t), + ('reserved_247', uint32_t), + ('reserved_248', uint32_t), + ('reserved_249', uint32_t), + ('reserved_250', uint32_t), + ('reserved_251', uint32_t), + ('reserved_252', uint32_t), + ('reserved_253', uint32_t), + ('reserved_254', uint32_t), + ('reserved_255', uint32_t), + ('reserved_256', uint32_t), + ('reserved_257', uint32_t), + ('reserved_258', uint32_t), + ('reserved_259', uint32_t), + ('reserved_260', uint32_t), + ('reserved_261', uint32_t), + ('reserved_262', uint32_t), + ('reserved_263', uint32_t), + ('reserved_264', uint32_t), + ('reserved_265', uint32_t), + ('reserved_266', uint32_t), + ('reserved_267', uint32_t), + ('reserved_268', uint32_t), + ('reserved_269', uint32_t), + ('reserved_270', uint32_t), + ('reserved_271', uint32_t), + ('dfwx_flags', uint32_t), + ('dfwx_slot', uint32_t), + ('dfwx_client_data_addr_lo', uint32_t), + ('dfwx_client_data_addr_hi', uint32_t), + ('reserved_276', uint32_t), + ('reserved_277', uint32_t), + ('reserved_278', uint32_t), + ('reserved_279', uint32_t), + ('reserved_280', uint32_t), + ('reserved_281', uint32_t), + ('reserved_282', uint32_t), + ('reserved_283', uint32_t), + ('reserved_284', uint32_t), + ('reserved_285', uint32_t), + ('reserved_286', uint32_t), + ('reserved_287', uint32_t), + ('reserved_288', uint32_t), + ('reserved_289', uint32_t), + ('reserved_290', uint32_t), + ('reserved_291', uint32_t), + ('reserved_292', uint32_t), + ('reserved_293', uint32_t), + ('reserved_294', uint32_t), + ('reserved_295', uint32_t), + ('reserved_296', uint32_t), + ('reserved_297', uint32_t), + ('reserved_298', uint32_t), + ('reserved_299', uint32_t), + ('reserved_300', uint32_t), + ('reserved_301', uint32_t), + ('reserved_302', uint32_t), + ('reserved_303', uint32_t), + ('reserved_304', uint32_t), + ('reserved_305', uint32_t), + ('reserved_306', uint32_t), + ('reserved_307', uint32_t), + ('reserved_308', uint32_t), + ('reserved_309', uint32_t), + ('reserved_310', uint32_t), + ('reserved_311', uint32_t), + ('reserved_312', uint32_t), + ('reserved_313', uint32_t), + ('reserved_314', uint32_t), + ('reserved_315', uint32_t), + ('reserved_316', uint32_t), + ('reserved_317', uint32_t), + ('reserved_318', uint32_t), + ('reserved_319', uint32_t), + ('reserved_320', uint32_t), + ('reserved_321', uint32_t), + ('reserved_322', uint32_t), + ('reserved_323', uint32_t), + ('reserved_324', uint32_t), + ('reserved_325', uint32_t), + ('reserved_326', uint32_t), + ('reserved_327', uint32_t), + ('reserved_328', uint32_t), + ('reserved_329', uint32_t), + ('reserved_330', uint32_t), + ('reserved_331', uint32_t), + ('reserved_332', uint32_t), + ('reserved_333', uint32_t), + ('reserved_334', uint32_t), + ('reserved_335', uint32_t), + ('reserved_336', uint32_t), + ('reserved_337', uint32_t), + ('reserved_338', uint32_t), + ('reserved_339', uint32_t), + ('reserved_340', uint32_t), + ('reserved_341', uint32_t), + ('reserved_342', uint32_t), + ('reserved_343', uint32_t), + ('reserved_344', uint32_t), + ('reserved_345', uint32_t), + ('reserved_346', uint32_t), + ('reserved_347', uint32_t), + ('reserved_348', uint32_t), + ('reserved_349', uint32_t), + ('reserved_350', uint32_t), + ('reserved_351', uint32_t), + ('reserved_352', uint32_t), + ('reserved_353', uint32_t), + ('reserved_354', uint32_t), + ('reserved_355', uint32_t), + ('reserved_356', uint32_t), + ('reserved_357', uint32_t), + ('reserved_358', uint32_t), + ('reserved_359', uint32_t), + ('reserved_360', uint32_t), + ('reserved_361', uint32_t), + ('reserved_362', uint32_t), + ('reserved_363', uint32_t), + ('reserved_364', uint32_t), + ('reserved_365', uint32_t), + ('reserved_366', uint32_t), + ('reserved_367', uint32_t), + ('reserved_368', uint32_t), + ('reserved_369', uint32_t), + ('reserved_370', uint32_t), + ('reserved_371', uint32_t), + ('reserved_372', uint32_t), + ('reserved_373', uint32_t), + ('reserved_374', uint32_t), + ('reserved_375', uint32_t), + ('reserved_376', uint32_t), + ('reserved_377', uint32_t), + ('reserved_378', uint32_t), + ('reserved_379', uint32_t), + ('reserved_380', uint32_t), + ('reserved_381', uint32_t), + ('reserved_382', uint32_t), + ('reserved_383', uint32_t), + ('reserved_384', uint32_t), + ('reserved_385', uint32_t), + ('reserved_386', uint32_t), + ('reserved_387', uint32_t), + ('reserved_388', uint32_t), + ('reserved_389', uint32_t), + ('reserved_390', uint32_t), + ('reserved_391', uint32_t), + ('reserved_392', uint32_t), + ('reserved_393', uint32_t), + ('reserved_394', uint32_t), + ('reserved_395', uint32_t), + ('reserved_396', uint32_t), + ('reserved_397', uint32_t), + ('reserved_398', uint32_t), + ('reserved_399', uint32_t), + ('reserved_400', uint32_t), + ('reserved_401', uint32_t), + ('reserved_402', uint32_t), + ('reserved_403', uint32_t), + ('reserved_404', uint32_t), + ('reserved_405', uint32_t), + ('reserved_406', uint32_t), + ('reserved_407', uint32_t), + ('reserved_408', uint32_t), + ('reserved_409', uint32_t), + ('reserved_410', uint32_t), + ('reserved_411', uint32_t), + ('reserved_412', uint32_t), + ('reserved_413', uint32_t), + ('reserved_414', uint32_t), + ('reserved_415', uint32_t), + ('reserved_416', uint32_t), + ('reserved_417', uint32_t), + ('reserved_418', uint32_t), + ('reserved_419', uint32_t), + ('reserved_420', uint32_t), + ('reserved_421', uint32_t), + ('reserved_422', uint32_t), + ('reserved_423', uint32_t), + ('reserved_424', uint32_t), + ('reserved_425', uint32_t), + ('reserved_426', uint32_t), + ('reserved_427', uint32_t), + ('reserved_428', uint32_t), + ('reserved_429', uint32_t), + ('reserved_430', uint32_t), + ('reserved_431', uint32_t), + ('reserved_432', uint32_t), + ('reserved_433', uint32_t), + ('reserved_434', uint32_t), + ('reserved_435', uint32_t), + ('reserved_436', uint32_t), + ('reserved_437', uint32_t), + ('reserved_438', uint32_t), + ('reserved_439', uint32_t), + ('reserved_440', uint32_t), + ('reserved_441', uint32_t), + ('reserved_442', uint32_t), + ('reserved_443', uint32_t), + ('reserved_444', uint32_t), + ('reserved_445', uint32_t), + ('reserved_446', uint32_t), + ('reserved_447', uint32_t), + ('reserved_448', uint32_t), + ('reserved_449', uint32_t), + ('reserved_450', uint32_t), + ('reserved_451', uint32_t), + ('reserved_452', uint32_t), + ('reserved_453', uint32_t), + ('reserved_454', uint32_t), + ('reserved_455', uint32_t), + ('reserved_456', uint32_t), + ('reserved_457', uint32_t), + ('reserved_458', uint32_t), + ('reserved_459', uint32_t), + ('reserved_460', uint32_t), + ('reserved_461', uint32_t), + ('reserved_462', uint32_t), + ('reserved_463', uint32_t), + ('reserved_464', uint32_t), + ('reserved_465', uint32_t), + ('reserved_466', uint32_t), + ('reserved_467', uint32_t), + ('reserved_468', uint32_t), + ('reserved_469', uint32_t), + ('reserved_470', uint32_t), + ('reserved_471', uint32_t), + ('reserved_472', uint32_t), + ('reserved_473', uint32_t), + ('reserved_474', uint32_t), + ('reserved_475', uint32_t), + ('reserved_476', uint32_t), + ('reserved_477', uint32_t), + ('reserved_478', uint32_t), + ('reserved_479', uint32_t), + ('reserved_480', uint32_t), + ('reserved_481', uint32_t), + ('reserved_482', uint32_t), + ('reserved_483', uint32_t), + ('reserved_484', uint32_t), + ('reserved_485', uint32_t), + ('reserved_486', uint32_t), + ('reserved_487', uint32_t), + ('reserved_488', uint32_t), + ('reserved_489', uint32_t), + ('reserved_490', uint32_t), + ('reserved_491', uint32_t), + ('reserved_492', uint32_t), + ('reserved_493', uint32_t), + ('reserved_494', uint32_t), + ('reserved_495', uint32_t), + ('reserved_496', uint32_t), + ('reserved_497', uint32_t), + ('reserved_498', uint32_t), + ('reserved_499', uint32_t), + ('reserved_500', uint32_t), + ('reserved_501', uint32_t), + ('reserved_502', uint32_t), + ('reserved_503', uint32_t), + ('reserved_504', uint32_t), + ('reserved_505', uint32_t), + ('reserved_506', uint32_t), + ('reserved_507', uint32_t), + ('reserved_508', uint32_t), + ('reserved_509', uint32_t), + ('reserved_510', uint32_t), + ('reserved_511', uint32_t), +] class struct_v12_sdma_mqd(Struct): pass +struct_v12_sdma_mqd._fields_ = [ + ('sdmax_rlcx_rb_cntl', uint32_t), + ('sdmax_rlcx_rb_base', uint32_t), + ('sdmax_rlcx_rb_base_hi', uint32_t), + ('sdmax_rlcx_rb_rptr', uint32_t), + ('sdmax_rlcx_rb_rptr_hi', uint32_t), + ('sdmax_rlcx_rb_wptr', uint32_t), + ('sdmax_rlcx_rb_wptr_hi', uint32_t), + ('sdmax_rlcx_rb_rptr_addr_lo', uint32_t), + ('sdmax_rlcx_rb_rptr_addr_hi', uint32_t), + ('sdmax_rlcx_ib_cntl', uint32_t), + ('sdmax_rlcx_ib_rptr', uint32_t), + ('sdmax_rlcx_ib_offset', uint32_t), + ('sdmax_rlcx_ib_base_lo', uint32_t), + ('sdmax_rlcx_ib_base_hi', uint32_t), + ('sdmax_rlcx_ib_size', uint32_t), + ('sdmax_rlcx_doorbell', uint32_t), + ('sdmax_rlcx_doorbell_log', uint32_t), + ('sdmax_rlcx_doorbell_offset', uint32_t), + ('sdmax_rlcx_csa_addr_lo', uint32_t), + ('sdmax_rlcx_csa_addr_hi', uint32_t), + ('sdmax_rlcx_sched_cntl', uint32_t), + ('sdmax_rlcx_ib_sub_remain', uint32_t), + ('sdmax_rlcx_preempt', uint32_t), + ('sdmax_rlcx_dummy_reg', uint32_t), + ('sdmax_rlcx_rb_wptr_poll_addr_lo', uint32_t), + ('sdmax_rlcx_rb_wptr_poll_addr_hi', uint32_t), + ('sdmax_rlcx_rb_aql_cntl', uint32_t), + ('sdmax_rlcx_minor_ptr_update', uint32_t), + ('sdmax_rlcx_mcu_dbg0', uint32_t), + ('sdmax_rlcx_mcu_dbg1', uint32_t), + ('sdmax_rlcx_context_switch_status', uint32_t), + ('sdmax_rlcx_midcmd_cntl', uint32_t), + ('sdmax_rlcx_midcmd_data0', uint32_t), + ('sdmax_rlcx_midcmd_data1', uint32_t), + ('sdmax_rlcx_midcmd_data2', uint32_t), + ('sdmax_rlcx_midcmd_data3', uint32_t), + ('sdmax_rlcx_midcmd_data4', uint32_t), + ('sdmax_rlcx_midcmd_data5', uint32_t), + ('sdmax_rlcx_midcmd_data6', uint32_t), + ('sdmax_rlcx_midcmd_data7', uint32_t), + ('sdmax_rlcx_midcmd_data8', uint32_t), + ('sdmax_rlcx_midcmd_data9', uint32_t), + ('sdmax_rlcx_midcmd_data10', uint32_t), + ('sdmax_rlcx_wait_unsatisfied_thd', uint32_t), + ('sdmax_rlcx_mqd_base_addr_lo', uint32_t), + ('sdmax_rlcx_mqd_base_addr_hi', uint32_t), + ('sdmax_rlcx_mqd_control', uint32_t), + ('reserved_47', uint32_t), + ('reserved_48', uint32_t), + ('reserved_49', uint32_t), + ('reserved_50', uint32_t), + ('reserved_51', uint32_t), + ('reserved_52', uint32_t), + ('reserved_53', uint32_t), + ('reserved_54', uint32_t), + ('reserved_55', uint32_t), + ('reserved_56', uint32_t), + ('reserved_57', uint32_t), + ('reserved_58', uint32_t), + ('reserved_59', uint32_t), + ('reserved_60', uint32_t), + ('reserved_61', uint32_t), + ('reserved_62', uint32_t), + ('reserved_63', uint32_t), + ('reserved_64', uint32_t), + ('reserved_65', uint32_t), + ('reserved_66', uint32_t), + ('reserved_67', uint32_t), + ('reserved_68', uint32_t), + ('reserved_69', uint32_t), + ('reserved_70', uint32_t), + ('reserved_71', uint32_t), + ('reserved_72', uint32_t), + ('reserved_73', uint32_t), + ('reserved_74', uint32_t), + ('reserved_75', uint32_t), + ('reserved_76', uint32_t), + ('reserved_77', uint32_t), + ('reserved_78', uint32_t), + ('reserved_79', uint32_t), + ('reserved_80', uint32_t), + ('reserved_81', uint32_t), + ('reserved_82', uint32_t), + ('reserved_83', uint32_t), + ('reserved_84', uint32_t), + ('reserved_85', uint32_t), + ('reserved_86', uint32_t), + ('reserved_87', uint32_t), + ('reserved_88', uint32_t), + ('reserved_89', uint32_t), + ('reserved_90', uint32_t), + ('reserved_91', uint32_t), + ('reserved_92', uint32_t), + ('reserved_93', uint32_t), + ('reserved_94', uint32_t), + ('reserved_95', uint32_t), + ('reserved_96', uint32_t), + ('reserved_97', uint32_t), + ('reserved_98', uint32_t), + ('reserved_99', uint32_t), + ('reserved_100', uint32_t), + ('reserved_101', uint32_t), + ('reserved_102', uint32_t), + ('reserved_103', uint32_t), + ('reserved_104', uint32_t), + ('reserved_105', uint32_t), + ('reserved_106', uint32_t), + ('reserved_107', uint32_t), + ('reserved_108', uint32_t), + ('reserved_109', uint32_t), + ('reserved_110', uint32_t), + ('reserved_111', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('reserved_114', uint32_t), + ('reserved_115', uint32_t), + ('reserved_116', uint32_t), + ('reserved_117', uint32_t), + ('reserved_118', uint32_t), + ('reserved_119', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('reserved_124', uint32_t), + ('reserved_125', uint32_t), + ('sdma_engine_id', uint32_t), + ('sdma_queue_id', uint32_t), +] class struct_v12_compute_mqd(Struct): pass +struct_v12_compute_mqd._fields_ = [ + ('header', uint32_t), + ('compute_dispatch_initiator', uint32_t), + ('compute_dim_x', uint32_t), + ('compute_dim_y', uint32_t), + ('compute_dim_z', uint32_t), + ('compute_start_x', uint32_t), + ('compute_start_y', uint32_t), + ('compute_start_z', uint32_t), + ('compute_num_thread_x', uint32_t), + ('compute_num_thread_y', uint32_t), + ('compute_num_thread_z', uint32_t), + ('compute_pipelinestat_enable', uint32_t), + ('compute_perfcount_enable', uint32_t), + ('compute_pgm_lo', uint32_t), + ('compute_pgm_hi', uint32_t), + ('compute_dispatch_pkt_addr_lo', uint32_t), + ('compute_dispatch_pkt_addr_hi', uint32_t), + ('compute_dispatch_scratch_base_lo', uint32_t), + ('compute_dispatch_scratch_base_hi', uint32_t), + ('compute_pgm_rsrc1', uint32_t), + ('compute_pgm_rsrc2', uint32_t), + ('compute_vmid', uint32_t), + ('compute_resource_limits', uint32_t), + ('compute_static_thread_mgmt_se0', uint32_t), + ('compute_static_thread_mgmt_se1', uint32_t), + ('compute_tmpring_size', uint32_t), + ('compute_static_thread_mgmt_se2', uint32_t), + ('compute_static_thread_mgmt_se3', uint32_t), + ('compute_restart_x', uint32_t), + ('compute_restart_y', uint32_t), + ('compute_restart_z', uint32_t), + ('compute_thread_trace_enable', uint32_t), + ('compute_misc_reserved', uint32_t), + ('compute_dispatch_id', uint32_t), + ('compute_threadgroup_id', uint32_t), + ('compute_req_ctrl', uint32_t), + ('reserved_36', uint32_t), + ('compute_user_accum_0', uint32_t), + ('compute_user_accum_1', uint32_t), + ('compute_user_accum_2', uint32_t), + ('compute_user_accum_3', uint32_t), + ('compute_pgm_rsrc3', uint32_t), + ('compute_ddid_index', uint32_t), + ('compute_shader_chksum', uint32_t), + ('compute_static_thread_mgmt_se4', uint32_t), + ('compute_static_thread_mgmt_se5', uint32_t), + ('compute_static_thread_mgmt_se6', uint32_t), + ('compute_static_thread_mgmt_se7', uint32_t), + ('compute_dispatch_interleave', uint32_t), + ('compute_relaunch', uint32_t), + ('compute_wave_restore_addr_lo', uint32_t), + ('compute_wave_restore_addr_hi', uint32_t), + ('compute_wave_restore_control', uint32_t), + ('reserved_53', uint32_t), + ('reserved_54', uint32_t), + ('reserved_55', uint32_t), + ('reserved_56', uint32_t), + ('reserved_57', uint32_t), + ('reserved_58', uint32_t), + ('compute_static_thread_mgmt_se8', uint32_t), + ('reserved_60', uint32_t), + ('reserved_61', uint32_t), + ('reserved_62', uint32_t), + ('reserved_63', uint32_t), + ('reserved_64', uint32_t), + ('compute_user_data_0', uint32_t), + ('compute_user_data_1', uint32_t), + ('compute_user_data_2', uint32_t), + ('compute_user_data_3', uint32_t), + ('compute_user_data_4', uint32_t), + ('compute_user_data_5', uint32_t), + ('compute_user_data_6', uint32_t), + ('compute_user_data_7', uint32_t), + ('compute_user_data_8', uint32_t), + ('compute_user_data_9', uint32_t), + ('compute_user_data_10', uint32_t), + ('compute_user_data_11', uint32_t), + ('compute_user_data_12', uint32_t), + ('compute_user_data_13', uint32_t), + ('compute_user_data_14', uint32_t), + ('compute_user_data_15', uint32_t), + ('cp_compute_csinvoc_count_lo', uint32_t), + ('cp_compute_csinvoc_count_hi', uint32_t), + ('reserved_83', uint32_t), + ('reserved_84', uint32_t), + ('reserved_85', uint32_t), + ('cp_mqd_query_time_lo', uint32_t), + ('cp_mqd_query_time_hi', uint32_t), + ('cp_mqd_connect_start_time_lo', uint32_t), + ('cp_mqd_connect_start_time_hi', uint32_t), + ('cp_mqd_connect_end_time_lo', uint32_t), + ('cp_mqd_connect_end_time_hi', uint32_t), + ('cp_mqd_connect_end_wf_count', uint32_t), + ('cp_mqd_connect_end_pq_rptr', uint32_t), + ('cp_mqd_connect_end_pq_wptr', uint32_t), + ('cp_mqd_connect_end_ib_rptr', uint32_t), + ('cp_mqd_readindex_lo', uint32_t), + ('cp_mqd_readindex_hi', uint32_t), + ('cp_mqd_save_start_time_lo', uint32_t), + ('cp_mqd_save_start_time_hi', uint32_t), + ('cp_mqd_save_end_time_lo', uint32_t), + ('cp_mqd_save_end_time_hi', uint32_t), + ('cp_mqd_restore_start_time_lo', uint32_t), + ('cp_mqd_restore_start_time_hi', uint32_t), + ('cp_mqd_restore_end_time_lo', uint32_t), + ('cp_mqd_restore_end_time_hi', uint32_t), + ('disable_queue', uint32_t), + ('reserved_107', uint32_t), + ('reserved_108', uint32_t), + ('reserved_109', uint32_t), + ('reserved_110', uint32_t), + ('reserved_111', uint32_t), + ('reserved_112', uint32_t), + ('reserved_113', uint32_t), + ('cp_pq_exe_status_lo', uint32_t), + ('cp_pq_exe_status_hi', uint32_t), + ('cp_packet_id_lo', uint32_t), + ('cp_packet_id_hi', uint32_t), + ('cp_packet_exe_status_lo', uint32_t), + ('cp_packet_exe_status_hi', uint32_t), + ('reserved_120', uint32_t), + ('reserved_121', uint32_t), + ('reserved_122', uint32_t), + ('reserved_123', uint32_t), + ('ctx_save_base_addr_lo', uint32_t), + ('ctx_save_base_addr_hi', uint32_t), + ('reserved_126', uint32_t), + ('reserved_127', uint32_t), + ('cp_mqd_base_addr_lo', uint32_t), + ('cp_mqd_base_addr_hi', uint32_t), + ('cp_hqd_active', uint32_t), + ('cp_hqd_vmid', uint32_t), + ('cp_hqd_persistent_state', uint32_t), + ('cp_hqd_pipe_priority', uint32_t), + ('cp_hqd_queue_priority', uint32_t), + ('cp_hqd_quantum', uint32_t), + ('cp_hqd_pq_base_lo', uint32_t), + ('cp_hqd_pq_base_hi', uint32_t), + ('cp_hqd_pq_rptr', uint32_t), + ('cp_hqd_pq_rptr_report_addr_lo', uint32_t), + ('cp_hqd_pq_rptr_report_addr_hi', uint32_t), + ('cp_hqd_pq_wptr_poll_addr_lo', uint32_t), + ('cp_hqd_pq_wptr_poll_addr_hi', uint32_t), + ('cp_hqd_pq_doorbell_control', uint32_t), + ('reserved_144', uint32_t), + ('cp_hqd_pq_control', uint32_t), + ('cp_hqd_ib_base_addr_lo', uint32_t), + ('cp_hqd_ib_base_addr_hi', uint32_t), + ('cp_hqd_ib_rptr', uint32_t), + ('cp_hqd_ib_control', uint32_t), + ('cp_hqd_iq_timer', uint32_t), + ('cp_hqd_iq_rptr', uint32_t), + ('cp_hqd_dequeue_request', uint32_t), + ('cp_hqd_dma_offload', uint32_t), + ('cp_hqd_sema_cmd', uint32_t), + ('cp_hqd_msg_type', uint32_t), + ('cp_hqd_atomic0_preop_lo', uint32_t), + ('cp_hqd_atomic0_preop_hi', uint32_t), + ('cp_hqd_atomic1_preop_lo', uint32_t), + ('cp_hqd_atomic1_preop_hi', uint32_t), + ('cp_hqd_hq_status0', uint32_t), + ('cp_hqd_hq_control0', uint32_t), + ('cp_mqd_control', uint32_t), + ('cp_hqd_hq_status1', uint32_t), + ('cp_hqd_hq_control1', uint32_t), + ('cp_hqd_eop_base_addr_lo', uint32_t), + ('cp_hqd_eop_base_addr_hi', uint32_t), + ('cp_hqd_eop_control', uint32_t), + ('cp_hqd_eop_rptr', uint32_t), + ('cp_hqd_eop_wptr', uint32_t), + ('cp_hqd_eop_done_events', uint32_t), + ('cp_hqd_ctx_save_base_addr_lo', uint32_t), + ('cp_hqd_ctx_save_base_addr_hi', uint32_t), + ('cp_hqd_ctx_save_control', uint32_t), + ('cp_hqd_cntl_stack_offset', uint32_t), + ('cp_hqd_cntl_stack_size', uint32_t), + ('cp_hqd_wg_state_offset', uint32_t), + ('cp_hqd_ctx_save_size', uint32_t), + ('reserved_178', uint32_t), + ('cp_hqd_error', uint32_t), + ('cp_hqd_eop_wptr_mem', uint32_t), + ('cp_hqd_aql_control', uint32_t), + ('cp_hqd_pq_wptr_lo', uint32_t), + ('cp_hqd_pq_wptr_hi', uint32_t), + ('reserved_184', uint32_t), + ('reserved_185', uint32_t), + ('reserved_186', uint32_t), + ('reserved_187', uint32_t), + ('reserved_188', uint32_t), + ('reserved_189', uint32_t), + ('reserved_190', uint32_t), + ('reserved_191', uint32_t), + ('iqtimer_pkt_header', uint32_t), + ('iqtimer_pkt_dw0', uint32_t), + ('iqtimer_pkt_dw1', uint32_t), + ('iqtimer_pkt_dw2', uint32_t), + ('iqtimer_pkt_dw3', uint32_t), + ('iqtimer_pkt_dw4', uint32_t), + ('iqtimer_pkt_dw5', uint32_t), + ('iqtimer_pkt_dw6', uint32_t), + ('iqtimer_pkt_dw7', uint32_t), + ('iqtimer_pkt_dw8', uint32_t), + ('iqtimer_pkt_dw9', uint32_t), + ('iqtimer_pkt_dw10', uint32_t), + ('iqtimer_pkt_dw11', uint32_t), + ('iqtimer_pkt_dw12', uint32_t), + ('iqtimer_pkt_dw13', uint32_t), + ('iqtimer_pkt_dw14', uint32_t), + ('iqtimer_pkt_dw15', uint32_t), + ('iqtimer_pkt_dw16', uint32_t), + ('iqtimer_pkt_dw17', uint32_t), + ('iqtimer_pkt_dw18', uint32_t), + ('iqtimer_pkt_dw19', uint32_t), + ('iqtimer_pkt_dw20', uint32_t), + ('iqtimer_pkt_dw21', uint32_t), + ('iqtimer_pkt_dw22', uint32_t), + ('iqtimer_pkt_dw23', uint32_t), + ('iqtimer_pkt_dw24', uint32_t), + ('iqtimer_pkt_dw25', uint32_t), + ('iqtimer_pkt_dw26', uint32_t), + ('iqtimer_pkt_dw27', uint32_t), + ('iqtimer_pkt_dw28', uint32_t), + ('iqtimer_pkt_dw29', uint32_t), + ('iqtimer_pkt_dw30', uint32_t), + ('iqtimer_pkt_dw31', uint32_t), + ('reserved_225', uint32_t), + ('reserved_226', uint32_t), + ('reserved_227', uint32_t), + ('set_resources_header', uint32_t), + ('set_resources_dw1', uint32_t), + ('set_resources_dw2', uint32_t), + ('set_resources_dw3', uint32_t), + ('set_resources_dw4', uint32_t), + ('set_resources_dw5', uint32_t), + ('set_resources_dw6', uint32_t), + ('set_resources_dw7', uint32_t), + ('reserved_236', uint32_t), + ('reserved_237', uint32_t), + ('reserved_238', uint32_t), + ('reserved_239', uint32_t), + ('queue_doorbell_id0', uint32_t), + ('queue_doorbell_id1', uint32_t), + ('queue_doorbell_id2', uint32_t), + ('queue_doorbell_id3', uint32_t), + ('queue_doorbell_id4', uint32_t), + ('queue_doorbell_id5', uint32_t), + ('queue_doorbell_id6', uint32_t), + ('queue_doorbell_id7', uint32_t), + ('queue_doorbell_id8', uint32_t), + ('queue_doorbell_id9', uint32_t), + ('queue_doorbell_id10', uint32_t), + ('queue_doorbell_id11', uint32_t), + ('queue_doorbell_id12', uint32_t), + ('queue_doorbell_id13', uint32_t), + ('queue_doorbell_id14', uint32_t), + ('queue_doorbell_id15', uint32_t), + ('control_buf_addr_lo', uint32_t), + ('control_buf_addr_hi', uint32_t), + ('control_buf_wptr_lo', uint32_t), + ('control_buf_wptr_hi', uint32_t), + ('control_buf_dptr_lo', uint32_t), + ('control_buf_dptr_hi', uint32_t), + ('control_buf_num_entries', uint32_t), + ('draw_ring_addr_lo', uint32_t), + ('draw_ring_addr_hi', uint32_t), + ('reserved_265', uint32_t), + ('reserved_266', uint32_t), + ('reserved_267', uint32_t), + ('reserved_268', uint32_t), + ('reserved_269', uint32_t), + ('reserved_270', uint32_t), + ('reserved_271', uint32_t), + ('dfwx_flags', uint32_t), + ('dfwx_slot', uint32_t), + ('dfwx_client_data_addr_lo', uint32_t), + ('dfwx_client_data_addr_hi', uint32_t), + ('reserved_276', uint32_t), + ('reserved_277', uint32_t), + ('reserved_278', uint32_t), + ('reserved_279', uint32_t), + ('reserved_280', uint32_t), + ('reserved_281', uint32_t), + ('reserved_282', uint32_t), + ('reserved_283', uint32_t), + ('reserved_284', uint32_t), + ('reserved_285', uint32_t), + ('reserved_286', uint32_t), + ('reserved_287', uint32_t), + ('reserved_288', uint32_t), + ('reserved_289', uint32_t), + ('reserved_290', uint32_t), + ('reserved_291', uint32_t), + ('reserved_292', uint32_t), + ('reserved_293', uint32_t), + ('reserved_294', uint32_t), + ('reserved_295', uint32_t), + ('reserved_296', uint32_t), + ('reserved_297', uint32_t), + ('reserved_298', uint32_t), + ('reserved_299', uint32_t), + ('reserved_300', uint32_t), + ('reserved_301', uint32_t), + ('reserved_302', uint32_t), + ('reserved_303', uint32_t), + ('reserved_304', uint32_t), + ('reserved_305', uint32_t), + ('reserved_306', uint32_t), + ('reserved_307', uint32_t), + ('reserved_308', uint32_t), + ('reserved_309', uint32_t), + ('reserved_310', uint32_t), + ('reserved_311', uint32_t), + ('reserved_312', uint32_t), + ('reserved_313', uint32_t), + ('reserved_314', uint32_t), + ('reserved_315', uint32_t), + ('reserved_316', uint32_t), + ('reserved_317', uint32_t), + ('reserved_318', uint32_t), + ('reserved_319', uint32_t), + ('reserved_320', uint32_t), + ('reserved_321', uint32_t), + ('reserved_322', uint32_t), + ('reserved_323', uint32_t), + ('reserved_324', uint32_t), + ('reserved_325', uint32_t), + ('reserved_326', uint32_t), + ('reserved_327', uint32_t), + ('reserved_328', uint32_t), + ('reserved_329', uint32_t), + ('reserved_330', uint32_t), + ('reserved_331', uint32_t), + ('reserved_332', uint32_t), + ('reserved_333', uint32_t), + ('reserved_334', uint32_t), + ('reserved_335', uint32_t), + ('reserved_336', uint32_t), + ('reserved_337', uint32_t), + ('reserved_338', uint32_t), + ('reserved_339', uint32_t), + ('reserved_340', uint32_t), + ('reserved_341', uint32_t), + ('reserved_342', uint32_t), + ('reserved_343', uint32_t), + ('reserved_344', uint32_t), + ('reserved_345', uint32_t), + ('reserved_346', uint32_t), + ('reserved_347', uint32_t), + ('reserved_348', uint32_t), + ('reserved_349', uint32_t), + ('reserved_350', uint32_t), + ('reserved_351', uint32_t), + ('reserved_352', uint32_t), + ('reserved_353', uint32_t), + ('reserved_354', uint32_t), + ('reserved_355', uint32_t), + ('reserved_356', uint32_t), + ('reserved_357', uint32_t), + ('reserved_358', uint32_t), + ('reserved_359', uint32_t), + ('reserved_360', uint32_t), + ('reserved_361', uint32_t), + ('reserved_362', uint32_t), + ('reserved_363', uint32_t), + ('reserved_364', uint32_t), + ('reserved_365', uint32_t), + ('reserved_366', uint32_t), + ('reserved_367', uint32_t), + ('reserved_368', uint32_t), + ('reserved_369', uint32_t), + ('reserved_370', uint32_t), + ('reserved_371', uint32_t), + ('reserved_372', uint32_t), + ('reserved_373', uint32_t), + ('reserved_374', uint32_t), + ('reserved_375', uint32_t), + ('reserved_376', uint32_t), + ('reserved_377', uint32_t), + ('reserved_378', uint32_t), + ('reserved_379', uint32_t), + ('reserved_380', uint32_t), + ('reserved_381', uint32_t), + ('reserved_382', uint32_t), + ('reserved_383', uint32_t), + ('reserved_384', uint32_t), + ('reserved_385', uint32_t), + ('reserved_386', uint32_t), + ('reserved_387', uint32_t), + ('reserved_388', uint32_t), + ('reserved_389', uint32_t), + ('reserved_390', uint32_t), + ('reserved_391', uint32_t), + ('reserved_392', uint32_t), + ('reserved_393', uint32_t), + ('reserved_394', uint32_t), + ('reserved_395', uint32_t), + ('reserved_396', uint32_t), + ('reserved_397', uint32_t), + ('reserved_398', uint32_t), + ('reserved_399', uint32_t), + ('reserved_400', uint32_t), + ('reserved_401', uint32_t), + ('reserved_402', uint32_t), + ('reserved_403', uint32_t), + ('reserved_404', uint32_t), + ('reserved_405', uint32_t), + ('reserved_406', uint32_t), + ('reserved_407', uint32_t), + ('reserved_408', uint32_t), + ('reserved_409', uint32_t), + ('reserved_410', uint32_t), + ('reserved_411', uint32_t), + ('reserved_412', uint32_t), + ('reserved_413', uint32_t), + ('reserved_414', uint32_t), + ('reserved_415', uint32_t), + ('reserved_416', uint32_t), + ('reserved_417', uint32_t), + ('reserved_418', uint32_t), + ('reserved_419', uint32_t), + ('reserved_420', uint32_t), + ('reserved_421', uint32_t), + ('reserved_422', uint32_t), + ('reserved_423', uint32_t), + ('reserved_424', uint32_t), + ('reserved_425', uint32_t), + ('reserved_426', uint32_t), + ('reserved_427', uint32_t), + ('reserved_428', uint32_t), + ('reserved_429', uint32_t), + ('reserved_430', uint32_t), + ('reserved_431', uint32_t), + ('reserved_432', uint32_t), + ('reserved_433', uint32_t), + ('reserved_434', uint32_t), + ('reserved_435', uint32_t), + ('reserved_436', uint32_t), + ('reserved_437', uint32_t), + ('reserved_438', uint32_t), + ('reserved_439', uint32_t), + ('reserved_440', uint32_t), + ('reserved_441', uint32_t), + ('reserved_442', uint32_t), + ('reserved_443', uint32_t), + ('reserved_444', uint32_t), + ('reserved_445', uint32_t), + ('reserved_446', uint32_t), + ('reserved_447', uint32_t), + ('gws_0_val', uint32_t), + ('gws_1_val', uint32_t), + ('gws_2_val', uint32_t), + ('gws_3_val', uint32_t), + ('gws_4_val', uint32_t), + ('gws_5_val', uint32_t), + ('gws_6_val', uint32_t), + ('gws_7_val', uint32_t), + ('gws_8_val', uint32_t), + ('gws_9_val', uint32_t), + ('gws_10_val', uint32_t), + ('gws_11_val', uint32_t), + ('gws_12_val', uint32_t), + ('gws_13_val', uint32_t), + ('gws_14_val', uint32_t), + ('gws_15_val', uint32_t), + ('gws_16_val', uint32_t), + ('gws_17_val', uint32_t), + ('gws_18_val', uint32_t), + ('gws_19_val', uint32_t), + ('gws_20_val', uint32_t), + ('gws_21_val', uint32_t), + ('gws_22_val', uint32_t), + ('gws_23_val', uint32_t), + ('gws_24_val', uint32_t), + ('gws_25_val', uint32_t), + ('gws_26_val', uint32_t), + ('gws_27_val', uint32_t), + ('gws_28_val', uint32_t), + ('gws_29_val', uint32_t), + ('gws_30_val', uint32_t), + ('gws_31_val', uint32_t), + ('gws_32_val', uint32_t), + ('gws_33_val', uint32_t), + ('gws_34_val', uint32_t), + ('gws_35_val', uint32_t), + ('gws_36_val', uint32_t), + ('gws_37_val', uint32_t), + ('gws_38_val', uint32_t), + ('gws_39_val', uint32_t), + ('gws_40_val', uint32_t), + ('gws_41_val', uint32_t), + ('gws_42_val', uint32_t), + ('gws_43_val', uint32_t), + ('gws_44_val', uint32_t), + ('gws_45_val', uint32_t), + ('gws_46_val', uint32_t), + ('gws_47_val', uint32_t), + ('gws_48_val', uint32_t), + ('gws_49_val', uint32_t), + ('gws_50_val', uint32_t), + ('gws_51_val', uint32_t), + ('gws_52_val', uint32_t), + ('gws_53_val', uint32_t), + ('gws_54_val', uint32_t), + ('gws_55_val', uint32_t), + ('gws_56_val', uint32_t), + ('gws_57_val', uint32_t), + ('gws_58_val', uint32_t), + ('gws_59_val', uint32_t), + ('gws_60_val', uint32_t), + ('gws_61_val', uint32_t), + ('gws_62_val', uint32_t), + ('gws_63_val', uint32_t), +] enum_amdgpu_vm_level = CEnum(ctypes.c_uint32) AMDGPU_VM_PDB2 = enum_amdgpu_vm_level.define('AMDGPU_VM_PDB2', 0) AMDGPU_VM_PDB1 = enum_amdgpu_vm_level.define('AMDGPU_VM_PDB1', 1) @@ -1191,7 +2350,6 @@ struct_table_info._fields_ = [ ] table_info = struct_table_info class struct_binary_header(Struct): pass -uint32_t = ctypes.c_uint32 struct_binary_header._fields_ = [ ('binary_signature', uint32_t), ('version_major', uint16_t), diff --git a/tinygrad/runtime/autogen/am/pm4_nv.py b/tinygrad/runtime/autogen/am/pm4_nv.py index 3112463e2e..4b99c40cd8 100644 --- a/tinygrad/runtime/autogen/am/pm4_nv.py +++ b/tinygrad/runtime/autogen/am/pm4_nv.py @@ -3,34 +3,193 @@ import ctypes from tinygrad.helpers import unwrap from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR class union_PM4_MES_TYPE_3_HEADER(ctypes.Union): pass -class _anonstruct0(Struct): pass +class union_PM4_MES_TYPE_3_HEADER_0(Struct): pass +uint32_t = ctypes.c_uint32 +union_PM4_MES_TYPE_3_HEADER_0._fields_ = [ + ('reserved1', uint32_t,8), + ('opcode', uint32_t,8), + ('count', uint32_t,14), + ('type', uint32_t,2), +] +union_PM4_MES_TYPE_3_HEADER._anonymous_ = ['_0'] +union_PM4_MES_TYPE_3_HEADER._fields_ = [ + ('_0', union_PM4_MES_TYPE_3_HEADER_0), + ('u32All', uint32_t), +] enum_mes_set_resources_queue_type_enum = CEnum(ctypes.c_uint32) queue_type__mes_set_resources__kernel_interface_queue_kiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__kernel_interface_queue_kiq', 0) queue_type__mes_set_resources__hsa_interface_queue_hiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_interface_queue_hiq', 1) queue_type__mes_set_resources__hsa_debug_interface_queue = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_debug_interface_queue', 4) class struct_pm4_mes_set_resources(Struct): pass -class _anonunion1(ctypes.Union): pass -class _anonunion2(ctypes.Union): pass -class _anonstruct3(Struct): pass -class _anonunion4(ctypes.Union): pass -class _anonstruct5(Struct): pass -class _anonunion6(ctypes.Union): pass -class _anonstruct7(Struct): pass +class struct_pm4_mes_set_resources_0(ctypes.Union): pass +struct_pm4_mes_set_resources_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_set_resources_1(ctypes.Union): pass +class struct_pm4_mes_set_resources_1_bitfields2(Struct): pass +struct_pm4_mes_set_resources_1_bitfields2._fields_ = [ + ('vmid_mask', uint32_t,16), + ('unmap_latency', uint32_t,8), + ('reserved1', uint32_t,5), + ('queue_type', enum_mes_set_resources_queue_type_enum,3), +] +struct_pm4_mes_set_resources_1._fields_ = [ + ('bitfields2', struct_pm4_mes_set_resources_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_set_resources_2(ctypes.Union): pass +class struct_pm4_mes_set_resources_2_bitfields7(Struct): pass +struct_pm4_mes_set_resources_2_bitfields7._fields_ = [ + ('oac_mask', uint32_t,16), + ('reserved2', uint32_t,16), +] +struct_pm4_mes_set_resources_2._fields_ = [ + ('bitfields7', struct_pm4_mes_set_resources_2_bitfields7), + ('ordinal7', uint32_t), +] +class struct_pm4_mes_set_resources_3(ctypes.Union): pass +class struct_pm4_mes_set_resources_3_bitfields8(Struct): pass +struct_pm4_mes_set_resources_3_bitfields8._fields_ = [ + ('gds_heap_base', uint32_t,10), + ('reserved3', uint32_t,1), + ('gds_heap_size', uint32_t,10), + ('reserved4', uint32_t,11), +] +struct_pm4_mes_set_resources_3._fields_ = [ + ('bitfields8', struct_pm4_mes_set_resources_3_bitfields8), + ('ordinal8', uint32_t), +] +struct_pm4_mes_set_resources._anonymous_ = ['_0', '_1', '_2', '_3'] +struct_pm4_mes_set_resources._fields_ = [ + ('_0', struct_pm4_mes_set_resources_0), + ('_1', struct_pm4_mes_set_resources_1), + ('queue_mask_lo', uint32_t), + ('queue_mask_hi', uint32_t), + ('gws_mask_lo', uint32_t), + ('gws_mask_hi', uint32_t), + ('_2', struct_pm4_mes_set_resources_2), + ('_3', struct_pm4_mes_set_resources_3), +] class struct_pm4_mes_runlist(Struct): pass -class _anonunion8(ctypes.Union): pass -class _anonunion9(ctypes.Union): pass -class _anonstruct10(Struct): pass -class _anonunion11(ctypes.Union): pass -class _anonstruct12(Struct): pass +class struct_pm4_mes_runlist_0(ctypes.Union): pass +struct_pm4_mes_runlist_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_runlist_1(ctypes.Union): pass +class struct_pm4_mes_runlist_1_bitfields2(Struct): pass +struct_pm4_mes_runlist_1_bitfields2._fields_ = [ + ('reserved1', uint32_t,2), + ('ib_base_lo', uint32_t,30), +] +struct_pm4_mes_runlist_1._fields_ = [ + ('bitfields2', struct_pm4_mes_runlist_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_runlist_2(ctypes.Union): pass +class struct_pm4_mes_runlist_2_bitfields4(Struct): pass +struct_pm4_mes_runlist_2_bitfields4._fields_ = [ + ('ib_size', uint32_t,20), + ('chain', uint32_t,1), + ('offload_polling', uint32_t,1), + ('chained_runlist_idle_disable', uint32_t,1), + ('valid', uint32_t,1), + ('process_cnt', uint32_t,4), + ('reserved3', uint32_t,4), +] +struct_pm4_mes_runlist_2._fields_ = [ + ('bitfields4', struct_pm4_mes_runlist_2_bitfields4), + ('ordinal4', uint32_t), +] +struct_pm4_mes_runlist._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_runlist._fields_ = [ + ('_0', struct_pm4_mes_runlist_0), + ('_1', struct_pm4_mes_runlist_1), + ('ib_base_hi', uint32_t), + ('_2', struct_pm4_mes_runlist_2), +] class struct_pm4_mes_map_process(Struct): pass -class _anonunion13(ctypes.Union): pass -class _anonunion14(ctypes.Union): pass -class _anonstruct15(Struct): pass -class _anonunion16(ctypes.Union): pass -class _anonstruct17(Struct): pass +class struct_pm4_mes_map_process_0(ctypes.Union): pass +struct_pm4_mes_map_process_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_map_process_1(ctypes.Union): pass +class struct_pm4_mes_map_process_1_bitfields2(Struct): pass +struct_pm4_mes_map_process_1_bitfields2._fields_ = [ + ('pasid', uint32_t,16), + ('reserved1', uint32_t,1), + ('exec_cleaner_shader', uint32_t,1), + ('debug_vmid', uint32_t,4), + ('new_debug', uint32_t,1), + ('reserved2', uint32_t,1), + ('diq_enable', uint32_t,1), + ('process_quantum', uint32_t,7), +] +struct_pm4_mes_map_process_1._fields_ = [ + ('bitfields2', struct_pm4_mes_map_process_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_map_process_2(ctypes.Union): pass +class struct_pm4_mes_map_process_2_bitfields14(Struct): pass +struct_pm4_mes_map_process_2_bitfields14._fields_ = [ + ('num_gws', uint32_t,7), + ('sdma_enable', uint32_t,1), + ('num_oac', uint32_t,4), + ('gds_size_hi', uint32_t,4), + ('gds_size', uint32_t,6), + ('num_queues', uint32_t,10), +] +struct_pm4_mes_map_process_2._fields_ = [ + ('bitfields14', struct_pm4_mes_map_process_2_bitfields14), + ('ordinal14', uint32_t), +] +struct_pm4_mes_map_process._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_map_process._fields_ = [ + ('_0', struct_pm4_mes_map_process_0), + ('_1', struct_pm4_mes_map_process_1), + ('vm_context_page_table_base_addr_lo32', uint32_t), + ('vm_context_page_table_base_addr_hi32', uint32_t), + ('sh_mem_bases', uint32_t), + ('sh_mem_config', uint32_t), + ('sq_shader_tba_lo', uint32_t), + ('sq_shader_tba_hi', uint32_t), + ('sq_shader_tma_lo', uint32_t), + ('sq_shader_tma_hi', uint32_t), + ('reserved6', uint32_t), + ('gds_addr_lo', uint32_t), + ('gds_addr_hi', uint32_t), + ('_2', struct_pm4_mes_map_process_2), + ('completion_signal_lo', uint32_t), + ('completion_signal_hi', uint32_t), +] class struct_PM4_MES_MAP_PROCESS_VM(Struct): pass -class _anonunion18(ctypes.Union): pass +class struct_PM4_MES_MAP_PROCESS_VM_0(ctypes.Union): pass +struct_PM4_MES_MAP_PROCESS_VM_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +struct_PM4_MES_MAP_PROCESS_VM._anonymous_ = ['_0'] +struct_PM4_MES_MAP_PROCESS_VM._fields_ = [ + ('_0', struct_PM4_MES_MAP_PROCESS_VM_0), + ('reserved1', uint32_t), + ('vm_context_cntl', uint32_t), + ('reserved2', uint32_t), + ('vm_context_page_table_end_addr_lo32', uint32_t), + ('vm_context_page_table_end_addr_hi32', uint32_t), + ('vm_context_page_table_start_addr_lo32', uint32_t), + ('vm_context_page_table_start_addr_hi32', uint32_t), + ('reserved3', uint32_t), + ('reserved4', uint32_t), + ('reserved5', uint32_t), + ('reserved6', uint32_t), + ('reserved7', uint32_t), + ('reserved8', uint32_t), + ('completion_signal_lo32', uint32_t), + ('completion_signal_hi32', uint32_t), +] enum_mes_map_queues_queue_sel_enum = CEnum(ctypes.c_uint32) queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', 0) queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi', 1) @@ -52,11 +211,51 @@ extended_engine_sel__mes_map_queues__sdma0_to_7_sel = enum_mes_map_queues_extend extended_engine_sel__mes_map_queues__sdma8_to_15_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma8_to_15_sel', 2) class struct_pm4_mes_map_queues(Struct): pass -class _anonunion19(ctypes.Union): pass -class _anonunion20(ctypes.Union): pass -class _anonstruct21(Struct): pass -class _anonunion22(ctypes.Union): pass -class _anonstruct23(Struct): pass +class struct_pm4_mes_map_queues_0(ctypes.Union): pass +struct_pm4_mes_map_queues_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_map_queues_1(ctypes.Union): pass +class struct_pm4_mes_map_queues_1_bitfields2(Struct): pass +struct_pm4_mes_map_queues_1_bitfields2._fields_ = [ + ('reserved1', uint32_t,2), + ('extended_engine_sel', enum_mes_map_queues_extended_engine_sel_enum,2), + ('queue_sel', enum_mes_map_queues_queue_sel_enum,2), + ('reserved5', uint32_t,6), + ('gws_control_queue', uint32_t,1), + ('reserved2', uint32_t,8), + ('queue_type', enum_mes_map_queues_queue_type_enum,3), + ('reserved3', uint32_t,2), + ('engine_sel', enum_mes_map_queues_engine_sel_enum,3), + ('num_queues', uint32_t,3), +] +struct_pm4_mes_map_queues_1._fields_ = [ + ('bitfields2', struct_pm4_mes_map_queues_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_map_queues_2(ctypes.Union): pass +class struct_pm4_mes_map_queues_2_bitfields3(Struct): pass +struct_pm4_mes_map_queues_2_bitfields3._fields_ = [ + ('reserved3', uint32_t,1), + ('check_disable', uint32_t,1), + ('doorbell_offset', uint32_t,26), + ('reserved4', uint32_t,4), +] +struct_pm4_mes_map_queues_2._fields_ = [ + ('bitfields3', struct_pm4_mes_map_queues_2_bitfields3), + ('ordinal3', uint32_t), +] +struct_pm4_mes_map_queues._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_map_queues._fields_ = [ + ('_0', struct_pm4_mes_map_queues_0), + ('_1', struct_pm4_mes_map_queues_1), + ('_2', struct_pm4_mes_map_queues_2), + ('mqd_addr_lo', uint32_t), + ('mqd_addr_hi', uint32_t), + ('wptr_addr_lo', uint32_t), + ('wptr_addr_hi', uint32_t), +] enum_mes_query_status_interrupt_sel_enum = CEnum(ctypes.c_uint32) interrupt_sel__mes_query_status__completion_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__completion_status', 0) interrupt_sel__mes_query_status__process_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__process_status', 1) @@ -74,12 +273,50 @@ engine_sel__mes_query_status__sdma0_queue = enum_mes_query_status_engine_sel_enu engine_sel__mes_query_status__sdma1_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma1_queue', 3) class struct_pm4_mes_query_status(Struct): pass -class _anonunion24(ctypes.Union): pass -class _anonunion25(ctypes.Union): pass -class _anonstruct26(Struct): pass -class _anonunion27(ctypes.Union): pass -class _anonstruct28(Struct): pass -class _anonstruct29(Struct): pass +class struct_pm4_mes_query_status_0(ctypes.Union): pass +struct_pm4_mes_query_status_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_query_status_1(ctypes.Union): pass +class struct_pm4_mes_query_status_1_bitfields2(Struct): pass +struct_pm4_mes_query_status_1_bitfields2._fields_ = [ + ('context_id', uint32_t,28), + ('interrupt_sel', enum_mes_query_status_interrupt_sel_enum,2), + ('command', enum_mes_query_status_command_enum,2), +] +struct_pm4_mes_query_status_1._fields_ = [ + ('bitfields2', struct_pm4_mes_query_status_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_query_status_2(ctypes.Union): pass +class struct_pm4_mes_query_status_2_bitfields3a(Struct): pass +struct_pm4_mes_query_status_2_bitfields3a._fields_ = [ + ('pasid', uint32_t,16), + ('reserved1', uint32_t,16), +] +class struct_pm4_mes_query_status_2_bitfields3b(Struct): pass +struct_pm4_mes_query_status_2_bitfields3b._fields_ = [ + ('reserved2', uint32_t,2), + ('doorbell_offset', uint32_t,26), + ('engine_sel', enum_mes_query_status_engine_sel_enum,3), + ('reserved3', uint32_t,1), +] +struct_pm4_mes_query_status_2._fields_ = [ + ('bitfields3a', struct_pm4_mes_query_status_2_bitfields3a), + ('bitfields3b', struct_pm4_mes_query_status_2_bitfields3b), + ('ordinal3', uint32_t), +] +struct_pm4_mes_query_status._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_query_status._fields_ = [ + ('_0', struct_pm4_mes_query_status_0), + ('_1', struct_pm4_mes_query_status_1), + ('_2', struct_pm4_mes_query_status_2), + ('addr_lo', uint32_t), + ('addr_hi', uint32_t), + ('data_lo', uint32_t), + ('data_hi', uint32_t), +] enum_mes_unmap_queues_action_enum = CEnum(ctypes.c_uint32) action__mes_unmap_queues__preempt_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__preempt_queues', 0) action__mes_unmap_queues__reset_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reset_queues', 1) @@ -102,18 +339,85 @@ extended_engine_sel__mes_unmap_queues__legacy_engine_sel = enum_mes_unmap_queues extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel', 1) class struct_pm4_mes_unmap_queues(Struct): pass -class _anonunion30(ctypes.Union): pass -class _anonunion31(ctypes.Union): pass -class _anonstruct32(Struct): pass -class _anonunion33(ctypes.Union): pass -class _anonstruct34(Struct): pass -class _anonstruct35(Struct): pass -class _anonunion36(ctypes.Union): pass -class _anonstruct37(Struct): pass -class _anonunion38(ctypes.Union): pass -class _anonstruct39(Struct): pass -class _anonunion40(ctypes.Union): pass -class _anonstruct41(Struct): pass +class struct_pm4_mes_unmap_queues_0(ctypes.Union): pass +struct_pm4_mes_unmap_queues_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_unmap_queues_1(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_1_bitfields2(Struct): pass +struct_pm4_mes_unmap_queues_1_bitfields2._fields_ = [ + ('action', enum_mes_unmap_queues_action_enum,2), + ('extended_engine_sel', enum_mes_unmap_queues_extended_engine_sel_enum,2), + ('queue_sel', enum_mes_unmap_queues_queue_sel_enum,2), + ('reserved2', uint32_t,20), + ('engine_sel', enum_mes_unmap_queues_engine_sel_enum,3), + ('num_queues', uint32_t,3), +] +struct_pm4_mes_unmap_queues_1._fields_ = [ + ('bitfields2', struct_pm4_mes_unmap_queues_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_unmap_queues_2(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_2_bitfields3a(Struct): pass +struct_pm4_mes_unmap_queues_2_bitfields3a._fields_ = [ + ('pasid', uint32_t,16), + ('reserved3', uint32_t,16), +] +class struct_pm4_mes_unmap_queues_2_bitfields3b(Struct): pass +int32_t = ctypes.c_int32 +struct_pm4_mes_unmap_queues_2_bitfields3b._fields_ = [ + ('reserved4', uint32_t,2), + ('doorbell_offset0', uint32_t,26), + ('reserved5', int32_t,4), +] +struct_pm4_mes_unmap_queues_2._fields_ = [ + ('bitfields3a', struct_pm4_mes_unmap_queues_2_bitfields3a), + ('bitfields3b', struct_pm4_mes_unmap_queues_2_bitfields3b), + ('ordinal3', uint32_t), +] +class struct_pm4_mes_unmap_queues_3(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_3_bitfields4(Struct): pass +struct_pm4_mes_unmap_queues_3_bitfields4._fields_ = [ + ('reserved6', uint32_t,2), + ('doorbell_offset1', uint32_t,26), + ('reserved7', uint32_t,4), +] +struct_pm4_mes_unmap_queues_3._fields_ = [ + ('bitfields4', struct_pm4_mes_unmap_queues_3_bitfields4), + ('ordinal4', uint32_t), +] +class struct_pm4_mes_unmap_queues_4(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_4_bitfields5(Struct): pass +struct_pm4_mes_unmap_queues_4_bitfields5._fields_ = [ + ('reserved8', uint32_t,2), + ('doorbell_offset2', uint32_t,26), + ('reserved9', uint32_t,4), +] +struct_pm4_mes_unmap_queues_4._fields_ = [ + ('bitfields5', struct_pm4_mes_unmap_queues_4_bitfields5), + ('ordinal5', uint32_t), +] +class struct_pm4_mes_unmap_queues_5(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_5_bitfields6(Struct): pass +struct_pm4_mes_unmap_queues_5_bitfields6._fields_ = [ + ('reserved10', uint32_t,2), + ('doorbell_offset3', uint32_t,26), + ('reserved11', uint32_t,4), +] +struct_pm4_mes_unmap_queues_5._fields_ = [ + ('bitfields6', struct_pm4_mes_unmap_queues_5_bitfields6), + ('ordinal6', uint32_t), +] +struct_pm4_mes_unmap_queues._anonymous_ = ['_0', '_1', '_2', '_3', '_4', '_5'] +struct_pm4_mes_unmap_queues._fields_ = [ + ('_0', struct_pm4_mes_unmap_queues_0), + ('_1', struct_pm4_mes_unmap_queues_1), + ('_2', struct_pm4_mes_unmap_queues_2), + ('_3', struct_pm4_mes_unmap_queues_3), + ('_4', struct_pm4_mes_unmap_queues_4), + ('_5', struct_pm4_mes_unmap_queues_5), +] enum_mec_release_mem_event_index_enum = CEnum(ctypes.c_uint32) event_index__mec_release_mem__end_of_pipe = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__end_of_pipe', 5) event_index__mec_release_mem__shader_done = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__shader_done', 6) @@ -150,18 +454,106 @@ data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = enum_mec_release_mem_data data_sel__mec_release_mem__store_gds_data_to_memory = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__store_gds_data_to_memory', 5) class struct_pm4_mec_release_mem(Struct): pass -class _anonunion42(ctypes.Union): pass -class _anonunion43(ctypes.Union): pass -class _anonstruct44(Struct): pass -class _anonunion45(ctypes.Union): pass -class _anonstruct46(Struct): pass -class _anonunion47(ctypes.Union): pass -class _anonstruct48(Struct): pass -class _anonstruct49(Struct): pass -class _anonunion50(ctypes.Union): pass -class _anonunion51(ctypes.Union): pass -class _anonstruct52(Struct): pass -class _anonunion53(ctypes.Union): pass +class struct_pm4_mec_release_mem_0(ctypes.Union): pass +struct_pm4_mec_release_mem_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_1(ctypes.Union): pass +class struct_pm4_mec_release_mem_1_bitfields2(Struct): pass +struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ + ('event_type', ctypes.c_uint32,6), + ('reserved1', ctypes.c_uint32,2), + ('event_index', enum_mec_release_mem_event_index_enum,4), + ('tcl1_vol_action_ena', ctypes.c_uint32,1), + ('tc_vol_action_ena', ctypes.c_uint32,1), + ('reserved2', ctypes.c_uint32,1), + ('tc_wb_action_ena', ctypes.c_uint32,1), + ('tcl1_action_ena', ctypes.c_uint32,1), + ('tc_action_ena', ctypes.c_uint32,1), + ('reserved3', uint32_t,1), + ('tc_nc_action_ena', uint32_t,1), + ('tc_wc_action_ena', uint32_t,1), + ('tc_md_action_ena', uint32_t,1), + ('reserved4', uint32_t,3), + ('cache_policy', enum_mec_release_mem_cache_policy_enum,2), + ('reserved5', uint32_t,2), + ('pq_exe_status', enum_mec_release_mem_pq_exe_status_enum,1), + ('reserved6', uint32_t,2), +] +struct_pm4_mec_release_mem_1._fields_ = [ + ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_2(ctypes.Union): pass +class struct_pm4_mec_release_mem_2_bitfields3(Struct): pass +struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ + ('reserved7', uint32_t,16), + ('dst_sel', enum_mec_release_mem_dst_sel_enum,2), + ('reserved8', uint32_t,6), + ('int_sel', enum_mec_release_mem_int_sel_enum,3), + ('reserved9', uint32_t,2), + ('data_sel', enum_mec_release_mem_data_sel_enum,3), +] +struct_pm4_mec_release_mem_2._fields_ = [ + ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_3(ctypes.Union): pass +class struct_pm4_mec_release_mem_3_bitfields4(Struct): pass +struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ + ('reserved10', uint32_t,2), + ('address_lo_32b', ctypes.c_uint32,30), +] +class struct_pm4_mec_release_mem_3_bitfields4b(Struct): pass +struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ + ('reserved11', uint32_t,3), + ('address_lo_64b', uint32_t,29), +] +struct_pm4_mec_release_mem_3._fields_ = [ + ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), + ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), + ('reserved12', uint32_t), + ('ordinal4', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_4(ctypes.Union): pass +struct_pm4_mec_release_mem_4._fields_ = [ + ('address_hi', uint32_t), + ('reserved13', uint32_t), + ('ordinal5', uint32_t), +] +class struct_pm4_mec_release_mem_5(ctypes.Union): pass +class struct_pm4_mec_release_mem_5_bitfields6c(Struct): pass +struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ + ('dw_offset', uint32_t,16), + ('num_dwords', uint32_t,16), +] +struct_pm4_mec_release_mem_5._fields_ = [ + ('data_lo', uint32_t), + ('cmp_data_lo', uint32_t), + ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), + ('reserved14', uint32_t), + ('ordinal6', uint32_t), +] +class struct_pm4_mec_release_mem_6(ctypes.Union): pass +struct_pm4_mec_release_mem_6._fields_ = [ + ('data_hi', uint32_t), + ('cmp_data_hi', uint32_t), + ('reserved15', uint32_t), + ('reserved16', uint32_t), + ('ordinal7', uint32_t), +] +struct_pm4_mec_release_mem._anonymous_ = ['_0', '_1', '_2', '_3', '_4', '_5', '_6'] +struct_pm4_mec_release_mem._fields_ = [ + ('_0', struct_pm4_mec_release_mem_0), + ('_1', struct_pm4_mec_release_mem_1), + ('_2', struct_pm4_mec_release_mem_2), + ('_3', struct_pm4_mec_release_mem_3), + ('_4', struct_pm4_mec_release_mem_4), + ('_5', struct_pm4_mec_release_mem_5), + ('_6', struct_pm4_mec_release_mem_6), + ('int_ctxid', uint32_t), +] enum_WRITE_DATA_dst_sel_enum = CEnum(ctypes.c_uint32) dst_sel___write_data__mem_mapped_register = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__mem_mapped_register', 0) dst_sel___write_data__tc_l2 = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__tc_l2', 2) @@ -182,10 +574,14 @@ cache_policy___write_data__lru = enum_WRITE_DATA_cache_policy_enum.define('cache cache_policy___write_data__stream = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__stream', 1) class struct_pm4_mec_write_data_mmio(Struct): pass -class _anonunion54(ctypes.Union): pass -class _anonunion55(ctypes.Union): pass -class _anonunion55_bitfields2(Struct): pass -_anonunion55_bitfields2._fields_ = [ +class struct_pm4_mec_write_data_mmio_0(ctypes.Union): pass +struct_pm4_mec_write_data_mmio_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] +class struct_pm4_mec_write_data_mmio_1(ctypes.Union): pass +class struct_pm4_mec_write_data_mmio_1_bitfields2(Struct): pass +struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ ('reserved1', ctypes.c_uint32,8), ('dst_sel', ctypes.c_uint32,4), ('reserved2', ctypes.c_uint32,4), @@ -197,22 +593,30 @@ _anonunion55_bitfields2._fields_ = [ ('cache_policy', ctypes.c_uint32,2), ('reserved5', ctypes.c_uint32,5), ] -_anonunion55._fields_ = [ - ('bitfields2', _anonunion55_bitfields2), +struct_pm4_mec_write_data_mmio_1._fields_ = [ + ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), ('ordinal2', ctypes.c_uint32), ] -class _anonunion56(ctypes.Union): pass -class _anonunion56_bitfields3(Struct): pass -_anonunion56_bitfields3._fields_ = [ +class struct_pm4_mec_write_data_mmio_2(ctypes.Union): pass +class struct_pm4_mec_write_data_mmio_2_bitfields3(Struct): pass +struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ ('dst_mmreg_addr', ctypes.c_uint32,18), ('reserved6', ctypes.c_uint32,14), ] -_anonunion56._fields_ = [ - ('bitfields3', _anonunion56_bitfields3), +struct_pm4_mec_write_data_mmio_2._fields_ = [ + ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), ('ordinal3', ctypes.c_uint32), ] -_anonenum57 = CEnum(ctypes.c_uint32) -CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum57.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) +struct_pm4_mec_write_data_mmio._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mec_write_data_mmio._fields_ = [ + ('_0', struct_pm4_mec_write_data_mmio_0), + ('_1', struct_pm4_mec_write_data_mmio_1), + ('_2', struct_pm4_mec_write_data_mmio_2), + ('reserved7', uint32_t), + ('data', uint32_t), +] +_anonenum0 = CEnum(ctypes.c_uint32) +CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum0.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) PACKET_TYPE0 = 0 PACKET_TYPE1 = 1 diff --git a/tinygrad/runtime/autogen/am/pm4_soc15.py b/tinygrad/runtime/autogen/am/pm4_soc15.py index e2e82937d1..8e69eba9e7 100644 --- a/tinygrad/runtime/autogen/am/pm4_soc15.py +++ b/tinygrad/runtime/autogen/am/pm4_soc15.py @@ -3,34 +3,193 @@ import ctypes from tinygrad.helpers import unwrap from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR class union_PM4_MES_TYPE_3_HEADER(ctypes.Union): pass -class _anonstruct0(Struct): pass +class union_PM4_MES_TYPE_3_HEADER_0(Struct): pass +uint32_t = ctypes.c_uint32 +union_PM4_MES_TYPE_3_HEADER_0._fields_ = [ + ('reserved1', uint32_t,8), + ('opcode', uint32_t,8), + ('count', uint32_t,14), + ('type', uint32_t,2), +] +union_PM4_MES_TYPE_3_HEADER._anonymous_ = ['_0'] +union_PM4_MES_TYPE_3_HEADER._fields_ = [ + ('_0', union_PM4_MES_TYPE_3_HEADER_0), + ('u32All', uint32_t), +] enum_mes_set_resources_queue_type_enum = CEnum(ctypes.c_uint32) queue_type__mes_set_resources__kernel_interface_queue_kiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__kernel_interface_queue_kiq', 0) queue_type__mes_set_resources__hsa_interface_queue_hiq = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_interface_queue_hiq', 1) queue_type__mes_set_resources__hsa_debug_interface_queue = enum_mes_set_resources_queue_type_enum.define('queue_type__mes_set_resources__hsa_debug_interface_queue', 4) class struct_pm4_mes_set_resources(Struct): pass -class _anonunion1(ctypes.Union): pass -class _anonunion2(ctypes.Union): pass -class _anonstruct3(Struct): pass -class _anonunion4(ctypes.Union): pass -class _anonstruct5(Struct): pass -class _anonunion6(ctypes.Union): pass -class _anonstruct7(Struct): pass +class struct_pm4_mes_set_resources_0(ctypes.Union): pass +struct_pm4_mes_set_resources_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_set_resources_1(ctypes.Union): pass +class struct_pm4_mes_set_resources_1_bitfields2(Struct): pass +struct_pm4_mes_set_resources_1_bitfields2._fields_ = [ + ('vmid_mask', uint32_t,16), + ('unmap_latency', uint32_t,8), + ('reserved1', uint32_t,5), + ('queue_type', enum_mes_set_resources_queue_type_enum,3), +] +struct_pm4_mes_set_resources_1._fields_ = [ + ('bitfields2', struct_pm4_mes_set_resources_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_set_resources_2(ctypes.Union): pass +class struct_pm4_mes_set_resources_2_bitfields7(Struct): pass +struct_pm4_mes_set_resources_2_bitfields7._fields_ = [ + ('oac_mask', uint32_t,16), + ('reserved2', uint32_t,16), +] +struct_pm4_mes_set_resources_2._fields_ = [ + ('bitfields7', struct_pm4_mes_set_resources_2_bitfields7), + ('ordinal7', uint32_t), +] +class struct_pm4_mes_set_resources_3(ctypes.Union): pass +class struct_pm4_mes_set_resources_3_bitfields8(Struct): pass +struct_pm4_mes_set_resources_3_bitfields8._fields_ = [ + ('gds_heap_base', uint32_t,10), + ('reserved3', uint32_t,1), + ('gds_heap_size', uint32_t,10), + ('reserved4', uint32_t,11), +] +struct_pm4_mes_set_resources_3._fields_ = [ + ('bitfields8', struct_pm4_mes_set_resources_3_bitfields8), + ('ordinal8', uint32_t), +] +struct_pm4_mes_set_resources._anonymous_ = ['_0', '_1', '_2', '_3'] +struct_pm4_mes_set_resources._fields_ = [ + ('_0', struct_pm4_mes_set_resources_0), + ('_1', struct_pm4_mes_set_resources_1), + ('queue_mask_lo', uint32_t), + ('queue_mask_hi', uint32_t), + ('gws_mask_lo', uint32_t), + ('gws_mask_hi', uint32_t), + ('_2', struct_pm4_mes_set_resources_2), + ('_3', struct_pm4_mes_set_resources_3), +] class struct_pm4_mes_runlist(Struct): pass -class _anonunion8(ctypes.Union): pass -class _anonunion9(ctypes.Union): pass -class _anonstruct10(Struct): pass -class _anonunion11(ctypes.Union): pass -class _anonstruct12(Struct): pass +class struct_pm4_mes_runlist_0(ctypes.Union): pass +struct_pm4_mes_runlist_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_runlist_1(ctypes.Union): pass +class struct_pm4_mes_runlist_1_bitfields2(Struct): pass +struct_pm4_mes_runlist_1_bitfields2._fields_ = [ + ('reserved1', uint32_t,2), + ('ib_base_lo', uint32_t,30), +] +struct_pm4_mes_runlist_1._fields_ = [ + ('bitfields2', struct_pm4_mes_runlist_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_runlist_2(ctypes.Union): pass +class struct_pm4_mes_runlist_2_bitfields4(Struct): pass +struct_pm4_mes_runlist_2_bitfields4._fields_ = [ + ('ib_size', uint32_t,20), + ('chain', uint32_t,1), + ('offload_polling', uint32_t,1), + ('chained_runlist_idle_disable', uint32_t,1), + ('valid', uint32_t,1), + ('process_cnt', uint32_t,4), + ('reserved3', uint32_t,4), +] +struct_pm4_mes_runlist_2._fields_ = [ + ('bitfields4', struct_pm4_mes_runlist_2_bitfields4), + ('ordinal4', uint32_t), +] +struct_pm4_mes_runlist._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_runlist._fields_ = [ + ('_0', struct_pm4_mes_runlist_0), + ('_1', struct_pm4_mes_runlist_1), + ('ib_base_hi', uint32_t), + ('_2', struct_pm4_mes_runlist_2), +] class struct_pm4_mes_map_process(Struct): pass -class _anonunion13(ctypes.Union): pass -class _anonunion14(ctypes.Union): pass -class _anonstruct15(Struct): pass -class _anonunion16(ctypes.Union): pass -class _anonstruct17(Struct): pass +class struct_pm4_mes_map_process_0(ctypes.Union): pass +struct_pm4_mes_map_process_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_map_process_1(ctypes.Union): pass +class struct_pm4_mes_map_process_1_bitfields2(Struct): pass +struct_pm4_mes_map_process_1_bitfields2._fields_ = [ + ('pasid', uint32_t,16), + ('reserved1', uint32_t,1), + ('exec_cleaner_shader', uint32_t,1), + ('debug_vmid', uint32_t,4), + ('new_debug', uint32_t,1), + ('reserved2', uint32_t,1), + ('diq_enable', uint32_t,1), + ('process_quantum', uint32_t,7), +] +struct_pm4_mes_map_process_1._fields_ = [ + ('bitfields2', struct_pm4_mes_map_process_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_map_process_2(ctypes.Union): pass +class struct_pm4_mes_map_process_2_bitfields14(Struct): pass +struct_pm4_mes_map_process_2_bitfields14._fields_ = [ + ('num_gws', uint32_t,7), + ('sdma_enable', uint32_t,1), + ('num_oac', uint32_t,4), + ('gds_size_hi', uint32_t,4), + ('gds_size', uint32_t,6), + ('num_queues', uint32_t,10), +] +struct_pm4_mes_map_process_2._fields_ = [ + ('bitfields14', struct_pm4_mes_map_process_2_bitfields14), + ('ordinal14', uint32_t), +] +struct_pm4_mes_map_process._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_map_process._fields_ = [ + ('_0', struct_pm4_mes_map_process_0), + ('_1', struct_pm4_mes_map_process_1), + ('vm_context_page_table_base_addr_lo32', uint32_t), + ('vm_context_page_table_base_addr_hi32', uint32_t), + ('sh_mem_bases', uint32_t), + ('sh_mem_config', uint32_t), + ('sq_shader_tba_lo', uint32_t), + ('sq_shader_tba_hi', uint32_t), + ('sq_shader_tma_lo', uint32_t), + ('sq_shader_tma_hi', uint32_t), + ('reserved6', uint32_t), + ('gds_addr_lo', uint32_t), + ('gds_addr_hi', uint32_t), + ('_2', struct_pm4_mes_map_process_2), + ('completion_signal_lo', uint32_t), + ('completion_signal_hi', uint32_t), +] class struct_PM4_MES_MAP_PROCESS_VM(Struct): pass -class _anonunion18(ctypes.Union): pass +class struct_PM4_MES_MAP_PROCESS_VM_0(ctypes.Union): pass +struct_PM4_MES_MAP_PROCESS_VM_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +struct_PM4_MES_MAP_PROCESS_VM._anonymous_ = ['_0'] +struct_PM4_MES_MAP_PROCESS_VM._fields_ = [ + ('_0', struct_PM4_MES_MAP_PROCESS_VM_0), + ('reserved1', uint32_t), + ('vm_context_cntl', uint32_t), + ('reserved2', uint32_t), + ('vm_context_page_table_end_addr_lo32', uint32_t), + ('vm_context_page_table_end_addr_hi32', uint32_t), + ('vm_context_page_table_start_addr_lo32', uint32_t), + ('vm_context_page_table_start_addr_hi32', uint32_t), + ('reserved3', uint32_t), + ('reserved4', uint32_t), + ('reserved5', uint32_t), + ('reserved6', uint32_t), + ('reserved7', uint32_t), + ('reserved8', uint32_t), + ('completion_signal_lo32', uint32_t), + ('completion_signal_hi32', uint32_t), +] enum_mes_map_queues_queue_sel_enum = CEnum(ctypes.c_uint32) queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_specified_queue_slots_vi', 0) queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = enum_mes_map_queues_queue_sel_enum.define('queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi', 1) @@ -52,11 +211,51 @@ extended_engine_sel__mes_map_queues__sdma0_to_7_sel = enum_mes_map_queues_extend extended_engine_sel__mes_map_queues__sdma8_to_15_sel = enum_mes_map_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_map_queues__sdma8_to_15_sel', 2) class struct_pm4_mes_map_queues(Struct): pass -class _anonunion19(ctypes.Union): pass -class _anonunion20(ctypes.Union): pass -class _anonstruct21(Struct): pass -class _anonunion22(ctypes.Union): pass -class _anonstruct23(Struct): pass +class struct_pm4_mes_map_queues_0(ctypes.Union): pass +struct_pm4_mes_map_queues_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_map_queues_1(ctypes.Union): pass +class struct_pm4_mes_map_queues_1_bitfields2(Struct): pass +struct_pm4_mes_map_queues_1_bitfields2._fields_ = [ + ('reserved1', uint32_t,2), + ('extended_engine_sel', enum_mes_map_queues_extended_engine_sel_enum,2), + ('queue_sel', enum_mes_map_queues_queue_sel_enum,2), + ('reserved5', uint32_t,6), + ('gws_control_queue', uint32_t,1), + ('reserved2', uint32_t,8), + ('queue_type', enum_mes_map_queues_queue_type_enum,3), + ('reserved3', uint32_t,2), + ('engine_sel', enum_mes_map_queues_engine_sel_enum,3), + ('num_queues', uint32_t,3), +] +struct_pm4_mes_map_queues_1._fields_ = [ + ('bitfields2', struct_pm4_mes_map_queues_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_map_queues_2(ctypes.Union): pass +class struct_pm4_mes_map_queues_2_bitfields3(Struct): pass +struct_pm4_mes_map_queues_2_bitfields3._fields_ = [ + ('reserved3', uint32_t,1), + ('check_disable', uint32_t,1), + ('doorbell_offset', uint32_t,26), + ('reserved4', uint32_t,4), +] +struct_pm4_mes_map_queues_2._fields_ = [ + ('bitfields3', struct_pm4_mes_map_queues_2_bitfields3), + ('ordinal3', uint32_t), +] +struct_pm4_mes_map_queues._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_map_queues._fields_ = [ + ('_0', struct_pm4_mes_map_queues_0), + ('_1', struct_pm4_mes_map_queues_1), + ('_2', struct_pm4_mes_map_queues_2), + ('mqd_addr_lo', uint32_t), + ('mqd_addr_hi', uint32_t), + ('wptr_addr_lo', uint32_t), + ('wptr_addr_hi', uint32_t), +] enum_mes_query_status_interrupt_sel_enum = CEnum(ctypes.c_uint32) interrupt_sel__mes_query_status__completion_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__completion_status', 0) interrupt_sel__mes_query_status__process_status = enum_mes_query_status_interrupt_sel_enum.define('interrupt_sel__mes_query_status__process_status', 1) @@ -74,12 +273,50 @@ engine_sel__mes_query_status__sdma0_queue = enum_mes_query_status_engine_sel_enu engine_sel__mes_query_status__sdma1_queue = enum_mes_query_status_engine_sel_enum.define('engine_sel__mes_query_status__sdma1_queue', 3) class struct_pm4_mes_query_status(Struct): pass -class _anonunion24(ctypes.Union): pass -class _anonunion25(ctypes.Union): pass -class _anonstruct26(Struct): pass -class _anonunion27(ctypes.Union): pass -class _anonstruct28(Struct): pass -class _anonstruct29(Struct): pass +class struct_pm4_mes_query_status_0(ctypes.Union): pass +struct_pm4_mes_query_status_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_query_status_1(ctypes.Union): pass +class struct_pm4_mes_query_status_1_bitfields2(Struct): pass +struct_pm4_mes_query_status_1_bitfields2._fields_ = [ + ('context_id', uint32_t,28), + ('interrupt_sel', enum_mes_query_status_interrupt_sel_enum,2), + ('command', enum_mes_query_status_command_enum,2), +] +struct_pm4_mes_query_status_1._fields_ = [ + ('bitfields2', struct_pm4_mes_query_status_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_query_status_2(ctypes.Union): pass +class struct_pm4_mes_query_status_2_bitfields3a(Struct): pass +struct_pm4_mes_query_status_2_bitfields3a._fields_ = [ + ('pasid', uint32_t,16), + ('reserved1', uint32_t,16), +] +class struct_pm4_mes_query_status_2_bitfields3b(Struct): pass +struct_pm4_mes_query_status_2_bitfields3b._fields_ = [ + ('reserved2', uint32_t,2), + ('doorbell_offset', uint32_t,26), + ('engine_sel', enum_mes_query_status_engine_sel_enum,3), + ('reserved3', uint32_t,1), +] +struct_pm4_mes_query_status_2._fields_ = [ + ('bitfields3a', struct_pm4_mes_query_status_2_bitfields3a), + ('bitfields3b', struct_pm4_mes_query_status_2_bitfields3b), + ('ordinal3', uint32_t), +] +struct_pm4_mes_query_status._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mes_query_status._fields_ = [ + ('_0', struct_pm4_mes_query_status_0), + ('_1', struct_pm4_mes_query_status_1), + ('_2', struct_pm4_mes_query_status_2), + ('addr_lo', uint32_t), + ('addr_hi', uint32_t), + ('data_lo', uint32_t), + ('data_hi', uint32_t), +] enum_mes_unmap_queues_action_enum = CEnum(ctypes.c_uint32) action__mes_unmap_queues__preempt_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__preempt_queues', 0) action__mes_unmap_queues__reset_queues = enum_mes_unmap_queues_action_enum.define('action__mes_unmap_queues__reset_queues', 1) @@ -102,18 +339,85 @@ extended_engine_sel__mes_unmap_queues__legacy_engine_sel = enum_mes_unmap_queues extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = enum_mes_unmap_queues_extended_engine_sel_enum.define('extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel', 1) class struct_pm4_mes_unmap_queues(Struct): pass -class _anonunion30(ctypes.Union): pass -class _anonunion31(ctypes.Union): pass -class _anonstruct32(Struct): pass -class _anonunion33(ctypes.Union): pass -class _anonstruct34(Struct): pass -class _anonstruct35(Struct): pass -class _anonunion36(ctypes.Union): pass -class _anonstruct37(Struct): pass -class _anonunion38(ctypes.Union): pass -class _anonstruct39(Struct): pass -class _anonunion40(ctypes.Union): pass -class _anonstruct41(Struct): pass +class struct_pm4_mes_unmap_queues_0(ctypes.Union): pass +struct_pm4_mes_unmap_queues_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', uint32_t), +] +class struct_pm4_mes_unmap_queues_1(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_1_bitfields2(Struct): pass +struct_pm4_mes_unmap_queues_1_bitfields2._fields_ = [ + ('action', enum_mes_unmap_queues_action_enum,2), + ('extended_engine_sel', enum_mes_unmap_queues_extended_engine_sel_enum,2), + ('queue_sel', enum_mes_unmap_queues_queue_sel_enum,2), + ('reserved2', uint32_t,20), + ('engine_sel', enum_mes_unmap_queues_engine_sel_enum,3), + ('num_queues', uint32_t,3), +] +struct_pm4_mes_unmap_queues_1._fields_ = [ + ('bitfields2', struct_pm4_mes_unmap_queues_1_bitfields2), + ('ordinal2', uint32_t), +] +class struct_pm4_mes_unmap_queues_2(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_2_bitfields3a(Struct): pass +struct_pm4_mes_unmap_queues_2_bitfields3a._fields_ = [ + ('pasid', uint32_t,16), + ('reserved3', uint32_t,16), +] +class struct_pm4_mes_unmap_queues_2_bitfields3b(Struct): pass +int32_t = ctypes.c_int32 +struct_pm4_mes_unmap_queues_2_bitfields3b._fields_ = [ + ('reserved4', uint32_t,2), + ('doorbell_offset0', uint32_t,26), + ('reserved5', int32_t,4), +] +struct_pm4_mes_unmap_queues_2._fields_ = [ + ('bitfields3a', struct_pm4_mes_unmap_queues_2_bitfields3a), + ('bitfields3b', struct_pm4_mes_unmap_queues_2_bitfields3b), + ('ordinal3', uint32_t), +] +class struct_pm4_mes_unmap_queues_3(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_3_bitfields4(Struct): pass +struct_pm4_mes_unmap_queues_3_bitfields4._fields_ = [ + ('reserved6', uint32_t,2), + ('doorbell_offset1', uint32_t,26), + ('reserved7', uint32_t,4), +] +struct_pm4_mes_unmap_queues_3._fields_ = [ + ('bitfields4', struct_pm4_mes_unmap_queues_3_bitfields4), + ('ordinal4', uint32_t), +] +class struct_pm4_mes_unmap_queues_4(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_4_bitfields5(Struct): pass +struct_pm4_mes_unmap_queues_4_bitfields5._fields_ = [ + ('reserved8', uint32_t,2), + ('doorbell_offset2', uint32_t,26), + ('reserved9', uint32_t,4), +] +struct_pm4_mes_unmap_queues_4._fields_ = [ + ('bitfields5', struct_pm4_mes_unmap_queues_4_bitfields5), + ('ordinal5', uint32_t), +] +class struct_pm4_mes_unmap_queues_5(ctypes.Union): pass +class struct_pm4_mes_unmap_queues_5_bitfields6(Struct): pass +struct_pm4_mes_unmap_queues_5_bitfields6._fields_ = [ + ('reserved10', uint32_t,2), + ('doorbell_offset3', uint32_t,26), + ('reserved11', uint32_t,4), +] +struct_pm4_mes_unmap_queues_5._fields_ = [ + ('bitfields6', struct_pm4_mes_unmap_queues_5_bitfields6), + ('ordinal6', uint32_t), +] +struct_pm4_mes_unmap_queues._anonymous_ = ['_0', '_1', '_2', '_3', '_4', '_5'] +struct_pm4_mes_unmap_queues._fields_ = [ + ('_0', struct_pm4_mes_unmap_queues_0), + ('_1', struct_pm4_mes_unmap_queues_1), + ('_2', struct_pm4_mes_unmap_queues_2), + ('_3', struct_pm4_mes_unmap_queues_3), + ('_4', struct_pm4_mes_unmap_queues_4), + ('_5', struct_pm4_mes_unmap_queues_5), +] enum_mec_release_mem_event_index_enum = CEnum(ctypes.c_uint32) event_index__mec_release_mem__end_of_pipe = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__end_of_pipe', 5) event_index__mec_release_mem__shader_done = enum_mec_release_mem_event_index_enum.define('event_index__mec_release_mem__shader_done', 6) @@ -150,18 +454,106 @@ data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = enum_mec_release_mem_data data_sel__mec_release_mem__store_gds_data_to_memory = enum_mec_release_mem_data_sel_enum.define('data_sel__mec_release_mem__store_gds_data_to_memory', 5) class struct_pm4_mec_release_mem(Struct): pass -class _anonunion42(ctypes.Union): pass -class _anonunion43(ctypes.Union): pass -class _anonstruct44(Struct): pass -class _anonunion45(ctypes.Union): pass -class _anonstruct46(Struct): pass -class _anonunion47(ctypes.Union): pass -class _anonstruct48(Struct): pass -class _anonstruct49(Struct): pass -class _anonunion50(ctypes.Union): pass -class _anonunion51(ctypes.Union): pass -class _anonstruct52(Struct): pass -class _anonunion53(ctypes.Union): pass +class struct_pm4_mec_release_mem_0(ctypes.Union): pass +struct_pm4_mec_release_mem_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_1(ctypes.Union): pass +class struct_pm4_mec_release_mem_1_bitfields2(Struct): pass +struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ + ('event_type', ctypes.c_uint32,6), + ('reserved1', ctypes.c_uint32,2), + ('event_index', enum_mec_release_mem_event_index_enum,4), + ('tcl1_vol_action_ena', ctypes.c_uint32,1), + ('tc_vol_action_ena', ctypes.c_uint32,1), + ('reserved2', ctypes.c_uint32,1), + ('tc_wb_action_ena', ctypes.c_uint32,1), + ('tcl1_action_ena', ctypes.c_uint32,1), + ('tc_action_ena', ctypes.c_uint32,1), + ('reserved3', uint32_t,1), + ('tc_nc_action_ena', uint32_t,1), + ('tc_wc_action_ena', uint32_t,1), + ('tc_md_action_ena', uint32_t,1), + ('reserved4', uint32_t,3), + ('cache_policy', enum_mec_release_mem_cache_policy_enum,2), + ('reserved5', uint32_t,2), + ('pq_exe_status', enum_mec_release_mem_pq_exe_status_enum,1), + ('reserved6', uint32_t,2), +] +struct_pm4_mec_release_mem_1._fields_ = [ + ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_2(ctypes.Union): pass +class struct_pm4_mec_release_mem_2_bitfields3(Struct): pass +struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ + ('reserved7', uint32_t,16), + ('dst_sel', enum_mec_release_mem_dst_sel_enum,2), + ('reserved8', uint32_t,6), + ('int_sel', enum_mec_release_mem_int_sel_enum,3), + ('reserved9', uint32_t,2), + ('data_sel', enum_mec_release_mem_data_sel_enum,3), +] +struct_pm4_mec_release_mem_2._fields_ = [ + ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_3(ctypes.Union): pass +class struct_pm4_mec_release_mem_3_bitfields4(Struct): pass +struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ + ('reserved10', uint32_t,2), + ('address_lo_32b', ctypes.c_uint32,30), +] +class struct_pm4_mec_release_mem_3_bitfields4b(Struct): pass +struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ + ('reserved11', uint32_t,3), + ('address_lo_64b', uint32_t,29), +] +struct_pm4_mec_release_mem_3._fields_ = [ + ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), + ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), + ('reserved12', uint32_t), + ('ordinal4', ctypes.c_uint32), +] +class struct_pm4_mec_release_mem_4(ctypes.Union): pass +struct_pm4_mec_release_mem_4._fields_ = [ + ('address_hi', uint32_t), + ('reserved13', uint32_t), + ('ordinal5', uint32_t), +] +class struct_pm4_mec_release_mem_5(ctypes.Union): pass +class struct_pm4_mec_release_mem_5_bitfields6c(Struct): pass +struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ + ('dw_offset', uint32_t,16), + ('num_dwords', uint32_t,16), +] +struct_pm4_mec_release_mem_5._fields_ = [ + ('data_lo', uint32_t), + ('cmp_data_lo', uint32_t), + ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), + ('reserved14', uint32_t), + ('ordinal6', uint32_t), +] +class struct_pm4_mec_release_mem_6(ctypes.Union): pass +struct_pm4_mec_release_mem_6._fields_ = [ + ('data_hi', uint32_t), + ('cmp_data_hi', uint32_t), + ('reserved15', uint32_t), + ('reserved16', uint32_t), + ('ordinal7', uint32_t), +] +struct_pm4_mec_release_mem._anonymous_ = ['_0', '_1', '_2', '_3', '_4', '_5', '_6'] +struct_pm4_mec_release_mem._fields_ = [ + ('_0', struct_pm4_mec_release_mem_0), + ('_1', struct_pm4_mec_release_mem_1), + ('_2', struct_pm4_mec_release_mem_2), + ('_3', struct_pm4_mec_release_mem_3), + ('_4', struct_pm4_mec_release_mem_4), + ('_5', struct_pm4_mec_release_mem_5), + ('_6', struct_pm4_mec_release_mem_6), + ('int_ctxid', uint32_t), +] enum_WRITE_DATA_dst_sel_enum = CEnum(ctypes.c_uint32) dst_sel___write_data__mem_mapped_register = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__mem_mapped_register', 0) dst_sel___write_data__tc_l2 = enum_WRITE_DATA_dst_sel_enum.define('dst_sel___write_data__tc_l2', 2) @@ -182,10 +574,14 @@ cache_policy___write_data__lru = enum_WRITE_DATA_cache_policy_enum.define('cache cache_policy___write_data__stream = enum_WRITE_DATA_cache_policy_enum.define('cache_policy___write_data__stream', 1) class struct_pm4_mec_write_data_mmio(Struct): pass -class _anonunion54(ctypes.Union): pass -class _anonunion55(ctypes.Union): pass -class _anonunion55_bitfields2(Struct): pass -_anonunion55_bitfields2._fields_ = [ +class struct_pm4_mec_write_data_mmio_0(ctypes.Union): pass +struct_pm4_mec_write_data_mmio_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] +class struct_pm4_mec_write_data_mmio_1(ctypes.Union): pass +class struct_pm4_mec_write_data_mmio_1_bitfields2(Struct): pass +struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ ('reserved1', ctypes.c_uint32,8), ('dst_sel', ctypes.c_uint32,4), ('reserved2', ctypes.c_uint32,4), @@ -197,22 +593,30 @@ _anonunion55_bitfields2._fields_ = [ ('cache_policy', ctypes.c_uint32,2), ('reserved5', ctypes.c_uint32,5), ] -_anonunion55._fields_ = [ - ('bitfields2', _anonunion55_bitfields2), +struct_pm4_mec_write_data_mmio_1._fields_ = [ + ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), ('ordinal2', ctypes.c_uint32), ] -class _anonunion56(ctypes.Union): pass -class _anonunion56_bitfields3(Struct): pass -_anonunion56_bitfields3._fields_ = [ +class struct_pm4_mec_write_data_mmio_2(ctypes.Union): pass +class struct_pm4_mec_write_data_mmio_2_bitfields3(Struct): pass +struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ ('dst_mmreg_addr', ctypes.c_uint32,18), ('reserved6', ctypes.c_uint32,14), ] -_anonunion56._fields_ = [ - ('bitfields3', _anonunion56_bitfields3), +struct_pm4_mec_write_data_mmio_2._fields_ = [ + ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), ('ordinal3', ctypes.c_uint32), ] -_anonenum57 = CEnum(ctypes.c_uint32) -CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum57.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) +struct_pm4_mec_write_data_mmio._anonymous_ = ['_0', '_1', '_2'] +struct_pm4_mec_write_data_mmio._fields_ = [ + ('_0', struct_pm4_mec_write_data_mmio_0), + ('_1', struct_pm4_mec_write_data_mmio_1), + ('_2', struct_pm4_mec_write_data_mmio_2), + ('reserved7', uint32_t), + ('data', uint32_t), +] +_anonenum0 = CEnum(ctypes.c_uint32) +CACHE_FLUSH_AND_INV_TS_EVENT = _anonenum0.define('CACHE_FLUSH_AND_INV_TS_EVENT', 20) GFX9_NUM_GFX_RINGS = 1 GFX9_NUM_COMPUTE_RINGS = 8 diff --git a/tinygrad/runtime/autogen/am/smu_v13_0_0.py b/tinygrad/runtime/autogen/am/smu_v13_0_0.py index af87e13984..53cb653e0b 100644 --- a/tinygrad/runtime/autogen/am/smu_v13_0_0.py +++ b/tinygrad/runtime/autogen/am/smu_v13_0_0.py @@ -77,8 +77,18 @@ I2C_CONTROLLER_PROTOCOL_INA3221 = I2cControllerProtocol_e.define('I2C_CONTROLLER I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', 4) I2C_CONTROLLER_PROTOCOL_COUNT = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_COUNT', 5) -class _anonstruct0(Struct): pass -I2cControllerConfig_t = _anonstruct0 +class I2cControllerConfig_t(Struct): pass +uint8_t = ctypes.c_ubyte +I2cControllerConfig_t._fields_ = [ + ('Enabled', uint8_t), + ('Speed', uint8_t), + ('SlaveAddress', uint8_t), + ('ControllerPort', uint8_t), + ('ControllerName', uint8_t), + ('ThermalThrotter', uint8_t), + ('I2cProtocol', uint8_t), + ('PaddingConfig', uint8_t), +] I2cPort_e = CEnum(ctypes.c_uint32) I2C_PORT_SVD_SCL = I2cPort_e.define('I2C_PORT_SVD_SCL', 0) I2C_PORT_GPIO = I2cPort_e.define('I2C_PORT_GPIO', 1) @@ -97,16 +107,40 @@ I2C_CMD_READ = I2cCmdType_e.define('I2C_CMD_READ', 0) I2C_CMD_WRITE = I2cCmdType_e.define('I2C_CMD_WRITE', 1) I2C_CMD_COUNT = I2cCmdType_e.define('I2C_CMD_COUNT', 2) -class _anonstruct1(Struct): pass -SwI2cCmd_t = _anonstruct1 -class _anonstruct2(Struct): pass -SwI2cRequest_t = _anonstruct2 -class _anonstruct3(Struct): pass -SwI2cRequestExternal_t = _anonstruct3 -class _anonstruct4(Struct): pass -EccInfo_t = _anonstruct4 -class _anonstruct5(Struct): pass -EccInfoTable_t = _anonstruct5 +class SwI2cCmd_t(Struct): pass +SwI2cCmd_t._fields_ = [ + ('ReadWriteData', uint8_t), + ('CmdConfig', uint8_t), +] +class SwI2cRequest_t(Struct): pass +SwI2cRequest_t._fields_ = [ + ('I2CcontrollerPort', uint8_t), + ('I2CSpeed', uint8_t), + ('SlaveAddress', uint8_t), + ('NumCmds', uint8_t), + ('SwI2cCmds', (SwI2cCmd_t * 24)), +] +class SwI2cRequestExternal_t(Struct): pass +uint32_t = ctypes.c_uint32 +SwI2cRequestExternal_t._fields_ = [ + ('SwI2cRequest', SwI2cRequest_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), +] +class EccInfo_t(Struct): pass +uint64_t = ctypes.c_uint64 +uint16_t = ctypes.c_uint16 +EccInfo_t._fields_ = [ + ('mca_umc_status', uint64_t), + ('mca_umc_addr', uint64_t), + ('ce_count_lo_chip', uint16_t), + ('ce_count_hi_chip', uint16_t), + ('eccPadding', uint32_t), +] +class EccInfoTable_t(Struct): pass +EccInfoTable_t._fields_ = [ + ('EccInfo', (EccInfo_t * 24)), +] D3HOTSequence_e = CEnum(ctypes.c_uint32) BACO_SEQUENCE = D3HOTSequence_e.define('BACO_SEQUENCE', 0) MSR_SEQUENCE = D3HOTSequence_e.define('MSR_SEQUENCE', 1) @@ -122,12 +156,23 @@ PowerGatingSettings_e = CEnum(ctypes.c_uint32) PG_POWER_DOWN = PowerGatingSettings_e.define('PG_POWER_DOWN', 0) PG_POWER_UP = PowerGatingSettings_e.define('PG_POWER_UP', 1) -class _anonstruct6(Struct): pass -QuadraticInt_t = _anonstruct6 -class _anonstruct7(Struct): pass -LinearInt_t = _anonstruct7 -class _anonstruct8(Struct): pass -DroopInt_t = _anonstruct8 +class QuadraticInt_t(Struct): pass +QuadraticInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), +] +class LinearInt_t(Struct): pass +LinearInt_t._fields_ = [ + ('m', uint32_t), + ('b', uint32_t), +] +class DroopInt_t(Struct): pass +DroopInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), +] DCS_ARCH_e = CEnum(ctypes.c_uint32) DCS_ARCH_DISABLED = DCS_ARCH_e.define('DCS_ARCH_DISABLED', 0) DCS_ARCH_FADCS = DCS_ARCH_e.define('DCS_ARCH_FADCS', 1) @@ -186,8 +231,19 @@ PWR_CONFIG_TGP = PwrConfig_e.define('PWR_CONFIG_TGP', 1) PWR_CONFIG_TCP_ESTIMATED = PwrConfig_e.define('PWR_CONFIG_TCP_ESTIMATED', 2) PWR_CONFIG_TCP_MEASURED = PwrConfig_e.define('PWR_CONFIG_TCP_MEASURED', 3) -class _anonstruct9(Struct): pass -DpmDescriptor_t = _anonstruct9 +class DpmDescriptor_t(Struct): pass +DpmDescriptor_t._fields_ = [ + ('Padding', uint8_t), + ('SnapToDiscrete', uint8_t), + ('NumDiscreteLevels', uint8_t), + ('CalculateFopt', uint8_t), + ('ConversionToAvfsClk', LinearInt_t), + ('Padding3', (uint32_t * 3)), + ('Padding4', uint16_t), + ('FoptimalDc', uint16_t), + ('FoptimalAc', uint16_t), + ('Padding2', uint16_t), +] PPT_THROTTLER_e = CEnum(ctypes.c_uint32) PPT_THROTTLER_PPT0 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT0', 0) PPT_THROTTLER_PPT1 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT1', 1) @@ -332,18 +388,70 @@ PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = PP_GRTAVFS_FW_SEP_FUSE_e.de PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', 18) PP_GRTAVFS_FW_SEP_FUSE_COUNT = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_COUNT', 19) -class _anonstruct10(Struct): pass -SviTelemetryScale_t = _anonstruct10 +class SviTelemetryScale_t(Struct): pass +int8_t = ctypes.c_char +SviTelemetryScale_t._fields_ = [ + ('Offset', int8_t), + ('Padding', uint8_t), + ('MaxCurrent', uint16_t), +] FanMode_e = CEnum(ctypes.c_uint32) FAN_MODE_AUTO = FanMode_e.define('FAN_MODE_AUTO', 0) FAN_MODE_MANUAL_LINEAR = FanMode_e.define('FAN_MODE_MANUAL_LINEAR', 1) -class _anonstruct11(Struct): pass -OverDriveTable_t = _anonstruct11 -class _anonstruct12(Struct): pass -OverDriveTableExternal_t = _anonstruct12 -class _anonstruct13(Struct): pass -OverDriveLimits_t = _anonstruct13 +class OverDriveTable_t(Struct): pass +int16_t = ctypes.c_int16 +OverDriveTable_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', (int16_t * 6)), + ('Reserved', uint32_t), + ('GfxclkFmin', int16_t), + ('GfxclkFmax', int16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', (uint8_t * 6)), + ('FanLinearTempPoints', (uint8_t * 6)), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('FanZeroRpmStopTemp', uint8_t), + ('FanMode', uint8_t), + ('MaxOpTemp', uint8_t), + ('Spare', (uint32_t * 13)), + ('MmHubPadding', (uint32_t * 8)), +] +class OverDriveTableExternal_t(Struct): pass +OverDriveTableExternal_t._fields_ = [ + ('OverDriveTable', OverDriveTable_t), +] +class OverDriveLimits_t(Struct): pass +OverDriveLimits_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', int16_t), + ('Reserved1', uint16_t), + ('Reserved2', uint16_t), + ('GfxclkFmin', int16_t), + ('GfxclkFmax', int16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', uint8_t), + ('FanLinearTempPoints', uint8_t), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('FanZeroRpmStopTemp', uint8_t), + ('FanMode', uint8_t), + ('MaxOpTemp', uint8_t), + ('Spare', (uint32_t * 13)), +] BOARD_GPIO_TYPE_e = CEnum(ctypes.c_uint32) BOARD_GPIO_SMUIO_0 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_0', 0) BOARD_GPIO_SMUIO_1 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_1', 1) @@ -390,52 +498,521 @@ BOARD_GPIO_DC_GENLK_VSYNC = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_GENLK_VSYNC' BOARD_GPIO_DC_SWAPLOCK_A = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_A', 42) BOARD_GPIO_DC_SWAPLOCK_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_B', 43) -class _anonstruct14(Struct): pass -BootValues_t = _anonstruct14 -class _anonstruct15(Struct): pass -MsgLimits_t = _anonstruct15 -class _anonstruct16(Struct): pass -DriverReportedClocks_t = _anonstruct16 -class _anonstruct17(Struct): pass -AvfsDcBtcParams_t = _anonstruct17 -class _anonstruct18(Struct): pass -AvfsFuseOverride_t = _anonstruct18 -class _anonstruct19(Struct): pass -SkuTable_t = _anonstruct19 -class _anonstruct20(Struct): pass -BoardTable_t = _anonstruct20 -class _anonstruct21(Struct): pass -PPTable_t = _anonstruct21 -class _anonstruct22(Struct): pass -DriverSmuConfig_t = _anonstruct22 -class _anonstruct23(Struct): pass -DriverSmuConfigExternal_t = _anonstruct23 -class _anonstruct24(Struct): pass -DriverInfoTable_t = _anonstruct24 -class _anonstruct25(Struct): pass -SmuMetrics_t = _anonstruct25 -class _anonstruct26(Struct): pass -SmuMetricsExternal_t = _anonstruct26 -class _anonstruct27(Struct): pass -WatermarkRowGeneric_t = _anonstruct27 +class BootValues_t(Struct): pass +BootValues_t._fields_ = [ + ('InitGfxclk_bypass', uint16_t), + ('InitSocclk', uint16_t), + ('InitMp0clk', uint16_t), + ('InitMpioclk', uint16_t), + ('InitSmnclk', uint16_t), + ('InitUcpclk', uint16_t), + ('InitCsrclk', uint16_t), + ('InitDprefclk', uint16_t), + ('InitDcfclk', uint16_t), + ('InitDtbclk', uint16_t), + ('InitDclk', uint16_t), + ('InitVclk', uint16_t), + ('InitUsbdfsclk', uint16_t), + ('InitMp1clk', uint16_t), + ('InitLclk', uint16_t), + ('InitBaco400clk_bypass', uint16_t), + ('InitBaco1200clk_bypass', uint16_t), + ('InitBaco700clk_bypass', uint16_t), + ('InitFclk', uint16_t), + ('InitGfxclk_clkb', uint16_t), + ('InitUclkDPMState', uint8_t), + ('Padding', (uint8_t * 3)), + ('InitVcoFreqPll0', uint32_t), + ('InitVcoFreqPll1', uint32_t), + ('InitVcoFreqPll2', uint32_t), + ('InitVcoFreqPll3', uint32_t), + ('InitVcoFreqPll4', uint32_t), + ('InitVcoFreqPll5', uint32_t), + ('InitVcoFreqPll6', uint32_t), + ('InitGfx', uint16_t), + ('InitSoc', uint16_t), + ('InitU', uint16_t), + ('Padding2', uint16_t), + ('Spare', (uint32_t * 8)), +] +class MsgLimits_t(Struct): pass +MsgLimits_t._fields_ = [ + ('Power', ((uint16_t * 2) * 4)), + ('Tdc', (uint16_t * 3)), + ('Temperature', (uint16_t * 13)), + ('PwmLimitMin', uint8_t), + ('PwmLimitMax', uint8_t), + ('FanTargetTemperature', uint8_t), + ('Spare1', (uint8_t * 1)), + ('AcousticTargetRpmThresholdMin', uint16_t), + ('AcousticTargetRpmThresholdMax', uint16_t), + ('AcousticLimitRpmThresholdMin', uint16_t), + ('AcousticLimitRpmThresholdMax', uint16_t), + ('PccLimitMin', uint16_t), + ('PccLimitMax', uint16_t), + ('FanStopTempMin', uint16_t), + ('FanStopTempMax', uint16_t), + ('FanStartTempMin', uint16_t), + ('FanStartTempMax', uint16_t), + ('PowerMinPpt0', (uint16_t * 2)), + ('Spare', (uint32_t * 11)), +] +class DriverReportedClocks_t(Struct): pass +DriverReportedClocks_t._fields_ = [ + ('BaseClockAc', uint16_t), + ('GameClockAc', uint16_t), + ('BoostClockAc', uint16_t), + ('BaseClockDc', uint16_t), + ('GameClockDc', uint16_t), + ('BoostClockDc', uint16_t), + ('Reserved', (uint32_t * 4)), +] +class AvfsDcBtcParams_t(Struct): pass +AvfsDcBtcParams_t._fields_ = [ + ('DcBtcEnabled', uint8_t), + ('Padding', (uint8_t * 3)), + ('DcTol', uint16_t), + ('DcBtcGb', uint16_t), + ('DcBtcMin', uint16_t), + ('DcBtcMax', uint16_t), + ('DcBtcGbScalar', LinearInt_t), +] +class AvfsFuseOverride_t(Struct): pass +AvfsFuseOverride_t._fields_ = [ + ('AvfsTemp', (uint16_t * 2)), + ('VftFMin', uint16_t), + ('VInversion', uint16_t), + ('qVft', (QuadraticInt_t * 2)), + ('qAvfsGb', QuadraticInt_t), + ('qAvfsGb2', QuadraticInt_t), +] +class SkuTable_t(Struct): pass +int32_t = ctypes.c_int32 +SkuTable_t._fields_ = [ + ('Version', uint32_t), + ('FeaturesToRun', (uint32_t * 2)), + ('TotalPowerConfig', uint8_t), + ('CustomerVariant', uint8_t), + ('MemoryTemperatureTypeMask', uint8_t), + ('SmartShiftVersion', uint8_t), + ('SocketPowerLimitAc', (uint16_t * 4)), + ('SocketPowerLimitDc', (uint16_t * 4)), + ('SocketPowerLimitSmartShift2', uint16_t), + ('EnableLegacyPptLimit', uint8_t), + ('UseInputTelemetry', uint8_t), + ('SmartShiftMinReportedPptinDcs', uint8_t), + ('PaddingPpt', (uint8_t * 1)), + ('VrTdcLimit', (uint16_t * 3)), + ('PlatformTdcLimit', (uint16_t * 3)), + ('TemperatureLimit', (uint16_t * 13)), + ('HwCtfTempLimit', uint16_t), + ('PaddingInfra', uint16_t), + ('FitControllerFailureRateLimit', uint32_t), + ('FitControllerGfxDutyCycle', uint32_t), + ('FitControllerSocDutyCycle', uint32_t), + ('FitControllerSocOffset', uint32_t), + ('GfxApccPlusResidencyLimit', uint32_t), + ('ThrottlerControlMask', uint32_t), + ('FwDStateMask', uint32_t), + ('UlvVoltageOffset', (uint16_t * 2)), + ('UlvVoltageOffsetU', uint16_t), + ('DeepUlvVoltageOffsetSoc', uint16_t), + ('DefaultMaxVoltage', (uint16_t * 2)), + ('BoostMaxVoltage', (uint16_t * 2)), + ('VminTempHystersis', (int16_t * 2)), + ('VminTempThreshold', (int16_t * 2)), + ('Vmin_Hot_T0', (uint16_t * 2)), + ('Vmin_Cold_T0', (uint16_t * 2)), + ('Vmin_Hot_Eol', (uint16_t * 2)), + ('Vmin_Cold_Eol', (uint16_t * 2)), + ('Vmin_Aging_Offset', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Hot', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Cold', (uint16_t * 2)), + ('VcBtcFixedVminAgingOffset', (uint16_t * 2)), + ('VcBtcVmin2PsmDegrationGb', (uint16_t * 2)), + ('VcBtcPsmA', (uint32_t * 2)), + ('VcBtcPsmB', (uint32_t * 2)), + ('VcBtcVminA', (uint32_t * 2)), + ('VcBtcVminB', (uint32_t * 2)), + ('PerPartVminEnabled', (uint8_t * 2)), + ('VcBtcEnabled', (uint8_t * 2)), + ('SocketPowerLimitAcTau', (uint16_t * 4)), + ('SocketPowerLimitDcTau', (uint16_t * 4)), + ('Vmin_droop', QuadraticInt_t), + ('SpareVmin', (uint32_t * 9)), + ('DpmDescriptor', (DpmDescriptor_t * 13)), + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 4)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint32_t * 13)), + ('Mp0clkFreq', (uint16_t * 2)), + ('Mp0DpmVoltage', (uint16_t * 2)), + ('GfxclkSpare', (uint8_t * 2)), + ('GfxclkFreqCap', uint16_t), + ('GfxclkFgfxoffEntry', uint16_t), + ('GfxclkFgfxoffExitImu', uint16_t), + ('GfxclkFgfxoffExitRlc', uint16_t), + ('GfxclkThrottleClock', uint16_t), + ('EnableGfxPowerStagesGpio', uint8_t), + ('GfxIdlePadding', uint8_t), + ('SmsRepairWRCKClkDivEn', uint8_t), + ('SmsRepairWRCKClkDivVal', uint8_t), + ('GfxOffEntryEarlyMGCGEn', uint8_t), + ('GfxOffEntryForceCGCGEn', uint8_t), + ('GfxOffEntryForceCGCGDelayEn', uint8_t), + ('GfxOffEntryForceCGCGDelayVal', uint8_t), + ('GfxclkFreqGfxUlv', uint16_t), + ('GfxIdlePadding2', (uint8_t * 2)), + ('GfxOffEntryHysteresis', uint32_t), + ('GfxoffSpare', (uint32_t * 15)), + ('DfllBtcMasterScalerM', uint32_t), + ('DfllBtcMasterScalerB', int32_t), + ('DfllBtcSlaveScalerM', uint32_t), + ('DfllBtcSlaveScalerB', int32_t), + ('DfllPccAsWaitCtrl', uint32_t), + ('DfllPccAsStepCtrl', uint32_t), + ('DfllL2FrequencyBoostM', uint32_t), + ('DfllL2FrequencyBoostB', uint32_t), + ('GfxGpoSpare', (uint32_t * 8)), + ('DcsGfxOffVoltage', uint16_t), + ('PaddingDcs', uint16_t), + ('DcsMinGfxOffTime', uint16_t), + ('DcsMaxGfxOffTime', uint16_t), + ('DcsMinCreditAccum', uint32_t), + ('DcsExitHysteresis', uint16_t), + ('DcsTimeout', uint16_t), + ('FoptEnabled', uint8_t), + ('DcsSpare2', (uint8_t * 3)), + ('DcsFoptM', uint32_t), + ('DcsFoptB', uint32_t), + ('DcsSpare', (uint32_t * 11)), + ('ShadowFreqTableUclk', (uint16_t * 4)), + ('UseStrobeModeOptimizations', uint8_t), + ('PaddingMem', (uint8_t * 3)), + ('UclkDpmPstates', (uint8_t * 4)), + ('FreqTableUclkDiv', (uint8_t * 4)), + ('MemVmempVoltage', (uint16_t * 4)), + ('MemVddioVoltage', (uint16_t * 4)), + ('FclkDpmUPstates', (uint8_t * 8)), + ('FclkDpmVddU', (uint16_t * 8)), + ('FclkDpmUSpeed', (uint16_t * 8)), + ('FclkDpmDisallowPstateFreq', uint16_t), + ('PaddingFclk', uint16_t), + ('PcieGenSpeed', (uint8_t * 3)), + ('PcieLaneCount', (uint8_t * 3)), + ('LclkFreq', (uint16_t * 3)), + ('FanStopTemp', (uint16_t * 13)), + ('FanStartTemp', (uint16_t * 13)), + ('FanGain', (uint16_t * 13)), + ('FanGainPadding', uint16_t), + ('FanPwmMin', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanMaximumRpm', uint16_t), + ('MGpuAcousticLimitRpmThreshold', uint16_t), + ('FanTargetGfxclk', uint16_t), + ('TempInputSelectMask', uint32_t), + ('FanZeroRpmEnable', uint8_t), + ('FanTachEdgePerRev', uint8_t), + ('FanTargetTemperature', (uint16_t * 13)), + ('FuzzyFan_ErrorSetDelta', int16_t), + ('FuzzyFan_ErrorRateSetDelta', int16_t), + ('FuzzyFan_PwmSetDelta', int16_t), + ('FuzzyFan_Reserved', uint16_t), + ('FwCtfLimit', (uint16_t * 13)), + ('IntakeTempEnableRPM', uint16_t), + ('IntakeTempOffsetTemp', int16_t), + ('IntakeTempReleaseTemp', uint16_t), + ('IntakeTempHighIntakeAcousticLimit', uint16_t), + ('IntakeTempAcouticLimitReleaseRate', uint16_t), + ('FanAbnormalTempLimitOffset', int16_t), + ('FanStalledTriggerRpm', uint16_t), + ('FanAbnormalTriggerRpmCoeff', uint16_t), + ('FanAbnormalDetectionEnable', uint16_t), + ('FanIntakeSensorSupport', uint8_t), + ('FanIntakePadding', (uint8_t * 3)), + ('FanSpare', (uint32_t * 13)), + ('OverrideGfxAvfsFuses', uint8_t), + ('GfxAvfsPadding', (uint8_t * 3)), + ('L2HwRtAvfsFuses', (uint32_t * 32)), + ('SeHwRtAvfsFuses', (uint32_t * 32)), + ('CommonRtAvfs', (uint32_t * 13)), + ('L2FwRtAvfsFuses', (uint32_t * 19)), + ('SeFwRtAvfsFuses', (uint32_t * 19)), + ('Droop_PWL_F', (uint32_t * 5)), + ('Droop_PWL_a', (uint32_t * 5)), + ('Droop_PWL_b', (uint32_t * 5)), + ('Droop_PWL_c', (uint32_t * 5)), + ('Static_PWL_Offset', (uint32_t * 5)), + ('dGbV_dT_vmin', uint32_t), + ('dGbV_dT_vmax', uint32_t), + ('V2F_vmin_range_low', uint32_t), + ('V2F_vmin_range_high', uint32_t), + ('V2F_vmax_range_low', uint32_t), + ('V2F_vmax_range_high', uint32_t), + ('DcBtcGfxParams', AvfsDcBtcParams_t), + ('GfxAvfsSpare', (uint32_t * 32)), + ('OverrideSocAvfsFuses', uint8_t), + ('MinSocAvfsRevision', uint8_t), + ('SocAvfsPadding', (uint8_t * 2)), + ('SocAvfsFuseOverride', (AvfsFuseOverride_t * 3)), + ('dBtcGbSoc', (DroopInt_t * 3)), + ('qAgingGb', (LinearInt_t * 3)), + ('qStaticVoltageOffset', (QuadraticInt_t * 3)), + ('DcBtcSocParams', (AvfsDcBtcParams_t * 3)), + ('SocAvfsSpare', (uint32_t * 32)), + ('BootValues', BootValues_t), + ('DriverReportedClocks', DriverReportedClocks_t), + ('MsgLimits', MsgLimits_t), + ('OverDriveLimitsMin', OverDriveLimits_t), + ('OverDriveLimitsBasicMax', OverDriveLimits_t), + ('reserved', (uint32_t * 22)), + ('DebugOverrides', uint32_t), + ('TotalBoardPowerSupport', uint8_t), + ('TotalBoardPowerPadding', (uint8_t * 3)), + ('TotalIdleBoardPowerM', int16_t), + ('TotalIdleBoardPowerB', int16_t), + ('TotalBoardPowerM', int16_t), + ('TotalBoardPowerB', int16_t), + ('qFeffCoeffGameClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBaseClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBoostClock', (QuadraticInt_t * 2)), + ('TemperatureLimit_Hynix', uint16_t), + ('TemperatureLimit_Micron', uint16_t), + ('TemperatureFwCtfLimit_Hynix', uint16_t), + ('TemperatureFwCtfLimit_Micron', uint16_t), + ('Spare', (uint32_t * 41)), + ('MmHubPadding', (uint32_t * 8)), +] +class BoardTable_t(Struct): pass +BoardTable_t._fields_ = [ + ('Version', uint32_t), + ('I2cControllers', (I2cControllerConfig_t * 8)), + ('VddGfxVrMapping', uint8_t), + ('VddSocVrMapping', uint8_t), + ('VddMem0VrMapping', uint8_t), + ('VddMem1VrMapping', uint8_t), + ('GfxUlvPhaseSheddingMask', uint8_t), + ('SocUlvPhaseSheddingMask', uint8_t), + ('VmempUlvPhaseSheddingMask', uint8_t), + ('VddioUlvPhaseSheddingMask', uint8_t), + ('SlaveAddrMapping', (uint8_t * 5)), + ('VrPsiSupport', (uint8_t * 5)), + ('PaddingPsi', (uint8_t * 5)), + ('EnablePsi6', (uint8_t * 5)), + ('SviTelemetryScale', (SviTelemetryScale_t * 5)), + ('VoltageTelemetryRatio', (uint32_t * 5)), + ('DownSlewRateVr', (uint8_t * 5)), + ('LedOffGpio', uint8_t), + ('FanOffGpio', uint8_t), + ('GfxVrPowerStageOffGpio', uint8_t), + ('AcDcGpio', uint8_t), + ('AcDcPolarity', uint8_t), + ('VR0HotGpio', uint8_t), + ('VR0HotPolarity', uint8_t), + ('GthrGpio', uint8_t), + ('GthrPolarity', uint8_t), + ('LedPin0', uint8_t), + ('LedPin1', uint8_t), + ('LedPin2', uint8_t), + ('LedEnableMask', uint8_t), + ('LedPcie', uint8_t), + ('LedError', uint8_t), + ('UclkTrainingModeSpreadPercent', uint8_t), + ('UclkSpreadPadding', uint8_t), + ('UclkSpreadFreq', uint16_t), + ('UclkSpreadPercent', (uint8_t * 16)), + ('GfxclkSpreadEnable', uint8_t), + ('FclkSpreadPercent', uint8_t), + ('FclkSpreadFreq', uint16_t), + ('DramWidth', uint8_t), + ('PaddingMem1', (uint8_t * 7)), + ('HsrEnabled', uint8_t), + ('VddqOffEnabled', uint8_t), + ('PaddingUmcFlags', (uint8_t * 2)), + ('PostVoltageSetBacoDelay', uint32_t), + ('BacoEntryDelay', uint32_t), + ('FuseWritePowerMuxPresent', uint8_t), + ('FuseWritePadding', (uint8_t * 3)), + ('BoardSpare', (uint32_t * 63)), + ('MmHubPadding', (uint32_t * 8)), +] +class PPTable_t(Struct): pass +PPTable_t._fields_ = [ + ('SkuTable', SkuTable_t), + ('BoardTable', BoardTable_t), +] +class DriverSmuConfig_t(Struct): pass +DriverSmuConfig_t._fields_ = [ + ('GfxclkAverageLpfTau', uint16_t), + ('FclkAverageLpfTau', uint16_t), + ('UclkAverageLpfTau', uint16_t), + ('GfxActivityLpfTau', uint16_t), + ('UclkActivityLpfTau', uint16_t), + ('SocketPowerLpfTau', uint16_t), + ('VcnClkAverageLpfTau', uint16_t), + ('VcnUsageAverageLpfTau', uint16_t), +] +class DriverSmuConfigExternal_t(Struct): pass +DriverSmuConfigExternal_t._fields_ = [ + ('DriverSmuConfig', DriverSmuConfig_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), +] +class DriverInfoTable_t(Struct): pass +DriverInfoTable_t._fields_ = [ + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 4)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint16_t * 13)), + ('Padding', uint16_t), + ('Spare', (uint32_t * 32)), + ('MmHubPadding', (uint32_t * 8)), +] +class SmuMetrics_t(Struct): pass +SmuMetrics_t._fields_ = [ + ('CurrClock', (uint32_t * 13)), + ('AverageGfxclkFrequencyTarget', uint16_t), + ('AverageGfxclkFrequencyPreDs', uint16_t), + ('AverageGfxclkFrequencyPostDs', uint16_t), + ('AverageFclkFrequencyPreDs', uint16_t), + ('AverageFclkFrequencyPostDs', uint16_t), + ('AverageMemclkFrequencyPreDs', uint16_t), + ('AverageMemclkFrequencyPostDs', uint16_t), + ('AverageVclk0Frequency', uint16_t), + ('AverageDclk0Frequency', uint16_t), + ('AverageVclk1Frequency', uint16_t), + ('AverageDclk1Frequency', uint16_t), + ('PCIeBusy', uint16_t), + ('dGPU_W_MAX', uint16_t), + ('padding', uint16_t), + ('MetricsCounter', uint32_t), + ('AvgVoltage', (uint16_t * 5)), + ('AvgCurrent', (uint16_t * 5)), + ('AverageGfxActivity', uint16_t), + ('AverageUclkActivity', uint16_t), + ('Vcn0ActivityPercentage', uint16_t), + ('Vcn1ActivityPercentage', uint16_t), + ('EnergyAccumulator', uint32_t), + ('AverageSocketPower', uint16_t), + ('AverageTotalBoardPower', uint16_t), + ('AvgTemperature', (uint16_t * 13)), + ('AvgTemperatureFanIntake', uint16_t), + ('PcieRate', uint8_t), + ('PcieWidth', uint8_t), + ('AvgFanPwm', uint8_t), + ('Padding', (uint8_t * 1)), + ('AvgFanRpm', uint16_t), + ('ThrottlingPercentage', (uint8_t * 22)), + ('VmaxThrottlingPercentage', uint8_t), + ('Padding1', (uint8_t * 3)), + ('D3HotEntryCountPerMode', (uint32_t * 4)), + ('D3HotExitCountPerMode', (uint32_t * 4)), + ('ArmMsgReceivedCountPerMode', (uint32_t * 4)), + ('ApuSTAPMSmartShiftLimit', uint16_t), + ('ApuSTAPMLimit', uint16_t), + ('AvgApuSocketPower', uint16_t), + ('AverageUclkActivity_MAX', uint16_t), + ('PublicSerialNumberLower', uint32_t), + ('PublicSerialNumberUpper', uint32_t), +] +class SmuMetricsExternal_t(Struct): pass +SmuMetricsExternal_t._fields_ = [ + ('SmuMetrics', SmuMetrics_t), + ('Spare', (uint32_t * 29)), + ('MmHubPadding', (uint32_t * 8)), +] +class WatermarkRowGeneric_t(Struct): pass +WatermarkRowGeneric_t._fields_ = [ + ('WmSetting', uint8_t), + ('Flags', uint8_t), + ('Padding', (uint8_t * 2)), +] WATERMARKS_FLAGS_e = CEnum(ctypes.c_uint32) WATERMARKS_CLOCK_RANGE = WATERMARKS_FLAGS_e.define('WATERMARKS_CLOCK_RANGE', 0) WATERMARKS_DUMMY_PSTATE = WATERMARKS_FLAGS_e.define('WATERMARKS_DUMMY_PSTATE', 1) WATERMARKS_MALL = WATERMARKS_FLAGS_e.define('WATERMARKS_MALL', 2) WATERMARKS_COUNT = WATERMARKS_FLAGS_e.define('WATERMARKS_COUNT', 3) -class _anonstruct28(Struct): pass -Watermarks_t = _anonstruct28 -class _anonstruct29(Struct): pass -WatermarksExternal_t = _anonstruct29 -class _anonstruct30(Struct): pass -AvfsDebugTable_t = _anonstruct30 -class _anonstruct31(Struct): pass -AvfsDebugTableExternal_t = _anonstruct31 -class _anonstruct32(Struct): pass -DpmActivityMonitorCoeffInt_t = _anonstruct32 -class _anonstruct33(Struct): pass -DpmActivityMonitorCoeffIntExternal_t = _anonstruct33 +class Watermarks_t(Struct): pass +Watermarks_t._fields_ = [ + ('WatermarkRow', (WatermarkRowGeneric_t * 4)), +] +class WatermarksExternal_t(Struct): pass +WatermarksExternal_t._fields_ = [ + ('Watermarks', Watermarks_t), + ('Spare', (uint32_t * 16)), + ('MmHubPadding', (uint32_t * 8)), +] +class AvfsDebugTable_t(Struct): pass +AvfsDebugTable_t._fields_ = [ + ('avgPsmCount', (uint16_t * 214)), + ('minPsmCount', (uint16_t * 214)), + ('avgPsmVoltage', (ctypes.c_float * 214)), + ('minPsmVoltage', (ctypes.c_float * 214)), +] +class AvfsDebugTableExternal_t(Struct): pass +AvfsDebugTableExternal_t._fields_ = [ + ('AvfsDebugTable', AvfsDebugTable_t), + ('MmHubPadding', (uint32_t * 8)), +] +class DpmActivityMonitorCoeffInt_t(Struct): pass +DpmActivityMonitorCoeffInt_t._fields_ = [ + ('Gfx_ActiveHystLimit', uint8_t), + ('Gfx_IdleHystLimit', uint8_t), + ('Gfx_FPS', uint8_t), + ('Gfx_MinActiveFreqType', uint8_t), + ('Gfx_BoosterFreqType', uint8_t), + ('PaddingGfx', uint8_t), + ('Gfx_MinActiveFreq', uint16_t), + ('Gfx_BoosterFreq', uint16_t), + ('Gfx_PD_Data_time_constant', uint16_t), + ('Gfx_PD_Data_limit_a', uint32_t), + ('Gfx_PD_Data_limit_b', uint32_t), + ('Gfx_PD_Data_limit_c', uint32_t), + ('Gfx_PD_Data_error_coeff', uint32_t), + ('Gfx_PD_Data_error_rate_coeff', uint32_t), + ('Fclk_ActiveHystLimit', uint8_t), + ('Fclk_IdleHystLimit', uint8_t), + ('Fclk_FPS', uint8_t), + ('Fclk_MinActiveFreqType', uint8_t), + ('Fclk_BoosterFreqType', uint8_t), + ('PaddingFclk', uint8_t), + ('Fclk_MinActiveFreq', uint16_t), + ('Fclk_BoosterFreq', uint16_t), + ('Fclk_PD_Data_time_constant', uint16_t), + ('Fclk_PD_Data_limit_a', uint32_t), + ('Fclk_PD_Data_limit_b', uint32_t), + ('Fclk_PD_Data_limit_c', uint32_t), + ('Fclk_PD_Data_error_coeff', uint32_t), + ('Fclk_PD_Data_error_rate_coeff', uint32_t), + ('Mem_UpThreshold_Limit', (uint32_t * 4)), + ('Mem_UpHystLimit', (uint8_t * 4)), + ('Mem_DownHystLimit', (uint8_t * 4)), + ('Mem_Fps', uint16_t), + ('padding', (uint8_t * 2)), +] +class DpmActivityMonitorCoeffIntExternal_t(Struct): pass +DpmActivityMonitorCoeffIntExternal_t._fields_ = [ + ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), + ('MmHubPadding', (uint32_t * 8)), +] class struct_smu_hw_power_state(Struct): pass struct_smu_hw_power_state._fields_ = [ ('magic', ctypes.c_uint32), diff --git a/tinygrad/runtime/autogen/am/smu_v14_0_2.py b/tinygrad/runtime/autogen/am/smu_v14_0_2.py index ce1074f87c..5d2a7e25e7 100644 --- a/tinygrad/runtime/autogen/am/smu_v14_0_2.py +++ b/tinygrad/runtime/autogen/am/smu_v14_0_2.py @@ -3,13 +3,80 @@ import ctypes from tinygrad.helpers import unwrap from tinygrad.runtime.support.c import Struct, CEnum, _IO, _IOW, _IOR, _IOWR class struct_SMU14_Firmware_Footer(Struct): pass +uint32_t = ctypes.c_uint32 +struct_SMU14_Firmware_Footer._fields_ = [ + ('Signature', uint32_t), +] SMU14_Firmware_Footer = struct_SMU14_Firmware_Footer -class _anonstruct0(Struct): pass -SMU_Firmware_Header = _anonstruct0 -class _anonstruct1(Struct): pass -FwStatus_t = _anonstruct1 -class _anonstruct2(Struct): pass -FwStatus_t_v14_0_1 = _anonstruct2 +class SMU_Firmware_Header(Struct): pass +SMU_Firmware_Header._fields_ = [ + ('ImageVersion', uint32_t), + ('ImageVersion2', uint32_t), + ('Padding0', (uint32_t * 3)), + ('SizeFWSigned', uint32_t), + ('Padding1', (uint32_t * 25)), + ('FirmwareType', uint32_t), + ('Filler', (uint32_t * 32)), +] +class FwStatus_t(Struct): pass +FwStatus_t._fields_ = [ + ('DpmHandlerID', uint32_t,8), + ('ActivityMonitorID', uint32_t,8), + ('DpmTimerID', uint32_t,8), + ('DpmHubID', uint32_t,4), + ('DpmHubTask', uint32_t,4), + ('CclkSyncStatus', uint32_t,8), + ('Ccx0CpuOff', uint32_t,2), + ('Ccx1CpuOff', uint32_t,2), + ('GfxOffStatus', uint32_t,2), + ('VddOff', uint32_t,1), + ('InWhisperMode', uint32_t,1), + ('ZstateStatus', uint32_t,4), + ('spare0', uint32_t,4), + ('DstateFun', uint32_t,4), + ('DstateDev', uint32_t,4), + ('P2JobHandler', uint32_t,24), + ('RsmuPmiP2PendingCnt', uint32_t,8), + ('PostCode', uint32_t,32), + ('MsgPortBusy', uint32_t,24), + ('RsmuPmiP1Pending', uint32_t,1), + ('DfCstateExitPending', uint32_t,1), + ('Ccx0Pc6ExitPending', uint32_t,1), + ('Ccx1Pc6ExitPending', uint32_t,1), + ('WarmResetPending', uint32_t,1), + ('spare1', uint32_t,3), + ('IdleMask', uint32_t,32), +] +class FwStatus_t_v14_0_1(Struct): pass +FwStatus_t_v14_0_1._fields_ = [ + ('DpmHandlerID', uint32_t,8), + ('ActivityMonitorID', uint32_t,8), + ('DpmTimerID', uint32_t,8), + ('DpmHubID', uint32_t,4), + ('DpmHubTask', uint32_t,4), + ('CclkSyncStatus', uint32_t,8), + ('ZstateStatus', uint32_t,4), + ('Cpu1VddOff', uint32_t,4), + ('DstateFun', uint32_t,4), + ('DstateDev', uint32_t,4), + ('GfxOffStatus', uint32_t,2), + ('Cpu0Off', uint32_t,2), + ('Cpu1Off', uint32_t,2), + ('Cpu0VddOff', uint32_t,2), + ('P2JobHandler', uint32_t,32), + ('PostCode', uint32_t,32), + ('MsgPortBusy', uint32_t,15), + ('RsmuPmiP1Pending', uint32_t,1), + ('RsmuPmiP2PendingCnt', uint32_t,8), + ('DfCstateExitPending', uint32_t,1), + ('Pc6EntryPending', uint32_t,1), + ('Pc6ExitPending', uint32_t,1), + ('WarmResetPending', uint32_t,1), + ('Mp0ClkPending', uint32_t,1), + ('InWhisperMode', uint32_t,1), + ('spare2', uint32_t,2), + ('IdleMask', uint32_t,32), +] FEATURE_PWR_DOMAIN_e = CEnum(ctypes.c_uint32) FEATURE_PWR_ALL = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_ALL', 0) FEATURE_PWR_S5 = FEATURE_PWR_DOMAIN_e.define('FEATURE_PWR_S5', 1) @@ -91,8 +158,18 @@ I2C_CONTROLLER_PROTOCOL_INA3221 = I2cControllerProtocol_e.define('I2C_CONTROLLER I2C_CONTROLLER_PROTOCOL_TMP_MAX6604 = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_TMP_MAX6604', 4) I2C_CONTROLLER_PROTOCOL_COUNT = I2cControllerProtocol_e.define('I2C_CONTROLLER_PROTOCOL_COUNT', 5) -class _anonstruct3(Struct): pass -I2cControllerConfig_t = _anonstruct3 +class I2cControllerConfig_t(Struct): pass +uint8_t = ctypes.c_ubyte +I2cControllerConfig_t._fields_ = [ + ('Enabled', uint8_t), + ('Speed', uint8_t), + ('SlaveAddress', uint8_t), + ('ControllerPort', uint8_t), + ('ControllerName', uint8_t), + ('ThermalThrotter', uint8_t), + ('I2cProtocol', uint8_t), + ('PaddingConfig', uint8_t), +] I2cPort_e = CEnum(ctypes.c_uint32) I2C_PORT_SVD_SCL = I2cPort_e.define('I2C_PORT_SVD_SCL', 0) I2C_PORT_GPIO = I2cPort_e.define('I2C_PORT_GPIO', 1) @@ -111,16 +188,39 @@ I2C_CMD_READ = I2cCmdType_e.define('I2C_CMD_READ', 0) I2C_CMD_WRITE = I2cCmdType_e.define('I2C_CMD_WRITE', 1) I2C_CMD_COUNT = I2cCmdType_e.define('I2C_CMD_COUNT', 2) -class _anonstruct4(Struct): pass -SwI2cCmd_t = _anonstruct4 -class _anonstruct5(Struct): pass -SwI2cRequest_t = _anonstruct5 -class _anonstruct6(Struct): pass -SwI2cRequestExternal_t = _anonstruct6 -class _anonstruct7(Struct): pass -EccInfo_t = _anonstruct7 -class _anonstruct8(Struct): pass -EccInfoTable_t = _anonstruct8 +class SwI2cCmd_t(Struct): pass +SwI2cCmd_t._fields_ = [ + ('ReadWriteData', uint8_t), + ('CmdConfig', uint8_t), +] +class SwI2cRequest_t(Struct): pass +SwI2cRequest_t._fields_ = [ + ('I2CcontrollerPort', uint8_t), + ('I2CSpeed', uint8_t), + ('SlaveAddress', uint8_t), + ('NumCmds', uint8_t), + ('SwI2cCmds', (SwI2cCmd_t * 24)), +] +class SwI2cRequestExternal_t(Struct): pass +SwI2cRequestExternal_t._fields_ = [ + ('SwI2cRequest', SwI2cRequest_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), +] +class EccInfo_t(Struct): pass +uint64_t = ctypes.c_uint64 +uint16_t = ctypes.c_uint16 +EccInfo_t._fields_ = [ + ('mca_umc_status', uint64_t), + ('mca_umc_addr', uint64_t), + ('ce_count_lo_chip', uint16_t), + ('ce_count_hi_chip', uint16_t), + ('eccPadding', uint32_t), +] +class EccInfoTable_t(Struct): pass +EccInfoTable_t._fields_ = [ + ('EccInfo', (EccInfo_t * 24)), +] EPCS_STATUS_e = CEnum(ctypes.c_uint32) EPCS_SHORTED_LIMIT = EPCS_STATUS_e.define('EPCS_SHORTED_LIMIT', 0) EPCS_LOW_POWER_LIMIT = EPCS_STATUS_e.define('EPCS_LOW_POWER_LIMIT', 1) @@ -144,12 +244,23 @@ PowerGatingSettings_e = CEnum(ctypes.c_uint32) PG_POWER_DOWN = PowerGatingSettings_e.define('PG_POWER_DOWN', 0) PG_POWER_UP = PowerGatingSettings_e.define('PG_POWER_UP', 1) -class _anonstruct9(Struct): pass -QuadraticInt_t = _anonstruct9 -class _anonstruct10(Struct): pass -LinearInt_t = _anonstruct10 -class _anonstruct11(Struct): pass -DroopInt_t = _anonstruct11 +class QuadraticInt_t(Struct): pass +QuadraticInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), +] +class LinearInt_t(Struct): pass +LinearInt_t._fields_ = [ + ('m', uint32_t), + ('b', uint32_t), +] +class DroopInt_t(Struct): pass +DroopInt_t._fields_ = [ + ('a', uint32_t), + ('b', uint32_t), + ('c', uint32_t), +] DCS_ARCH_e = CEnum(ctypes.c_uint32) DCS_ARCH_DISABLED = DCS_ARCH_e.define('DCS_ARCH_DISABLED', 0) DCS_ARCH_FADCS = DCS_ARCH_e.define('DCS_ARCH_FADCS', 1) @@ -206,8 +317,19 @@ PWR_CONFIG_TCP_MEASURED = PwrConfig_e.define('PWR_CONFIG_TCP_MEASURED', 3) PWR_CONFIG_TBP_DESKTOP = PwrConfig_e.define('PWR_CONFIG_TBP_DESKTOP', 4) PWR_CONFIG_TBP_MOBILE = PwrConfig_e.define('PWR_CONFIG_TBP_MOBILE', 5) -class _anonstruct12(Struct): pass -DpmDescriptor_t = _anonstruct12 +class DpmDescriptor_t(Struct): pass +DpmDescriptor_t._fields_ = [ + ('Padding', uint8_t), + ('SnapToDiscrete', uint8_t), + ('NumDiscreteLevels', uint8_t), + ('CalculateFopt', uint8_t), + ('ConversionToAvfsClk', LinearInt_t), + ('Padding3', (uint32_t * 3)), + ('Padding4', uint16_t), + ('FoptimalDc', uint16_t), + ('FoptimalAc', uint16_t), + ('Padding2', uint16_t), +] PPT_THROTTLER_e = CEnum(ctypes.c_uint32) PPT_THROTTLER_PPT0 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT0', 0) PPT_THROTTLER_PPT1 = PPT_THROTTLER_e.define('PPT_THROTTLER_PPT1', 1) @@ -349,8 +471,13 @@ PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3 = PP_GRTAVFS_FW_SEP_FUSE_e.de PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4 = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4', 18) PP_GRTAVFS_FW_SEP_FUSE_COUNT = PP_GRTAVFS_FW_SEP_FUSE_e.define('PP_GRTAVFS_FW_SEP_FUSE_COUNT', 19) -class _anonstruct13(Struct): pass -SviTelemetryScale_t = _anonstruct13 +class SviTelemetryScale_t(Struct): pass +int8_t = ctypes.c_char +SviTelemetryScale_t._fields_ = [ + ('Offset', int8_t), + ('Padding', uint8_t), + ('MaxCurrent', uint16_t), +] PP_OD_POWER_FEATURE_e = CEnum(ctypes.c_uint32) PP_OD_POWER_FEATURE_ALWAYS_ENABLED = PP_OD_POWER_FEATURE_e.define('PP_OD_POWER_FEATURE_ALWAYS_ENABLED', 0) PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING = PP_OD_POWER_FEATURE_e.define('PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING', 1) @@ -390,12 +517,87 @@ OD_OP_GFX_EDC_ERROR = OD_FAIL_e.define('OD_OP_GFX_EDC_ERROR', 25) OD_OP_GFX_PCC_ERROR = OD_FAIL_e.define('OD_OP_GFX_PCC_ERROR', 26) OD_POWER_FEATURE_CTRL_ERROR = OD_FAIL_e.define('OD_POWER_FEATURE_CTRL_ERROR', 27) -class _anonstruct14(Struct): pass -OverDriveTable_t = _anonstruct14 -class _anonstruct15(Struct): pass -OverDriveTableExternal_t = _anonstruct15 -class _anonstruct16(Struct): pass -OverDriveLimits_t = _anonstruct16 +class OverDriveTable_t(Struct): pass +int16_t = ctypes.c_int16 +OverDriveTable_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', (int16_t * 6)), + ('VddGfxVmax', uint16_t), + ('VddSocVmax', uint16_t), + ('IdlePwrSavingFeaturesCtrl', uint8_t), + ('RuntimePwrSavingFeaturesCtrl', uint8_t), + ('Padding', uint16_t), + ('GfxclkFoffset', int16_t), + ('Padding1', uint16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('FclkFmin', uint16_t), + ('FclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', (uint8_t * 6)), + ('FanLinearTempPoints', (uint8_t * 6)), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('FanZeroRpmStopTemp', uint8_t), + ('FanMode', uint8_t), + ('MaxOpTemp', uint8_t), + ('AdvancedOdModeEnabled', uint8_t), + ('Padding2', (uint8_t * 3)), + ('GfxVoltageFullCtrlMode', uint16_t), + ('SocVoltageFullCtrlMode', uint16_t), + ('GfxclkFullCtrlMode', uint16_t), + ('UclkFullCtrlMode', uint16_t), + ('FclkFullCtrlMode', uint16_t), + ('Padding3', uint16_t), + ('GfxEdc', int16_t), + ('GfxPccLimitControl', int16_t), + ('GfxclkFmaxVmax', uint16_t), + ('GfxclkFmaxVmaxTemperature', uint8_t), + ('Padding4', (uint8_t * 1)), + ('Spare', (uint32_t * 9)), + ('MmHubPadding', (uint32_t * 8)), +] +class OverDriveTableExternal_t(Struct): pass +OverDriveTableExternal_t._fields_ = [ + ('OverDriveTable', OverDriveTable_t), +] +class OverDriveLimits_t(Struct): pass +OverDriveLimits_t._fields_ = [ + ('FeatureCtrlMask', uint32_t), + ('VoltageOffsetPerZoneBoundary', (int16_t * 6)), + ('VddGfxVmax', uint16_t), + ('VddSocVmax', uint16_t), + ('GfxclkFoffset', int16_t), + ('Padding', uint16_t), + ('UclkFmin', uint16_t), + ('UclkFmax', uint16_t), + ('FclkFmin', uint16_t), + ('FclkFmax', uint16_t), + ('Ppt', int16_t), + ('Tdc', int16_t), + ('FanLinearPwmPoints', (uint8_t * 6)), + ('FanLinearTempPoints', (uint8_t * 6)), + ('FanMinimumPwm', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanTargetTemperature', uint16_t), + ('FanZeroRpmEnable', uint8_t), + ('MaxOpTemp', uint8_t), + ('Padding1', (uint8_t * 2)), + ('GfxVoltageFullCtrlMode', uint16_t), + ('SocVoltageFullCtrlMode', uint16_t), + ('GfxclkFullCtrlMode', uint16_t), + ('UclkFullCtrlMode', uint16_t), + ('FclkFullCtrlMode', uint16_t), + ('GfxEdc', int16_t), + ('GfxPccLimitControl', int16_t), + ('Padding2', int16_t), + ('Spare', (uint32_t * 5)), +] BOARD_GPIO_TYPE_e = CEnum(ctypes.c_uint32) BOARD_GPIO_SMUIO_0 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_0', 0) BOARD_GPIO_SMUIO_1 = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_SMUIO_1', 1) @@ -444,58 +646,662 @@ BOARD_GPIO_DC_SWAPLOCK_B = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_DC_SWAPLOCK_B', MAX_BOARD_DC_GPIO_NUM = BOARD_GPIO_TYPE_e.define('MAX_BOARD_DC_GPIO_NUM', 44) BOARD_GPIO_LV_EN = BOARD_GPIO_TYPE_e.define('BOARD_GPIO_LV_EN', 45) -class _anonstruct17(Struct): pass -BootValues_t = _anonstruct17 -class _anonstruct18(Struct): pass -MsgLimits_t = _anonstruct18 -class _anonstruct19(Struct): pass -DriverReportedClocks_t = _anonstruct19 -class _anonstruct20(Struct): pass -AvfsDcBtcParams_t = _anonstruct20 -class _anonstruct21(Struct): pass -AvfsFuseOverride_t = _anonstruct21 -class _anonstruct22(Struct): pass -PFE_Settings_t = _anonstruct22 -class _anonstruct23(Struct): pass -SkuTable_t = _anonstruct23 -class _anonstruct24(Struct): pass -Svi3RegulatorSettings_t = _anonstruct24 -class _anonstruct25(Struct): pass -BoardTable_t = _anonstruct25 -class _anonstruct26(Struct): pass -CustomSkuTable_t = _anonstruct26 -class _anonstruct27(Struct): pass -PPTable_t = _anonstruct27 -class _anonstruct28(Struct): pass -DriverSmuConfig_t = _anonstruct28 -class _anonstruct29(Struct): pass -DriverSmuConfigExternal_t = _anonstruct29 -class _anonstruct30(Struct): pass -DriverInfoTable_t = _anonstruct30 -class _anonstruct31(Struct): pass -SmuMetrics_t = _anonstruct31 -class _anonstruct32(Struct): pass -SmuMetricsExternal_t = _anonstruct32 -class _anonstruct33(Struct): pass -WatermarkRowGeneric_t = _anonstruct33 +class BootValues_t(Struct): pass +BootValues_t._fields_ = [ + ('InitImuClk', uint16_t), + ('InitSocclk', uint16_t), + ('InitMpioclk', uint16_t), + ('InitSmnclk', uint16_t), + ('InitDispClk', uint16_t), + ('InitDppClk', uint16_t), + ('InitDprefclk', uint16_t), + ('InitDcfclk', uint16_t), + ('InitDtbclk', uint16_t), + ('InitDbguSocClk', uint16_t), + ('InitGfxclk_bypass', uint16_t), + ('InitMp1clk', uint16_t), + ('InitLclk', uint16_t), + ('InitDbguBacoClk', uint16_t), + ('InitBaco400clk', uint16_t), + ('InitBaco1200clk_bypass', uint16_t), + ('InitBaco700clk_bypass', uint16_t), + ('InitBaco500clk', uint16_t), + ('InitDclk0', uint16_t), + ('InitVclk0', uint16_t), + ('InitFclk', uint16_t), + ('Padding1', uint16_t), + ('InitUclkLevel', uint8_t), + ('Padding', (uint8_t * 3)), + ('InitVcoFreqPll0', uint32_t), + ('InitVcoFreqPll1', uint32_t), + ('InitVcoFreqPll2', uint32_t), + ('InitVcoFreqPll3', uint32_t), + ('InitVcoFreqPll4', uint32_t), + ('InitVcoFreqPll5', uint32_t), + ('InitVcoFreqPll6', uint32_t), + ('InitVcoFreqPll7', uint32_t), + ('InitVcoFreqPll8', uint32_t), + ('InitGfx', uint16_t), + ('InitSoc', uint16_t), + ('InitVddIoMem', uint16_t), + ('InitVddCiMem', uint16_t), + ('Spare', (uint32_t * 8)), +] +class MsgLimits_t(Struct): pass +MsgLimits_t._fields_ = [ + ('Power', ((uint16_t * 2) * 4)), + ('Tdc', (uint16_t * 2)), + ('Temperature', (uint16_t * 12)), + ('PwmLimitMin', uint8_t), + ('PwmLimitMax', uint8_t), + ('FanTargetTemperature', uint8_t), + ('Spare1', (uint8_t * 1)), + ('AcousticTargetRpmThresholdMin', uint16_t), + ('AcousticTargetRpmThresholdMax', uint16_t), + ('AcousticLimitRpmThresholdMin', uint16_t), + ('AcousticLimitRpmThresholdMax', uint16_t), + ('PccLimitMin', uint16_t), + ('PccLimitMax', uint16_t), + ('FanStopTempMin', uint16_t), + ('FanStopTempMax', uint16_t), + ('FanStartTempMin', uint16_t), + ('FanStartTempMax', uint16_t), + ('PowerMinPpt0', (uint16_t * 2)), + ('Spare', (uint32_t * 11)), +] +class DriverReportedClocks_t(Struct): pass +DriverReportedClocks_t._fields_ = [ + ('BaseClockAc', uint16_t), + ('GameClockAc', uint16_t), + ('BoostClockAc', uint16_t), + ('BaseClockDc', uint16_t), + ('GameClockDc', uint16_t), + ('BoostClockDc', uint16_t), + ('MaxReportedClock', uint16_t), + ('Padding', uint16_t), + ('Reserved', (uint32_t * 3)), +] +class AvfsDcBtcParams_t(Struct): pass +AvfsDcBtcParams_t._fields_ = [ + ('DcBtcEnabled', uint8_t), + ('Padding', (uint8_t * 3)), + ('DcTol', uint16_t), + ('DcBtcGb', uint16_t), + ('DcBtcMin', uint16_t), + ('DcBtcMax', uint16_t), + ('DcBtcGbScalar', LinearInt_t), +] +class AvfsFuseOverride_t(Struct): pass +AvfsFuseOverride_t._fields_ = [ + ('AvfsTemp', (uint16_t * 2)), + ('VftFMin', uint16_t), + ('VInversion', uint16_t), + ('qVft', (QuadraticInt_t * 2)), + ('qAvfsGb', QuadraticInt_t), + ('qAvfsGb2', QuadraticInt_t), +] +class PFE_Settings_t(Struct): pass +PFE_Settings_t._fields_ = [ + ('Version', uint8_t), + ('Spare8', (uint8_t * 3)), + ('FeaturesToRun', (uint32_t * 2)), + ('FwDStateMask', uint32_t), + ('DebugOverrides', uint32_t), + ('Spare', (uint32_t * 2)), +] +class SkuTable_t(Struct): pass +int32_t = ctypes.c_int32 +SkuTable_t._fields_ = [ + ('Version', uint32_t), + ('TotalPowerConfig', uint8_t), + ('CustomerVariant', uint8_t), + ('MemoryTemperatureTypeMask', uint8_t), + ('SmartShiftVersion', uint8_t), + ('SocketPowerLimitSpare', (uint8_t * 10)), + ('EnableLegacyPptLimit', uint8_t), + ('UseInputTelemetry', uint8_t), + ('SmartShiftMinReportedPptinDcs', uint8_t), + ('PaddingPpt', (uint8_t * 7)), + ('HwCtfTempLimit', uint16_t), + ('PaddingInfra', uint16_t), + ('FitControllerFailureRateLimit', uint32_t), + ('FitControllerGfxDutyCycle', uint32_t), + ('FitControllerSocDutyCycle', uint32_t), + ('FitControllerSocOffset', uint32_t), + ('GfxApccPlusResidencyLimit', uint32_t), + ('ThrottlerControlMask', uint32_t), + ('UlvVoltageOffset', (uint16_t * 2)), + ('Padding', (uint8_t * 2)), + ('DeepUlvVoltageOffsetSoc', uint16_t), + ('DefaultMaxVoltage', (uint16_t * 2)), + ('BoostMaxVoltage', (uint16_t * 2)), + ('VminTempHystersis', (int16_t * 2)), + ('VminTempThreshold', (int16_t * 2)), + ('Vmin_Hot_T0', (uint16_t * 2)), + ('Vmin_Cold_T0', (uint16_t * 2)), + ('Vmin_Hot_Eol', (uint16_t * 2)), + ('Vmin_Cold_Eol', (uint16_t * 2)), + ('Vmin_Aging_Offset', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Hot', (uint16_t * 2)), + ('Spare_Vmin_Plat_Offset_Cold', (uint16_t * 2)), + ('VcBtcFixedVminAgingOffset', (uint16_t * 2)), + ('VcBtcVmin2PsmDegrationGb', (uint16_t * 2)), + ('VcBtcPsmA', (uint32_t * 2)), + ('VcBtcPsmB', (uint32_t * 2)), + ('VcBtcVminA', (uint32_t * 2)), + ('VcBtcVminB', (uint32_t * 2)), + ('PerPartVminEnabled', (uint8_t * 2)), + ('VcBtcEnabled', (uint8_t * 2)), + ('SocketPowerLimitAcTau', (uint16_t * 4)), + ('SocketPowerLimitDcTau', (uint16_t * 4)), + ('Gfx_Vmin_droop', QuadraticInt_t), + ('Soc_Vmin_droop', QuadraticInt_t), + ('SpareVmin', (uint32_t * 6)), + ('DpmDescriptor', (DpmDescriptor_t * 11)), + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 6)), + ('FreqTableShadowUclk', (uint16_t * 6)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint32_t * 11)), + ('GfxclkAibFmax', uint16_t), + ('GfxDpmPadding', uint16_t), + ('GfxclkFgfxoffEntry', uint16_t), + ('GfxclkFgfxoffExitImu', uint16_t), + ('GfxclkFgfxoffExitRlc', uint16_t), + ('GfxclkThrottleClock', uint16_t), + ('EnableGfxPowerStagesGpio', uint8_t), + ('GfxIdlePadding', uint8_t), + ('SmsRepairWRCKClkDivEn', uint8_t), + ('SmsRepairWRCKClkDivVal', uint8_t), + ('GfxOffEntryEarlyMGCGEn', uint8_t), + ('GfxOffEntryForceCGCGEn', uint8_t), + ('GfxOffEntryForceCGCGDelayEn', uint8_t), + ('GfxOffEntryForceCGCGDelayVal', uint8_t), + ('GfxclkFreqGfxUlv', uint16_t), + ('GfxIdlePadding2', (uint8_t * 2)), + ('GfxOffEntryHysteresis', uint32_t), + ('GfxoffSpare', (uint32_t * 15)), + ('DfllMstrOscConfigA', uint16_t), + ('DfllSlvOscConfigA', uint16_t), + ('DfllBtcMasterScalerM', uint32_t), + ('DfllBtcMasterScalerB', int32_t), + ('DfllBtcSlaveScalerM', uint32_t), + ('DfllBtcSlaveScalerB', int32_t), + ('DfllPccAsWaitCtrl', uint32_t), + ('DfllPccAsStepCtrl', uint32_t), + ('GfxDfllSpare', (uint32_t * 9)), + ('DvoPsmDownThresholdVoltage', uint32_t), + ('DvoPsmUpThresholdVoltage', uint32_t), + ('DvoFmaxLowScaler', uint32_t), + ('PaddingDcs', uint32_t), + ('DcsMinGfxOffTime', uint16_t), + ('DcsMaxGfxOffTime', uint16_t), + ('DcsMinCreditAccum', uint32_t), + ('DcsExitHysteresis', uint16_t), + ('DcsTimeout', uint16_t), + ('DcsPfGfxFopt', uint32_t), + ('DcsPfUclkFopt', uint32_t), + ('FoptEnabled', uint8_t), + ('DcsSpare2', (uint8_t * 3)), + ('DcsFoptM', uint32_t), + ('DcsFoptB', uint32_t), + ('DcsSpare', (uint32_t * 9)), + ('UseStrobeModeOptimizations', uint8_t), + ('PaddingMem', (uint8_t * 3)), + ('UclkDpmPstates', (uint8_t * 6)), + ('UclkDpmShadowPstates', (uint8_t * 6)), + ('FreqTableUclkDiv', (uint8_t * 6)), + ('FreqTableShadowUclkDiv', (uint8_t * 6)), + ('MemVmempVoltage', (uint16_t * 6)), + ('MemVddioVoltage', (uint16_t * 6)), + ('DalDcModeMaxUclkFreq', uint16_t), + ('PaddingsMem', (uint8_t * 2)), + ('PaddingFclk', uint32_t), + ('PcieGenSpeed', (uint8_t * 3)), + ('PcieLaneCount', (uint8_t * 3)), + ('LclkFreq', (uint16_t * 3)), + ('OverrideGfxAvfsFuses', uint8_t), + ('GfxAvfsPadding', (uint8_t * 1)), + ('DroopGBStDev', uint16_t), + ('SocHwRtAvfsFuses', (uint32_t * 32)), + ('GfxL2HwRtAvfsFuses', (uint32_t * 32)), + ('PsmDidt_Vcross', (uint16_t * 2)), + ('PsmDidt_StaticDroop_A', (uint32_t * 3)), + ('PsmDidt_StaticDroop_B', (uint32_t * 3)), + ('PsmDidt_DynDroop_A', (uint32_t * 3)), + ('PsmDidt_DynDroop_B', (uint32_t * 3)), + ('spare_HwRtAvfsFuses', (uint32_t * 19)), + ('SocCommonRtAvfs', (uint32_t * 13)), + ('GfxCommonRtAvfs', (uint32_t * 13)), + ('SocFwRtAvfsFuses', (uint32_t * 19)), + ('GfxL2FwRtAvfsFuses', (uint32_t * 19)), + ('spare_FwRtAvfsFuses', (uint32_t * 19)), + ('Soc_Droop_PWL_F', (uint32_t * 5)), + ('Soc_Droop_PWL_a', (uint32_t * 5)), + ('Soc_Droop_PWL_b', (uint32_t * 5)), + ('Soc_Droop_PWL_c', (uint32_t * 5)), + ('Gfx_Droop_PWL_F', (uint32_t * 5)), + ('Gfx_Droop_PWL_a', (uint32_t * 5)), + ('Gfx_Droop_PWL_b', (uint32_t * 5)), + ('Gfx_Droop_PWL_c', (uint32_t * 5)), + ('Gfx_Static_PWL_Offset', (uint32_t * 5)), + ('Soc_Static_PWL_Offset', (uint32_t * 5)), + ('dGbV_dT_vmin', uint32_t), + ('dGbV_dT_vmax', uint32_t), + ('PaddingV2F', (uint32_t * 4)), + ('DcBtcGfxParams', AvfsDcBtcParams_t), + ('SSCurve_GFX', QuadraticInt_t), + ('GfxAvfsSpare', (uint32_t * 29)), + ('OverrideSocAvfsFuses', uint8_t), + ('MinSocAvfsRevision', uint8_t), + ('SocAvfsPadding', (uint8_t * 2)), + ('SocAvfsFuseOverride', (AvfsFuseOverride_t * 1)), + ('dBtcGbSoc', (DroopInt_t * 1)), + ('qAgingGb', (LinearInt_t * 1)), + ('qStaticVoltageOffset', (QuadraticInt_t * 1)), + ('DcBtcSocParams', (AvfsDcBtcParams_t * 1)), + ('SSCurve_SOC', QuadraticInt_t), + ('SocAvfsSpare', (uint32_t * 29)), + ('BootValues', BootValues_t), + ('DriverReportedClocks', DriverReportedClocks_t), + ('MsgLimits', MsgLimits_t), + ('OverDriveLimitsBasicMin', OverDriveLimits_t), + ('OverDriveLimitsBasicMax', OverDriveLimits_t), + ('OverDriveLimitsAdvancedMin', OverDriveLimits_t), + ('OverDriveLimitsAdvancedMax', OverDriveLimits_t), + ('TotalBoardPowerSupport', uint8_t), + ('TotalBoardPowerPadding', (uint8_t * 1)), + ('TotalBoardPowerRoc', uint16_t), + ('qFeffCoeffGameClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBaseClock', (QuadraticInt_t * 2)), + ('qFeffCoeffBoostClock', (QuadraticInt_t * 2)), + ('AptUclkGfxclkLookup', ((int32_t * 6) * 2)), + ('AptUclkGfxclkLookupHyst', ((uint32_t * 6) * 2)), + ('AptPadding', uint32_t), + ('GfxXvminDidtDroopThresh', QuadraticInt_t), + ('GfxXvminDidtResetDDWait', uint32_t), + ('GfxXvminDidtClkStopWait', uint32_t), + ('GfxXvminDidtFcsStepCtrl', uint32_t), + ('GfxXvminDidtFcsWaitCtrl', uint32_t), + ('PsmModeEnabled', uint32_t), + ('P2v_a', uint32_t), + ('P2v_b', uint32_t), + ('P2v_c', uint32_t), + ('T2p_a', uint32_t), + ('T2p_b', uint32_t), + ('T2p_c', uint32_t), + ('P2vTemp', uint32_t), + ('PsmDidtStaticSettings', QuadraticInt_t), + ('PsmDidtDynamicSettings', QuadraticInt_t), + ('PsmDidtAvgDiv', uint8_t), + ('PsmDidtForceStall', uint8_t), + ('PsmDidtReleaseTimer', uint16_t), + ('PsmDidtStallPattern', uint32_t), + ('CacEdcCacLeakageC0', uint32_t), + ('CacEdcCacLeakageC1', uint32_t), + ('CacEdcCacLeakageC2', uint32_t), + ('CacEdcCacLeakageC3', uint32_t), + ('CacEdcCacLeakageC4', uint32_t), + ('CacEdcCacLeakageC5', uint32_t), + ('CacEdcGfxClkScalar', uint32_t), + ('CacEdcGfxClkIntercept', uint32_t), + ('CacEdcCac_m', uint32_t), + ('CacEdcCac_b', uint32_t), + ('CacEdcCurrLimitGuardband', uint32_t), + ('CacEdcDynToTotalCacRatio', uint32_t), + ('XVmin_Gfx_EdcThreshScalar', uint32_t), + ('XVmin_Gfx_EdcEnableFreq', uint32_t), + ('XVmin_Gfx_EdcPccAsStepCtrl', uint32_t), + ('XVmin_Gfx_EdcPccAsWaitCtrl', uint32_t), + ('XVmin_Gfx_EdcThreshold', uint16_t), + ('XVmin_Gfx_EdcFiltHysWaitCtrl', uint16_t), + ('XVmin_Soc_EdcThreshScalar', uint32_t), + ('XVmin_Soc_EdcEnableFreq', uint32_t), + ('XVmin_Soc_EdcThreshold', uint32_t), + ('XVmin_Soc_EdcStepUpTime', uint16_t), + ('XVmin_Soc_EdcStepDownTime', uint16_t), + ('XVmin_Soc_EdcInitPccStep', uint8_t), + ('PaddingSocEdc', (uint8_t * 3)), + ('GfxXvminFuseOverride', uint8_t), + ('SocXvminFuseOverride', uint8_t), + ('PaddingXvminFuseOverride', (uint8_t * 2)), + ('GfxXvminFddTempLow', uint8_t), + ('GfxXvminFddTempHigh', uint8_t), + ('SocXvminFddTempLow', uint8_t), + ('SocXvminFddTempHigh', uint8_t), + ('GfxXvminFddVolt0', uint16_t), + ('GfxXvminFddVolt1', uint16_t), + ('GfxXvminFddVolt2', uint16_t), + ('SocXvminFddVolt0', uint16_t), + ('SocXvminFddVolt1', uint16_t), + ('SocXvminFddVolt2', uint16_t), + ('GfxXvminDsFddDsm', (uint16_t * 6)), + ('GfxXvminEdcFddDsm', (uint16_t * 6)), + ('SocXvminEdcFddDsm', (uint16_t * 6)), + ('Spare', uint32_t), + ('MmHubPadding', (uint32_t * 8)), +] +class Svi3RegulatorSettings_t(Struct): pass +Svi3RegulatorSettings_t._fields_ = [ + ('SlewRateConditions', uint8_t), + ('LoadLineAdjust', uint8_t), + ('VoutOffset', uint8_t), + ('VidMax', uint8_t), + ('VidMin', uint8_t), + ('TenBitTelEn', uint8_t), + ('SixteenBitTelEn', uint8_t), + ('OcpThresh', uint8_t), + ('OcpWarnThresh', uint8_t), + ('OcpSettings', uint8_t), + ('VrhotThresh', uint8_t), + ('OtpThresh', uint8_t), + ('UvpOvpDeltaRef', uint8_t), + ('PhaseShed', uint8_t), + ('Padding', (uint8_t * 10)), + ('SettingOverrideMask', uint32_t), +] +class BoardTable_t(Struct): pass +BoardTable_t._fields_ = [ + ('Version', uint32_t), + ('I2cControllers', (I2cControllerConfig_t * 8)), + ('SlaveAddrMapping', (uint8_t * 4)), + ('VrPsiSupport', (uint8_t * 4)), + ('Svi3SvcSpeed', uint32_t), + ('EnablePsi6', (uint8_t * 4)), + ('Svi3RegSettings', (Svi3RegulatorSettings_t * 4)), + ('LedOffGpio', uint8_t), + ('FanOffGpio', uint8_t), + ('GfxVrPowerStageOffGpio', uint8_t), + ('AcDcGpio', uint8_t), + ('AcDcPolarity', uint8_t), + ('VR0HotGpio', uint8_t), + ('VR0HotPolarity', uint8_t), + ('GthrGpio', uint8_t), + ('GthrPolarity', uint8_t), + ('LedPin0', uint8_t), + ('LedPin1', uint8_t), + ('LedPin2', uint8_t), + ('LedEnableMask', uint8_t), + ('LedPcie', uint8_t), + ('LedError', uint8_t), + ('PaddingLed', uint8_t), + ('UclkTrainingModeSpreadPercent', uint8_t), + ('UclkSpreadPadding', uint8_t), + ('UclkSpreadFreq', uint16_t), + ('UclkSpreadPercent', (uint8_t * 16)), + ('GfxclkSpreadEnable', uint8_t), + ('FclkSpreadPercent', uint8_t), + ('FclkSpreadFreq', uint16_t), + ('DramWidth', uint8_t), + ('PaddingMem1', (uint8_t * 7)), + ('HsrEnabled', uint8_t), + ('VddqOffEnabled', uint8_t), + ('PaddingUmcFlags', (uint8_t * 2)), + ('Paddign1', uint32_t), + ('BacoEntryDelay', uint32_t), + ('FuseWritePowerMuxPresent', uint8_t), + ('FuseWritePadding', (uint8_t * 3)), + ('LoadlineGfx', uint32_t), + ('LoadlineSoc', uint32_t), + ('GfxEdcLimit', uint32_t), + ('SocEdcLimit', uint32_t), + ('RestBoardPower', uint32_t), + ('ConnectorsImpedance', uint32_t), + ('EpcsSens0', uint8_t), + ('EpcsSens1', uint8_t), + ('PaddingEpcs', (uint8_t * 2)), + ('BoardSpare', (uint32_t * 52)), + ('MmHubPadding', (uint32_t * 8)), +] +class CustomSkuTable_t(Struct): pass +CustomSkuTable_t._fields_ = [ + ('SocketPowerLimitAc', (uint16_t * 4)), + ('VrTdcLimit', (uint16_t * 2)), + ('TotalIdleBoardPowerM', int16_t), + ('TotalIdleBoardPowerB', int16_t), + ('TotalBoardPowerM', int16_t), + ('TotalBoardPowerB', int16_t), + ('TemperatureLimit', (uint16_t * 12)), + ('FanStopTemp', (uint16_t * 12)), + ('FanStartTemp', (uint16_t * 12)), + ('FanGain', (uint16_t * 12)), + ('FanPwmMin', uint16_t), + ('AcousticTargetRpmThreshold', uint16_t), + ('AcousticLimitRpmThreshold', uint16_t), + ('FanMaximumRpm', uint16_t), + ('MGpuAcousticLimitRpmThreshold', uint16_t), + ('FanTargetGfxclk', uint16_t), + ('TempInputSelectMask', uint32_t), + ('FanZeroRpmEnable', uint8_t), + ('FanTachEdgePerRev', uint8_t), + ('FanPadding', uint16_t), + ('FanTargetTemperature', (uint16_t * 12)), + ('FuzzyFan_ErrorSetDelta', int16_t), + ('FuzzyFan_ErrorRateSetDelta', int16_t), + ('FuzzyFan_PwmSetDelta', int16_t), + ('FanPadding2', uint16_t), + ('FwCtfLimit', (uint16_t * 12)), + ('IntakeTempEnableRPM', uint16_t), + ('IntakeTempOffsetTemp', int16_t), + ('IntakeTempReleaseTemp', uint16_t), + ('IntakeTempHighIntakeAcousticLimit', uint16_t), + ('IntakeTempAcouticLimitReleaseRate', uint16_t), + ('FanAbnormalTempLimitOffset', int16_t), + ('FanStalledTriggerRpm', uint16_t), + ('FanAbnormalTriggerRpmCoeff', uint16_t), + ('FanSpare', (uint16_t * 1)), + ('FanIntakeSensorSupport', uint8_t), + ('FanIntakePadding', uint8_t), + ('FanSpare2', (uint32_t * 12)), + ('ODFeatureCtrlMask', uint32_t), + ('TemperatureLimit_Hynix', uint16_t), + ('TemperatureLimit_Micron', uint16_t), + ('TemperatureFwCtfLimit_Hynix', uint16_t), + ('TemperatureFwCtfLimit_Micron', uint16_t), + ('PlatformTdcLimit', (uint16_t * 2)), + ('SocketPowerLimitDc', (uint16_t * 4)), + ('SocketPowerLimitSmartShift2', uint16_t), + ('CustomSkuSpare16b', uint16_t), + ('CustomSkuSpare32b', (uint32_t * 10)), + ('MmHubPadding', (uint32_t * 8)), +] +class PPTable_t(Struct): pass +PPTable_t._fields_ = [ + ('PFE_Settings', PFE_Settings_t), + ('SkuTable', SkuTable_t), + ('CustomSkuTable', CustomSkuTable_t), + ('BoardTable', BoardTable_t), +] +class DriverSmuConfig_t(Struct): pass +DriverSmuConfig_t._fields_ = [ + ('GfxclkAverageLpfTau', uint16_t), + ('FclkAverageLpfTau', uint16_t), + ('UclkAverageLpfTau', uint16_t), + ('GfxActivityLpfTau', uint16_t), + ('UclkActivityLpfTau', uint16_t), + ('UclkMaxActivityLpfTau', uint16_t), + ('SocketPowerLpfTau', uint16_t), + ('VcnClkAverageLpfTau', uint16_t), + ('VcnUsageAverageLpfTau', uint16_t), + ('PcieActivityLpTau', uint16_t), +] +class DriverSmuConfigExternal_t(Struct): pass +DriverSmuConfigExternal_t._fields_ = [ + ('DriverSmuConfig', DriverSmuConfig_t), + ('Spare', (uint32_t * 8)), + ('MmHubPadding', (uint32_t * 8)), +] +class DriverInfoTable_t(Struct): pass +DriverInfoTable_t._fields_ = [ + ('FreqTableGfx', (uint16_t * 16)), + ('FreqTableVclk', (uint16_t * 8)), + ('FreqTableDclk', (uint16_t * 8)), + ('FreqTableSocclk', (uint16_t * 8)), + ('FreqTableUclk', (uint16_t * 6)), + ('FreqTableDispclk', (uint16_t * 8)), + ('FreqTableDppClk', (uint16_t * 8)), + ('FreqTableDprefclk', (uint16_t * 8)), + ('FreqTableDcfclk', (uint16_t * 8)), + ('FreqTableDtbclk', (uint16_t * 8)), + ('FreqTableFclk', (uint16_t * 8)), + ('DcModeMaxFreq', (uint16_t * 11)), + ('Padding', uint16_t), + ('Spare', (uint32_t * 32)), + ('MmHubPadding', (uint32_t * 8)), +] +class SmuMetrics_t(Struct): pass +SmuMetrics_t._fields_ = [ + ('CurrClock', (uint32_t * 11)), + ('AverageGfxclkFrequencyTarget', uint16_t), + ('AverageGfxclkFrequencyPreDs', uint16_t), + ('AverageGfxclkFrequencyPostDs', uint16_t), + ('AverageFclkFrequencyPreDs', uint16_t), + ('AverageFclkFrequencyPostDs', uint16_t), + ('AverageMemclkFrequencyPreDs', uint16_t), + ('AverageMemclkFrequencyPostDs', uint16_t), + ('AverageVclk0Frequency', uint16_t), + ('AverageDclk0Frequency', uint16_t), + ('AverageVclk1Frequency', uint16_t), + ('AverageDclk1Frequency', uint16_t), + ('AveragePCIeBusy', uint16_t), + ('dGPU_W_MAX', uint16_t), + ('padding', uint16_t), + ('MovingAverageGfxclkFrequencyTarget', uint16_t), + ('MovingAverageGfxclkFrequencyPreDs', uint16_t), + ('MovingAverageGfxclkFrequencyPostDs', uint16_t), + ('MovingAverageFclkFrequencyPreDs', uint16_t), + ('MovingAverageFclkFrequencyPostDs', uint16_t), + ('MovingAverageMemclkFrequencyPreDs', uint16_t), + ('MovingAverageMemclkFrequencyPostDs', uint16_t), + ('MovingAverageVclk0Frequency', uint16_t), + ('MovingAverageDclk0Frequency', uint16_t), + ('MovingAverageGfxActivity', uint16_t), + ('MovingAverageUclkActivity', uint16_t), + ('MovingAverageVcn0ActivityPercentage', uint16_t), + ('MovingAveragePCIeBusy', uint16_t), + ('MovingAverageUclkActivity_MAX', uint16_t), + ('MovingAverageSocketPower', uint16_t), + ('MovingAveragePadding', uint16_t), + ('MetricsCounter', uint32_t), + ('AvgVoltage', (uint16_t * 4)), + ('AvgCurrent', (uint16_t * 4)), + ('AverageGfxActivity', uint16_t), + ('AverageUclkActivity', uint16_t), + ('AverageVcn0ActivityPercentage', uint16_t), + ('Vcn1ActivityPercentage', uint16_t), + ('EnergyAccumulator', uint32_t), + ('AverageSocketPower', uint16_t), + ('AverageTotalBoardPower', uint16_t), + ('AvgTemperature', (uint16_t * 12)), + ('AvgTemperatureFanIntake', uint16_t), + ('PcieRate', uint8_t), + ('PcieWidth', uint8_t), + ('AvgFanPwm', uint8_t), + ('Padding', (uint8_t * 1)), + ('AvgFanRpm', uint16_t), + ('ThrottlingPercentage', (uint8_t * 21)), + ('VmaxThrottlingPercentage', uint8_t), + ('padding1', (uint8_t * 2)), + ('D3HotEntryCountPerMode', (uint32_t * 4)), + ('D3HotExitCountPerMode', (uint32_t * 4)), + ('ArmMsgReceivedCountPerMode', (uint32_t * 4)), + ('ApuSTAPMSmartShiftLimit', uint16_t), + ('ApuSTAPMLimit', uint16_t), + ('AvgApuSocketPower', uint16_t), + ('AverageUclkActivity_MAX', uint16_t), + ('PublicSerialNumberLower', uint32_t), + ('PublicSerialNumberUpper', uint32_t), +] +class SmuMetricsExternal_t(Struct): pass +SmuMetricsExternal_t._fields_ = [ + ('SmuMetrics', SmuMetrics_t), + ('Spare', (uint32_t * 30)), + ('MmHubPadding', (uint32_t * 8)), +] +class WatermarkRowGeneric_t(Struct): pass +WatermarkRowGeneric_t._fields_ = [ + ('WmSetting', uint8_t), + ('Flags', uint8_t), + ('Padding', (uint8_t * 2)), +] WATERMARKS_FLAGS_e = CEnum(ctypes.c_uint32) WATERMARKS_CLOCK_RANGE = WATERMARKS_FLAGS_e.define('WATERMARKS_CLOCK_RANGE', 0) WATERMARKS_DUMMY_PSTATE = WATERMARKS_FLAGS_e.define('WATERMARKS_DUMMY_PSTATE', 1) WATERMARKS_MALL = WATERMARKS_FLAGS_e.define('WATERMARKS_MALL', 2) WATERMARKS_COUNT = WATERMARKS_FLAGS_e.define('WATERMARKS_COUNT', 3) -class _anonstruct34(Struct): pass -Watermarks_t = _anonstruct34 -class _anonstruct35(Struct): pass -WatermarksExternal_t = _anonstruct35 -class _anonstruct36(Struct): pass -AvfsDebugTable_t = _anonstruct36 -class _anonstruct37(Struct): pass -AvfsDebugTableExternal_t = _anonstruct37 -class _anonstruct38(Struct): pass -DpmActivityMonitorCoeffInt_t = _anonstruct38 -class _anonstruct39(Struct): pass -DpmActivityMonitorCoeffIntExternal_t = _anonstruct39 +class Watermarks_t(Struct): pass +Watermarks_t._fields_ = [ + ('WatermarkRow', (WatermarkRowGeneric_t * 4)), +] +class WatermarksExternal_t(Struct): pass +WatermarksExternal_t._fields_ = [ + ('Watermarks', Watermarks_t), + ('Spare', (uint32_t * 16)), + ('MmHubPadding', (uint32_t * 8)), +] +class AvfsDebugTable_t(Struct): pass +AvfsDebugTable_t._fields_ = [ + ('avgPsmCount', (uint16_t * 76)), + ('minPsmCount', (uint16_t * 76)), + ('maxPsmCount', (uint16_t * 76)), + ('avgPsmVoltage', (ctypes.c_float * 76)), + ('minPsmVoltage', (ctypes.c_float * 76)), + ('maxPsmVoltage', (ctypes.c_float * 76)), +] +class AvfsDebugTableExternal_t(Struct): pass +AvfsDebugTableExternal_t._fields_ = [ + ('AvfsDebugTable', AvfsDebugTable_t), + ('MmHubPadding', (uint32_t * 8)), +] +class DpmActivityMonitorCoeffInt_t(Struct): pass +DpmActivityMonitorCoeffInt_t._fields_ = [ + ('Gfx_ActiveHystLimit', uint8_t), + ('Gfx_IdleHystLimit', uint8_t), + ('Gfx_FPS', uint8_t), + ('Gfx_MinActiveFreqType', uint8_t), + ('Gfx_BoosterFreqType', uint8_t), + ('PaddingGfx', uint8_t), + ('Gfx_MinActiveFreq', uint16_t), + ('Gfx_BoosterFreq', uint16_t), + ('Gfx_PD_Data_time_constant', uint16_t), + ('Gfx_PD_Data_limit_a', uint32_t), + ('Gfx_PD_Data_limit_b', uint32_t), + ('Gfx_PD_Data_limit_c', uint32_t), + ('Gfx_PD_Data_error_coeff', uint32_t), + ('Gfx_PD_Data_error_rate_coeff', uint32_t), + ('Fclk_ActiveHystLimit', uint8_t), + ('Fclk_IdleHystLimit', uint8_t), + ('Fclk_FPS', uint8_t), + ('Fclk_MinActiveFreqType', uint8_t), + ('Fclk_BoosterFreqType', uint8_t), + ('PaddingFclk', uint8_t), + ('Fclk_MinActiveFreq', uint16_t), + ('Fclk_BoosterFreq', uint16_t), + ('Fclk_PD_Data_time_constant', uint16_t), + ('Fclk_PD_Data_limit_a', uint32_t), + ('Fclk_PD_Data_limit_b', uint32_t), + ('Fclk_PD_Data_limit_c', uint32_t), + ('Fclk_PD_Data_error_coeff', uint32_t), + ('Fclk_PD_Data_error_rate_coeff', uint32_t), + ('Mem_UpThreshold_Limit', (uint32_t * 6)), + ('Mem_UpHystLimit', (uint8_t * 6)), + ('Mem_DownHystLimit', (uint16_t * 6)), + ('Mem_Fps', uint16_t), +] +class DpmActivityMonitorCoeffIntExternal_t(Struct): pass +DpmActivityMonitorCoeffIntExternal_t._fields_ = [ + ('DpmActivityMonitorCoeffInt', DpmActivityMonitorCoeffInt_t), + ('MmHubPadding', (uint32_t * 8)), +] class struct_smu_hw_power_state(Struct): pass struct_smu_hw_power_state._fields_ = [ ('magic', ctypes.c_uint32),