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amd: autogen ip bases (#9360)

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uuuvn
2025-03-06 00:30:38 +05:00
committed by GitHub
parent 2cb2fce8d9
commit b75f307234
5 changed files with 2524 additions and 106 deletions
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1
autogen_stubs.sh
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@@ -171,6 +171,7 @@ generate_amd() {
extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h \ extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h \
extra/hip_gpu_driver/gc_11_0_0_offset.h \ extra/hip_gpu_driver/gc_11_0_0_offset.h \
extra/hip_gpu_driver/gc_10_3_0_offset.h \ extra/hip_gpu_driver/gc_10_3_0_offset.h \
extra/hip_gpu_driver/sienna_cichlid_ip_offset.h \
--clang-args="-I/opt/rocm/include -x c++" \ --clang-args="-I/opt/rocm/include -x c++" \
-o $BASE/amd_gpu.py -o $BASE/amd_gpu.py

1166
extra/hip_gpu_driver/sienna_cichlid_ip_offset.h Normal file
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3
test/mockgpu/amd/amdgpu.py
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@@ -5,9 +5,8 @@ import tinygrad.runtime.autogen.amd_gpu as amd_gpu
SDMA_MAX_COPY_SIZE = 0x400000 SDMA_MAX_COPY_SIZE = 0x400000
BASE_ADDR = 0x00001260
PACKET3_SET_SH_REG_START = 0x2c00 PACKET3_SET_SH_REG_START = 0x2c00
SUB = PACKET3_SET_SH_REG_START - BASE_ADDR SUB = PACKET3_SET_SH_REG_START - amd_gpu.GC_BASE__INST0_SEG0
regCOMPUTE_PGM_LO = 0x1bac - SUB regCOMPUTE_PGM_LO = 0x1bac - SUB
regCOMPUTE_USER_DATA_0 = 0x1be0 - SUB regCOMPUTE_USER_DATA_0 = 0x1be0 - SUB

1456
tinygrad/runtime/autogen/amd_gpu.py
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4
tinygrad/runtime/ops_amd.py
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@@ -22,8 +22,8 @@ WAIT_REG_MEM_FUNCTION_GEQ = 5 # >=
COMPUTE_SHADER_EN, FORCE_START_AT_000, CS_W32_EN = (1 << 0), (1 << 2), (1 << 15) COMPUTE_SHADER_EN, FORCE_START_AT_000, CS_W32_EN = (1 << 0), (1 << 2), (1 << 15)
def gfxreg(reg): return reg + 0x00001260 - amd_gpu.PACKET3_SET_SH_REG_START def gfxreg(reg): return reg + amd_gpu.GC_BASE__INST0_SEG0 - amd_gpu.PACKET3_SET_SH_REG_START
def nbioreg(reg): return reg + 0x00000d20 # NBIO_BASE__INST0_SEG2 def nbioreg(reg): return reg + amd_gpu.NBIO_BASE__INST0_SEG2
class AMDSignal(HCQSignal): class AMDSignal(HCQSignal):
def __init__(self, base_addr:int|None=None, **kwargs): def __init__(self, base_addr:int|None=None, **kwargs):