From efc99d0c55124206d95fc4177b964bc21c27dba2 Mon Sep 17 00:00:00 2001 From: George Hotz <72895+geohot@users.noreply.github.com> Date: Tue, 30 Dec 2025 16:13:24 -0500 Subject: [PATCH] assembly/amd: more refactors (#13907) * assembly/amd: more refactors * more refactors * more refactors * simpler emu * generate.py * regen all * cleanups * more * work * more readme * lil --- .github/workflows/test.yml | 3 +- extra/assembly/amd/README | 43 + extra/assembly/amd/asm.py | 120 +- extra/assembly/amd/autogen/cdna/__init__.py | 2 +- extra/assembly/amd/autogen/cdna/gen_pcode.py | 1978 ++++++++--------- extra/assembly/amd/autogen/rdna3/__init__.py | 2 +- extra/assembly/amd/autogen/rdna3/gen_pcode.py | 424 ++-- extra/assembly/amd/autogen/rdna4/__init__.py | 2 +- extra/assembly/amd/autogen/rdna4/gen_pcode.py | 360 +-- extra/assembly/amd/dsl.py | 557 ++--- extra/assembly/amd/emu.py | 589 ++--- extra/assembly/amd/pcode.py | 760 +------ extra/assembly/amd/pdf.py | 623 ++++++ extra/assembly/amd/test/helpers.py | 42 + extra/assembly/amd/test/test_emu.py | 37 + extra/assembly/amd/test/test_formats.py | 77 +- extra/assembly/amd/test/test_pcode.py | 4 +- test/mockgpu/amd/amdgpu.py | 2 +- 18 files changed, 2585 insertions(+), 3040 deletions(-) create mode 100644 extra/assembly/amd/README create mode 100644 extra/assembly/amd/pdf.py diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index ef2f8ce66b..119071702a 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -698,8 +698,7 @@ jobs: pydeps: "pdfplumber" - name: Verify AMD autogen is up to date run: | - python -m extra.assembly.amd.dsl --arch all - python -m extra.assembly.amd.pcode --arch all + python -m extra.assembly.amd.pdf --arch all git diff --exit-code extra/assembly/amd/autogen/ testnvidia: diff --git a/extra/assembly/amd/README b/extra/assembly/amd/README new file mode 100644 index 0000000000..11a88b62f1 --- /dev/null +++ b/extra/assembly/amd/README @@ -0,0 +1,43 @@ +An integrated environment for AMD GPU assembly and emulation + +Test with `PYTHONPATH="." pytest -n12 extra/assembly/amd/` +`AMD_LLVM=1 PYTHONPATH="." pytest -n12 extra/assembly/amd/` + +* pdf.py -- extract assembly format + instruction psuedocode from AMD PDF +* dsl.py -- helpers for the autogen instruction classes in `__init__.py`. should be standalone with init +* pcode.py -- psuedocode execution environment. psuedocode should be transformed as little as possible. +* asm.py -- an asm/disasm function to transform to and from AMD assembly syntax +* emu.py -- an emulator for RDNA that runs in tinygrad with `AMD=1 MOCKGPU=1 PYTHON_REMU=1` + +The code should be as readable and deduplicated as possible. asm and emu shouldn't be required for dsl. + +test_emu.py has a good set of instruction tests for the emulation, with USE_HW=1 it will compare to real hardware. +Whenever an instruction is fixed, regression tests should be added here and confirmed with real hardware. + +test_llvm.py tests asm/disasm on the LLVM tests, confirming it behaves the same as LLVM. + +tinygrad's dtype tests should pass with and without LLVM. they run in about 12 seconds. + +`PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=12 test/test_dtype_alu.py test/test_dtype.py` +`PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=12 test/test_dtype_alu.py test/test_dtype.py` + +The ops tests also mostly pass, but they are very slow, so you should run them one at a time. + +`SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=12 test/test_ops.py` +with failure +`FAILED test/test_ops.py::TestOps::test_avg_pool3d - Exception: forward pass failed shape (1, 1, 3, 3, 3):` + +`SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=12 test/test_ops.py` +with failures +``` +FAILED test/test_ops.py::TestOps::test_avg_pool3d - Exception: forward pass failed shape (1, 1, 3, 3, 3): +FAILED test/test_ops.py::TestOps::test_negative_padding_conv2d - Exception: backward pass tensor 0 failed shape (1, 1, 10, 10): +FAILED test/test_ops.py::TestOps::test_unfold - Exception: backward pass tensor 0 failed shape (8,): +FAILED test/test_ops.py::TestOps::test_avg_pool2d_ceil_mode - Exception: backward pass tensor 0 failed shape (1, 1, 6, 6): +``` + +TODO: make all ops tests pass and add local regression tests. + +When something is caught by main tinygrad tests, a local regression test should be added to `extra/assembly/amd/test`. While working with tinygrad, you can dump the assembly with `DEBUG=7`. These tests all pass on real hardware, so if a test is failing with `AMD=1 PYTHON_REMU=1 MOCKGPU=1` it's likely because an instruction is emulated incorrectly. You can test without `MOCKGPU=1` to test on real hardware, if it works on real hardware there's a bug in the emulator. + +Currently, only RDNA3 is well supported, but when finished, this will support RDNA3+RDNA4+CDNA in ~2000 lines. diff --git a/extra/assembly/amd/asm.py b/extra/assembly/amd/asm.py index 6b88eb336f..f983e94afb 100644 --- a/extra/assembly/amd/asm.py +++ b/extra/assembly/amd/asm.py @@ -1,8 +1,9 @@ # RDNA3 assembler and disassembler from __future__ import annotations import re -from extra.assembly.amd.dsl import Inst, RawImm, Reg, SrcMod, SGPR, VGPR, TTMP, s, v, ttmp, _RegFactory, FLOAT_ENC, SRC_FIELDS, unwrap +from extra.assembly.amd.dsl import Inst, RawImm, Reg, SrcMod, SGPR, VGPR, TTMP, s, v, ttmp, _RegFactory, SRC_FIELDS, unwrap from extra.assembly.amd.dsl import VCC_LO, VCC_HI, VCC, EXEC_LO, EXEC_HI, EXEC, SCC, M0, NULL, OFF +from extra.assembly.amd.dsl import SPECIAL_GPRS, SPECIAL_PAIRS, FLOAT_DEC, FLOAT_ENC, decode_src from extra.assembly.amd.autogen.rdna3 import VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, VOPD, VINTERP, SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, DS, FLAT, MUBUF, MTBUF, MIMG, EXP from extra.assembly.amd.autogen.rdna3 import VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, VOPDOp, VINTERPOp from extra.assembly.amd.autogen.rdna3 import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, SMEMOp, DSOp, FLATOp, MUBUFOp, MTBUFOp, MIMGOp @@ -10,46 +11,35 @@ from extra.assembly.amd.autogen.rdna3 import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOP # VOP3SD opcodes that share VOP3 encoding VOP3SD_OPS = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770} +def _matches_encoding(word: int, cls: type[Inst]) -> bool: + """Check if word matches the encoding pattern of an instruction class.""" + if cls._encoding is None: return False + bf, val = cls._encoding + return ((word >> bf.lo) & bf.mask()) == val + +# Order matters: more specific encodings first, VOP2 last (it's a catch-all for bit31=0) +_FORMATS_64 = [VOPD, VOP3P, VINTERP, VOP3, DS, FLAT, MUBUF, MTBUF, MIMG, SMEM, EXP] +_FORMATS_32 = [SOP1, SOPC, SOPP, SOPK, VOPC, VOP1, SOP2, VOP2] # SOP2/VOP2 are catch-alls + def detect_format(data: bytes) -> type[Inst]: """Detect instruction format from machine code bytes.""" assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}" word = int.from_bytes(data[:4], 'little') - hi2 = (word >> 30) & 0x3 - if hi2 == 0b11: - enc = (word >> 26) & 0xf - if enc == 0b0010: return VOPD - if enc == 0b0011: return VOP3P - if enc == 0b0100: return VINTERP - if enc == 0b0101: return VOP3SD if ((word >> 16) & 0x3ff) in VOP3SD_OPS else VOP3 - if enc == 0b0110: return DS - if enc == 0b0111: return FLAT - if enc == 0b1000: return MUBUF - if enc == 0b1010: return MTBUF - if enc == 0b1100 or enc == 0b1111: return MIMG - if enc == 0b1101: return SMEM - if enc == 0b1110: return EXP - raise ValueError(f"unknown 64-bit format enc={enc:#06b} word={word:#010x}") - if hi2 == 0b10: - enc = (word >> 23) & 0x7f - if enc == 0b1111101: return SOP1 - if enc == 0b1111110: return SOPC - if enc == 0b1111111: return SOPP - return SOPK if ((word >> 28) & 0xf) == 0b1011 else SOP2 - # hi2 == 0b00 or 0b01: VOP1/VOP2/VOPC (bit 31 = 0) - assert (word >> 31) == 0, f"expected bit 31 = 0 for VOP, got word={word:#010x}" - enc = (word >> 25) & 0x7f - if enc == 0b0111110: return VOPC - if enc == 0b0111111: return VOP1 - if enc <= 0b0111101: return VOP2 - raise ValueError(f"unknown VOP format enc={enc:#09b} word={word:#010x}") + # Check 64-bit formats first (bits[31:30] == 0b11) + if (word >> 30) == 0b11: + for cls in _FORMATS_64: + if _matches_encoding(word, cls): + return VOP3SD if cls is VOP3 and ((word >> 16) & 0x3ff) in VOP3SD_OPS else cls + raise ValueError(f"unknown 64-bit format word={word:#010x}") + # 32-bit formats + for cls in _FORMATS_32: + if _matches_encoding(word, cls): return cls + raise ValueError(f"unknown 32-bit format word={word:#010x}") # ═══════════════════════════════════════════════════════════════════════════════ # CONSTANTS # ═══════════════════════════════════════════════════════════════════════════════ -SPECIAL_GPRS = {106: "vcc_lo", 107: "vcc_hi", 124: "null", 125: "m0", 126: "exec_lo", 127: "exec_hi", 253: "scc"} -SPECIAL_DEC = {**SPECIAL_GPRS, **{v: str(k) for k, v in FLOAT_ENC.items()}} -SPECIAL_PAIRS = {106: "vcc", 126: "exec"} HWREG = {1: 'HW_REG_MODE', 2: 'HW_REG_STATUS', 3: 'HW_REG_TRAPSTS', 4: 'HW_REG_HW_ID', 5: 'HW_REG_GPR_ALLOC', 6: 'HW_REG_LDS_ALLOC', 7: 'HW_REG_IB_STS', 15: 'HW_REG_SH_MEM_BASES', 18: 'HW_REG_PERF_SNAPSHOT_PC_LO', 19: 'HW_REG_PERF_SNAPSHOT_PC_HI', 20: 'HW_REG_FLAT_SCR_LO', 21: 'HW_REG_FLAT_SCR_HI', 22: 'HW_REG_XNACK_MASK', @@ -57,42 +47,33 @@ HWREG = {1: 'HW_REG_MODE', 2: 'HW_REG_STATUS', 3: 'HW_REG_TRAPSTS', 4: 'HW_REG_H HWREG_IDS = {v.lower(): k for k, v in HWREG.items()} MSG = {128: 'MSG_RTN_GET_DOORBELL', 129: 'MSG_RTN_GET_DDID', 130: 'MSG_RTN_GET_TMA', 131: 'MSG_RTN_GET_REALTIME', 132: 'MSG_RTN_SAVE_WAVE', 133: 'MSG_RTN_GET_TBA'} -VOP3SD_OPS = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770} # ═══════════════════════════════════════════════════════════════════════════════ # HELPERS # ═══════════════════════════════════════════════════════════════════════════════ -def decode_src(val: int) -> str: - if val <= 105: return f"s{val}" - if val in SPECIAL_DEC: return SPECIAL_DEC[val] - if 108 <= val <= 123: return f"ttmp{val - 108}" - if 128 <= val <= 192: return str(val - 128) - if 193 <= val <= 208: return str(-(val - 192)) - if 256 <= val <= 511: return f"v{val - 256}" - return "lit" if val == 255 else f"?{val}" - def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{b}" if n == 1 else f"{p}[{b}:{b+n-1}]" def _sreg(b: int, n: int = 1) -> str: return _reg("s", b, n) def _vreg(b: int, n: int = 1) -> str: return _reg("v", b, n) -def _hl(v: int, hi_thresh: int = 128) -> str: return 'h' if v >= hi_thresh else 'l' +def _ttmp(b: int, n: int = 1) -> str: return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None +def _sreg_or_ttmp(b: int, n: int = 1) -> str: return _ttmp(b, n) or _sreg(b, n) def _fmt_sdst(v: int, n: int = 1) -> str: if v == 124: return "null" - if 108 <= v <= 123: return _reg("ttmp", v - 108, n) + if t := _ttmp(v, n): return t if n > 1: return SPECIAL_PAIRS.get(v) or _sreg(v, n) - return {126: "exec_lo", 127: "exec_hi", 106: "vcc_lo", 107: "vcc_hi", 125: "m0"}.get(v, f"s{v}") + return SPECIAL_GPRS.get(v, f"s{v}") def _fmt_src(v: int, n: int = 1) -> str: if n == 1: return decode_src(v) if v >= 256: return _vreg(v - 256, n) if v <= 105: return _sreg(v, n) if n == 2 and v in SPECIAL_PAIRS: return SPECIAL_PAIRS[v] - if 108 <= v <= 123: return _reg("ttmp", v - 108, n) + if t := _ttmp(v, n): return t return decode_src(v) def _fmt_v16(v: int, base: int = 256, hi_thresh: int = 384) -> str: - return f"v{(v - base) & 0x7f}.{_hl(v, hi_thresh)}" + return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}" def waitcnt(vmcnt: int = 0x3f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int: return (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10) @@ -101,6 +82,7 @@ def _has(op: str, *subs) -> bool: return any(s in op for s in subs) def _is16(op: str) -> bool: return _has(op, 'f16', 'i16', 'u16', 'b16') and not _has(op, '_f32', '_i32') def _is64(op: str) -> bool: return _has(op, 'f64', 'i64', 'u64', 'b64') def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "") +def _src16(inst, v: int) -> str: return _fmt_v16(v) if v >= 256 else inst.lit(v) # format 16-bit src: vgpr.h/l or literal def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c) def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]" @@ -123,40 +105,36 @@ def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str: # DISASSEMBLER # ═══════════════════════════════════════════════════════════════════════════════ +_VOP1_F64 = {VOP1Op.V_CEIL_F64, VOP1Op.V_FLOOR_F64, VOP1Op.V_FRACT_F64, VOP1Op.V_FREXP_MANT_F64, VOP1Op.V_RCP_F64, VOP1Op.V_RNDNE_F64, VOP1Op.V_RSQ_F64, VOP1Op.V_SQRT_F64, VOP1Op.V_TRUNC_F64} + def _disasm_vop1(inst: VOP1) -> str: - op = VOP1Op(inst.op) - if op in (VOP1Op.V_NOP, VOP1Op.V_PIPEFLUSH): return op.name.lower() - F64_OPS = {VOP1Op.V_CEIL_F64, VOP1Op.V_FLOOR_F64, VOP1Op.V_FRACT_F64, VOP1Op.V_FREXP_MANT_F64, VOP1Op.V_RCP_F64, VOP1Op.V_RNDNE_F64, VOP1Op.V_RSQ_F64, VOP1Op.V_SQRT_F64, VOP1Op.V_TRUNC_F64} - is_f64_d = op in F64_OPS or op in (VOP1Op.V_CVT_F64_F32, VOP1Op.V_CVT_F64_I32, VOP1Op.V_CVT_F64_U32) - is_f64_s = op in F64_OPS or op in (VOP1Op.V_CVT_F32_F64, VOP1Op.V_CVT_I32_F64, VOP1Op.V_CVT_U32_F64, VOP1Op.V_FREXP_EXP_I32_F64) - name = op.name.lower() - parts = name.split('_') + op, name = VOP1Op(inst.op), VOP1Op(inst.op).name.lower() + if op in (VOP1Op.V_NOP, VOP1Op.V_PIPEFLUSH): return name + if op == VOP1Op.V_READFIRSTLANE_B32: return f"v_readfirstlane_b32 {decode_src(inst.vdst)}, v{inst.src0 - 256 if inst.src0 >= 256 else inst.src0}" + parts, is_f64_d = name.split('_'), op in _VOP1_F64 or op in (VOP1Op.V_CVT_F64_F32, VOP1Op.V_CVT_F64_I32, VOP1Op.V_CVT_F64_U32) + is_f64_s = op in _VOP1_F64 or op in (VOP1Op.V_CVT_F32_F64, VOP1Op.V_CVT_I32_F64, VOP1Op.V_CVT_U32_F64, VOP1Op.V_FREXP_EXP_I32_F64) is_16d = any(p in ('f16','i16','u16','b16') for p in parts[-2:-1]) or (len(parts) >= 2 and parts[-1] in ('f16','i16','u16','b16') and 'cvt' not in name) is_16s = parts[-1] in ('f16','i16','u16','b16') and 'sat_pk' not in name - if op == VOP1Op.V_READFIRSTLANE_B32: return f"v_readfirstlane_b32 {decode_src(inst.vdst)}, v{inst.src0 - 256 if inst.src0 >= 256 else inst.src0}" dst = _vreg(inst.vdst, 2) if is_f64_d else _fmt_v16(inst.vdst, 0, 128) if is_16d else f"v{inst.vdst}" - src = _fmt_src(inst.src0, 2) if is_f64_s else _fmt_v16(inst.src0) if is_16s and inst.src0 >= 256 else inst.lit(inst.src0) + src = _fmt_src(inst.src0, 2) if is_f64_s else _src16(inst, inst.src0) if is_16s else inst.lit(inst.src0) return f"{name}_e32 {dst}, {src}" def _disasm_vop2(inst: VOP2) -> str: - op = VOP2Op(inst.op) - name = op.name.lower() - suf = "" if op == VOP2Op.V_DOT2ACC_F32_F16 else "_e32" - is16 = _is16(name) and 'pk_' not in name + op, name = VOP2Op(inst.op), VOP2Op(inst.op).name.lower() + suf, is16 = "" if op == VOP2Op.V_DOT2ACC_F32_F16 else "_e32", _is16(name) and 'pk_' not in name # fmaak: dst = src0 * vsrc1 + K, fmamk: dst = src0 * K + vsrc1 if op in (VOP2Op.V_FMAAK_F32, VOP2Op.V_FMAAK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}, 0x{inst._literal:x}" if op in (VOP2Op.V_FMAMK_F32, VOP2Op.V_FMAMK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, 0x{inst._literal:x}, v{inst.vsrc1}" - if is16: return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_fmt_v16(inst.src0) if inst.src0 >= 256 else inst.lit(inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}" + if is16: return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}" return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}" + (", vcc_lo" if op == VOP2Op.V_CNDMASK_B32 else "") VOPC_CLASS = {VOPCOp.V_CMP_CLASS_F16, VOPCOp.V_CMP_CLASS_F32, VOPCOp.V_CMP_CLASS_F64, VOPCOp.V_CMPX_CLASS_F16, VOPCOp.V_CMPX_CLASS_F32, VOPCOp.V_CMPX_CLASS_F64} def _disasm_vopc(inst: VOPC) -> str: - op = VOPCOp(inst.op) - name = op.name.lower() + op, name = VOPCOp(inst.op), VOPCOp(inst.op).name.lower() is64, is16 = _is64(name), _is16(name) - s0 = _fmt_src(inst.src0, 2) if is64 else _fmt_v16(inst.src0) if is16 and inst.src0 >= 256 else inst.lit(inst.src0) + s0 = _fmt_src(inst.src0, 2) if is64 else _src16(inst, inst.src0) if is16 else inst.lit(inst.src0) s1 = _vreg(inst.vsrc1, 2) if is64 and op not in VOPC_CLASS else _fmt_v16(inst.vsrc1, 0, 128) if is16 else f"v{inst.vsrc1}" return f"{name}_e32 {s0}, {s1}" if op.value >= 128 else f"{name}_e32 vcc_lo, {s0}, {s1}" @@ -204,7 +182,7 @@ def _disasm_flat(inst: FLAT) -> str: elif inst.saddr == 124: saddr_s = ", off" elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr)}" elif inst.saddr in SPECIAL_PAIRS: saddr_s = f", {SPECIAL_PAIRS[inst.saddr]}" - elif 108 <= inst.saddr <= 123: saddr_s = f", {_reg('ttmp', inst.saddr - 108, 2)}" + elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}" else: saddr_s = f", {_sreg(inst.saddr, 2) if inst.saddr < 106 else decode_src(inst.saddr)}" # addtid: no addr if 'addtid' in name: return f"{instr} v{inst.data if 'store' in name else inst.vdst}{saddr_s}{mods}" @@ -351,7 +329,7 @@ def _disasm_buf(inst: MUBUF | MTBUF) -> str: {'b32':1,'b64':2,'b96':3,'b128':4,'b16':1,'x':1,'xy':2,'xyz':3,'xyzw':4}.get(name.split('_')[-1], 1) if inst.tfe: w += 1 vaddr = _vreg(inst.vaddr, 2) if inst.offen and inst.idxen else f"v{inst.vaddr}" if inst.offen or inst.idxen else "off" - srsrc = _reg("ttmp", inst.srsrc*4 - 108, 4) if 108 <= inst.srsrc*4 <= 123 else _sreg(inst.srsrc*4, 4) + srsrc = _sreg_or_ttmp(inst.srsrc*4, 4) mods = ([f"format:{inst.format}"] if isinstance(inst, MTBUF) else []) + [m for c, m in [(inst.idxen,"idxen"),(inst.offen,"offen"),(inst.offset,f"offset:{inst.offset}"),(inst.glc,"glc"),(inst.dlc,"dlc"),(inst.slc,"slc"),(inst.tfe,"tfe")] if c] return f"{name} {_vreg(inst.vdata, w)}, {vaddr}, {srsrc}, {decode_src(inst.soffset)}{' ' + ' '.join(mods) if mods else ''}" @@ -375,12 +353,11 @@ def _mimg_vaddr_width(name: str, dim: int, a16: bool) -> int: def _disasm_mimg(inst: MIMG) -> str: name = MIMGOp(inst.op).name.lower() srsrc_base = inst.srsrc * 4 - srsrc_str = _reg("ttmp", srsrc_base - 108, 8) if 108 <= srsrc_base <= 123 else _sreg(srsrc_base, 8) + srsrc_str = _sreg_or_ttmp(srsrc_base, 8) # BVH intersect ray: special case with 4 SGPR srsrc if 'bvh' in name: vaddr = (9 if '64' in name else 8) if inst.a16 else (12 if '64' in name else 11) - srsrc = _reg("ttmp", srsrc_base - 108, 4) if 108 <= srsrc_base <= 123 else _sreg(srsrc_base, 4) - return f"{name} {_vreg(inst.vdata, 4)}, {_vreg(inst.vaddr, vaddr)}, {srsrc}{' a16' if inst.a16 else ''}" + return f"{name} {_vreg(inst.vdata, 4)}, {_vreg(inst.vaddr, vaddr)}, {_sreg_or_ttmp(srsrc_base, 4)}{' a16' if inst.a16 else ''}" # vdata width from dmask (gather4/msaa_load always 4), d16 packs, tfe adds 1 vdata = 4 if 'gather4' in name or 'msaa_load' in name else (bin(inst.dmask).count('1') or 1) if inst.d16: vdata = (vdata + 1) // 2 @@ -399,8 +376,7 @@ def _disasm_mimg(inst: MIMG) -> str: # ssamp for sample/gather/get_lod ssamp_str = "" if 'sample' in name or 'gather' in name or 'get_lod' in name: - ssamp_base = inst.ssamp * 4 - ssamp_str = ", " + (_reg("ttmp", ssamp_base - 108, 4) if 108 <= ssamp_base <= 123 else _sreg(ssamp_base, 4)) + ssamp_str = ", " + _sreg_or_ttmp(inst.ssamp * 4, 4) return f"{name} {_vreg(inst.vdata, vdata)}, {vaddr_str}, {srsrc_str}{ssamp_str} {' '.join(mods)}" def _sop_widths(name: str) -> tuple[int, int, int]: @@ -470,7 +446,7 @@ def disasm(inst: Inst) -> str: return DISASM_HANDLERS.get(type(inst), _disasm_ge SPEC_REGS = {'vcc_lo': RawImm(106), 'vcc_hi': RawImm(107), 'vcc': RawImm(106), 'null': RawImm(124), 'off': RawImm(124), 'm0': RawImm(125), 'exec_lo': RawImm(126), 'exec_hi': RawImm(127), 'exec': RawImm(126), 'scc': RawImm(253), 'src_scc': RawImm(253)} -FLOATS = {'0.5': 0.5, '-0.5': -0.5, '1.0': 1.0, '-1.0': -1.0, '2.0': 2.0, '-2.0': -2.0, '4.0': 4.0, '-4.0': -4.0} +FLOATS = {str(k): k for k in FLOAT_ENC} # Valid float literal strings: '0.5', '-0.5', '1.0', etc. REG_MAP: dict[str, _RegFactory] = {'s': s, 'v': v, 't': ttmp, 'ttmp': ttmp} SMEM_OPS = {'s_load_b32', 's_load_b64', 's_load_b128', 's_load_b256', 's_load_b512', 's_buffer_load_b32', 's_buffer_load_b64', 's_buffer_load_b128', 's_buffer_load_b256', 's_buffer_load_b512'} diff --git a/extra/assembly/amd/autogen/cdna/__init__.py b/extra/assembly/amd/autogen/cdna/__init__.py index 416e4b9ac8..8ac6b7e358 100644 --- a/extra/assembly/amd/autogen/cdna/__init__.py +++ b/extra/assembly/amd/autogen/cdna/__init__.py @@ -1,4 +1,4 @@ -# autogenerated from AMD CDNA3+CDNA4 ISA PDF by dsl.py - do not edit +# autogenerated from AMD CDNA3+CDNA4 ISA PDF by pdf.py - do not edit from enum import IntEnum from typing import Annotated from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField diff --git a/extra/assembly/amd/autogen/cdna/gen_pcode.py b/extra/assembly/amd/autogen/cdna/gen_pcode.py index e95ab11713..8f7fdbcf5a 100644 --- a/extra/assembly/amd/autogen/cdna/gen_pcode.py +++ b/extra/assembly/amd/autogen/cdna/gen_pcode.py @@ -1,5 +1,5 @@ -# autogenerated by pcode.py - do not edit -# to regenerate: python -m extra.assembly.amd.pcode --arch cdna +# autogenerated by pdf.py - do not edit +# to regenerate: python -m extra.assembly.amd.pdf --arch cdna # ruff: noqa: E501,F405,F403 # mypy: ignore-errors from extra.assembly.amd.autogen.cdna import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3POp, VOPCOp, VOP3AOp, VOP3BOp @@ -490,7 +490,7 @@ def _SOP1Op_S_GETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -502,7 +502,7 @@ def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -520,7 +520,7 @@ def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -532,7 +532,7 @@ def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_AND_SAVEEXEC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2182,7 +2182,7 @@ def _SOPKOp_S_CALL_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result SOPKOp_FUNCTIONS = { @@ -2225,7 +2225,7 @@ def _SOPPOp_S_BRANCH(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _ # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2245,7 +2245,7 @@ def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2265,7 +2265,7 @@ def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2288,7 +2288,7 @@ def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2311,7 +2311,7 @@ def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2333,7 +2333,7 @@ def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2355,7 +2355,7 @@ def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_TRAP(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2368,7 +2368,7 @@ def _SOPPOp_S_TRAP(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _va # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2387,7 +2387,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGUSER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2406,7 +2406,7 @@ def _SOPPOp_S_CBRANCH_CDBGUSER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, litera # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS_OR_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2425,7 +2425,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS_OR_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS_AND_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -2444,7 +2444,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS_AND_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_SET_GPR_IDX_MODE(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3886,24 +3886,6 @@ def _VOP2Op_V_XOR_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} return result -def _VOP2Op_V_DOT2C_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp = D0.f32; - # tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16); - # tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16); - # D0.f32 = tmp - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp = Reg(D0.f32) - tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16) - tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16) - D0.f32 = tmp - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - def _VOP2Op_V_FMAMK_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): # D0.f32 = fma(S0.f32, SIMM32.f32, S1.f32) S0 = Reg(s0) @@ -4505,6 +4487,24 @@ def _VOP2Op_V_XNOR_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} return result +def _VOP2Op_V_DOT2C_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp = D0.f32; + # tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16); + # tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16); + # D0.f32 = tmp + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(D0.f32) + tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16) + tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16) + D0.f32 = tmp + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + VOP2Op_FUNCTIONS = { VOP2Op.V_CNDMASK_B32: _VOP2Op_V_CNDMASK_B32, VOP2Op.V_ADD_F32: _VOP2Op_V_ADD_F32, @@ -4528,7 +4528,6 @@ VOP2Op_FUNCTIONS = { VOP2Op.V_AND_B32: _VOP2Op_V_AND_B32, VOP2Op.V_OR_B32: _VOP2Op_V_OR_B32, VOP2Op.V_XOR_B32: _VOP2Op_V_XOR_B32, - VOP2Op.V_DOT2C_F32_BF16: _VOP2Op_V_DOT2C_F32_BF16, VOP2Op.V_FMAMK_F32: _VOP2Op_V_FMAMK_F32, VOP2Op.V_FMAAK_F32: _VOP2Op_V_FMAAK_F32, VOP2Op.V_ADD_CO_U32: _VOP2Op_V_ADD_CO_U32, @@ -4568,6 +4567,7 @@ VOP2Op_FUNCTIONS = { VOP2Op.V_FMAC_F32: _VOP2Op_V_FMAC_F32, VOP2Op.V_PK_FMAC_F16: _VOP2Op_V_PK_FMAC_F16, VOP2Op.V_XNOR_B32: _VOP2Op_V_XNOR_B32, + VOP2Op.V_DOT2C_F32_BF16: _VOP2Op_V_DOT2C_F32_BF16, } def _VOP3POp_V_PK_MAD_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -4892,59 +4892,6 @@ def _VOP3POp_V_PK_MAX_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result = {'d0': D0._val, 'scc': scc & 1} return result -def _VOP3POp_V_DOT2_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp = 32'F(S0[15 : 0].bf16) * 32'F(S1[15 : 0].bf16); - # tmp += 32'F(S0[31 : 16].bf16) * 32'F(S1[31 : 16].bf16); - # tmp += S2.f32; - # D0.f32 = tmp - S0 = Reg(s0) - S1 = Reg(s1) - S2 = Reg(s2) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp = Reg(F(S0[15 : 0].bf16) * F(S1[15 : 0].bf16)) - tmp += F(S0[31 : 16].bf16) * F(S1[31 : 16].bf16) - tmp += S2.f32 - D0.f32 = tmp - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3POp_V_PK_MINIMUM3_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp[31 : 16].f16 = 16'F(v_minimum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)); - # tmp[15 : 0].f16 = 16'F(v_minimum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)); - # D0.b32 = tmp.b32 - S0 = Reg(s0) - S1 = Reg(s1) - S2 = Reg(s2) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[31 : 16].f16 = F(v_minimum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)) - tmp[15 : 0].f16 = F(v_minimum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)) - D0.b32 = tmp.b32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3POp_V_PK_MAXIMUM3_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp[31 : 16].f16 = 16'F(v_maximum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)); - # tmp[15 : 0].f16 = 16'F(v_maximum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)); - # D0.b32 = tmp.b32 - S0 = Reg(s0) - S1 = Reg(s1) - S2 = Reg(s2) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[31 : 16].f16 = F(v_maximum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)) - tmp[15 : 0].f16 = F(v_maximum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)) - D0.b32 = tmp.b32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - def _VOP3POp_V_DOT2_F32_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): # tmp = S2.f32; # tmp += f16_to_f32(S0[15 : 0].f16) * f16_to_f32(S1[15 : 0].f16); @@ -5183,6 +5130,59 @@ def _VOP3POp_V_PK_MOV_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result = {'d0': D0._val, 'scc': scc & 1} return result +def _VOP3POp_V_DOT2_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp = 32'F(S0[15 : 0].bf16) * 32'F(S1[15 : 0].bf16); + # tmp += 32'F(S0[31 : 16].bf16) * 32'F(S1[31 : 16].bf16); + # tmp += S2.f32; + # D0.f32 = tmp + S0 = Reg(s0) + S1 = Reg(s1) + S2 = Reg(s2) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(F(S0[15 : 0].bf16) * F(S1[15 : 0].bf16)) + tmp += F(S0[31 : 16].bf16) * F(S1[31 : 16].bf16) + tmp += S2.f32 + D0.f32 = tmp + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3POp_V_PK_MINIMUM3_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp[31 : 16].f16 = 16'F(v_minimum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)); + # tmp[15 : 0].f16 = 16'F(v_minimum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)); + # D0.b32 = tmp.b32 + S0 = Reg(s0) + S1 = Reg(s1) + S2 = Reg(s2) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[31 : 16].f16 = F(v_minimum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)) + tmp[15 : 0].f16 = F(v_minimum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)) + D0.b32 = tmp.b32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3POp_V_PK_MAXIMUM3_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp[31 : 16].f16 = 16'F(v_maximum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)); + # tmp[15 : 0].f16 = 16'F(v_maximum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)); + # D0.b32 = tmp.b32 + S0 = Reg(s0) + S1 = Reg(s1) + S2 = Reg(s2) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[31 : 16].f16 = F(v_maximum3_f16(S0[31 : 16].f16, S1[31 : 16].f16, S2[31 : 16].f16)) + tmp[15 : 0].f16 = F(v_maximum3_f16(S0[15 : 0].f16, S1[15 : 0].f16, S2[15 : 0].f16)) + D0.b32 = tmp.b32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + VOP3POp_FUNCTIONS = { VOP3POp.V_PK_MAD_I16: _VOP3POp_V_PK_MAD_I16, VOP3POp.V_PK_MUL_LO_U16: _VOP3POp_V_PK_MUL_LO_U16, @@ -5203,9 +5203,6 @@ VOP3POp_FUNCTIONS = { VOP3POp.V_PK_MUL_F16: _VOP3POp_V_PK_MUL_F16, VOP3POp.V_PK_MIN_F16: _VOP3POp_V_PK_MIN_F16, VOP3POp.V_PK_MAX_F16: _VOP3POp_V_PK_MAX_F16, - VOP3POp.V_DOT2_F32_BF16: _VOP3POp_V_DOT2_F32_BF16, - VOP3POp.V_PK_MINIMUM3_F16: _VOP3POp_V_PK_MINIMUM3_F16, - VOP3POp.V_PK_MAXIMUM3_F16: _VOP3POp_V_PK_MAXIMUM3_F16, VOP3POp.V_DOT2_F32_F16: _VOP3POp_V_DOT2_F32_F16, VOP3POp.V_DOT2_I32_I16: _VOP3POp_V_DOT2_I32_I16, VOP3POp.V_DOT2_U32_U16: _VOP3POp_V_DOT2_U32_U16, @@ -5217,6 +5214,9 @@ VOP3POp_FUNCTIONS = { VOP3POp.V_PK_MUL_F32: _VOP3POp_V_PK_MUL_F32, VOP3POp.V_PK_ADD_F32: _VOP3POp_V_PK_ADD_F32, VOP3POp.V_PK_MOV_B32: _VOP3POp_V_PK_MOV_B32, + VOP3POp.V_DOT2_F32_BF16: _VOP3POp_V_DOT2_F32_BF16, + VOP3POp.V_PK_MINIMUM3_F16: _VOP3POp_V_PK_MINIMUM3_F16, + VOP3POp.V_PK_MAXIMUM3_F16: _VOP3POp_V_PK_MAXIMUM3_F16, } def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5277,7 +5277,7 @@ def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5395,7 +5395,7 @@ def _VOPCOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5513,7 +5513,7 @@ def _VOPCOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5589,7 +5589,7 @@ def _VOPCOp_V_CMP_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5610,7 +5610,7 @@ def _VOPCOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5631,7 +5631,7 @@ def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5651,7 +5651,7 @@ def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5672,7 +5672,7 @@ def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5692,7 +5692,7 @@ def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5712,7 +5712,7 @@ def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5733,7 +5733,7 @@ def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5754,7 +5754,7 @@ def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5775,7 +5775,7 @@ def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5796,7 +5796,7 @@ def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5818,7 +5818,7 @@ def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5839,7 +5839,7 @@ def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5861,7 +5861,7 @@ def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5883,7 +5883,7 @@ def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5902,7 +5902,7 @@ def _VOPCOp_V_CMP_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5923,7 +5923,7 @@ def _VOPCOp_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5946,7 +5946,7 @@ def _VOPCOp_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5969,7 +5969,7 @@ def _VOPCOp_V_CMPX_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5991,7 +5991,7 @@ def _VOPCOp_V_CMPX_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6014,7 +6014,7 @@ def _VOPCOp_V_CMPX_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6036,7 +6036,7 @@ def _VOPCOp_V_CMPX_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6058,7 +6058,7 @@ def _VOPCOp_V_CMPX_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6081,7 +6081,7 @@ def _VOPCOp_V_CMPX_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6103,7 +6103,7 @@ def _VOPCOp_V_CMPX_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6126,7 +6126,7 @@ def _VOPCOp_V_CMPX_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6149,7 +6149,7 @@ def _VOPCOp_V_CMPX_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6172,7 +6172,7 @@ def _VOPCOp_V_CMPX_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6195,7 +6195,7 @@ def _VOPCOp_V_CMPX_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6219,7 +6219,7 @@ def _VOPCOp_V_CMPX_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6243,7 +6243,7 @@ def _VOPCOp_V_CMPX_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6264,7 +6264,7 @@ def _VOPCOp_V_CMPX_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6283,7 +6283,7 @@ def _VOPCOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6304,7 +6304,7 @@ def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6325,7 +6325,7 @@ def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6345,7 +6345,7 @@ def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6366,7 +6366,7 @@ def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6386,7 +6386,7 @@ def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6406,7 +6406,7 @@ def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6427,7 +6427,7 @@ def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6448,7 +6448,7 @@ def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6469,7 +6469,7 @@ def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6490,7 +6490,7 @@ def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6512,7 +6512,7 @@ def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6533,7 +6533,7 @@ def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6555,7 +6555,7 @@ def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6577,7 +6577,7 @@ def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6596,7 +6596,7 @@ def _VOPCOp_V_CMP_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6617,7 +6617,7 @@ def _VOPCOp_V_CMPX_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6640,7 +6640,7 @@ def _VOPCOp_V_CMPX_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6663,7 +6663,7 @@ def _VOPCOp_V_CMPX_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6685,7 +6685,7 @@ def _VOPCOp_V_CMPX_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6708,7 +6708,7 @@ def _VOPCOp_V_CMPX_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6730,7 +6730,7 @@ def _VOPCOp_V_CMPX_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6752,7 +6752,7 @@ def _VOPCOp_V_CMPX_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6775,7 +6775,7 @@ def _VOPCOp_V_CMPX_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6797,7 +6797,7 @@ def _VOPCOp_V_CMPX_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6820,7 +6820,7 @@ def _VOPCOp_V_CMPX_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6843,7 +6843,7 @@ def _VOPCOp_V_CMPX_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6866,7 +6866,7 @@ def _VOPCOp_V_CMPX_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6889,7 +6889,7 @@ def _VOPCOp_V_CMPX_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6913,7 +6913,7 @@ def _VOPCOp_V_CMPX_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6937,7 +6937,7 @@ def _VOPCOp_V_CMPX_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6958,7 +6958,7 @@ def _VOPCOp_V_CMPX_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6977,7 +6977,7 @@ def _VOPCOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6998,7 +6998,7 @@ def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7019,7 +7019,7 @@ def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7039,7 +7039,7 @@ def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7060,7 +7060,7 @@ def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7080,7 +7080,7 @@ def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7100,7 +7100,7 @@ def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7121,7 +7121,7 @@ def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7142,7 +7142,7 @@ def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7163,7 +7163,7 @@ def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7184,7 +7184,7 @@ def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7206,7 +7206,7 @@ def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7227,7 +7227,7 @@ def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7249,7 +7249,7 @@ def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7271,7 +7271,7 @@ def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7290,7 +7290,7 @@ def _VOPCOp_V_CMP_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7311,7 +7311,7 @@ def _VOPCOp_V_CMPX_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7334,7 +7334,7 @@ def _VOPCOp_V_CMPX_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7357,7 +7357,7 @@ def _VOPCOp_V_CMPX_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7379,7 +7379,7 @@ def _VOPCOp_V_CMPX_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7402,7 +7402,7 @@ def _VOPCOp_V_CMPX_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7424,7 +7424,7 @@ def _VOPCOp_V_CMPX_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7446,7 +7446,7 @@ def _VOPCOp_V_CMPX_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7469,7 +7469,7 @@ def _VOPCOp_V_CMPX_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7491,7 +7491,7 @@ def _VOPCOp_V_CMPX_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7514,7 +7514,7 @@ def _VOPCOp_V_CMPX_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7537,7 +7537,7 @@ def _VOPCOp_V_CMPX_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7560,7 +7560,7 @@ def _VOPCOp_V_CMPX_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7583,7 +7583,7 @@ def _VOPCOp_V_CMPX_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7607,7 +7607,7 @@ def _VOPCOp_V_CMPX_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7631,7 +7631,7 @@ def _VOPCOp_V_CMPX_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7652,7 +7652,7 @@ def _VOPCOp_V_CMPX_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7671,7 +7671,7 @@ def _VOPCOp_V_CMP_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7692,7 +7692,7 @@ def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7713,7 +7713,7 @@ def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7733,7 +7733,7 @@ def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7754,7 +7754,7 @@ def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7775,7 +7775,7 @@ def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7795,7 +7795,7 @@ def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7814,7 +7814,7 @@ def _VOPCOp_V_CMP_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7833,7 +7833,7 @@ def _VOPCOp_V_CMP_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7854,7 +7854,7 @@ def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7875,7 +7875,7 @@ def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7895,7 +7895,7 @@ def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7916,7 +7916,7 @@ def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7937,7 +7937,7 @@ def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7957,7 +7957,7 @@ def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7976,7 +7976,7 @@ def _VOPCOp_V_CMP_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7997,7 +7997,7 @@ def _VOPCOp_V_CMPX_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8020,7 +8020,7 @@ def _VOPCOp_V_CMPX_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8043,7 +8043,7 @@ def _VOPCOp_V_CMPX_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8065,7 +8065,7 @@ def _VOPCOp_V_CMPX_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8088,7 +8088,7 @@ def _VOPCOp_V_CMPX_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8111,7 +8111,7 @@ def _VOPCOp_V_CMPX_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8133,7 +8133,7 @@ def _VOPCOp_V_CMPX_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8154,7 +8154,7 @@ def _VOPCOp_V_CMPX_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8175,7 +8175,7 @@ def _VOPCOp_V_CMPX_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8198,7 +8198,7 @@ def _VOPCOp_V_CMPX_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8221,7 +8221,7 @@ def _VOPCOp_V_CMPX_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8243,7 +8243,7 @@ def _VOPCOp_V_CMPX_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8266,7 +8266,7 @@ def _VOPCOp_V_CMPX_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8289,7 +8289,7 @@ def _VOPCOp_V_CMPX_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8311,7 +8311,7 @@ def _VOPCOp_V_CMPX_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8332,7 +8332,7 @@ def _VOPCOp_V_CMPX_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8351,7 +8351,7 @@ def _VOPCOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8372,7 +8372,7 @@ def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8393,7 +8393,7 @@ def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8413,7 +8413,7 @@ def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8434,7 +8434,7 @@ def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8455,7 +8455,7 @@ def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8475,7 +8475,7 @@ def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8494,7 +8494,7 @@ def _VOPCOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8513,7 +8513,7 @@ def _VOPCOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8534,7 +8534,7 @@ def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8555,7 +8555,7 @@ def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8575,7 +8575,7 @@ def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8596,7 +8596,7 @@ def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8617,7 +8617,7 @@ def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8637,7 +8637,7 @@ def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8656,7 +8656,7 @@ def _VOPCOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8677,7 +8677,7 @@ def _VOPCOp_V_CMPX_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8700,7 +8700,7 @@ def _VOPCOp_V_CMPX_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8723,7 +8723,7 @@ def _VOPCOp_V_CMPX_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8745,7 +8745,7 @@ def _VOPCOp_V_CMPX_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8768,7 +8768,7 @@ def _VOPCOp_V_CMPX_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8791,7 +8791,7 @@ def _VOPCOp_V_CMPX_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8813,7 +8813,7 @@ def _VOPCOp_V_CMPX_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8834,7 +8834,7 @@ def _VOPCOp_V_CMPX_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8855,7 +8855,7 @@ def _VOPCOp_V_CMPX_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8878,7 +8878,7 @@ def _VOPCOp_V_CMPX_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8901,7 +8901,7 @@ def _VOPCOp_V_CMPX_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8923,7 +8923,7 @@ def _VOPCOp_V_CMPX_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8946,7 +8946,7 @@ def _VOPCOp_V_CMPX_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8969,7 +8969,7 @@ def _VOPCOp_V_CMPX_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -8991,7 +8991,7 @@ def _VOPCOp_V_CMPX_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9012,7 +9012,7 @@ def _VOPCOp_V_CMPX_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9031,7 +9031,7 @@ def _VOPCOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9052,7 +9052,7 @@ def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9073,7 +9073,7 @@ def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9093,7 +9093,7 @@ def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9114,7 +9114,7 @@ def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9135,7 +9135,7 @@ def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9155,7 +9155,7 @@ def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9174,7 +9174,7 @@ def _VOPCOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9193,7 +9193,7 @@ def _VOPCOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9214,7 +9214,7 @@ def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9235,7 +9235,7 @@ def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9255,7 +9255,7 @@ def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9276,7 +9276,7 @@ def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9297,7 +9297,7 @@ def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9317,7 +9317,7 @@ def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9336,7 +9336,7 @@ def _VOPCOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9357,7 +9357,7 @@ def _VOPCOp_V_CMPX_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9380,7 +9380,7 @@ def _VOPCOp_V_CMPX_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9403,7 +9403,7 @@ def _VOPCOp_V_CMPX_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9425,7 +9425,7 @@ def _VOPCOp_V_CMPX_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9448,7 +9448,7 @@ def _VOPCOp_V_CMPX_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9471,7 +9471,7 @@ def _VOPCOp_V_CMPX_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9493,7 +9493,7 @@ def _VOPCOp_V_CMPX_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9514,7 +9514,7 @@ def _VOPCOp_V_CMPX_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9535,7 +9535,7 @@ def _VOPCOp_V_CMPX_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9558,7 +9558,7 @@ def _VOPCOp_V_CMPX_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9581,7 +9581,7 @@ def _VOPCOp_V_CMPX_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9603,7 +9603,7 @@ def _VOPCOp_V_CMPX_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9626,7 +9626,7 @@ def _VOPCOp_V_CMPX_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9649,7 +9649,7 @@ def _VOPCOp_V_CMPX_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9671,7 +9671,7 @@ def _VOPCOp_V_CMPX_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -9684,9 +9684,6 @@ def _VOPCOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP # tmp = MEM[addr].u32; # addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); # tmp = MEM[addr].u32; - # addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); - # tmp = MEM[addr].u32; - # src = DATA.u32; D0 = Reg(d0) VCC = Reg(vcc) EXEC = Reg(exec_mask) @@ -9701,9 +9698,6 @@ def _VOPCOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP tmp = Reg(MEM[addr].u32) addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - src = DATA.u32 # --- end pseudocode --- result = {'d0': D0._val, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 @@ -9711,7 +9705,7 @@ def _VOPCOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result VOPCOp_FUNCTIONS = { @@ -9972,7 +9966,7 @@ def _VOP3AOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10088,7 +10082,7 @@ def _VOP3AOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10204,7 +10198,7 @@ def _VOP3AOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10278,7 +10272,7 @@ def _VOP3AOp_V_CMP_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10298,7 +10292,7 @@ def _VOP3AOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10318,7 +10312,7 @@ def _VOP3AOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10337,7 +10331,7 @@ def _VOP3AOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10357,7 +10351,7 @@ def _VOP3AOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10376,7 +10370,7 @@ def _VOP3AOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10395,7 +10389,7 @@ def _VOP3AOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10415,7 +10409,7 @@ def _VOP3AOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10435,7 +10429,7 @@ def _VOP3AOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10455,7 +10449,7 @@ def _VOP3AOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10475,7 +10469,7 @@ def _VOP3AOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10496,7 +10490,7 @@ def _VOP3AOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10516,7 +10510,7 @@ def _VOP3AOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10537,7 +10531,7 @@ def _VOP3AOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10558,7 +10552,7 @@ def _VOP3AOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10576,7 +10570,7 @@ def _VOP3AOp_V_CMP_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10596,7 +10590,7 @@ def _VOP3AOp_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10618,7 +10612,7 @@ def _VOP3AOp_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10640,7 +10634,7 @@ def _VOP3AOp_V_CMPX_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10661,7 +10655,7 @@ def _VOP3AOp_V_CMPX_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10683,7 +10677,7 @@ def _VOP3AOp_V_CMPX_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10704,7 +10698,7 @@ def _VOP3AOp_V_CMPX_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10725,7 +10719,7 @@ def _VOP3AOp_V_CMPX_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10747,7 +10741,7 @@ def _VOP3AOp_V_CMPX_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10768,7 +10762,7 @@ def _VOP3AOp_V_CMPX_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10790,7 +10784,7 @@ def _VOP3AOp_V_CMPX_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10812,7 +10806,7 @@ def _VOP3AOp_V_CMPX_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10834,7 +10828,7 @@ def _VOP3AOp_V_CMPX_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10856,7 +10850,7 @@ def _VOP3AOp_V_CMPX_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10879,7 +10873,7 @@ def _VOP3AOp_V_CMPX_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10902,7 +10896,7 @@ def _VOP3AOp_V_CMPX_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10922,7 +10916,7 @@ def _VOP3AOp_V_CMPX_TRU_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10940,7 +10934,7 @@ def _VOP3AOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10960,7 +10954,7 @@ def _VOP3AOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10980,7 +10974,7 @@ def _VOP3AOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -10999,7 +10993,7 @@ def _VOP3AOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11019,7 +11013,7 @@ def _VOP3AOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11038,7 +11032,7 @@ def _VOP3AOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11057,7 +11051,7 @@ def _VOP3AOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11077,7 +11071,7 @@ def _VOP3AOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11097,7 +11091,7 @@ def _VOP3AOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11117,7 +11111,7 @@ def _VOP3AOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11137,7 +11131,7 @@ def _VOP3AOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11158,7 +11152,7 @@ def _VOP3AOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11178,7 +11172,7 @@ def _VOP3AOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11199,7 +11193,7 @@ def _VOP3AOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11220,7 +11214,7 @@ def _VOP3AOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11238,7 +11232,7 @@ def _VOP3AOp_V_CMP_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11258,7 +11252,7 @@ def _VOP3AOp_V_CMPX_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11280,7 +11274,7 @@ def _VOP3AOp_V_CMPX_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11302,7 +11296,7 @@ def _VOP3AOp_V_CMPX_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11323,7 +11317,7 @@ def _VOP3AOp_V_CMPX_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11345,7 +11339,7 @@ def _VOP3AOp_V_CMPX_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11366,7 +11360,7 @@ def _VOP3AOp_V_CMPX_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11387,7 +11381,7 @@ def _VOP3AOp_V_CMPX_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11409,7 +11403,7 @@ def _VOP3AOp_V_CMPX_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11430,7 +11424,7 @@ def _VOP3AOp_V_CMPX_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11452,7 +11446,7 @@ def _VOP3AOp_V_CMPX_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11474,7 +11468,7 @@ def _VOP3AOp_V_CMPX_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11496,7 +11490,7 @@ def _VOP3AOp_V_CMPX_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11518,7 +11512,7 @@ def _VOP3AOp_V_CMPX_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11541,7 +11535,7 @@ def _VOP3AOp_V_CMPX_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11564,7 +11558,7 @@ def _VOP3AOp_V_CMPX_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11584,7 +11578,7 @@ def _VOP3AOp_V_CMPX_TRU_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11602,7 +11596,7 @@ def _VOP3AOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11622,7 +11616,7 @@ def _VOP3AOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11642,7 +11636,7 @@ def _VOP3AOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11661,7 +11655,7 @@ def _VOP3AOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11681,7 +11675,7 @@ def _VOP3AOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11700,7 +11694,7 @@ def _VOP3AOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11719,7 +11713,7 @@ def _VOP3AOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11739,7 +11733,7 @@ def _VOP3AOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11759,7 +11753,7 @@ def _VOP3AOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11779,7 +11773,7 @@ def _VOP3AOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11799,7 +11793,7 @@ def _VOP3AOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11820,7 +11814,7 @@ def _VOP3AOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11840,7 +11834,7 @@ def _VOP3AOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11861,7 +11855,7 @@ def _VOP3AOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11882,7 +11876,7 @@ def _VOP3AOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11900,7 +11894,7 @@ def _VOP3AOp_V_CMP_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11920,7 +11914,7 @@ def _VOP3AOp_V_CMPX_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11942,7 +11936,7 @@ def _VOP3AOp_V_CMPX_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11964,7 +11958,7 @@ def _VOP3AOp_V_CMPX_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -11985,7 +11979,7 @@ def _VOP3AOp_V_CMPX_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12007,7 +12001,7 @@ def _VOP3AOp_V_CMPX_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12028,7 +12022,7 @@ def _VOP3AOp_V_CMPX_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12049,7 +12043,7 @@ def _VOP3AOp_V_CMPX_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12071,7 +12065,7 @@ def _VOP3AOp_V_CMPX_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12092,7 +12086,7 @@ def _VOP3AOp_V_CMPX_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12114,7 +12108,7 @@ def _VOP3AOp_V_CMPX_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12136,7 +12130,7 @@ def _VOP3AOp_V_CMPX_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12158,7 +12152,7 @@ def _VOP3AOp_V_CMPX_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12180,7 +12174,7 @@ def _VOP3AOp_V_CMPX_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12203,7 +12197,7 @@ def _VOP3AOp_V_CMPX_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12226,7 +12220,7 @@ def _VOP3AOp_V_CMPX_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12246,7 +12240,7 @@ def _VOP3AOp_V_CMPX_TRU_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12264,7 +12258,7 @@ def _VOP3AOp_V_CMP_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12284,7 +12278,7 @@ def _VOP3AOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12304,7 +12298,7 @@ def _VOP3AOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12323,7 +12317,7 @@ def _VOP3AOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12343,7 +12337,7 @@ def _VOP3AOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12363,7 +12357,7 @@ def _VOP3AOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12382,7 +12376,7 @@ def _VOP3AOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12400,7 +12394,7 @@ def _VOP3AOp_V_CMP_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12418,7 +12412,7 @@ def _VOP3AOp_V_CMP_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12438,7 +12432,7 @@ def _VOP3AOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12458,7 +12452,7 @@ def _VOP3AOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12477,7 +12471,7 @@ def _VOP3AOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12497,7 +12491,7 @@ def _VOP3AOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12517,7 +12511,7 @@ def _VOP3AOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12536,7 +12530,7 @@ def _VOP3AOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12554,7 +12548,7 @@ def _VOP3AOp_V_CMP_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12574,7 +12568,7 @@ def _VOP3AOp_V_CMPX_F_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12596,7 +12590,7 @@ def _VOP3AOp_V_CMPX_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12618,7 +12612,7 @@ def _VOP3AOp_V_CMPX_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12639,7 +12633,7 @@ def _VOP3AOp_V_CMPX_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12661,7 +12655,7 @@ def _VOP3AOp_V_CMPX_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12683,7 +12677,7 @@ def _VOP3AOp_V_CMPX_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12704,7 +12698,7 @@ def _VOP3AOp_V_CMPX_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12724,7 +12718,7 @@ def _VOP3AOp_V_CMPX_T_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12744,7 +12738,7 @@ def _VOP3AOp_V_CMPX_F_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12766,7 +12760,7 @@ def _VOP3AOp_V_CMPX_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12788,7 +12782,7 @@ def _VOP3AOp_V_CMPX_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12809,7 +12803,7 @@ def _VOP3AOp_V_CMPX_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12831,7 +12825,7 @@ def _VOP3AOp_V_CMPX_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12853,7 +12847,7 @@ def _VOP3AOp_V_CMPX_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12874,7 +12868,7 @@ def _VOP3AOp_V_CMPX_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12894,7 +12888,7 @@ def _VOP3AOp_V_CMPX_T_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12912,7 +12906,7 @@ def _VOP3AOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12932,7 +12926,7 @@ def _VOP3AOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12952,7 +12946,7 @@ def _VOP3AOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12971,7 +12965,7 @@ def _VOP3AOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12991,7 +12985,7 @@ def _VOP3AOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13011,7 +13005,7 @@ def _VOP3AOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13030,7 +13024,7 @@ def _VOP3AOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13048,7 +13042,7 @@ def _VOP3AOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13066,7 +13060,7 @@ def _VOP3AOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13086,7 +13080,7 @@ def _VOP3AOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13106,7 +13100,7 @@ def _VOP3AOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13125,7 +13119,7 @@ def _VOP3AOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13145,7 +13139,7 @@ def _VOP3AOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13165,7 +13159,7 @@ def _VOP3AOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13184,7 +13178,7 @@ def _VOP3AOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13202,7 +13196,7 @@ def _VOP3AOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13222,7 +13216,7 @@ def _VOP3AOp_V_CMPX_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13244,7 +13238,7 @@ def _VOP3AOp_V_CMPX_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13266,7 +13260,7 @@ def _VOP3AOp_V_CMPX_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13287,7 +13281,7 @@ def _VOP3AOp_V_CMPX_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13309,7 +13303,7 @@ def _VOP3AOp_V_CMPX_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13331,7 +13325,7 @@ def _VOP3AOp_V_CMPX_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13352,7 +13346,7 @@ def _VOP3AOp_V_CMPX_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13372,7 +13366,7 @@ def _VOP3AOp_V_CMPX_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13392,7 +13386,7 @@ def _VOP3AOp_V_CMPX_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13414,7 +13408,7 @@ def _VOP3AOp_V_CMPX_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13436,7 +13430,7 @@ def _VOP3AOp_V_CMPX_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13457,7 +13451,7 @@ def _VOP3AOp_V_CMPX_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13479,7 +13473,7 @@ def _VOP3AOp_V_CMPX_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13501,7 +13495,7 @@ def _VOP3AOp_V_CMPX_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13522,7 +13516,7 @@ def _VOP3AOp_V_CMPX_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13542,7 +13536,7 @@ def _VOP3AOp_V_CMPX_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13560,7 +13554,7 @@ def _VOP3AOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13580,7 +13574,7 @@ def _VOP3AOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13600,7 +13594,7 @@ def _VOP3AOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13619,7 +13613,7 @@ def _VOP3AOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13639,7 +13633,7 @@ def _VOP3AOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13659,7 +13653,7 @@ def _VOP3AOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13678,7 +13672,7 @@ def _VOP3AOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13696,7 +13690,7 @@ def _VOP3AOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13714,7 +13708,7 @@ def _VOP3AOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13734,7 +13728,7 @@ def _VOP3AOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13754,7 +13748,7 @@ def _VOP3AOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13773,7 +13767,7 @@ def _VOP3AOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13793,7 +13787,7 @@ def _VOP3AOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13813,7 +13807,7 @@ def _VOP3AOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13832,7 +13826,7 @@ def _VOP3AOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13850,7 +13844,7 @@ def _VOP3AOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13870,7 +13864,7 @@ def _VOP3AOp_V_CMPX_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13892,7 +13886,7 @@ def _VOP3AOp_V_CMPX_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13914,7 +13908,7 @@ def _VOP3AOp_V_CMPX_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13935,7 +13929,7 @@ def _VOP3AOp_V_CMPX_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13957,7 +13951,7 @@ def _VOP3AOp_V_CMPX_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13979,7 +13973,7 @@ def _VOP3AOp_V_CMPX_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14000,7 +13994,7 @@ def _VOP3AOp_V_CMPX_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14020,7 +14014,7 @@ def _VOP3AOp_V_CMPX_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14040,7 +14034,7 @@ def _VOP3AOp_V_CMPX_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14062,7 +14056,7 @@ def _VOP3AOp_V_CMPX_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14084,7 +14078,7 @@ def _VOP3AOp_V_CMPX_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14105,7 +14099,7 @@ def _VOP3AOp_V_CMPX_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14127,7 +14121,7 @@ def _VOP3AOp_V_CMPX_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14149,7 +14143,7 @@ def _VOP3AOp_V_CMPX_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14170,7 +14164,7 @@ def _VOP3AOp_V_CMPX_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14183,9 +14177,6 @@ def _VOP3AOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG # tmp = MEM[addr].u32; # addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); # tmp = MEM[addr].u32; - # addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); - # tmp = MEM[addr].u32; - # src = DATA.u32; D0 = Reg(d0) VCC = Reg(vcc) EXEC = Reg(exec_mask) @@ -14200,16 +14191,13 @@ def _VOP3AOp_V_CMPX_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG tmp = Reg(MEM[addr].u32) addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - src = DATA.u32 # --- end pseudocode --- result = {'d0': D0._val, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 if EXEC._val != exec_mask: result['exec'] = EXEC._val result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3AOp_V_MOV_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15232,24 +15220,6 @@ def _VOP3AOp_V_XOR_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} return result -def _VOP3AOp_V_DOT2C_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp = D0.f32; - # tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16); - # tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16); - # D0.f32 = tmp - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp = Reg(D0.f32) - tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16) - tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16) - D0.f32 = tmp - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - def _VOP3AOp_V_ADD_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): # D0.f16 = S0.f16 + S1.f16 S0 = Reg(s0) @@ -16977,6 +16947,473 @@ def _VOP3AOp_V_LSHL_ADD_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['d0_64'] = True return result +def _VOP3AOp_V_ADD_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.f64 = S0.f64 + S1.f64 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.f64 = S0.f64 + S1.f64 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_MUL_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.f64 = S0.f64 * S1.f64 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.f64 = S0.f64 * S1.f64 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_MIN_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # if (WAVE_MODE.IEEE && isSignalNAN(S0.f64)) then + # D0.f64 = cvtToQuietNAN(S0.f64) + # elsif (WAVE_MODE.IEEE && isSignalNAN(S1.f64)) then + # D0.f64 = cvtToQuietNAN(S1.f64) + # elsif isNAN(S0.f64) then + # D0.f64 = S1.f64 + # elsif isNAN(S1.f64) then + # D0.f64 = S0.f64 + # elsif ((S0.f64 == +0.0) && (S1.f64 == -0.0)) then + # D0.f64 = S1.f64 + # elsif ((S0.f64 == -0.0) && (S1.f64 == +0.0)) then + # D0.f64 = S0.f64 + # else + # D0.f64 = S0.f64 < S1.f64 ? S0.f64 : S1.f64 + # endif + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + if (WAVE_MODE.IEEE and isSignalNAN(S0.f64)): + D0.f64 = cvtToQuietNAN(S0.f64) + elif (WAVE_MODE.IEEE and isSignalNAN(S1.f64)): + D0.f64 = cvtToQuietNAN(S1.f64) + elif isNAN(S0.f64): + D0.f64 = S1.f64 + elif isNAN(S1.f64): + D0.f64 = S0.f64 + elif ((S0.f64 == +0.0) and (S1.f64 == -0.0)): + D0.f64 = S1.f64 + elif ((S0.f64 == -0.0) and (S1.f64 == +0.0)): + D0.f64 = S0.f64 + else: + D0.f64 = ((S0.f64) if (S0.f64 < S1.f64) else (S1.f64)) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_MAX_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # if (WAVE_MODE.IEEE && isSignalNAN(S0.f64)) then + # D0.f64 = cvtToQuietNAN(S0.f64) + # elsif (WAVE_MODE.IEEE && isSignalNAN(S1.f64)) then + # D0.f64 = cvtToQuietNAN(S1.f64) + # elsif isNAN(S0.f64) then + # D0.f64 = S1.f64 + # elsif isNAN(S1.f64) then + # D0.f64 = S0.f64 + # elsif ((S0.f64 == +0.0) && (S1.f64 == -0.0)) then + # D0.f64 = S0.f64 + # elsif ((S0.f64 == -0.0) && (S1.f64 == +0.0)) then + # D0.f64 = S1.f64 + # elsif WAVE_MODE.IEEE then + # D0.f64 = S0.f64 >= S1.f64 ? S0.f64 : S1.f64 + # else + # D0.f64 = S0.f64 > S1.f64 ? S0.f64 : S1.f64 + # endif + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + if (WAVE_MODE.IEEE and isSignalNAN(S0.f64)): + D0.f64 = cvtToQuietNAN(S0.f64) + elif (WAVE_MODE.IEEE and isSignalNAN(S1.f64)): + D0.f64 = cvtToQuietNAN(S1.f64) + elif isNAN(S0.f64): + D0.f64 = S1.f64 + elif isNAN(S1.f64): + D0.f64 = S0.f64 + elif ((S0.f64 == +0.0) and (S1.f64 == -0.0)): + D0.f64 = S0.f64 + elif ((S0.f64 == -0.0) and (S1.f64 == +0.0)): + D0.f64 = S1.f64 + elif WAVE_MODE.IEEE: + D0.f64 = ((S0.f64) if (S0.f64 >= S1.f64) else (S1.f64)) + else: + D0.f64 = ((S0.f64) if (S0.f64 > S1.f64) else (S1.f64)) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_LDEXP_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.f64 = S0.f64 * 2.0 ** S1.i32 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.f64 = S0.f64 * 2.0 ** S1.i32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_MUL_LO_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.u32 = S0.u32 * S1.u32 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.u32 = S0.u32 * S1.u32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_MUL_HI_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.u32 = 32'U((64'U(S0.u32) * 64'U(S1.u32)) >> 32U) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.u32 = (((S0.u32) * (S1.u32)) >> 32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_MUL_HI_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i32 = (((S0.i32) * (S1.i32)) >> 32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_LDEXP_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.f32 = S0.f32 * 2.0F ** S1.i32 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.f32 = S0.f32 * 2.0 ** S1.i32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_READLANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # lane = S1.u32[5 : 0]; + # // Lane select + # D0.b32 = VGPR[lane][SRC0.u32] + S1 = Reg(s1) + D0 = Reg(d0) + SRC0 = Reg(src0_idx) + # --- compiled pseudocode --- + lane = S1.u32[5 : 0] + D0.b32 = VGPR[lane][SRC0.u32] + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_BCNT_U32_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp = S1.u32; + # for i in 0 : 31 do + # tmp += S0[i].u32; + # // count i'th bit + # endfor; + # D0.u32 = tmp + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(S1.u32) + for i in range(0, int(31)+1): + tmp += S0[i].u32 + D0.u32 = tmp + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_LSHLREV_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.u64 = (S1.u64 << S0[5 : 0].u32) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.u64 = (S1.u64 << S0[5 : 0].u32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_LSHRREV_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.u64 = (S1.u64 >> S0[5 : 0].u32) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.u64 = (S1.u64 >> S0[5 : 0].u32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_ASHRREV_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i64 = (S1.i64 >> S0[5 : 0].u32) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i64 = (S1.i64 >> S0[5 : 0].u32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_TRIG_PREOP_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # shift = 32'I(S1[4 : 0].u32) * 53; + # if exponent(S0.f64) > 1077 then + # shift += exponent(S0.f64) - 1077 + # endif; + # // (2.0/PI) == 0.{b_1200, b_1199, b_1198, ..., b_1, b_0} + # // b_1200 is the MSB of the fractional part of 2.0/PI + # // Left shift operation indicates which bits are brought + # result = 64'F((1201'B(2.0 / PI)[1200 : 0] << shift.u32) & 1201'0x1fffffffffffff); + # scale = -53 - shift; + # if exponent(S0.f64) >= 1968 then + # scale += 128 + # endif; + # D0.f64 = ldexp(result, scale) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + shift = (S1[4 : 0].u32) * 53 + if exponent(S0.f64) > 1077: + shift += exponent(S0.f64) - 1077 + result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff) + scale = -53 - shift + if exponent(S0.f64) >= 1968: + scale += 128 + D0.f64 = ldexp(result, scale) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + result['d0_64'] = True + return result + +def _VOP3AOp_V_BFM_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.u32 = (((1U << S0[4 : 0].u32) - 1U) << S1[4 : 0].u32) + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.u32 = (((1 << S0[4 : 0].u32) - 1) << S1[4 : 0].u32) + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PKNORM_I16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].i16 = f32_to_snorm(S0.f32); + # tmp[31 : 16].i16 = f32_to_snorm(S1.f32); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].i16 = f32_to_snorm(S0.f32) + tmp[31 : 16].i16 = f32_to_snorm(S1.f32) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PKNORM_U16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].u16 = f32_to_unorm(S0.f32); + # tmp[31 : 16].u16 = f32_to_unorm(S1.f32); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].u16 = f32_to_unorm(S0.f32) + tmp[31 : 16].u16 = f32_to_unorm(S1.f32) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PKRTZ_F16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # prev_mode = ROUND_MODE; + # tmp[15 : 0].f16 = f32_to_f16(S0.f32); + # tmp[31 : 16].f16 = f32_to_f16(S1.f32); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + prev_mode = ROUND_MODE + tmp[15 : 0].f16 = f32_to_f16(S0.f32) + tmp[31 : 16].f16 = f32_to_f16(S1.f32) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PK_U16_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].u16 = u32_to_u16(S0.u32); + # tmp[31 : 16].u16 = u32_to_u16(S1.u32); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].u16 = u32_to_u16(S0.u32) + tmp[31 : 16].u16 = u32_to_u16(S1.u32) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PK_I16_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].i16 = i32_to_i16(S0.i32); + # tmp[31 : 16].i16 = i32_to_i16(S1.i32); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].i16 = i32_to_i16(S0.i32) + tmp[31 : 16].i16 = i32_to_i16(S1.i32) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PKNORM_I16_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].i16 = f16_to_snorm(S0.f16); + # tmp[31 : 16].i16 = f16_to_snorm(S1.f16); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].i16 = f16_to_snorm(S0.f16) + tmp[31 : 16].i16 = f16_to_snorm(S1.f16) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_CVT_PKNORM_U16_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # declare tmp : 32'B; + # tmp[15 : 0].u16 = f16_to_unorm(S0.f16); + # tmp[31 : 16].u16 = f16_to_unorm(S1.f16); + S0 = Reg(s0) + S1 = Reg(s1) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp[15 : 0].u16 = f16_to_unorm(S0.f16) + tmp[31 : 16].u16 = f16_to_unorm(S1.f16) + # --- end pseudocode --- + result = {'d0': d0, 'scc': scc & 1} + return result + +def _VOP3AOp_V_ADD_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i32 = S0.i32 + S1.i32 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i32 = S0.i32 + S1.i32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_SUB_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i32 = S0.i32 - S1.i32 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i32 = S0.i32 - S1.i32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_ADD_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i16 = S0.i16 + S1.i16 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i16 = S0.i16 + S1.i16 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_SUB_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0.i16 = S0.i16 - S1.i16 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0.i16 = S0.i16 - S1.i16 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_PACK_B32_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # D0[31 : 16].f16 = S1.f16; + # D0[15 : 0].f16 = S0.f16 + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + D0[31 : 16].f16 = S1.f16 + D0[15 : 0].f16 = S0.f16 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_MUL_LEGACY_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # if ((64'F(S0.f32) == 0.0) || (64'F(S1.f32) == 0.0)) then + # // DX9 rules, 0.0 * x = 0.0 + # D0.f32 = 0.0F + # else + # D0.f32 = S0.f32 * S1.f32 + # endif + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + # --- compiled pseudocode --- + if ((F(S0.f32) == 0.0) or (F(S1.f32) == 0.0)): + D0.f32 = 0.0 + else: + D0.f32 = S0.f32 * S1.f32 + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + +def _VOP3AOp_V_DOT2C_F32_BF16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): + # tmp = D0.f32; + # tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16); + # tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16); + # D0.f32 = tmp + S0 = Reg(s0) + S1 = Reg(s1) + D0 = Reg(d0) + tmp = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(D0.f32) + tmp += bf16_to_f32(S0[15 : 0].bf16) * bf16_to_f32(S1[15 : 0].bf16) + tmp += bf16_to_f32(S0[31 : 16].bf16) * bf16_to_f32(S1[31 : 16].bf16) + D0.f32 = tmp + # --- end pseudocode --- + result = {'d0': D0._val, 'scc': scc & 1} + return result + def _VOP3AOp_V_BITOP3_B16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): # tmp = 16'0U; # tmp = (tmp | (32'I(TTBL.b32 & 0x1) != 0 ? 16'U(~S0.b16 & ~S1.b16 & ~S2.b16) : 16'0U)); @@ -18052,455 +18489,6 @@ def _VOP3AOp_V_CVT_SCALEF32_PK_BF16_BF8(s0, s1, s2, d0, scc, vcc, lane, exec_mas result = {'d0': D0._val, 'scc': scc & 1} return result -def _VOP3AOp_V_ADD_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.f64 = S0.f64 + S1.f64 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.f64 = S0.f64 + S1.f64 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_MUL_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.f64 = S0.f64 * S1.f64 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.f64 = S0.f64 * S1.f64 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_MIN_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # if (WAVE_MODE.IEEE && isSignalNAN(S0.f64)) then - # D0.f64 = cvtToQuietNAN(S0.f64) - # elsif (WAVE_MODE.IEEE && isSignalNAN(S1.f64)) then - # D0.f64 = cvtToQuietNAN(S1.f64) - # elsif isNAN(S0.f64) then - # D0.f64 = S1.f64 - # elsif isNAN(S1.f64) then - # D0.f64 = S0.f64 - # elsif ((S0.f64 == +0.0) && (S1.f64 == -0.0)) then - # D0.f64 = S1.f64 - # elsif ((S0.f64 == -0.0) && (S1.f64 == +0.0)) then - # D0.f64 = S0.f64 - # else - # D0.f64 = S0.f64 < S1.f64 ? S0.f64 : S1.f64 - # endif - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - if (WAVE_MODE.IEEE and isSignalNAN(S0.f64)): - D0.f64 = cvtToQuietNAN(S0.f64) - elif (WAVE_MODE.IEEE and isSignalNAN(S1.f64)): - D0.f64 = cvtToQuietNAN(S1.f64) - elif isNAN(S0.f64): - D0.f64 = S1.f64 - elif isNAN(S1.f64): - D0.f64 = S0.f64 - elif ((S0.f64 == +0.0) and (S1.f64 == -0.0)): - D0.f64 = S1.f64 - elif ((S0.f64 == -0.0) and (S1.f64 == +0.0)): - D0.f64 = S0.f64 - else: - D0.f64 = ((S0.f64) if (S0.f64 < S1.f64) else (S1.f64)) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_MAX_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # if (WAVE_MODE.IEEE && isSignalNAN(S0.f64)) then - # D0.f64 = cvtToQuietNAN(S0.f64) - # elsif (WAVE_MODE.IEEE && isSignalNAN(S1.f64)) then - # D0.f64 = cvtToQuietNAN(S1.f64) - # elsif isNAN(S0.f64) then - # D0.f64 = S1.f64 - # elsif isNAN(S1.f64) then - # D0.f64 = S0.f64 - # elsif ((S0.f64 == +0.0) && (S1.f64 == -0.0)) then - # D0.f64 = S0.f64 - # elsif ((S0.f64 == -0.0) && (S1.f64 == +0.0)) then - # D0.f64 = S1.f64 - # elsif WAVE_MODE.IEEE then - # D0.f64 = S0.f64 >= S1.f64 ? S0.f64 : S1.f64 - # else - # D0.f64 = S0.f64 > S1.f64 ? S0.f64 : S1.f64 - # endif - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - if (WAVE_MODE.IEEE and isSignalNAN(S0.f64)): - D0.f64 = cvtToQuietNAN(S0.f64) - elif (WAVE_MODE.IEEE and isSignalNAN(S1.f64)): - D0.f64 = cvtToQuietNAN(S1.f64) - elif isNAN(S0.f64): - D0.f64 = S1.f64 - elif isNAN(S1.f64): - D0.f64 = S0.f64 - elif ((S0.f64 == +0.0) and (S1.f64 == -0.0)): - D0.f64 = S0.f64 - elif ((S0.f64 == -0.0) and (S1.f64 == +0.0)): - D0.f64 = S1.f64 - elif WAVE_MODE.IEEE: - D0.f64 = ((S0.f64) if (S0.f64 >= S1.f64) else (S1.f64)) - else: - D0.f64 = ((S0.f64) if (S0.f64 > S1.f64) else (S1.f64)) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_LDEXP_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.f64 = S0.f64 * 2.0 ** S1.i32 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.f64 = S0.f64 * 2.0 ** S1.i32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_MUL_LO_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.u32 = S0.u32 * S1.u32 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.u32 = S0.u32 * S1.u32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_MUL_HI_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.u32 = 32'U((64'U(S0.u32) * 64'U(S1.u32)) >> 32U) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.u32 = (((S0.u32) * (S1.u32)) >> 32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_MUL_HI_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i32 = (((S0.i32) * (S1.i32)) >> 32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_LDEXP_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.f32 = S0.f32 * 2.0F ** S1.i32 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.f32 = S0.f32 * 2.0 ** S1.i32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_READLANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # lane = S1.u32[5 : 0]; - # // Lane select - # D0.b32 = VGPR[lane][SRC0.u32] - S1 = Reg(s1) - D0 = Reg(d0) - SRC0 = Reg(src0_idx) - # --- compiled pseudocode --- - lane = S1.u32[5 : 0] - D0.b32 = VGPR[lane][SRC0.u32] - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_BCNT_U32_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # tmp = S1.u32; - # for i in 0 : 31 do - # tmp += S0[i].u32; - # // count i'th bit - # endfor; - # D0.u32 = tmp - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp = Reg(S1.u32) - for i in range(0, int(31)+1): - tmp += S0[i].u32 - D0.u32 = tmp - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_LSHLREV_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.u64 = (S1.u64 << S0[5 : 0].u32) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.u64 = (S1.u64 << S0[5 : 0].u32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_LSHRREV_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.u64 = (S1.u64 >> S0[5 : 0].u32) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.u64 = (S1.u64 >> S0[5 : 0].u32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_ASHRREV_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i64 = (S1.i64 >> S0[5 : 0].u32) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i64 = (S1.i64 >> S0[5 : 0].u32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_TRIG_PREOP_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # shift = 32'I(S1[4 : 0].u32) * 53; - # if exponent(S0.f64) > 1077 then - # shift += exponent(S0.f64) - 1077 - # endif; - # // (2.0/PI) == 0.{b_1200, b_1199, b_1198, ..., b_1, b_0} - # // b_1200 is the MSB of the fractional part of 2.0/PI - # // Left shift operation indicates which bits are brought - # result = 64'F((1201'B(2.0 / PI)[1200 : 0] << shift.u32) & 1201'0x1fffffffffffff); - # scale = -53 - shift; - # if exponent(S0.f64) >= 1968 then - # scale += 128 - # endif; - # D0.f64 = ldexp(result, scale) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - shift = (S1[4 : 0].u32) * 53 - if exponent(S0.f64) > 1077: - shift += exponent(S0.f64) - 1077 - result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff) - scale = -53 - shift - if exponent(S0.f64) >= 1968: - scale += 128 - D0.f64 = ldexp(result, scale) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - result['d0_64'] = True - return result - -def _VOP3AOp_V_BFM_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.u32 = (((1U << S0[4 : 0].u32) - 1U) << S1[4 : 0].u32) - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.u32 = (((1 << S0[4 : 0].u32) - 1) << S1[4 : 0].u32) - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PKNORM_I16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].i16 = f32_to_snorm(S0.f32); - # tmp[31 : 16].i16 = f32_to_snorm(S1.f32); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].i16 = f32_to_snorm(S0.f32) - tmp[31 : 16].i16 = f32_to_snorm(S1.f32) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PKNORM_U16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].u16 = f32_to_unorm(S0.f32); - # tmp[31 : 16].u16 = f32_to_unorm(S1.f32); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].u16 = f32_to_unorm(S0.f32) - tmp[31 : 16].u16 = f32_to_unorm(S1.f32) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PKRTZ_F16_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # prev_mode = ROUND_MODE; - # tmp[15 : 0].f16 = f32_to_f16(S0.f32); - # tmp[31 : 16].f16 = f32_to_f16(S1.f32); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - prev_mode = ROUND_MODE - tmp[15 : 0].f16 = f32_to_f16(S0.f32) - tmp[31 : 16].f16 = f32_to_f16(S1.f32) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PK_U16_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].u16 = u32_to_u16(S0.u32); - # tmp[31 : 16].u16 = u32_to_u16(S1.u32); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].u16 = u32_to_u16(S0.u32) - tmp[31 : 16].u16 = u32_to_u16(S1.u32) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PK_I16_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].i16 = i32_to_i16(S0.i32); - # tmp[31 : 16].i16 = i32_to_i16(S1.i32); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].i16 = i32_to_i16(S0.i32) - tmp[31 : 16].i16 = i32_to_i16(S1.i32) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PKNORM_I16_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].i16 = f16_to_snorm(S0.f16); - # tmp[31 : 16].i16 = f16_to_snorm(S1.f16); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].i16 = f16_to_snorm(S0.f16) - tmp[31 : 16].i16 = f16_to_snorm(S1.f16) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_CVT_PKNORM_U16_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # declare tmp : 32'B; - # tmp[15 : 0].u16 = f16_to_unorm(S0.f16); - # tmp[31 : 16].u16 = f16_to_unorm(S1.f16); - S0 = Reg(s0) - S1 = Reg(s1) - tmp = Reg(0) - # --- compiled pseudocode --- - tmp[15 : 0].u16 = f16_to_unorm(S0.f16) - tmp[31 : 16].u16 = f16_to_unorm(S1.f16) - # --- end pseudocode --- - result = {'d0': d0, 'scc': scc & 1} - return result - -def _VOP3AOp_V_ADD_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i32 = S0.i32 + S1.i32 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i32 = S0.i32 + S1.i32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_SUB_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i32 = S0.i32 - S1.i32 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i32 = S0.i32 - S1.i32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_ADD_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i16 = S0.i16 + S1.i16 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i16 = S0.i16 + S1.i16 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_SUB_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0.i16 = S0.i16 - S1.i16 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0.i16 = S0.i16 - S1.i16 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_PACK_B32_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # D0[31 : 16].f16 = S1.f16; - # D0[15 : 0].f16 = S0.f16 - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - D0[31 : 16].f16 = S1.f16 - D0[15 : 0].f16 = S0.f16 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - -def _VOP3AOp_V_MUL_LEGACY_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): - # if ((64'F(S0.f32) == 0.0) || (64'F(S1.f32) == 0.0)) then - # // DX9 rules, 0.0 * x = 0.0 - # D0.f32 = 0.0F - # else - # D0.f32 = S0.f32 * S1.f32 - # endif - S0 = Reg(s0) - S1 = Reg(s1) - D0 = Reg(d0) - # --- compiled pseudocode --- - if ((F(S0.f32) == 0.0) or (F(S1.f32) == 0.0)): - D0.f32 = 0.0 - else: - D0.f32 = S0.f32 * S1.f32 - # --- end pseudocode --- - result = {'d0': D0._val, 'scc': scc & 1} - return result - def _VOP3AOp_V_MINIMUM3_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): # D0.f32 = 32'F(v_minimum_f32(v_minimum_f32(S0.f32, S1.f32), S2.f32)) S0 = Reg(s0) @@ -18806,7 +18794,6 @@ VOP3AOp_FUNCTIONS = { VOP3AOp.V_AND_B32: _VOP3AOp_V_AND_B32, VOP3AOp.V_OR_B32: _VOP3AOp_V_OR_B32, VOP3AOp.V_XOR_B32: _VOP3AOp_V_XOR_B32, - VOP3AOp.V_DOT2C_F32_BF16: _VOP3AOp_V_DOT2C_F32_BF16, VOP3AOp.V_ADD_F16: _VOP3AOp_V_ADD_F16, VOP3AOp.V_SUB_F16: _VOP3AOp_V_SUB_F16, VOP3AOp.V_SUBREV_F16: _VOP3AOp_V_SUBREV_F16, @@ -18903,6 +18890,36 @@ VOP3AOp_FUNCTIONS = { VOP3AOp.V_FMA_F16: _VOP3AOp_V_FMA_F16, VOP3AOp.V_DIV_FIXUP_F16: _VOP3AOp_V_DIV_FIXUP_F16, VOP3AOp.V_LSHL_ADD_U64: _VOP3AOp_V_LSHL_ADD_U64, + VOP3AOp.V_ADD_F64: _VOP3AOp_V_ADD_F64, + VOP3AOp.V_MUL_F64: _VOP3AOp_V_MUL_F64, + VOP3AOp.V_MIN_F64: _VOP3AOp_V_MIN_F64, + VOP3AOp.V_MAX_F64: _VOP3AOp_V_MAX_F64, + VOP3AOp.V_LDEXP_F64: _VOP3AOp_V_LDEXP_F64, + VOP3AOp.V_MUL_LO_U32: _VOP3AOp_V_MUL_LO_U32, + VOP3AOp.V_MUL_HI_U32: _VOP3AOp_V_MUL_HI_U32, + VOP3AOp.V_MUL_HI_I32: _VOP3AOp_V_MUL_HI_I32, + VOP3AOp.V_LDEXP_F32: _VOP3AOp_V_LDEXP_F32, + VOP3AOp.V_READLANE_B32: _VOP3AOp_V_READLANE_B32, + VOP3AOp.V_BCNT_U32_B32: _VOP3AOp_V_BCNT_U32_B32, + VOP3AOp.V_LSHLREV_B64: _VOP3AOp_V_LSHLREV_B64, + VOP3AOp.V_LSHRREV_B64: _VOP3AOp_V_LSHRREV_B64, + VOP3AOp.V_ASHRREV_I64: _VOP3AOp_V_ASHRREV_I64, + VOP3AOp.V_TRIG_PREOP_F64: _VOP3AOp_V_TRIG_PREOP_F64, + VOP3AOp.V_BFM_B32: _VOP3AOp_V_BFM_B32, + VOP3AOp.V_CVT_PKNORM_I16_F32: _VOP3AOp_V_CVT_PKNORM_I16_F32, + VOP3AOp.V_CVT_PKNORM_U16_F32: _VOP3AOp_V_CVT_PKNORM_U16_F32, + VOP3AOp.V_CVT_PKRTZ_F16_F32: _VOP3AOp_V_CVT_PKRTZ_F16_F32, + VOP3AOp.V_CVT_PK_U16_U32: _VOP3AOp_V_CVT_PK_U16_U32, + VOP3AOp.V_CVT_PK_I16_I32: _VOP3AOp_V_CVT_PK_I16_I32, + VOP3AOp.V_CVT_PKNORM_I16_F16: _VOP3AOp_V_CVT_PKNORM_I16_F16, + VOP3AOp.V_CVT_PKNORM_U16_F16: _VOP3AOp_V_CVT_PKNORM_U16_F16, + VOP3AOp.V_ADD_I32: _VOP3AOp_V_ADD_I32, + VOP3AOp.V_SUB_I32: _VOP3AOp_V_SUB_I32, + VOP3AOp.V_ADD_I16: _VOP3AOp_V_ADD_I16, + VOP3AOp.V_SUB_I16: _VOP3AOp_V_SUB_I16, + VOP3AOp.V_PACK_B32_F16: _VOP3AOp_V_PACK_B32_F16, + VOP3AOp.V_MUL_LEGACY_F32: _VOP3AOp_V_MUL_LEGACY_F32, + VOP3AOp.V_DOT2C_F32_BF16: _VOP3AOp_V_DOT2C_F32_BF16, VOP3AOp.V_BITOP3_B16: _VOP3AOp_V_BITOP3_B16, VOP3AOp.V_BITOP3_B32: _VOP3AOp_V_BITOP3_B32, VOP3AOp.V_CVT_SCALEF32_PK_FP8_F32: _VOP3AOp_V_CVT_SCALEF32_PK_FP8_F32, @@ -18957,35 +18974,6 @@ VOP3AOp_FUNCTIONS = { VOP3AOp.V_CVT_PK_BF16_F32: _VOP3AOp_V_CVT_PK_BF16_F32, VOP3AOp.V_CVT_SCALEF32_PK_BF16_FP8: _VOP3AOp_V_CVT_SCALEF32_PK_BF16_FP8, VOP3AOp.V_CVT_SCALEF32_PK_BF16_BF8: _VOP3AOp_V_CVT_SCALEF32_PK_BF16_BF8, - VOP3AOp.V_ADD_F64: _VOP3AOp_V_ADD_F64, - VOP3AOp.V_MUL_F64: _VOP3AOp_V_MUL_F64, - VOP3AOp.V_MIN_F64: _VOP3AOp_V_MIN_F64, - VOP3AOp.V_MAX_F64: _VOP3AOp_V_MAX_F64, - VOP3AOp.V_LDEXP_F64: _VOP3AOp_V_LDEXP_F64, - VOP3AOp.V_MUL_LO_U32: _VOP3AOp_V_MUL_LO_U32, - VOP3AOp.V_MUL_HI_U32: _VOP3AOp_V_MUL_HI_U32, - VOP3AOp.V_MUL_HI_I32: _VOP3AOp_V_MUL_HI_I32, - VOP3AOp.V_LDEXP_F32: _VOP3AOp_V_LDEXP_F32, - VOP3AOp.V_READLANE_B32: _VOP3AOp_V_READLANE_B32, - VOP3AOp.V_BCNT_U32_B32: _VOP3AOp_V_BCNT_U32_B32, - VOP3AOp.V_LSHLREV_B64: _VOP3AOp_V_LSHLREV_B64, - VOP3AOp.V_LSHRREV_B64: _VOP3AOp_V_LSHRREV_B64, - VOP3AOp.V_ASHRREV_I64: _VOP3AOp_V_ASHRREV_I64, - VOP3AOp.V_TRIG_PREOP_F64: _VOP3AOp_V_TRIG_PREOP_F64, - VOP3AOp.V_BFM_B32: _VOP3AOp_V_BFM_B32, - VOP3AOp.V_CVT_PKNORM_I16_F32: _VOP3AOp_V_CVT_PKNORM_I16_F32, - VOP3AOp.V_CVT_PKNORM_U16_F32: _VOP3AOp_V_CVT_PKNORM_U16_F32, - VOP3AOp.V_CVT_PKRTZ_F16_F32: _VOP3AOp_V_CVT_PKRTZ_F16_F32, - VOP3AOp.V_CVT_PK_U16_U32: _VOP3AOp_V_CVT_PK_U16_U32, - VOP3AOp.V_CVT_PK_I16_I32: _VOP3AOp_V_CVT_PK_I16_I32, - VOP3AOp.V_CVT_PKNORM_I16_F16: _VOP3AOp_V_CVT_PKNORM_I16_F16, - VOP3AOp.V_CVT_PKNORM_U16_F16: _VOP3AOp_V_CVT_PKNORM_U16_F16, - VOP3AOp.V_ADD_I32: _VOP3AOp_V_ADD_I32, - VOP3AOp.V_SUB_I32: _VOP3AOp_V_SUB_I32, - VOP3AOp.V_ADD_I16: _VOP3AOp_V_ADD_I16, - VOP3AOp.V_SUB_I16: _VOP3AOp_V_SUB_I16, - VOP3AOp.V_PACK_B32_F16: _VOP3AOp_V_PACK_B32_F16, - VOP3AOp.V_MUL_LEGACY_F32: _VOP3AOp_V_MUL_LEGACY_F32, VOP3AOp.V_MINIMUM3_F32: _VOP3AOp_V_MINIMUM3_F32, VOP3AOp.V_MAXIMUM3_F32: _VOP3AOp_V_MAXIMUM3_F32, } @@ -19155,7 +19143,7 @@ def _VOP3BOp_V_DIV_SCALE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if S0.f32 == S1.f32: D0.f32 = ldexp(S0.f32, 64) elif False: - pass # denorm check moved to end + pass elif ((1.0 / F(S1.f32) == DENORM.f64) and (S2.f32 / S1.f32 == DENORM.f32)): VCC = Reg(0x1) if S0.f32 == S1.f32: @@ -19218,7 +19206,7 @@ def _VOP3BOp_V_DIV_SCALE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, if S0.f64 == S1.f64: D0.f64 = ldexp(S0.f64, 128) elif False: - pass # denorm check moved to end + pass elif ((1.0 / S1.f64 == DENORM.f64) and (S2.f64 / S1.f64 == DENORM.f64)): VCC = Reg(0x1) if S0.f64 == S1.f64: diff --git a/extra/assembly/amd/autogen/rdna3/__init__.py b/extra/assembly/amd/autogen/rdna3/__init__.py index a1d5780754..0f342cc61b 100644 --- a/extra/assembly/amd/autogen/rdna3/__init__.py +++ b/extra/assembly/amd/autogen/rdna3/__init__.py @@ -1,4 +1,4 @@ -# autogenerated from AMD RDNA3.5 ISA PDF by dsl.py - do not edit +# autogenerated from AMD RDNA3.5 ISA PDF by pdf.py - do not edit from enum import IntEnum from typing import Annotated from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField diff --git a/extra/assembly/amd/autogen/rdna3/gen_pcode.py b/extra/assembly/amd/autogen/rdna3/gen_pcode.py index 698ca243eb..47a47951cb 100644 --- a/extra/assembly/amd/autogen/rdna3/gen_pcode.py +++ b/extra/assembly/amd/autogen/rdna3/gen_pcode.py @@ -1,5 +1,5 @@ -# autogenerated by pcode.py - do not edit -# to regenerate: python -m extra.assembly.amd.pcode --arch rdna3 +# autogenerated by pdf.py - do not edit +# to regenerate: python -m extra.assembly.amd.pdf --arch rdna3 # ruff: noqa: E501,F405,F403 # mypy: ignore-errors from extra.assembly.amd.autogen.rdna3 import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp @@ -1051,7 +1051,7 @@ def _SOP1Op_S_GETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1063,7 +1063,7 @@ def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1081,7 +1081,7 @@ def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1093,7 +1093,7 @@ def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SENDMSG_RTN_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3336,7 +3336,7 @@ def _SOPKOp_S_CALL_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result SOPKOp_FUNCTIONS = { @@ -3393,7 +3393,7 @@ def _SOPPOp_S_TRAP(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _va # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_BRANCH(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3405,7 +3405,7 @@ def _SOPPOp_S_BRANCH(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _ # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3425,7 +3425,7 @@ def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3445,7 +3445,7 @@ def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3468,7 +3468,7 @@ def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3491,7 +3491,7 @@ def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3513,7 +3513,7 @@ def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3535,7 +3535,7 @@ def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3554,7 +3554,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGUSER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3573,7 +3573,7 @@ def _SOPPOp_S_CBRANCH_CDBGUSER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, litera # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS_OR_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3592,7 +3592,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS_OR_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_CDBGSYS_AND_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3611,7 +3611,7 @@ def _SOPPOp_S_CBRANCH_CDBGSYS_AND_USER(s0, s1, s2, d0, scc, vcc, lane, exec_mask # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result SOPPOp_FUNCTIONS = { @@ -5500,7 +5500,7 @@ def _VOP3Op_V_CMP_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5521,7 +5521,7 @@ def _VOP3Op_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5542,7 +5542,7 @@ def _VOP3Op_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5562,7 +5562,7 @@ def _VOP3Op_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5583,7 +5583,7 @@ def _VOP3Op_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5603,7 +5603,7 @@ def _VOP3Op_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5623,7 +5623,7 @@ def _VOP3Op_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5644,7 +5644,7 @@ def _VOP3Op_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5665,7 +5665,7 @@ def _VOP3Op_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5686,7 +5686,7 @@ def _VOP3Op_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5707,7 +5707,7 @@ def _VOP3Op_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5729,7 +5729,7 @@ def _VOP3Op_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5750,7 +5750,7 @@ def _VOP3Op_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5772,7 +5772,7 @@ def _VOP3Op_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5794,7 +5794,7 @@ def _VOP3Op_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5813,7 +5813,7 @@ def _VOP3Op_V_CMP_T_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5832,7 +5832,7 @@ def _VOP3Op_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5853,7 +5853,7 @@ def _VOP3Op_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5874,7 +5874,7 @@ def _VOP3Op_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5894,7 +5894,7 @@ def _VOP3Op_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5915,7 +5915,7 @@ def _VOP3Op_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5935,7 +5935,7 @@ def _VOP3Op_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5955,7 +5955,7 @@ def _VOP3Op_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5976,7 +5976,7 @@ def _VOP3Op_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5997,7 +5997,7 @@ def _VOP3Op_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6018,7 +6018,7 @@ def _VOP3Op_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6039,7 +6039,7 @@ def _VOP3Op_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6061,7 +6061,7 @@ def _VOP3Op_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6082,7 +6082,7 @@ def _VOP3Op_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6104,7 +6104,7 @@ def _VOP3Op_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6126,7 +6126,7 @@ def _VOP3Op_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6145,7 +6145,7 @@ def _VOP3Op_V_CMP_T_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6164,7 +6164,7 @@ def _VOP3Op_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6185,7 +6185,7 @@ def _VOP3Op_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6206,7 +6206,7 @@ def _VOP3Op_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6226,7 +6226,7 @@ def _VOP3Op_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6247,7 +6247,7 @@ def _VOP3Op_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6267,7 +6267,7 @@ def _VOP3Op_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6287,7 +6287,7 @@ def _VOP3Op_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6308,7 +6308,7 @@ def _VOP3Op_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6329,7 +6329,7 @@ def _VOP3Op_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6350,7 +6350,7 @@ def _VOP3Op_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6371,7 +6371,7 @@ def _VOP3Op_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6393,7 +6393,7 @@ def _VOP3Op_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6414,7 +6414,7 @@ def _VOP3Op_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6436,7 +6436,7 @@ def _VOP3Op_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6458,7 +6458,7 @@ def _VOP3Op_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6477,7 +6477,7 @@ def _VOP3Op_V_CMP_T_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6498,7 +6498,7 @@ def _VOP3Op_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6519,7 +6519,7 @@ def _VOP3Op_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6539,7 +6539,7 @@ def _VOP3Op_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6560,7 +6560,7 @@ def _VOP3Op_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6581,7 +6581,7 @@ def _VOP3Op_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6601,7 +6601,7 @@ def _VOP3Op_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6622,7 +6622,7 @@ def _VOP3Op_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6643,7 +6643,7 @@ def _VOP3Op_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6663,7 +6663,7 @@ def _VOP3Op_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6684,7 +6684,7 @@ def _VOP3Op_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6705,7 +6705,7 @@ def _VOP3Op_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6725,7 +6725,7 @@ def _VOP3Op_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6744,7 +6744,7 @@ def _VOP3Op_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6765,7 +6765,7 @@ def _VOP3Op_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6786,7 +6786,7 @@ def _VOP3Op_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6806,7 +6806,7 @@ def _VOP3Op_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6827,7 +6827,7 @@ def _VOP3Op_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6848,7 +6848,7 @@ def _VOP3Op_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6868,7 +6868,7 @@ def _VOP3Op_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6887,7 +6887,7 @@ def _VOP3Op_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6906,7 +6906,7 @@ def _VOP3Op_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6927,7 +6927,7 @@ def _VOP3Op_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6948,7 +6948,7 @@ def _VOP3Op_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6968,7 +6968,7 @@ def _VOP3Op_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6989,7 +6989,7 @@ def _VOP3Op_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7010,7 +7010,7 @@ def _VOP3Op_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7030,7 +7030,7 @@ def _VOP3Op_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7049,7 +7049,7 @@ def _VOP3Op_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7068,7 +7068,7 @@ def _VOP3Op_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7089,7 +7089,7 @@ def _VOP3Op_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7110,7 +7110,7 @@ def _VOP3Op_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7130,7 +7130,7 @@ def _VOP3Op_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7151,7 +7151,7 @@ def _VOP3Op_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7172,7 +7172,7 @@ def _VOP3Op_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7192,7 +7192,7 @@ def _VOP3Op_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7211,7 +7211,7 @@ def _VOP3Op_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7230,7 +7230,7 @@ def _VOP3Op_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7251,7 +7251,7 @@ def _VOP3Op_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7272,7 +7272,7 @@ def _VOP3Op_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7292,7 +7292,7 @@ def _VOP3Op_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7313,7 +7313,7 @@ def _VOP3Op_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7334,7 +7334,7 @@ def _VOP3Op_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7354,7 +7354,7 @@ def _VOP3Op_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7373,7 +7373,7 @@ def _VOP3Op_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7434,7 +7434,7 @@ def _VOP3Op_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7495,7 +7495,7 @@ def _VOP3Op_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7556,7 +7556,7 @@ def _VOP3Op_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12939,7 +12939,7 @@ def _VOP3SDOp_V_DIV_SCALE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal if S0.f32 == S1.f32: D0.f32 = ldexp(S0.f32, 64) elif False: - pass # denorm check moved to end + pass elif ((1.0 / F(S1.f32) == DENORM.f64) and (S2.f32 / S1.f32 == DENORM.f32)): VCC = Reg(0x1) if S0.f32 == S1.f32: @@ -13002,7 +13002,7 @@ def _VOP3SDOp_V_DIV_SCALE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal if S0.f64 == S1.f64: D0.f64 = ldexp(S0.f64, 128) elif False: - pass # denorm check moved to end + pass elif ((1.0 / S1.f64 == DENORM.f64) and (S2.f64 / S1.f64 == DENORM.f64)): VCC = Reg(0x1) if S0.f64 == S1.f64: @@ -13570,7 +13570,7 @@ def _VOPCOp_V_CMP_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13591,7 +13591,7 @@ def _VOPCOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13612,7 +13612,7 @@ def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13632,7 +13632,7 @@ def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13653,7 +13653,7 @@ def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13673,7 +13673,7 @@ def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13693,7 +13693,7 @@ def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13714,7 +13714,7 @@ def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13735,7 +13735,7 @@ def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13756,7 +13756,7 @@ def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13777,7 +13777,7 @@ def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13799,7 +13799,7 @@ def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13820,7 +13820,7 @@ def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13842,7 +13842,7 @@ def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13864,7 +13864,7 @@ def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13883,7 +13883,7 @@ def _VOPCOp_V_CMP_T_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13902,7 +13902,7 @@ def _VOPCOp_V_CMP_F_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13923,7 +13923,7 @@ def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13944,7 +13944,7 @@ def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13964,7 +13964,7 @@ def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13985,7 +13985,7 @@ def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14005,7 +14005,7 @@ def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14025,7 +14025,7 @@ def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14046,7 +14046,7 @@ def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14067,7 +14067,7 @@ def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14088,7 +14088,7 @@ def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14109,7 +14109,7 @@ def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14131,7 +14131,7 @@ def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14152,7 +14152,7 @@ def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14174,7 +14174,7 @@ def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14196,7 +14196,7 @@ def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14215,7 +14215,7 @@ def _VOPCOp_V_CMP_T_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14234,7 +14234,7 @@ def _VOPCOp_V_CMP_F_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14255,7 +14255,7 @@ def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14276,7 +14276,7 @@ def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14296,7 +14296,7 @@ def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14317,7 +14317,7 @@ def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14337,7 +14337,7 @@ def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14357,7 +14357,7 @@ def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14378,7 +14378,7 @@ def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14399,7 +14399,7 @@ def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14420,7 +14420,7 @@ def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14441,7 +14441,7 @@ def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14463,7 +14463,7 @@ def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14484,7 +14484,7 @@ def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14506,7 +14506,7 @@ def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14528,7 +14528,7 @@ def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14547,7 +14547,7 @@ def _VOPCOp_V_CMP_T_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14568,7 +14568,7 @@ def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14589,7 +14589,7 @@ def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14609,7 +14609,7 @@ def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14630,7 +14630,7 @@ def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14651,7 +14651,7 @@ def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14671,7 +14671,7 @@ def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14692,7 +14692,7 @@ def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14713,7 +14713,7 @@ def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14733,7 +14733,7 @@ def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14754,7 +14754,7 @@ def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14775,7 +14775,7 @@ def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14795,7 +14795,7 @@ def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14814,7 +14814,7 @@ def _VOPCOp_V_CMP_F_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14835,7 +14835,7 @@ def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14856,7 +14856,7 @@ def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14876,7 +14876,7 @@ def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14897,7 +14897,7 @@ def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14918,7 +14918,7 @@ def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14938,7 +14938,7 @@ def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14957,7 +14957,7 @@ def _VOPCOp_V_CMP_T_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14976,7 +14976,7 @@ def _VOPCOp_V_CMP_F_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14997,7 +14997,7 @@ def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15018,7 +15018,7 @@ def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15038,7 +15038,7 @@ def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15059,7 +15059,7 @@ def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15080,7 +15080,7 @@ def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15100,7 +15100,7 @@ def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15119,7 +15119,7 @@ def _VOPCOp_V_CMP_T_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15138,7 +15138,7 @@ def _VOPCOp_V_CMP_F_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15159,7 +15159,7 @@ def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15180,7 +15180,7 @@ def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15200,7 +15200,7 @@ def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15221,7 +15221,7 @@ def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15242,7 +15242,7 @@ def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15262,7 +15262,7 @@ def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15281,7 +15281,7 @@ def _VOPCOp_V_CMP_T_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15300,7 +15300,7 @@ def _VOPCOp_V_CMP_F_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15321,7 +15321,7 @@ def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15342,7 +15342,7 @@ def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15362,7 +15362,7 @@ def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15383,7 +15383,7 @@ def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15404,7 +15404,7 @@ def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15424,7 +15424,7 @@ def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15443,7 +15443,7 @@ def _VOPCOp_V_CMP_T_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15504,7 +15504,7 @@ def _VOPCOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15565,7 +15565,7 @@ def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15626,7 +15626,7 @@ def _VOPCOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_F_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -17179,7 +17179,7 @@ VOPCOp_FUNCTIONS = { # V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): - wr_lane = s1 & 0x1f # lane select (5 bits for wave32) + wr_lane = s1 & 0x1f return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)} VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32 diff --git a/extra/assembly/amd/autogen/rdna4/__init__.py b/extra/assembly/amd/autogen/rdna4/__init__.py index 898c789549..72b42cae8a 100644 --- a/extra/assembly/amd/autogen/rdna4/__init__.py +++ b/extra/assembly/amd/autogen/rdna4/__init__.py @@ -1,4 +1,4 @@ -# autogenerated from AMD RDNA4 ISA PDF by dsl.py - do not edit +# autogenerated from AMD RDNA4 ISA PDF by pdf.py - do not edit from enum import IntEnum from typing import Annotated from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField diff --git a/extra/assembly/amd/autogen/rdna4/gen_pcode.py b/extra/assembly/amd/autogen/rdna4/gen_pcode.py index 4f8633e01f..76930f5223 100644 --- a/extra/assembly/amd/autogen/rdna4/gen_pcode.py +++ b/extra/assembly/amd/autogen/rdna4/gen_pcode.py @@ -1,5 +1,5 @@ -# autogenerated by pcode.py - do not edit -# to regenerate: python -m extra.assembly.amd.pcode --arch rdna4 +# autogenerated by pdf.py - do not edit +# to regenerate: python -m extra.assembly.amd.pdf --arch rdna4 # ruff: noqa: E501,F405,F403 # mypy: ignore-errors from extra.assembly.amd.autogen.rdna4 import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp @@ -1051,7 +1051,7 @@ def _SOP1Op_S_GETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1063,7 +1063,7 @@ def _SOP1Op_S_SETPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1081,7 +1081,7 @@ def _SOP1Op_S_SWAPPC_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -1093,7 +1093,7 @@ def _SOP1Op_S_RFE_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOP1Op_S_SENDMSG_RTN_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3410,7 +3410,7 @@ def _SOPKOp_S_CALL_B64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, result = {'d0': D0._val, 'scc': scc & 1} result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result SOPKOp_FUNCTIONS = { @@ -3455,7 +3455,7 @@ def _SOPPOp_S_TRAP(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _va # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_BARRIER_WAIT(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3478,7 +3478,7 @@ def _SOPPOp_S_BRANCH(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _ # --- end pseudocode --- result = {'d0': d0, 'scc': scc & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3498,7 +3498,7 @@ def _SOPPOp_S_CBRANCH_SCC0(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3518,7 +3518,7 @@ def _SOPPOp_S_CBRANCH_SCC1(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V # --- end pseudocode --- result = {'d0': d0, 'scc': SCC._val & 1} _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3541,7 +3541,7 @@ def _SOPPOp_S_CBRANCH_VCCZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, V result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3564,7 +3564,7 @@ def _SOPPOp_S_CBRANCH_VCCNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1 _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3586,7 +3586,7 @@ def _SOPPOp_S_CBRANCH_EXECZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -3608,7 +3608,7 @@ def _SOPPOp_S_CBRANCH_EXECNZ(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result = {'d0': d0, 'scc': scc & 1} if EXEC._val != exec_mask: result['exec'] = EXEC._val _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result SOPPOp_FUNCTIONS = { @@ -5578,7 +5578,7 @@ def _VOP3Op_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5599,7 +5599,7 @@ def _VOP3Op_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5619,7 +5619,7 @@ def _VOP3Op_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5640,7 +5640,7 @@ def _VOP3Op_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5660,7 +5660,7 @@ def _VOP3Op_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5680,7 +5680,7 @@ def _VOP3Op_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5701,7 +5701,7 @@ def _VOP3Op_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5722,7 +5722,7 @@ def _VOP3Op_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5743,7 +5743,7 @@ def _VOP3Op_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5764,7 +5764,7 @@ def _VOP3Op_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5786,7 +5786,7 @@ def _VOP3Op_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5807,7 +5807,7 @@ def _VOP3Op_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5829,7 +5829,7 @@ def _VOP3Op_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5851,7 +5851,7 @@ def _VOP3Op_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5872,7 +5872,7 @@ def _VOP3Op_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5893,7 +5893,7 @@ def _VOP3Op_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5913,7 +5913,7 @@ def _VOP3Op_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5934,7 +5934,7 @@ def _VOP3Op_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5954,7 +5954,7 @@ def _VOP3Op_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5974,7 +5974,7 @@ def _VOP3Op_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -5995,7 +5995,7 @@ def _VOP3Op_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6016,7 +6016,7 @@ def _VOP3Op_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6037,7 +6037,7 @@ def _VOP3Op_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6058,7 +6058,7 @@ def _VOP3Op_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6080,7 +6080,7 @@ def _VOP3Op_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6101,7 +6101,7 @@ def _VOP3Op_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6123,7 +6123,7 @@ def _VOP3Op_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6145,7 +6145,7 @@ def _VOP3Op_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6166,7 +6166,7 @@ def _VOP3Op_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6187,7 +6187,7 @@ def _VOP3Op_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6207,7 +6207,7 @@ def _VOP3Op_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6228,7 +6228,7 @@ def _VOP3Op_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6248,7 +6248,7 @@ def _VOP3Op_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6268,7 +6268,7 @@ def _VOP3Op_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6289,7 +6289,7 @@ def _VOP3Op_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6310,7 +6310,7 @@ def _VOP3Op_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6331,7 +6331,7 @@ def _VOP3Op_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6352,7 +6352,7 @@ def _VOP3Op_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6374,7 +6374,7 @@ def _VOP3Op_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6395,7 +6395,7 @@ def _VOP3Op_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6417,7 +6417,7 @@ def _VOP3Op_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6439,7 +6439,7 @@ def _VOP3Op_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6460,7 +6460,7 @@ def _VOP3Op_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6481,7 +6481,7 @@ def _VOP3Op_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6501,7 +6501,7 @@ def _VOP3Op_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6522,7 +6522,7 @@ def _VOP3Op_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6543,7 +6543,7 @@ def _VOP3Op_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6563,7 +6563,7 @@ def _VOP3Op_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6584,7 +6584,7 @@ def _VOP3Op_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6605,7 +6605,7 @@ def _VOP3Op_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6625,7 +6625,7 @@ def _VOP3Op_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6646,7 +6646,7 @@ def _VOP3Op_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6667,7 +6667,7 @@ def _VOP3Op_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6687,7 +6687,7 @@ def _VOP3Op_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6708,7 +6708,7 @@ def _VOP3Op_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6729,7 +6729,7 @@ def _VOP3Op_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6749,7 +6749,7 @@ def _VOP3Op_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6770,7 +6770,7 @@ def _VOP3Op_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6791,7 +6791,7 @@ def _VOP3Op_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6811,7 +6811,7 @@ def _VOP3Op_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6832,7 +6832,7 @@ def _VOP3Op_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6853,7 +6853,7 @@ def _VOP3Op_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6873,7 +6873,7 @@ def _VOP3Op_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6894,7 +6894,7 @@ def _VOP3Op_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6915,7 +6915,7 @@ def _VOP3Op_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6935,7 +6935,7 @@ def _VOP3Op_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6956,7 +6956,7 @@ def _VOP3Op_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6977,7 +6977,7 @@ def _VOP3Op_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -6997,7 +6997,7 @@ def _VOP3Op_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7018,7 +7018,7 @@ def _VOP3Op_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7039,7 +7039,7 @@ def _VOP3Op_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7059,7 +7059,7 @@ def _VOP3Op_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7080,7 +7080,7 @@ def _VOP3Op_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7101,7 +7101,7 @@ def _VOP3Op_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7121,7 +7121,7 @@ def _VOP3Op_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7142,7 +7142,7 @@ def _VOP3Op_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7163,7 +7163,7 @@ def _VOP3Op_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7183,7 +7183,7 @@ def _VOP3Op_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7244,7 +7244,7 @@ def _VOP3Op_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7305,7 +7305,7 @@ def _VOP3Op_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -7366,7 +7366,7 @@ def _VOP3Op_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOP3Op_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -12983,7 +12983,7 @@ def _VOP3SDOp_V_DIV_SCALE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal if S0.f32 == S1.f32: D0.f32 = ldexp(S0.f32, 64) elif False: - pass # denorm check moved to end + pass elif ((1.0 / F(S1.f32) == DENORM.f64) and (S2.f32 / S1.f32 == DENORM.f32)): VCC = Reg(0x1) if S0.f32 == S1.f32: @@ -13046,7 +13046,7 @@ def _VOP3SDOp_V_DIV_SCALE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal if S0.f64 == S1.f64: D0.f64 = ldexp(S0.f64, 128) elif False: - pass # denorm check moved to end + pass elif ((1.0 / S1.f64 == DENORM.f64) and (S2.f64 / S1.f64 == DENORM.f64)): VCC = Reg(0x1) if S0.f64 == S1.f64: @@ -13762,7 +13762,7 @@ def _VOPCOp_V_CMP_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13783,7 +13783,7 @@ def _VOPCOp_V_CMP_EQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13803,7 +13803,7 @@ def _VOPCOp_V_CMP_LE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13824,7 +13824,7 @@ def _VOPCOp_V_CMP_GT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13844,7 +13844,7 @@ def _VOPCOp_V_CMP_LG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13864,7 +13864,7 @@ def _VOPCOp_V_CMP_GE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13885,7 +13885,7 @@ def _VOPCOp_V_CMP_O_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13906,7 +13906,7 @@ def _VOPCOp_V_CMP_U_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13927,7 +13927,7 @@ def _VOPCOp_V_CMP_NGE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13948,7 +13948,7 @@ def _VOPCOp_V_CMP_NLG_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13970,7 +13970,7 @@ def _VOPCOp_V_CMP_NGT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -13991,7 +13991,7 @@ def _VOPCOp_V_CMP_NLE_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14013,7 +14013,7 @@ def _VOPCOp_V_CMP_NEQ_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14035,7 +14035,7 @@ def _VOPCOp_V_CMP_NLT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14056,7 +14056,7 @@ def _VOPCOp_V_CMP_LT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14077,7 +14077,7 @@ def _VOPCOp_V_CMP_EQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14097,7 +14097,7 @@ def _VOPCOp_V_CMP_LE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14118,7 +14118,7 @@ def _VOPCOp_V_CMP_GT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14138,7 +14138,7 @@ def _VOPCOp_V_CMP_LG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14158,7 +14158,7 @@ def _VOPCOp_V_CMP_GE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14179,7 +14179,7 @@ def _VOPCOp_V_CMP_O_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14200,7 +14200,7 @@ def _VOPCOp_V_CMP_U_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14221,7 +14221,7 @@ def _VOPCOp_V_CMP_NGE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14242,7 +14242,7 @@ def _VOPCOp_V_CMP_NLG_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14264,7 +14264,7 @@ def _VOPCOp_V_CMP_NGT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14285,7 +14285,7 @@ def _VOPCOp_V_CMP_NLE_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14307,7 +14307,7 @@ def _VOPCOp_V_CMP_NEQ_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14329,7 +14329,7 @@ def _VOPCOp_V_CMP_NLT_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14350,7 +14350,7 @@ def _VOPCOp_V_CMP_LT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14371,7 +14371,7 @@ def _VOPCOp_V_CMP_EQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14391,7 +14391,7 @@ def _VOPCOp_V_CMP_LE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14412,7 +14412,7 @@ def _VOPCOp_V_CMP_GT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14432,7 +14432,7 @@ def _VOPCOp_V_CMP_LG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14452,7 +14452,7 @@ def _VOPCOp_V_CMP_GE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14473,7 +14473,7 @@ def _VOPCOp_V_CMP_O_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14494,7 +14494,7 @@ def _VOPCOp_V_CMP_U_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14515,7 +14515,7 @@ def _VOPCOp_V_CMP_NGE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14536,7 +14536,7 @@ def _VOPCOp_V_CMP_NLG_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14558,7 +14558,7 @@ def _VOPCOp_V_CMP_NGT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14579,7 +14579,7 @@ def _VOPCOp_V_CMP_NLE_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14601,7 +14601,7 @@ def _VOPCOp_V_CMP_NEQ_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14623,7 +14623,7 @@ def _VOPCOp_V_CMP_NLT_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VG result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14644,7 +14644,7 @@ def _VOPCOp_V_CMP_LT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14665,7 +14665,7 @@ def _VOPCOp_V_CMP_EQ_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14685,7 +14685,7 @@ def _VOPCOp_V_CMP_LE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14706,7 +14706,7 @@ def _VOPCOp_V_CMP_GT_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14727,7 +14727,7 @@ def _VOPCOp_V_CMP_NE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14747,7 +14747,7 @@ def _VOPCOp_V_CMP_GE_I16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14768,7 +14768,7 @@ def _VOPCOp_V_CMP_LT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14789,7 +14789,7 @@ def _VOPCOp_V_CMP_EQ_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14809,7 +14809,7 @@ def _VOPCOp_V_CMP_LE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14830,7 +14830,7 @@ def _VOPCOp_V_CMP_GT_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14851,7 +14851,7 @@ def _VOPCOp_V_CMP_NE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14871,7 +14871,7 @@ def _VOPCOp_V_CMP_GE_U16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14892,7 +14892,7 @@ def _VOPCOp_V_CMP_LT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14913,7 +14913,7 @@ def _VOPCOp_V_CMP_EQ_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14933,7 +14933,7 @@ def _VOPCOp_V_CMP_LE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14954,7 +14954,7 @@ def _VOPCOp_V_CMP_GT_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14975,7 +14975,7 @@ def _VOPCOp_V_CMP_NE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -14995,7 +14995,7 @@ def _VOPCOp_V_CMP_GE_I32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15016,7 +15016,7 @@ def _VOPCOp_V_CMP_LT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15037,7 +15037,7 @@ def _VOPCOp_V_CMP_EQ_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15057,7 +15057,7 @@ def _VOPCOp_V_CMP_LE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15078,7 +15078,7 @@ def _VOPCOp_V_CMP_GT_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15099,7 +15099,7 @@ def _VOPCOp_V_CMP_NE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15119,7 +15119,7 @@ def _VOPCOp_V_CMP_GE_U32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15140,7 +15140,7 @@ def _VOPCOp_V_CMP_LT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15161,7 +15161,7 @@ def _VOPCOp_V_CMP_EQ_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15181,7 +15181,7 @@ def _VOPCOp_V_CMP_LE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15202,7 +15202,7 @@ def _VOPCOp_V_CMP_GT_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15223,7 +15223,7 @@ def _VOPCOp_V_CMP_NE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15243,7 +15243,7 @@ def _VOPCOp_V_CMP_GE_I64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15264,7 +15264,7 @@ def _VOPCOp_V_CMP_LT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15285,7 +15285,7 @@ def _VOPCOp_V_CMP_EQ_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15305,7 +15305,7 @@ def _VOPCOp_V_CMP_LE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15326,7 +15326,7 @@ def _VOPCOp_V_CMP_GT_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15347,7 +15347,7 @@ def _VOPCOp_V_CMP_NE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15367,7 +15367,7 @@ def _VOPCOp_V_CMP_GE_U64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGP result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15428,7 +15428,7 @@ def _VOPCOp_V_CMP_CLASS_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15489,7 +15489,7 @@ def _VOPCOp_V_CMP_CLASS_F32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -15550,7 +15550,7 @@ def _VOPCOp_V_CMP_CLASS_F64(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, result['vcc_lane'] = (D0._val >> lane) & 1 result['d0_64'] = True _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000 - result['new_pc'] = _pc # absolute byte address + result['new_pc'] = _pc return result def _VOPCOp_V_CMPX_LT_F16(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0): @@ -16921,7 +16921,7 @@ VOPCOp_FUNCTIONS = { # V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): - wr_lane = s1 & 0x1f # lane select (5 bits for wave32) + wr_lane = s1 & 0x1f return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)} VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32 diff --git a/extra/assembly/amd/dsl.py b/extra/assembly/amd/dsl.py index d4ac98f431..4ae1fbc8f0 100644 --- a/extra/assembly/amd/dsl.py +++ b/extra/assembly/amd/dsl.py @@ -1,9 +1,33 @@ # library for RDNA3 assembly DSL # mypy: ignore-errors from __future__ import annotations +import struct, math from enum import IntEnum from typing import overload, Annotated, TypeVar, Generic +# Common masks and bit conversion functions +MASK32, MASK64 = 0xffffffff, 0xffffffffffffffff +def _f32(i): return struct.unpack(" 0 else 0xff800000 + try: return struct.unpack(" 0 else 0xff800000 +def _sext(v, b): return v - (1 << b) if v & (1 << (b - 1)) else v +def _f16(i): return struct.unpack(" 0 else 0xfc00 + try: return struct.unpack(" 0 else 0xfc00 +def _f64(i): return struct.unpack(" 0 else 0xfff0000000000000 + try: return struct.unpack(" 0 else 0xfff0000000000000 + # Bit field DSL class BitField: def __init__(self, hi: int, lo: int, name: str | None = None): self.hi, self.lo, self.name, self._marker = hi, lo, name, None @@ -112,31 +136,36 @@ def unwrap(val) -> int: if hasattr(val, 'idx'): return val.idx # Reg return val -# Encoding helpers +# Encoding/decoding constants FLOAT_ENC = {0.5: 240, -0.5: 241, 1.0: 242, -1.0: 243, 2.0: 244, -2.0: 245, 4.0: 246, -4.0: 247} +FLOAT_DEC = {v: str(k) for k, v in FLOAT_ENC.items()} +SPECIAL_GPRS = {106: "vcc_lo", 107: "vcc_hi", 124: "null", 125: "m0", 126: "exec_lo", 127: "exec_hi", 253: "scc"} +SPECIAL_PAIRS = {106: "vcc", 126: "exec"} SRC_FIELDS = {'src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'soffset', 'srcx0', 'srcy0'} RAW_FIELDS = {'vdata', 'vdst', 'vaddr', 'addr', 'data', 'data0', 'data1', 'sdst', 'sdata', 'vsrc1'} -def _encode_reg(val: Reg) -> int: - if isinstance(val, TTMP): return 108 + val.idx - return val.idx # hi bit is handled via opsel, not in register encoding +def _encode_reg(val: Reg) -> int: return (108 if isinstance(val, TTMP) else 0) + val.idx + +def _is_inline_const(v: int) -> bool: return 0 <= v <= 127 or 128 <= v <= 208 or 240 <= v <= 255 def encode_src(val) -> int: if isinstance(val, VGPR): return 256 + _encode_reg(val) if isinstance(val, Reg): return _encode_reg(val) - if isinstance(val, SrcMod) and not isinstance(val, Reg): - # SrcMod wraps either special registers (VCC_LO=106, EXEC_LO=126, etc.) or literals - # Special register values are in valid encoding ranges - return as-is - # Literals (large integers) need 255 marker - v = val.val - # Valid source encoding ranges: 0-127 (SGPRs/special), 128-192 (inline const), 193-208 (neg inline), 240-247 (float), 251-253 (special) - if 0 <= v <= 127 or 240 <= v <= 255: return v # SGPRs, special regs, float constants - if 128 <= v <= 192: return v # Inline positive constants (0-64) - if 193 <= v <= 208: return v # Inline negative constants (-1 to -16) - return 255 # Literal marker - value stored separately + if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val if _is_inline_const(val.val) else 255 if hasattr(val, 'value'): return val.value # IntEnum if isinstance(val, float): return 128 if val == 0.0 else FLOAT_ENC.get(val, 255) - return 128 + val if isinstance(val, int) and 0 <= val <= 64 else 192 + (-val) if isinstance(val, int) and -16 <= val <= -1 else 255 + if isinstance(val, int): return 128 + val if 0 <= val <= 64 else 192 - val if -16 <= val <= -1 else 255 + return 255 + +def decode_src(val: int) -> str: + if val <= 105: return f"s{val}" + if val in SPECIAL_GPRS: return SPECIAL_GPRS[val] + if val in FLOAT_DEC: return FLOAT_DEC[val] + if 108 <= val <= 123: return f"ttmp{val - 108}" + if 128 <= val <= 192: return str(val - 128) + if 193 <= val <= 208: return str(-(val - 192)) + if 256 <= val <= 511: return f"v{val - 256}" + return "lit" if val == 255 else f"?{val}" # Instruction base class class Inst: @@ -152,119 +181,94 @@ class Inst: cls._fields = {n: v[0] if isinstance(v, tuple) else v for n, v in cls.__dict__.items() if isinstance(v, BitField) or (isinstance(v, tuple) and len(v) == 2 and isinstance(v[0], BitField))} if 'encoding' in cls._fields and isinstance(cls.__dict__.get('encoding'), tuple): cls._encoding = cls.__dict__['encoding'] + def _or_field(self, name: str, bit: int): + cur = self._values.get(name, 0) + self._values[name] = (cur.val if isinstance(cur, RawImm) else cur) | bit + + def _encode_src(self, name: str, val): + """Encode a source field, handling modifiers and literals.""" + encoded = encode_src(val) + has_opsel = 'opsel' in self._fields + if isinstance(val, Reg) and val.hi and not has_opsel: encoded |= 0x80 # hi bit in src for VOP1/2/C + self._values[name] = RawImm(encoded) + # Handle neg/abs/opsel modifiers + if isinstance(val, SrcMod): + mod_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0) + if val.neg and 'neg' in self._fields: self._or_field('neg', mod_bit) + if val.abs_ and 'abs' in self._fields: self._or_field('abs', mod_bit) + if isinstance(val, Reg) and val.hi and has_opsel: + self._or_field('opsel', {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0)) + # Track literal value if needed + if encoded == 255 and self._literal is None: + import struct + is_64 = self._is_64bit_op() + if isinstance(val, SrcMod) and not isinstance(val, Reg): lit32 = val.val & MASK32 + elif isinstance(val, int) and not isinstance(val, IntEnum): lit32 = val & MASK32 + elif isinstance(val, float): lit32 = _i32(val) + else: return + self._literal = (lit32 << 32) if is_64 else lit32 + + def _encode_raw(self, name: str, val): + """Encode a raw register field (vdst, vdata, etc.).""" + if isinstance(val, Reg): + encoded = _encode_reg(val) + if val.hi and 'opsel' not in self._fields: encoded |= 0x80 + self._values[name] = encoded + if name == 'vdst' and val.hi and 'opsel' in self._fields: self._or_field('opsel', 8) + elif hasattr(val, 'value'): self._values[name] = val.value + + def _validate(self, orig_args: dict): + """Format-specific validation. Override in subclass or check by class name.""" + cls_name, op = self.__class__.__name__, orig_args.get('op') + if hasattr(op, 'value'): op = op.value + # SMEM: register count must match opcode + if cls_name == 'SMEM' and op is not None: + expected = {0:1, 1:2, 2:4, 3:8, 4:16, 8:1, 9:2, 10:4, 11:8, 12:16}.get(op) + sdata = orig_args.get('sdata') + if expected and isinstance(sdata, Reg) and sdata.count != expected: + raise ValueError(f"SMEM op {op} expects {expected} registers, got {sdata.count}") + # SOP1: b32=1 reg, b64=2 regs + if cls_name == 'SOP1' and hasattr(orig_args.get('op'), 'name'): + expected = 2 if orig_args['op'].name.endswith('_B64') else 1 + for fld in ('sdst', 'ssrc0'): + if isinstance(orig_args.get(fld), Reg) and orig_args[fld].count != expected: + raise ValueError(f"SOP1 {orig_args['op'].name} expects {expected} register(s) for {fld}, got {orig_args[fld].count}") + def __init__(self, *args, literal: int | None = None, **kwargs): self._values, self._literal = dict(self._defaults), literal - # Map positional args to field names field_names = [n for n in self._fields if n != 'encoding'] - orig_args = dict(zip(field_names, args)) - orig_args.update(kwargs) + orig_args = dict(zip(field_names, args)) | kwargs self._values.update(orig_args) - # Validate register counts for SMEM instructions (before encoding) - if self.__class__.__name__ == 'SMEM': - op_val = orig_args.get(field_names[0]) if args else orig_args.get('op') - if op_val is not None: - if hasattr(op_val, 'value'): op_val = op_val.value - expected_cnt = {0:1, 1:2, 2:4, 3:8, 4:16, 8:1, 9:2, 10:4, 11:8, 12:16}.get(op_val) - sdata_val = orig_args.get('sdata') - if expected_cnt is not None and isinstance(sdata_val, Reg) and sdata_val.count != expected_cnt: - raise ValueError(f"SMEM op {op_val} expects {expected_cnt} registers, got {sdata_val.count}") - # Validate register counts for SOP1 instructions (b32 = 1 reg, b64 = 2 regs) - if self.__class__.__name__ == 'SOP1': - op_val = orig_args.get(field_names[0]) if args else orig_args.get('op') - if op_val is not None and hasattr(op_val, 'name'): - expected = 2 if op_val.name.endswith('_B64') else 1 - sdst_val, ssrc0_val = orig_args.get('sdst'), orig_args.get('ssrc0') - if isinstance(sdst_val, Reg) and sdst_val.count != expected: - raise ValueError(f"SOP1 {op_val.name} expects {expected} destination register(s), got {sdst_val.count}") - if isinstance(ssrc0_val, Reg) and ssrc0_val.count != expected: - raise ValueError(f"SOP1 {op_val.name} expects {expected} source register(s), got {ssrc0_val.count}") - # FLAT: set sve=1 when addr is a VGPR for scratch only - # For scratch (seg=1), sve=1 means addr VGPR is used; sve=0 means addr is "off" - # For global (seg=2) and flat (seg=0), sve is always 0 - if self.__class__.__name__ == 'FLAT' and 'sve' in self._fields: - seg_val = self._values.get('seg', 0) - if isinstance(seg_val, RawImm): seg_val = seg_val.val - addr_val = orig_args.get('addr') - if seg_val == 1 and isinstance(addr_val, VGPR): self._values['sve'] = 1 - # VOP3P: v_fma_mix* instructions (opcodes 32-34) have opsel_hi default of 0, not 7 - if self.__class__.__name__ == 'VOP3P': - op_val = orig_args.get(field_names[0]) if args else orig_args.get('op') - if hasattr(op_val, 'value'): op_val = op_val.value - if op_val in (32, 33, 34) and 'opsel_hi' not in orig_args and 'opsel_hi2' not in orig_args: - self._values['opsel_hi'] = 0 - self._values['opsel_hi2'] = 0 - # Type check and encode values + self._validate(orig_args) + cls_name = self.__class__.__name__ + + # Format-specific setup + if cls_name == 'FLAT' and 'sve' in self._fields: + seg = self._values.get('seg', 0) + if (seg.val if isinstance(seg, RawImm) else seg) == 1 and isinstance(orig_args.get('addr'), VGPR): self._values['sve'] = 1 + if cls_name == 'VOP3P': + op = orig_args.get('op') + if hasattr(op, 'value'): op = op.value + if op in (32, 33, 34) and 'opsel_hi' not in orig_args: self._values['opsel_hi'] = self._values['opsel_hi2'] = 0 + + # Encode all fields for name, val in list(self._values.items()): if name == 'encoding': continue - # For RawImm, only process RAW_FIELDS to unwrap to int if isinstance(val, RawImm): if name in RAW_FIELDS: self._values[name] = val.val continue field = self._fields.get(name) marker = field.marker if field else None # Type validation - if marker is _SGPRField: - if isinstance(val, VGPR): raise TypeError(f"field '{name}' requires SGPR, got VGPR") - if not isinstance(val, (SGPR, TTMP, SrcMod, int, RawImm)): raise TypeError(f"field '{name}' requires SGPR, got {type(val).__name__}") - if marker is _VGPRField: - if not isinstance(val, VGPR): raise TypeError(f"field '{name}' requires VGPR, got {type(val).__name__}") + if marker is _SGPRField and isinstance(val, VGPR): raise TypeError(f"field '{name}' requires SGPR, got VGPR") + if marker is _VGPRField and not isinstance(val, VGPR): raise TypeError(f"field '{name}' requires VGPR, got {type(val).__name__}") if marker is _SSrc and isinstance(val, VGPR): raise TypeError(f"field '{name}' requires scalar source, got VGPR") - # Encode source fields as RawImm for consistent disassembly - if name in SRC_FIELDS: - encoded = encode_src(val) - # For VOP1/VOP2/VOPC (no opsel field), encode hi bit in src value - if isinstance(val, Reg) and val.hi and 'opsel' not in self._fields: - encoded |= 0x80 - self._values[name] = RawImm(encoded) - # Handle neg/abs/opsel modifiers for VOP3 instructions - if isinstance(val, SrcMod): - if val.neg and 'neg' in self._fields: - neg_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0) - cur_neg = self._values.get('neg', 0) - self._values['neg'] = (cur_neg.val if isinstance(cur_neg, RawImm) else cur_neg) | neg_bit - if val.abs_ and 'abs' in self._fields: - abs_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0) - cur_abs = self._values.get('abs', 0) - self._values['abs'] = (cur_abs.val if isinstance(cur_abs, RawImm) else cur_abs) | abs_bit - # Handle hi (opsel) for 16-bit ops - only for formats with opsel field - if isinstance(val, Reg) and val.hi and 'opsel' in self._fields: - opsel_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0) - cur_opsel = self._values.get('opsel', 0) - self._values['opsel'] = (cur_opsel.val if isinstance(cur_opsel, RawImm) else cur_opsel) | opsel_bit - # Track literal value if needed (encoded as 255) - # For 64-bit ops, store literal in high 32 bits (to match from_bytes decoding and to_bytes encoding) - if encoded == 255 and self._literal is None: - if isinstance(val, SrcMod) and not isinstance(val, Reg): - # SrcMod wrapping a literal value - self._literal = (val.val << 32) if self._is_64bit_op() else val.val - elif isinstance(val, int) and not isinstance(val, IntEnum): - self._literal = (val << 32) if self._is_64bit_op() else val - elif isinstance(val, float): - import struct - lit32 = struct.unpack('> 1 (constraint: vdsty parity must be opposite of vdstx) - elif marker is _VDSTYEnc and isinstance(val, VGPR): - self._values[name] = val.idx >> 1 + # Encode by field type + if name in SRC_FIELDS: self._encode_src(name, val) + elif name in RAW_FIELDS: self._encode_raw(name, val) + elif name == 'sbase': self._values[name] = (val.idx if isinstance(val, Reg) else val.val if isinstance(val, SrcMod) else val * 2) // 2 + elif name in {'srsrc', 'ssamp'} and isinstance(val, Reg): self._values[name] = val.idx // 4 + elif marker is _VDSTYEnc and isinstance(val, VGPR): self._values[name] = val.idx >> 1 def _encode_field(self, name: str, val) -> int: if isinstance(val, RawImm): return val.val @@ -287,12 +291,11 @@ class Inst: return None def _is_64bit_op(self) -> bool: - """Check if this instruction uses 64-bit operands (and thus 64-bit literals). - Exception: V_LDEXP_F64 has 32-bit integer src1, so its literal is 32-bit.""" + """Check if this instruction uses 64-bit operands (and thus 64-bit literals).""" op = self._values.get('op') if op is None: return False - # op may be an enum (from __init__) or an int (from from_int) op_name = op.name if hasattr(op, 'name') else None + # Look up op name from int if needed (happens in from_bytes path) if op_name is None and self.__class__.__name__ == 'VOP3': from extra.assembly.amd.autogen.rdna3 import VOP3Op try: op_name = VOP3Op(op).name @@ -302,9 +305,8 @@ class Inst: try: op_name = VOPCOp(op).name except ValueError: pass if op_name is None: return False - # V_LDEXP_F64 has 32-bit integer exponent in src1, so literal is 32-bit - if op_name == 'V_LDEXP_F64': return False - return op_name.endswith(('_F64', '_B64', '_I64', '_U64')) + # V_LDEXP_F64 has 32-bit integer src1, so literal is 32-bit + return op_name != 'V_LDEXP_F64' and op_name.endswith(('_F64', '_B64', '_I64', '_U64')) def to_bytes(self) -> bytes: result = self.to_int().to_bytes(self._size(), 'little') @@ -312,7 +314,7 @@ class Inst: if lit is None: return result # For 64-bit ops, literal is stored in high 32 bits internally, but encoded as 4 bytes lit32 = (lit >> 32) if self._is_64bit_op() else lit - return result + (lit32 & 0xffffffff).to_bytes(4, 'little') + return result + (lit32 & MASK32).to_bytes(4, 'little') @classmethod def _size(cls) -> int: return 4 if issubclass(cls, Inst32) else 8 @@ -358,9 +360,7 @@ class Inst: if name.startswith('_'): raise AttributeError(name) return unwrap(self._values.get(name, 0)) - def lit(self, v: int) -> str: - from extra.assembly.amd.asm import decode_src - return f"0x{self._literal:x}" if v == 255 and self._literal else decode_src(v) + def lit(self, v: int) -> str: return f"0x{self._literal:x}" if v == 255 and self._literal else decode_src(v) def __eq__(self, other): if not isinstance(other, Inst): return NotImplemented @@ -374,310 +374,3 @@ class Inst: class Inst32(Inst): pass class Inst64(Inst): pass - -# ═══════════════════════════════════════════════════════════════════════════════ -# CODE GENERATION: generates autogen/__init__.py by parsing AMD ISA PDFs -# Supports both RDNA3.5 and CDNA4 instruction set PDFs - auto-detects format -# ═══════════════════════════════════════════════════════════════════════════════ - -PDF_URLS = { - "rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content", # RDNA3.5 - "rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content", - "cdna": ["https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf", - "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"], -} -FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src', - 'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField', 'VDATA': 'VGPRField', - 'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField', 'SIMM16': 'SImm', 'OFFSET': 'Imm', - 'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src', 'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'} -FIELD_ORDER = { - 'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'], - 'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'], - 'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'], - 'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'], - 'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'], - 'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'], - 'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'], - 'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'], - 'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'], - 'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'], - 'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'], - 'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'], - 'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'], - 'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']} -SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'} -FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO', - '4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'} - -def _parse_bits(s: str) -> tuple[int, int] | None: - import re - return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None - -def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]: - import re - fields = [] - for row in table[1:]: - if not row or not row[0]: continue - name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip() - if not (bits := _parse_bits(bits_str)): continue - enc_val, hi, lo = None, bits[0], bits[1] - if name == 'ENCODING' and row[2]: - # Handle both RDNA3 ('bXX) and CDNA4 (Must be: XX) encoding formats - if m := re.search(r"(?:'b|Must be:\s*)([01_]+)", row[2]): - enc_bits = m.group(1).replace('_', '') - enc_val = int(enc_bits, 2) - declared_width, actual_width = hi - lo + 1, len(enc_bits) - if actual_width > declared_width: lo = hi - actual_width + 1 - ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper()) - fields.append((name, hi, lo, enc_val, ftype)) - return fields - -def _parse_single_pdf(url: str) -> dict: - """Parse a single PDF and return raw data (formats, enums, src_enum, doc_name, is_cdna).""" - import re, pdfplumber - from tinygrad.helpers import fetch - - pdf = pdfplumber.open(fetch(url)) - - # Auto-detect document type from first page - first_page_text = pdf.pages[0].extract_text() or '' - is_cdna4 = 'CDNA4' in first_page_text or 'CDNA 4' in first_page_text - is_cdna3 = 'CDNA3' in first_page_text or 'CDNA 3' in first_page_text or 'MI300' in first_page_text - is_cdna = is_cdna3 or is_cdna4 - is_rdna4 = 'RDNA4' in first_page_text or 'RDNA 4' in first_page_text - is_rdna35 = 'RDNA3.5' in first_page_text or 'RDNA 3.5' in first_page_text # Check 3.5 before 3 - is_rdna3 = not is_rdna35 and ('RDNA3' in first_page_text or 'RDNA 3' in first_page_text) - doc_name = "CDNA4" if is_cdna4 else "CDNA3" if is_cdna3 else "RDNA4" if is_rdna4 else "RDNA3.5" if is_rdna35 else "RDNA3" if is_rdna3 else "Unknown" - - # Find the "Microcode Formats" section - search for SOP2 format definition - microcode_start = None - total_pages = len(pdf.pages) - # Search from likely locations (formats are typically 20-95% through the document - RDNA3 has them at ~25%) - for i in range(int(total_pages * 0.2), total_pages): - text = pdf.pages[i].extract_text() or '' - # Look for "X.Y.Z. SOP2" section header or "Chapter X. Microcode Formats" - if re.search(r'\d+\.\d+\.\d+\.\s+SOP2\b', text) or re.search(r'Chapter \d+\.\s+Microcode Formats', text): - microcode_start = i - break - if microcode_start is None: microcode_start = int(total_pages * 0.9) - - pages = pdf.pages[microcode_start:microcode_start + 50] - page_texts = [p.extract_text() or '' for p in pages] - page_tables = [[t.extract() for t in p.find_tables()] for p in pages] - full_text = '\n'.join(page_texts) - - # parse SSRC encoding from first page with VCC_LO - src_enum = dict(SRC_EXTRAS) - for text in page_texts[:10]: - if 'SSRC0' in text and 'VCC_LO' in text: - for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M): - val, name = int(m.group(1)), m.group(2).rstrip('.:') - if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name] - elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name - break - - # parse opcode tables - enums: dict[str, dict[int, str]] = {} - for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S): - if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}: - enums[m.group(1) + "Op"] = ops - if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S): - if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}: - enums["VOPDOp"] = ops - enum_names = set(enums.keys()) - - def is_fields_table(t) -> bool: return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '') - def has_encoding(fields) -> bool: return any(f[0] == 'ENCODING' for f in fields) - def has_header_before_fields(text) -> bool: - return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos])) - - # find format headers with their page indices - format_headers = [] - for i, text in enumerate(page_texts): - for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start())) - for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text): - fmt_name = m.group(1) - if is_cdna and fmt_name.isupper() and len(fmt_name) >= 2: - format_headers.append((fmt_name, i, m.start())) - elif m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < len(page_texts): - next_text = page_texts[i + 1].lstrip() - if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]): - format_headers.append((fmt_name, i, m.start())) - - # parse instruction formats - formats: dict[str, list] = {} - for fmt_name, page_idx, header_pos in format_headers: - if fmt_name in formats: continue - text, tables = page_texts[page_idx], page_tables[page_idx] - field_pos = text.find('Field Name', header_pos) - - fields = None - for offset in range(3): - if page_idx + offset >= len(pages): break - if offset > 0 and has_header_before_fields(page_texts[page_idx + offset]): break - for t in page_tables[page_idx + offset] if offset > 0 or field_pos > header_pos else []: - if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f): - fields = f - break - if fields: break - - if not fields and field_pos > header_pos: - for t in tables: - if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)): - fields = f - break - - if not fields: continue - field_names = {f[0] for f in fields} - - for pg_offset in range(1, 3): - if page_idx + pg_offset >= len(pages) or has_header_before_fields(page_texts[page_idx + pg_offset]): break - for t in page_tables[page_idx + pg_offset]: - if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra): - for ef in extra: - if ef[0] not in field_names: - fields.append(ef) - field_names.add(ef[0]) - break - formats[fmt_name] = fields - - # fix known PDF errors - assert if already present (so we know when the bug is fixed) - if 'SMEM' in formats: - formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t) - for n, h, l, e, t in formats['SMEM']] - # add missing opcodes not in PDF tables (RDNA3/RDNA3.5 specific) - if doc_name in ('RDNA3', 'RDNA3.5'): - if 'SOPPOp' in enums: - assert 8 not in enums['SOPPOp'], "S_WAITCNT_DEPCTR now in PDF, remove workaround" - enums['SOPPOp'][8] = 'S_WAITCNT_DEPCTR' - if 'DSOp' in enums: - gws_ops = {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', - 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'} - for k in gws_ops: assert k not in enums['DSOp'], f"{gws_ops[k]} now in PDF, remove workaround" - enums['DSOp'].update(gws_ops) - if 'FLATOp' in enums: - flat_ops = {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'} - for k in flat_ops: assert k not in enums['FLATOp'], f"{flat_ops[k]} now in PDF, remove workaround" - enums['FLATOp'].update(flat_ops) - - return {"formats": formats, "enums": enums, "src_enum": src_enum, "doc_name": doc_name, "is_cdna": is_cdna} - -def _merge_results(results: list[dict]) -> dict: - """Merge multiple PDF parse results into a superset. Asserts if any conflicts.""" - merged = {"formats": {}, "enums": {}, "src_enum": dict(SRC_EXTRAS), "doc_names": [], "is_cdna": False} - for r in results: - merged["doc_names"].append(r["doc_name"]) - merged["is_cdna"] = merged["is_cdna"] or r["is_cdna"] - # Merge src_enum (union, assert no conflicts) - for val, name in r["src_enum"].items(): - if val in merged["src_enum"]: - assert merged["src_enum"][val] == name, f"SrcEnum conflict: {val} = {merged['src_enum'][val]} vs {name}" - else: - merged["src_enum"][val] = name - # Merge enums (union of ops per enum, assert no conflicts) - for enum_name, ops in r["enums"].items(): - if enum_name not in merged["enums"]: merged["enums"][enum_name] = {} - for val, name in ops.items(): - if val in merged["enums"][enum_name]: - assert merged["enums"][enum_name][val] == name, f"{enum_name} conflict: {val} = {merged['enums'][enum_name][val]} vs {name}" - else: - merged["enums"][enum_name][val] = name - # Merge formats (union of fields, assert no bit position conflicts for same field name) - for fmt_name, fields in r["formats"].items(): - if fmt_name not in merged["formats"]: - merged["formats"][fmt_name] = list(fields) - else: - existing = {f[0]: (f[1], f[2]) for f in merged["formats"][fmt_name]} # name -> (hi, lo) - for f in fields: - name, hi, lo = f[0], f[1], f[2] - if name in existing: - assert existing[name] == (hi, lo), f"Format {fmt_name} field {name} conflict: bits {existing[name]} vs ({hi}, {lo})" - else: - merged["formats"][fmt_name].append(f) - return merged - -def generate(output_path: str | None = None, arch: str = "rdna3") -> dict: - """Generate instruction definitions from AMD ISA PDF(s). Returns dict with formats for testing.""" - urls = PDF_URLS[arch] - if isinstance(urls, str): urls = [urls] - - # Parse all PDFs and merge - results = [_parse_single_pdf(url) for url in urls] - if len(results) == 1: - merged = results[0] - doc_name = merged["doc_name"] - else: - merged = _merge_results(results) - doc_name = "+".join(merged["doc_names"]) - - formats, enums, src_enum = merged["formats"], merged["enums"], merged["src_enum"] - - # generate output - def enum_lines(name, items): - return [f"class {name}(IntEnum):"] + [f" {n} = {v}" for v, n in sorted(items.items())] + [""] - def field_key(f): return order.index(f[0].lower()) if f[0].lower() in order else 1000 - lines = [f"# autogenerated from AMD {doc_name} ISA PDF by dsl.py - do not edit", "from enum import IntEnum", - "from typing import Annotated", - "from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField", - "import functools", ""] - lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], []) - # Format-specific field defaults (verified against LLVM test vectors) - format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}} - lines.append("# instruction formats") - for fmt_name, fields in sorted(formats.items()): - base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32" - order = FIELD_ORDER.get(fmt_name, []) - lines.append(f"class {fmt_name}({base}):") - if enc := next((f for f in fields if f[0] == 'ENCODING'), None): - enc_str = f"bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f"bits[{enc[1]}] == {enc[3]}" - lines.append(f" encoding = {enc_str}") - if defaults := format_defaults.get(fmt_name): - lines.append(f" _defaults = {defaults}") - for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=field_key): - if ftype and ftype.endswith('Op'): - ann = f":Annotated[BitField, {ftype}]" - else: - ann = f":{ftype}" if ftype else "" - lines.append(f" {name.lower()}{ann} = bits[{hi}]" if hi == lo else f" {name.lower()}{ann} = bits[{hi}:{lo}]") - lines.append("") - lines.append("# instruction helpers") - for cls_name, ops in sorted(enums.items()): - fmt = cls_name[:-2] - for op_val, name in sorted(ops.items()): - seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt, "") - tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}") - if fmt in formats or fmt in ("GLOBAL", "SCRATCH"): - if fmt in ("VOP1", "VOP2", "VOPC"): - suffix = "_e32" - elif fmt == "VOP3" and op_val < 512: - suffix = "_e64" - else: - suffix = "" - if name in ('V_FMAMK_F32', 'V_FMAMK_F16'): - lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)") - elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'): - lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)") - else: - lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})") - skip_exports = {'DPP8', 'DPP16'} - src_names = {name for _, name in src_enum.items()} - lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in skip_exports] - if "NULL" in src_names: lines.append("OFF = NULL\n") - - if output_path is not None: - import pathlib - pathlib.Path(output_path).write_text('\n'.join(lines)) - return {"formats": formats, "enums": enums, "src_enum": src_enum} - -if __name__ == "__main__": - import argparse - parser = argparse.ArgumentParser(description="Generate instruction definitions from AMD ISA PDF") - parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3", help="Target architecture (default: rdna3)") - args = parser.parse_args() - if args.arch == "all": - for arch in PDF_URLS.keys(): - result = generate(f"extra/assembly/amd/autogen/{arch}/__init__.py", arch=arch) - print(f"{arch}: generated SrcEnum ({len(result['src_enum'])}) + {len(result['enums'])} opcode enums + {len(result['formats'])} format classes") - else: - result = generate(f"extra/assembly/amd/autogen/{args.arch}/__init__.py", arch=args.arch) - print(f"generated SrcEnum ({len(result['src_enum'])}) + {len(result['enums'])} opcode enums + {len(result['formats'])} format classes") diff --git a/extra/assembly/amd/emu.py b/extra/assembly/amd/emu.py index 18d50f6a25..56592e48e4 100644 --- a/extra/assembly/amd/emu.py +++ b/extra/assembly/amd/emu.py @@ -1,10 +1,9 @@ # RDNA3 emulator - executes compiled pseudocode from AMD ISA PDF # mypy: ignore-errors from __future__ import annotations -import ctypes, os -from extra.assembly.amd.dsl import Inst, RawImm +import ctypes, struct +from extra.assembly.amd.dsl import Inst, RawImm, unwrap, FLOAT_ENC, MASK32, MASK64, _f32, _i32, _sext, _f16, _i16, _f64, _i64 from extra.assembly.amd.asm import detect_format -from extra.assembly.amd.pcode import _f32, _i32, _sext, _f16, _i16, _f64, _i64 from extra.assembly.amd.autogen.rdna3.gen_pcode import get_compiled_functions from extra.assembly.amd.autogen.rdna3 import ( SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, DS, FLAT, VOPD, SrcEnum, @@ -15,49 +14,55 @@ Program = dict[int, Inst] WAVE_SIZE, SGPR_COUNT, VGPR_COUNT = 32, 128, 256 VCC_LO, VCC_HI, NULL, EXEC_LO, EXEC_HI, SCC = SrcEnum.VCC_LO, SrcEnum.VCC_HI, SrcEnum.NULL, SrcEnum.EXEC_LO, SrcEnum.EXEC_HI, SrcEnum.SCC -# VOP3 ops that use 64-bit operands (and thus 64-bit literals when src is 255) -# Exception: V_LDEXP_F64 has 32-bit integer src1, so literal should NOT be 64-bit when src1=255 -_VOP3_64BIT_OPS = {op.value for op in VOP3Op if op.name.endswith(('_F64', '_B64', '_I64', '_U64'))} -_VOPC_64BIT_OPS = {op.value for op in VOPCOp if op.name.endswith(('_F64', '_B64', '_I64', '_U64'))} -# Ops where src1 is 32-bit (exponent/shift amount) even though the op name suggests 64-bit -_VOP3_64BIT_OPS_32BIT_SRC1 = {VOP3Op.V_LDEXP_F64.value} -# Ops with 16-bit types in name (for source/dest handling) -# Exception: SAD/MSAD ops take 32-bit packed sources and extract 16-bit/8-bit chunks internally -_VOP3_16BIT_OPS = {op for op in VOP3Op if any(s in op.name for s in ('_F16', '_B16', '_I16', '_U16')) and 'SAD' not in op.name} -_VOP1_16BIT_OPS = {op for op in VOP1Op if any(s in op.name for s in ('_F16', '_B16', '_I16', '_U16'))} -_VOP2_16BIT_OPS = {op for op in VOP2Op if any(s in op.name for s in ('_F16', '_B16', '_I16', '_U16'))} -_VOPC_16BIT_OPS = {op for op in VOPCOp if any(s in op.name for s in ('_F16', '_B16', '_I16', '_U16'))} -# CVT ops with 32/64-bit source (despite 16-bit in name) -_CVT_32_64_SRC_OPS = {op for op in VOP3Op if op.name.startswith('V_CVT_') and op.name.endswith(('_F32', '_I32', '_U32', '_F64', '_I64', '_U64'))} | \ - {op for op in VOP1Op if op.name.startswith('V_CVT_') and op.name.endswith(('_F32', '_I32', '_U32', '_F64', '_I64', '_U64'))} -# CVT ops with 32-bit destination (convert FROM 16-bit TO 32-bit): V_CVT_F32_F16, V_CVT_I32_I16, V_CVT_U32_U16 -_CVT_32_DST_OPS = {op for op in VOP3Op if op.name.startswith('V_CVT_') and any(s in op.name for s in ('F32_F16', 'I32_I16', 'U32_U16', 'I32_F16', 'U32_F16'))} | \ - {op for op in VOP1Op if op.name.startswith('V_CVT_') and any(s in op.name for s in ('F32_F16', 'I32_I16', 'U32_U16', 'I32_F16', 'U32_F16'))} -# 16-bit dst ops (PACK has 32-bit dst despite F16 in name, CVT to 32-bit has 32-bit dst) +# Op classification helpers - build sets from op name patterns +def _ops_matching(enum, *patterns, exclude=()): return {op for op in enum if any(p in op.name for p in patterns) and not any(e in op.name for e in exclude)} +def _ops_ending(enum, *suffixes): return {op for op in enum if op.name.endswith(suffixes)} + +# 64-bit ops (for literal handling) +_VOP3_64BIT_OPS = {op.value for op in _ops_ending(VOP3Op, '_F64', '_B64', '_I64', '_U64')} +_VOPC_64BIT_OPS = {op.value for op in _ops_ending(VOPCOp, '_F64', '_B64', '_I64', '_U64')} +_VOP3_64BIT_OPS_32BIT_SRC1 = {VOP3Op.V_LDEXP_F64.value} # src1 is 32-bit exponent + +# 16-bit ops (SAD/MSAD excluded - they use 32-bit packed sources) +_VOP3_16BIT_OPS = _ops_matching(VOP3Op, '_F16', '_B16', '_I16', '_U16', exclude=('SAD',)) +_VOP1_16BIT_OPS = _ops_matching(VOP1Op, '_F16', '_B16', '_I16', '_U16') +_VOP2_16BIT_OPS = _ops_matching(VOP2Op, '_F16', '_B16', '_I16', '_U16') +_VOPC_16BIT_OPS = _ops_matching(VOPCOp, '_F16', '_B16', '_I16', '_U16') + +# CVT ops with 32/64-bit source (despite 16-bit in name) - must end with the type suffix +_CVT_32_64_SRC_OPS = {op for op in _ops_ending(VOP3Op, '_F32', '_I32', '_U32', '_F64', '_I64', '_U64') if op.name.startswith('V_CVT_')} | \ + {op for op in _ops_ending(VOP1Op, '_F32', '_I32', '_U32', '_F64', '_I64', '_U64') if op.name.startswith('V_CVT_')} +# CVT ops with 32-bit destination (FROM 16-bit TO 32-bit) - match patterns like F32_F16 in name +_CVT_32_DST_OPS = _ops_matching(VOP3Op, 'F32_F16', 'I32_I16', 'U32_U16', 'I32_F16', 'U32_F16') | \ + _ops_matching(VOP1Op, 'F32_F16', 'I32_I16', 'U32_U16', 'I32_F16', 'U32_F16') + +# 16-bit dst ops (PACK has 32-bit dst, CVT to 32-bit has 32-bit dst) _VOP3_16BIT_DST_OPS = {op for op in _VOP3_16BIT_OPS if 'PACK' not in op.name} - _CVT_32_DST_OPS _VOP1_16BIT_DST_OPS = {op for op in _VOP1_16BIT_OPS if 'PACK' not in op.name} - _CVT_32_DST_OPS -# VOP1 16-bit source ops (excluding CVT ops with 32/64-bit source) - for VOP1 e32, .h encoded in register index _VOP1_16BIT_SRC_OPS = _VOP1_16BIT_OPS - _CVT_32_64_SRC_OPS # Inline constants for src operands 128-254. Build tables for f32, f16, and f64 formats. -import struct as _struct -_FLOAT_CONSTS = {SrcEnum.POS_HALF: 0.5, SrcEnum.NEG_HALF: -0.5, SrcEnum.POS_ONE: 1.0, SrcEnum.NEG_ONE: -1.0, - SrcEnum.POS_TWO: 2.0, SrcEnum.NEG_TWO: -2.0, SrcEnum.POS_FOUR: 4.0, SrcEnum.NEG_FOUR: -4.0, SrcEnum.INV_2PI: 0.15915494309189535} -def _build_inline_consts(neg_mask, float_to_bits): - tbl = list(range(65)) + [((-i) & neg_mask) for i in range(1, 17)] + [0] * (127 - 81) - for k, v in _FLOAT_CONSTS.items(): tbl[k - 128] = float_to_bits(v) +# Inline constants for src operands 128-254. Build tables for f32, f16, and f64 formats. +_FLOAT_CONSTS = {v: k for k, v in FLOAT_ENC.items()} | {248: 0.15915494309189535} # INV_2PI +def _build_inline_consts(mask, to_bits): + tbl = list(range(65)) + [((-i) & mask) for i in range(1, 17)] + [0] * (127 - 81) + for k, v in _FLOAT_CONSTS.items(): tbl[k - 128] = to_bits(v) return tbl -_INLINE_CONSTS = _build_inline_consts(0xffffffff, lambda f: _struct.unpack(' int: return ((raw >> 16) & 0xffff) if is_hi else (raw & 0xffff) +def _dst16(cur: int, val: int, is_hi: bool) -> int: return (cur & 0x0000ffff) | ((val & 0xffff) << 16) if is_hi else (cur & 0xffff0000) | (val & 0xffff) +def _vgpr_hi(src: int) -> bool: return src >= 256 and ((src - 256) & 0x80) != 0 +def _vgpr_masked(src: int) -> int: return ((src - 256) & 0x7f) + 256 if src >= 256 else src # Memory access _valid_mem_ranges: list[tuple[int, int]] = [] def set_valid_mem_ranges(ranges: set[tuple[int, int]]) -> None: _valid_mem_ranges.clear(); _valid_mem_ranges.extend(ranges) def _mem_valid(addr: int, size: int) -> bool: - for s, z in _valid_mem_ranges: - if s <= addr and addr + size <= s + z: return True - return not _valid_mem_ranges + return not _valid_mem_ranges or any(s <= addr and addr + size <= s + z for s, z in _valid_mem_ranges) def _ctypes_at(addr: int, size: int): return (ctypes.c_uint8 if size == 1 else ctypes.c_uint16 if size == 2 else ctypes.c_uint32).from_address(addr) def mem_read(addr: int, size: int) -> int: return _ctypes_at(addr, size).value if _mem_valid(addr, size) else 0 def mem_write(addr: int, size: int, val: int) -> None: @@ -106,38 +111,29 @@ class WaveState: @property def vcc(self) -> int: return self.sgpr[VCC_LO] | (self.sgpr[VCC_HI] << 32) @vcc.setter - def vcc(self, v: int): self.sgpr[VCC_LO], self.sgpr[VCC_HI] = v & 0xffffffff, (v >> 32) & 0xffffffff + def vcc(self, v: int): self.sgpr[VCC_LO], self.sgpr[VCC_HI] = v & MASK32, (v >> 32) & MASK32 @property def exec_mask(self) -> int: return self.sgpr[EXEC_LO] | (self.sgpr[EXEC_HI] << 32) @exec_mask.setter - def exec_mask(self, v: int): self.sgpr[EXEC_LO], self.sgpr[EXEC_HI] = v & 0xffffffff, (v >> 32) & 0xffffffff + def exec_mask(self, v: int): self.sgpr[EXEC_LO], self.sgpr[EXEC_HI] = v & MASK32, (v >> 32) & MASK32 def rsgpr(self, i: int) -> int: return 0 if i == NULL else self.scc if i == SCC else self.sgpr[i] if i < SGPR_COUNT else 0 def wsgpr(self, i: int, v: int): - if i < SGPR_COUNT and i != NULL: self.sgpr[i] = v & 0xffffffff + if i < SGPR_COUNT and i != NULL: self.sgpr[i] = v & MASK32 def rsgpr64(self, i: int) -> int: return self.rsgpr(i) | (self.rsgpr(i+1) << 32) - def wsgpr64(self, i: int, v: int): self.wsgpr(i, v & 0xffffffff); self.wsgpr(i+1, (v >> 32) & 0xffffffff) + def wsgpr64(self, i: int, v: int): self.wsgpr(i, v & MASK32); self.wsgpr(i+1, (v >> 32) & MASK32) - def rsrc(self, v: int, lane: int) -> int: + def _rsrc_base(self, v: int, lane: int, consts): if v < SGPR_COUNT: return self.sgpr[v] if v == SCC: return self.scc - if v < 255: return _INLINE_CONSTS[v - 128] + if v < 255: return consts[v - 128] if v == 255: return self.literal return self.vgpr[lane][v - 256] if v <= 511 else 0 - - def rsrc_f16(self, v: int, lane: int) -> int: - """Read source operand for VOP3P packed f16 operations. Uses f16 inline constants.""" - if v < SGPR_COUNT: return self.sgpr[v] - if v == SCC: return self.scc - if v < 255: return _INLINE_CONSTS_F16[v - 128] - if v == 255: return self.literal - return self.vgpr[lane][v - 256] if v <= 511 else 0 - + def rsrc(self, v: int, lane: int) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS) + def rsrc_f16(self, v: int, lane: int) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS_F16) def rsrc64(self, v: int, lane: int) -> int: - """Read 64-bit source operand. For inline constants, returns 64-bit representation.""" - # Inline constants 128-254 need special handling for 64-bit ops if 128 <= v < 255: return _INLINE_CONSTS_F64[v - 128] - if v == 255: return self.literal # 32-bit literal, caller handles extension + if v == 255: return self.literal return self.rsrc(v, lane) | ((self.rsrc(v+1, lane) if v < VCC_LO or 256 <= v <= 511 else 0) << 32) def pend_sgpr_lane(self, reg: int, lane: int, val: int): @@ -148,9 +144,6 @@ class WaveState: self._pend_sgpr.clear() - -def _unwrap(v) -> int: return v.val if isinstance(v, RawImm) else v.value if hasattr(v, 'value') else v - def decode_program(data: bytes) -> Program: result: Program = {} i = 0 @@ -161,22 +154,18 @@ def decode_program(data: bytes) -> Program: base_size = inst_class._size() # Pass enough data for potential 64-bit literal (base + 8 bytes max) inst = inst_class.from_bytes(data[i:i+base_size+8]) - for name, val in inst._values.items(): setattr(inst, name, _unwrap(val)) + for name, val in inst._values.items(): setattr(inst, name, unwrap(val)) # from_bytes already handles literal reading - only need fallback for cases it doesn't handle if inst._literal is None: - has_literal = any(getattr(inst, fld, None) == 255 for fld in ('src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'srcx0', 'srcy0')) - if inst_class == VOP2 and inst.op in (44, 45, 55, 56): has_literal = True - if inst_class == VOPD and (inst.opx in (1, 2) or inst.opy in (1, 2)): has_literal = True - if inst_class == SOP2 and inst.op in (69, 70): has_literal = True + has_literal = any(getattr(inst, fld, None) == 255 for fld in ('src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'srcx0', 'srcy0')) or \ + (inst_class == VOP2 and inst.op in (44, 45, 55, 56)) or \ + (inst_class == VOPD and (inst.opx in (1, 2) or inst.opy in (1, 2))) or \ + (inst_class == SOP2 and inst.op in (69, 70)) if has_literal: # For 64-bit ops, the 32-bit literal is placed in HIGH 32 bits (low 32 bits = 0) - # Exception: some ops have mixed src sizes (e.g., V_LDEXP_F64 has 32-bit src1) - op_val = inst._values.get('op') - if hasattr(op_val, 'value'): op_val = op_val.value - is_64bit = (inst_class is VOP3 and op_val in _VOP3_64BIT_OPS) or (inst_class is VOPC and op_val in _VOPC_64BIT_OPS) - # Don't treat literal as 64-bit if the op has 32-bit src1 and src1 is the literal - if is_64bit and op_val in _VOP3_64BIT_OPS_32BIT_SRC1 and getattr(inst, 'src1', None) == 255: - is_64bit = False + op_val = getattr(inst._values.get('op'), 'value', inst._values.get('op')) + is_64bit = ((inst_class is VOP3 and op_val in _VOP3_64BIT_OPS) or (inst_class is VOPC and op_val in _VOPC_64BIT_OPS)) and \ + not (op_val in _VOP3_64BIT_OPS_32BIT_SRC1 and getattr(inst, 'src1', None) == 255) lit32 = int.from_bytes(data[i+base_size:i+base_size+4], 'little') inst._literal = (lit32 << 32) if is_64bit else lit32 inst._words = inst.size() // 4 @@ -204,7 +193,7 @@ def exec_scalar(st: WaveState, inst: Inst) -> int: addr = st.rsgpr64(inst.sbase * 2) + _sext(inst.offset, 21) if inst.soffset not in (NULL, 0x7f): addr += st.rsrc(inst.soffset, 0) if (cnt := SMEM_LOAD.get(inst.op)) is None: raise NotImplementedError(f"SMEM op {inst.op}") - for i in range(cnt): st.wsgpr(inst.sdata + i, mem_read((addr + i * 4) & 0xffffffffffffffff, 4)) + for i in range(cnt): st.wsgpr(inst.sdata + i, mem_read((addr + i * 4) & MASK64, 4)) return 0 # Get op enum and lookup compiled function @@ -243,10 +232,7 @@ def exec_scalar(st: WaveState, inst: Inst) -> int: # Apply results if sdst is not None: - if result.get('d0_64'): - st.wsgpr64(sdst, result['d0']) - else: - st.wsgpr(sdst, result['d0']) + (st.wsgpr64 if result.get('d0_64') else st.wsgpr)(sdst, result['d0']) if 'scc' in result: st.scc = result['scc'] if 'exec' in result: st.exec_mask = result['exec'] if 'new_pc' in result: @@ -265,10 +251,10 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No if inst_type is FLAT: op, addr_reg, data_reg, vdst, offset, saddr = inst.op, inst.addr, inst.data, inst.vdst, _sext(inst.offset, 13), inst.saddr addr = V[addr_reg] | (V[addr_reg+1] << 32) - addr = (st.rsgpr64(saddr) + V[addr_reg] + offset) & 0xffffffffffffffff if saddr not in (NULL, 0x7f) else (addr + offset) & 0xffffffffffffffff + addr = (st.rsgpr64(saddr) + V[addr_reg] + offset) & MASK64 if saddr not in (NULL, 0x7f) else (addr + offset) & MASK64 if op in FLAT_LOAD: cnt, sz, sign = FLAT_LOAD[op] - for i in range(cnt): val = mem_read(addr + i * sz, sz); V[vdst + i] = _sext(val, sz * 8) & 0xffffffff if sign else val + for i in range(cnt): val = mem_read(addr + i * sz, sz); V[vdst + i] = _sext(val, sz * 8) & MASK32 if sign else val elif op in FLAT_STORE: cnt, sz = FLAT_STORE[op] for i in range(cnt): mem_write(addr + i * sz, sz, V[data_reg + i] & ((1 << (sz * 8)) - 1)) @@ -276,12 +262,10 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No sz, sign, hi = FLAT_D16_LOAD[op] val = mem_read(addr, sz) if sign: val = _sext(val, sz * 8) & 0xffff - if hi: V[vdst] = (V[vdst] & 0xffff) | (val << 16) # upper 16 bits - else: V[vdst] = (V[vdst] & 0xffff0000) | (val & 0xffff) # lower 16 bits + V[vdst] = _dst16(V[vdst], val, hi) elif op in FLAT_D16_STORE: sz, hi = FLAT_D16_STORE[op] - val = (V[data_reg] >> 16) & 0xffff if hi else V[data_reg] & 0xffff - mem_write(addr, sz, val & ((1 << (sz * 8)) - 1)) + mem_write(addr, sz, _src16(V[data_reg], hi) & ((1 << (sz * 8)) - 1)) else: raise NotImplementedError(f"FLAT op {op}") return @@ -289,34 +273,21 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No op, addr, vdst = inst.op, (V[inst.addr] + inst.offset0) & 0xffff, inst.vdst if op in DS_LOAD: cnt, sz, sign = DS_LOAD[op] - for i in range(cnt): val = int.from_bytes(lds[addr+i*sz:addr+i*sz+sz], 'little'); V[vdst + i] = _sext(val, sz * 8) & 0xffffffff if sign else val + for i in range(cnt): val = int.from_bytes(lds[addr+i*sz:addr+i*sz+sz], 'little'); V[vdst + i] = _sext(val, sz * 8) & MASK32 if sign else val elif op in DS_STORE: cnt, sz = DS_STORE[op] for i in range(cnt): lds[addr+i*sz:addr+i*sz+sz] = (V[inst.data0 + i] & ((1 << (sz * 8)) - 1)).to_bytes(sz, 'little') else: raise NotImplementedError(f"DS op {op}") return - # VOPD: dual-issue, execute two ops using VOP2/VOP3 compiled functions - # Both ops execute simultaneously using pre-instruction values, so read all inputs first + # VOPD: dual-issue, execute two ops simultaneously (read all inputs before writes) if inst_type is VOPD: vdsty = (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1) - # Read all source operands BEFORE any writes (dual-issue semantics) - sx0, sx1 = st.rsrc(inst.srcx0, lane), V[inst.vsrcx1] - sy0, sy1 = st.rsrc(inst.srcy0, lane), V[inst.vsrcy1] - dx0, dy0 = V[inst.vdstx], V[vdsty] - # Execute X op - res_x = None - if (op_x := _VOPD_TO_VOP.get(inst.opx)): - if (fn_x := compiled.get(type(op_x), {}).get(op_x)): - res_x = fn_x(sx0, sx1, 0, dx0, st.scc, st.vcc, lane, st.exec_mask, st.literal, None, {}) - # Execute Y op - res_y = None - if (op_y := _VOPD_TO_VOP.get(inst.opy)): - if (fn_y := compiled.get(type(op_y), {}).get(op_y)): - res_y = fn_y(sy0, sy1, 0, dy0, st.scc, st.vcc, lane, st.exec_mask, st.literal, None, {}) - # Write results after both ops complete - if res_x is not None: V[inst.vdstx] = res_x['d0'] - if res_y is not None: V[vdsty] = res_y['d0'] + inputs = [(inst.opx, st.rsrc(inst.srcx0, lane), V[inst.vsrcx1], V[inst.vdstx], inst.vdstx), + (inst.opy, st.rsrc(inst.srcy0, lane), V[inst.vsrcy1], V[vdsty], vdsty)] + results = [(dst, fn(s0, s1, 0, d0, st.scc, st.vcc, lane, st.exec_mask, st.literal, None, {})['d0']) + for vopd_op, s0, s1, d0, dst in inputs if (op := _VOPD_TO_VOP.get(vopd_op)) and (fn := compiled.get(type(op), {}).get(op))] + for dst, val in results: V[dst] = val return # VOP3SD: has extra scalar dest for carry output @@ -324,61 +295,29 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No op = VOP3SDOp(inst.op) fn = compiled.get(VOP3SDOp, {}).get(op) if fn is None: raise NotImplementedError(f"{op.name} not in pseudocode") - # VOP3SD has both 32-bit ops (V_ADD_CO_CI_U32, etc.) and 64-bit ops (V_DIV_SCALE_F64, V_MAD_U64_U32, etc.) - div_scale_64_ops = (VOP3SDOp.V_DIV_SCALE_F64,) - mad64_ops = (VOP3SDOp.V_MAD_U64_U32, VOP3SDOp.V_MAD_I64_I32) - if op in div_scale_64_ops: - # V_DIV_SCALE_F64: all sources are 64-bit - s0, s1, s2 = st.rsrc64(inst.src0, lane), st.rsrc64(inst.src1, lane), st.rsrc64(inst.src2, lane) - elif op in mad64_ops: - # V_MAD_U64_U32, V_MAD_I64_I32: src0/src1 are 32-bit, src2 is 64-bit - s0, s1 = st.rsrc(inst.src0, lane), st.rsrc(inst.src1, lane) - if inst.src2 >= 256: # VGPR - s2 = V[inst.src2 - 256] | (V[inst.src2 - 256 + 1] << 32) - else: # SGPR - read 64-bit from consecutive SGPRs - s2 = st.rsgpr64(inst.src2) - else: - # Default: 32-bit sources - s0, s1, s2 = st.rsrc(inst.src0, lane), st.rsrc(inst.src1, lane), st.rsrc(inst.src2, lane) - d0 = V[inst.vdst] - # For carry-in operations (V_*_CO_CI_*), src2 register contains the carry bitmask (not VCC). - # The pseudocode uses VCC but in VOP3SD encoding, the actual carry source is inst.src2. - # We pass the src2 register value as 'vcc' to the interpreter so it reads the correct carry. + # Source sizes vary: DIV_SCALE=all 64-bit, MAD64=32/32/64, others=32-bit + r64 = op == VOP3SDOp.V_DIV_SCALE_F64 + s0, s1 = (st.rsrc64 if r64 else st.rsrc)(inst.src0, lane), (st.rsrc64 if r64 else st.rsrc)(inst.src1, lane) + mad64 = op in (VOP3SDOp.V_MAD_U64_U32, VOP3SDOp.V_MAD_I64_I32) + s2 = st.rsrc64(inst.src2, lane) if r64 else ((V[inst.src2-256]|(V[inst.src2-255]<<32)) if inst.src2>=256 else st.rsgpr64(inst.src2)) if mad64 else st.rsrc(inst.src2, lane) + # Carry-in ops use src2 as carry bitmask instead of VCC carry_ops = (VOP3SDOp.V_ADD_CO_CI_U32, VOP3SDOp.V_SUB_CO_CI_U32, VOP3SDOp.V_SUBREV_CO_CI_U32) - vcc_for_exec = st.rsgpr64(inst.src2) if op in carry_ops else st.vcc - result = fn(s0, s1, s2, d0, st.scc, vcc_for_exec, lane, st.exec_mask, st.literal, None, {}) - # Write result - handle 64-bit destinations - if result.get('d0_64'): - V[inst.vdst] = result['d0'] & 0xffffffff - V[inst.vdst + 1] = (result['d0'] >> 32) & 0xffffffff - else: - V[inst.vdst] = result['d0'] & 0xffffffff - if result.get('vcc_lane') is not None: - st.pend_sgpr_lane(inst.sdst, lane, result['vcc_lane']) + result = fn(s0, s1, s2, V[inst.vdst], st.scc, st.rsgpr64(inst.src2) if op in carry_ops else st.vcc, lane, st.exec_mask, st.literal, None, {}) + V[inst.vdst] = result['d0'] & MASK32 + if result.get('d0_64'): V[inst.vdst + 1] = (result['d0'] >> 32) & MASK32 + if result.get('vcc_lane') is not None: st.pend_sgpr_lane(inst.sdst, lane, result['vcc_lane']) return - - # Get op enum and sources (None means "no source" for that operand) - # vop1_dst_hi/vop2_dst_hi: for VOP1/VOP2 16-bit dst ops, bit 7 of vdst indicates .h (high 16-bit) destination - vop1_dst_hi, vop2_dst_hi = False, False + # dst_hi: for VOP1/VOP2 16-bit dst ops, bit 7 of vdst indicates .h (high 16-bit) destination + dst_hi = False if inst_type is VOP1: if inst.op == VOP1Op.V_NOP: return op_cls, op, src0, src1, src2 = VOP1Op, VOP1Op(inst.op), inst.src0, None, None - # For 16-bit dst ops, vdst encodes .h in bit 7 - if op in _VOP1_16BIT_DST_OPS: - vop1_dst_hi = (inst.vdst & 0x80) != 0 - vdst = inst.vdst & 0x7f - else: - vdst = inst.vdst + dst_hi, vdst = (inst.vdst & 0x80) != 0 and op in _VOP1_16BIT_DST_OPS, inst.vdst & 0x7f if op in _VOP1_16BIT_DST_OPS else inst.vdst elif inst_type is VOP2: op_cls, op, src0, src1, src2 = VOP2Op, VOP2Op(inst.op), inst.src0, inst.vsrc1 + 256, None - # For 16-bit dst ops, vdst encodes .h in bit 7 - if op in _VOP2_16BIT_OPS: - vop2_dst_hi = (inst.vdst & 0x80) != 0 - vdst = inst.vdst & 0x7f - else: - vdst = inst.vdst + dst_hi, vdst = (inst.vdst & 0x80) != 0 and op in _VOP2_16BIT_OPS, inst.vdst & 0x7f if op in _VOP2_16BIT_OPS else inst.vdst elif inst_type is VOP3: # VOP3 ops 0-255 are VOPC comparisons encoded as VOP3 (use VOPCOp pseudocode) if inst.op < 256: @@ -399,97 +338,30 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No if lane == 0: # Only execute once per wave, write results for all lanes exec_wmma(st, inst, op) return - # V_FMA_MIX: Mixed precision FMA - inputs can be f16 or f32 controlled by opsel_hi/opsel_hi2 - # opsel_hi[0]: src0 is f32 (0) or f16 from hi bits (1) - # opsel_hi[1]: src1 is f32 (0) or f16 from hi bits (1) - # opsel_hi2: src2 is f32 (0) or f16 from hi bits (1) - # opsel[i]: when source is f16, use lo (0) or hi (1) 16 bits - BUT for V_FMA_MIX, opsel selects lo/hi when opsel_hi=1 - # neg_hi[i]: abs modifier for source i (reuses neg_hi field for abs in V_FMA_MIX) + # V_FMA_MIX: Mixed precision FMA - opsel_hi controls f32(0) vs f16(1), opsel selects which f16 half if op in (VOP3POp.V_FMA_MIX_F32, VOP3POp.V_FMA_MIXLO_F16, VOP3POp.V_FMA_MIXHI_F16): - opsel = getattr(inst, 'opsel', 0) - opsel_hi = getattr(inst, 'opsel_hi', 0) - opsel_hi2 = getattr(inst, 'opsel_hi2', 0) - neg = getattr(inst, 'neg', 0) - abs_ = getattr(inst, 'neg_hi', 0) # neg_hi field is reused as abs for V_FMA_MIX - vdst = inst.vdst - # Read raw 32-bit values - s0_raw = st.rsrc(inst.src0, lane) - s1_raw = st.rsrc(inst.src1, lane) - s2_raw = st.rsrc(inst.src2, lane) if inst.src2 is not None else 0 - # Decode sources based on opsel_hi (controls f32 vs f16) and opsel (controls which half for f16) - # src0: opsel_hi[0]=1 means f16, opsel[0] selects hi(1) or lo(0) half - if opsel_hi & 1: - s0 = _f16((s0_raw >> 16) & 0xffff) if (opsel & 1) else _f16(s0_raw & 0xffff) - else: - s0 = _f32(s0_raw) - # src1: opsel_hi[1]=1 means f16, opsel[1] selects hi(1) or lo(0) half - if opsel_hi & 2: - s1 = _f16((s1_raw >> 16) & 0xffff) if (opsel & 2) else _f16(s1_raw & 0xffff) - else: - s1 = _f32(s1_raw) - # src2: opsel_hi2=1 means f16, opsel[2] selects hi(1) or lo(0) half - if opsel_hi2: - s2 = _f16((s2_raw >> 16) & 0xffff) if (opsel & 4) else _f16(s2_raw & 0xffff) - else: - s2 = _f32(s2_raw) - # Apply abs modifiers (abs_ field reuses neg_hi position) - if abs_ & 1: s0 = abs(s0) - if abs_ & 2: s1 = abs(s1) - if abs_ & 4: s2 = abs(s2) - # Apply neg modifiers - if neg & 1: s0 = -s0 - if neg & 2: s1 = -s1 - if neg & 4: s2 = -s2 - # Compute FMA: d = s0 * s1 + s2 - result = s0 * s1 + s2 + opsel, opsel_hi, opsel_hi2 = getattr(inst, 'opsel', 0), getattr(inst, 'opsel_hi', 0), getattr(inst, 'opsel_hi2', 0) + neg, abs_ = getattr(inst, 'neg', 0), getattr(inst, 'neg_hi', 0) # neg_hi reused as abs + raws = [st.rsrc(inst.src0, lane), st.rsrc(inst.src1, lane), st.rsrc(inst.src2, lane) if inst.src2 is not None else 0] + is_f16 = [opsel_hi & 1, opsel_hi & 2, opsel_hi2] + srcs = [_f16(_src16(raws[i], bool(opsel & (1<> 16) & 0xffff if (opsel & 1) else s0_raw & 0xffff - s1_lo = (s1_raw >> 16) & 0xffff if (opsel & 2) else s1_raw & 0xffff - s2_lo = (s2_raw >> 16) & 0xffff if (opsel & 4) else s2_raw & 0xffff - s0_hi = (s0_raw >> 16) & 0xffff if (opsel_hi & 1) else s0_raw & 0xffff - s1_hi = (s1_raw >> 16) & 0xffff if (opsel_hi & 2) else s1_raw & 0xffff - s2_hi = (s2_raw >> 16) & 0xffff if opsel_hi2 else s2_raw & 0xffff - # Apply neg to lo result inputs (toggle f16 sign bit) - if neg & 1: s0_lo ^= 0x8000 - if neg & 2: s1_lo ^= 0x8000 - if neg & 4: s2_lo ^= 0x8000 - # Apply neg_hi to hi result inputs - if neg_hi & 1: s0_hi ^= 0x8000 - if neg_hi & 2: s1_hi ^= 0x8000 - if neg_hi & 4: s2_hi ^= 0x8000 - # Pack into format expected by pseudocode: [31:16] = hi input, [15:0] = lo input - s0 = (s0_hi << 16) | s0_lo - s1 = (s1_hi << 16) | s1_lo - s2 = (s2_hi << 16) | s2_lo - op_cls, vdst = VOP3POp, inst.vdst - fn = compiled.get(op_cls, {}).get(op) + # VOP3P packed ops: opsel selects halves for lo, opsel_hi for hi; neg toggles f16 sign + raws = [st.rsrc_f16(inst.src0, lane), st.rsrc_f16(inst.src1, lane), st.rsrc_f16(inst.src2, lane) if inst.src2 is not None else 0] + opsel, opsel_hi, opsel_hi2 = getattr(inst, 'opsel', 0), getattr(inst, 'opsel_hi', 3), getattr(inst, 'opsel_hi2', 1) + neg, neg_hi = getattr(inst, 'neg', 0), getattr(inst, 'neg_hi', 0) + hi_sels = [opsel_hi & 1, opsel_hi & 2, opsel_hi2] + srcs = [((_src16(raws[i], hi_sels[i]) ^ (0x8000 if neg_hi & (1< int: - if (abs_ >> idx) & 1: val = _i32(abs(_f32(val))) - if (neg >> idx) & 1: val = _i32(-_f32(val)) - return val - def mod_src64(val: int, idx: int) -> int: - if (abs_ >> idx) & 1: val = _i64(abs(_f64(val))) - if (neg >> idx) & 1: val = _i64(-_f64(val)) + def mod_src(val: int, idx: int, is64=False) -> int: + to_f, to_i = (_f64, _i64) if is64 else (_f32, _i32) + if (abs_ >> idx) & 1: val = to_i(abs(to_f(val))) + if (neg >> idx) & 1: val = to_i(-to_f(val)) return val # Determine if sources are 64-bit based on instruction type @@ -523,103 +392,41 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No is_vop2_16bit = op_cls is VOP2Op and op in _VOP2_16BIT_OPS if is_shift_64: - s0 = mod_src(st.rsrc(src0, lane), 0) # shift amount is 32-bit - s1 = st.rsrc64(src1, lane) if src1 is not None else 0 # value to shift is 64-bit + s0, s1 = mod_src(st.rsrc(src0, lane), 0), st.rsrc64(src1, lane) if src1 else 0 s2 = mod_src(st.rsrc(src2, lane), 2) if src2 is not None else 0 elif is_ldexp_64: - s0 = mod_src64(st.rsrc64(src0, lane), 0) # mantissa is 64-bit float - # src1 is 32-bit int. For 64-bit ops (like V_CMP_CLASS_F64), the literal is stored shifted left by 32. - # For V_LDEXP_F64/V_TRIG_PREOP_F64, _is_64bit_op() returns False so literal is stored as-is. + s0 = mod_src(st.rsrc64(src0, lane), 0, is64=True) s1_raw = st.rsrc(src1, lane) if src1 is not None else 0 - # Only shift if src1 is literal AND this is a true 64-bit op (V_CMP_CLASS ops, not LDEXP/TRIG_PREOP) is_class_op = op in (VOP3Op.V_CMP_CLASS_F64, VOP3Op.V_CMPX_CLASS_F64, VOPCOp.V_CMP_CLASS_F64, VOPCOp.V_CMPX_CLASS_F64) - s1 = mod_src((s1_raw >> 32) if src1 == 255 and is_class_op else s1_raw, 1) - s2 = mod_src(st.rsrc(src2, lane), 2) if src2 is not None else 0 + s1, s2 = mod_src((s1_raw >> 32) if src1 == 255 and is_class_op else s1_raw, 1), mod_src(st.rsrc(src2, lane), 2) if src2 is not None else 0 elif is_64bit_op: - # 64-bit ops: apply neg/abs modifiers using f64 interpretation for float ops - s0 = mod_src64(st.rsrc64(src0, lane), 0) - s1 = mod_src64(st.rsrc64(src1, lane), 1) if src1 is not None else 0 - s2 = mod_src64(st.rsrc64(src2, lane), 2) if src2 is not None else 0 + s0, s1 = mod_src(st.rsrc64(src0, lane), 0, is64=True), mod_src(st.rsrc64(src1, lane), 1, is64=True) if src1 is not None else 0 + s2 = mod_src(st.rsrc64(src2, lane), 2, is64=True) if src2 is not None else 0 elif is_16bit_src: - # For 16-bit source ops, opsel bits select which half to use - # Inline constants (128-254) must use f16 encoding, not f32 - def rsrc_16bit(src, lane): return st.rsrc_f16(src, lane) if 128 <= src < 255 else st.rsrc(src, lane) - s0_raw = rsrc_16bit(src0, lane) - s1_raw = rsrc_16bit(src1, lane) if src1 is not None else 0 - s2_raw = rsrc_16bit(src2, lane) if src2 is not None else 0 - # opsel[0] selects hi(1) or lo(0) for src0, opsel[1] for src1, opsel[2] for src2 - s0 = ((s0_raw >> 16) & 0xffff) if (opsel & 1) else (s0_raw & 0xffff) - s1 = ((s1_raw >> 16) & 0xffff) if (opsel & 2) else (s1_raw & 0xffff) - s2 = ((s2_raw >> 16) & 0xffff) if (opsel & 4) else (s2_raw & 0xffff) - # Apply abs/neg modifiers as f16 operations (toggle sign bit 15) - if abs_ & 1: s0 &= 0x7fff - if abs_ & 2: s1 &= 0x7fff - if abs_ & 4: s2 &= 0x7fff - if neg & 1: s0 ^= 0x8000 - if neg & 2: s1 ^= 0x8000 - if neg & 4: s2 ^= 0x8000 - elif is_vop2_16bit: - # VOP2 16-bit ops: src0 uses f16 inline constants, or VGPR where v128+ = hi half of v0-v127 - # RDNA3 encoding: for VGPRs, bit 7 of VGPR index (src0-256) selects hi(1) or lo(0) half - if src0 >= 256: # VGPR - src0_hi = (src0 - 256) & 0x80 != 0 - src0_masked = ((src0 - 256) & 0x7f) + 256 # mask out hi bit to get actual VGPR - s0_raw = mod_src(st.rsrc(src0_masked, lane), 0) - s0 = ((s0_raw >> 16) & 0xffff) if src0_hi else (s0_raw & 0xffff) - else: # SGPR or inline constant - s0_raw = mod_src(st.rsrc_f16(src0, lane), 0) - s0 = s0_raw & 0xffff - # vsrc1: .h suffix encoded in bit 7 of VGPR index (src1 = 256 + vgpr_idx + 0x80 if hi) - if src1 is not None: - src1_hi = (src1 - 256) & 0x80 != 0 - src1_masked = ((src1 - 256) & 0x7f) + 256 - s1_raw = mod_src(st.rsrc(src1_masked, lane), 1) - s1 = ((s1_raw >> 16) & 0xffff) if src1_hi else (s1_raw & 0xffff) - else: - s1 = 0 + # VOP3 16-bit ops: opsel bits select which half, abs/neg as f16 bit ops + def rsrc_16bit(src, idx): + if src is None: return 0 + raw = st.rsrc_f16(src, lane) if 128 <= src < 255 else st.rsrc(src, lane) + val = _src16(raw, bool(opsel & (1 << idx))) + if abs_ & (1 << idx): val &= 0x7fff + if neg & (1 << idx): val ^= 0x8000 + return val + s0, s1, s2 = rsrc_16bit(src0, 0), rsrc_16bit(src1, 1), rsrc_16bit(src2, 2) + elif is_vop2_16bit or (op_cls is VOP1Op and op in _VOP1_16BIT_SRC_OPS) or (op_cls is VOPCOp and op in _VOPC_16BIT_OPS): + # VOP1/VOP2/VOPC 16-bit ops: VGPRs use bit 7 for hi/lo, non-VGPRs use f16 inline consts + # Special case: VOPC V_CMP_CLASS uses full 32-bit mask for src1 when non-VGPR + def rsrc16_vgpr(src, idx, full32=False): + if src is None: return 0 + if src >= 256: return _src16(mod_src(st.rsrc(_vgpr_masked(src), lane), idx), _vgpr_hi(src)) + return mod_src(st.rsrc(src, lane) if full32 else st.rsrc_f16(src, lane), idx) & (0xffffffff if full32 else 0xffff) + s0, s1 = rsrc16_vgpr(src0, 0), rsrc16_vgpr(src1, 1, full32=op_cls is VOPCOp) s2 = mod_src(st.rsrc(src2, lane), 2) if src2 is not None else 0 - elif op_cls is VOP1Op and op in _VOP1_16BIT_SRC_OPS: - # VOP1 16-bit source ops: .h encoded in bit 7 of VGPR index (src0 >= 384 means hi half) - # For VGPRs: src0 = 256 + vgpr_idx + (0x80 if hi else 0), so bit 7 of (src0-256) is the hi flag - src0_hi = src0 >= 256 and ((src0 - 256) & 0x80) != 0 - src0_masked = ((src0 - 256) & 0x7f) + 256 if src0 >= 256 else src0 # mask out hi bit for VGPR - s0_raw = mod_src(st.rsrc(src0_masked, lane), 0) - s0 = ((s0_raw >> 16) & 0xffff) if src0_hi else (s0_raw & 0xffff) - s1, s2 = 0, 0 - elif op_cls is VOPCOp and op in _VOPC_16BIT_OPS: - # VOPC 16-bit ops: src0 and vsrc1 use same encoding as VOP2 16-bit - # For VGPRs, bit 7 of VGPR index selects hi(1) or lo(0) half - if src0 >= 256: # VGPR - src0_hi = (src0 - 256) & 0x80 != 0 - src0_masked = ((src0 - 256) & 0x7f) + 256 - s0_raw = mod_src(st.rsrc(src0_masked, lane), 0) - s0 = ((s0_raw >> 16) & 0xffff) if src0_hi else (s0_raw & 0xffff) - else: # SGPR or inline constant - s0_raw = mod_src(st.rsrc_f16(src0, lane), 0) - s0 = s0_raw & 0xffff - # vsrc1: bit 7 of VGPR index selects hi(1) or lo(0) half - if src1 is not None: - if src1 >= 256: # VGPR - use hi/lo encoding - src1_hi = (src1 - 256) & 0x80 != 0 - src1_masked = ((src1 - 256) & 0x7f) + 256 - s1_raw = mod_src(st.rsrc(src1_masked, lane), 1) - s1 = ((s1_raw >> 16) & 0xffff) if src1_hi else (s1_raw & 0xffff) - else: # SGPR or inline constant - read as 32-bit, use low 16 bits - s1_raw = mod_src(st.rsrc(src1, lane), 1) - s1 = s1_raw & 0xffffffff # V_CMP_CLASS uses full 32-bit mask - else: - s1 = 0 - s2 = 0 else: s0 = mod_src(st.rsrc(src0, lane), 0) s1 = mod_src(st.rsrc(src1, lane), 1) if src1 is not None else 0 s2 = mod_src(st.rsrc(src2, lane), 2) if src2 is not None else 0 - # For VOP2 16-bit ops (like V_FMAC_F16), the destination is used as an accumulator. - # The pseudocode reads D0.f16 from low 16 bits, so we need to shift hi->lo when vop2_dst_hi is True. - if is_vop2_16bit: - d0 = ((V[vdst] >> 16) & 0xffff) if vop2_dst_hi else (V[vdst] & 0xffff) - else: - d0 = V[vdst] if not is_64bit_op else (V[vdst] | (V[vdst + 1] << 32)) + # Read destination (accumulator for VOP2 f16, 64-bit for 64-bit ops) + d0 = _src16(V[vdst], dst_hi) if is_vop2_16bit else (V[vdst] | (V[vdst + 1] << 32)) if is_64bit_op else V[vdst] # V_CNDMASK_B32/B16: VOP3 encoding uses src2 as mask (not VCC); VOP2 uses VCC implicitly # Pass the correct mask as vcc to the function so pseudocode VCC.u64[laneId] works correctly @@ -636,46 +443,19 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No wr_lane, wr_idx, wr_val = result['vgpr_write'] st.vgpr[wr_lane][wr_idx] = wr_val if 'vcc_lane' in result: - # VOP2 carry instructions (V_ADD_CO_CI_U32, V_SUB_CO_CI_U32, V_SUBREV_CO_CI_U32) write carry to VCC implicitly - # VOPC and VOP3-encoded VOPC write to vdst (which is VCC_LO for VOPC, inst.sdst for VOP3) - vcc_dst = VCC_LO if op_cls is VOP2Op and op in (VOP2Op.V_ADD_CO_CI_U32, VOP2Op.V_SUB_CO_CI_U32, VOP2Op.V_SUBREV_CO_CI_U32) else vdst - st.pend_sgpr_lane(vcc_dst, lane, result['vcc_lane']) + # VOP2 carry ops write to VCC implicitly; VOPC/VOP3 write to vdst + st.pend_sgpr_lane(VCC_LO if op_cls is VOP2Op and 'CO_CI' in op.name else vdst, lane, result['vcc_lane']) if 'exec_lane' in result: # V_CMPX instructions write to EXEC per-lane st.pend_sgpr_lane(EXEC_LO, lane, result['exec_lane']) if 'd0' in result and op_cls not in (VOPCOp,) and 'vgpr_write' not in result: - # V_READFIRSTLANE_B32 and V_READLANE_B32 write to SGPR, not VGPR - # V_WRITELANE_B32 uses vgpr_write for cross-lane writes, don't overwrite with d0 - writes_to_sgpr = op in (VOP1Op.V_READFIRSTLANE_B32,) or \ - (op_cls is VOP3Op and op in (VOP3Op.V_READFIRSTLANE_B32, VOP3Op.V_READLANE_B32)) - # Check for 16-bit destination ops (opsel[3] controls hi/lo write) - # Must check op_cls to avoid cross-enum value collisions (e.g., VOP1Op.V_MOV_B32=1 vs VOP3Op.V_CMP_LT_F16=1) - is_16bit_dst = (op_cls is VOP3Op and op in _VOP3_16BIT_DST_OPS) or (op_cls is VOP1Op and op in _VOP1_16BIT_DST_OPS) - if writes_to_sgpr: - st.wsgpr(vdst, result['d0'] & 0xffffffff) - elif result.get('d0_64'): - V[vdst] = result['d0'] & 0xffffffff - V[vdst + 1] = (result['d0'] >> 32) & 0xffffffff - elif is_16bit_dst and inst_type is VOP3: - # VOP3 16-bit ops: opsel[3] (bit 3 of opsel field) controls hi/lo destination - if opsel & 8: # opsel[3] = 1: write to high 16 bits - V[vdst] = (V[vdst] & 0x0000ffff) | ((result['d0'] & 0xffff) << 16) - else: # opsel[3] = 0: write to low 16 bits - V[vdst] = (V[vdst] & 0xffff0000) | (result['d0'] & 0xffff) - elif is_16bit_dst and inst_type is VOP1: - # VOP1 16-bit ops: .h suffix encoded in bit 7 of vdst (extracted as vop1_dst_hi) - if vop1_dst_hi: # .h: write to high 16 bits - V[vdst] = (V[vdst] & 0x0000ffff) | ((result['d0'] & 0xffff) << 16) - else: # .l: write to low 16 bits - V[vdst] = (V[vdst] & 0xffff0000) | (result['d0'] & 0xffff) - elif is_vop2_16bit: - # VOP2 16-bit ops: .h suffix encoded in bit 7 of vdst (extracted as vop2_dst_hi) - if vop2_dst_hi: # .h: write to high 16 bits - V[vdst] = (V[vdst] & 0x0000ffff) | ((result['d0'] & 0xffff) << 16) - else: # .l: write to low 16 bits - V[vdst] = (V[vdst] & 0xffff0000) | (result['d0'] & 0xffff) - else: - V[vdst] = result['d0'] & 0xffffffff + writes_to_sgpr = op in (VOP1Op.V_READFIRSTLANE_B32,) or (op_cls is VOP3Op and op in (VOP3Op.V_READFIRSTLANE_B32, VOP3Op.V_READLANE_B32)) + is_16bit_dst = (op_cls is VOP3Op and op in _VOP3_16BIT_DST_OPS) or (op_cls is VOP1Op and op in _VOP1_16BIT_DST_OPS) or is_vop2_16bit + d0_val = result['d0'] + if writes_to_sgpr: st.wsgpr(vdst, d0_val & MASK32) + elif result.get('d0_64'): V[vdst], V[vdst + 1] = d0_val & MASK32, (d0_val >> 32) & MASK32 + elif is_16bit_dst: V[vdst] = _dst16(V[vdst], d0_val, bool(opsel & 8) if inst_type is VOP3 else dst_hi) + else: V[vdst] = d0_val & MASK32 # ═══════════════════════════════════════════════════════════════════════════════ # WMMA (Wave Matrix Multiply-Accumulate) @@ -684,54 +464,20 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No def exec_wmma(st: WaveState, inst, op: VOP3POp) -> None: """Execute WMMA instruction - 16x16x16 matrix multiply across the wave.""" src0, src1, src2, vdst = inst.src0, inst.src1, inst.src2, inst.vdst - # Read matrix A (16x16 f16/bf16) from lanes 0-15, VGPRs src0 to src0+7 (2 f16 per VGPR = 16 values per lane) - # Layout: A[row][k] where row = lane (0-15), k comes from 8 VGPRs × 2 halves - mat_a = [] - for lane in range(16): - for reg in range(8): - val = st.vgpr[lane][src0 - 256 + reg] if src0 >= 256 else st.rsgpr(src0 + reg) - mat_a.append(_f16(val & 0xffff)) - mat_a.append(_f16((val >> 16) & 0xffff)) - # Read matrix B (16x16 f16/bf16) - same layout, B[col][k] where col comes from lane - mat_b = [] - for lane in range(16): - for reg in range(8): - val = st.vgpr[lane][src1 - 256 + reg] if src1 >= 256 else st.rsgpr(src1 + reg) - mat_b.append(_f16(val & 0xffff)) - mat_b.append(_f16((val >> 16) & 0xffff)) - + # Read 16x16 f16 matrix from 16 lanes × 8 VGPRs (2 f16 per VGPR) + def read_f16_mat(src): + return [f for l in range(16) for r in range(8) for v in [st.vgpr[l][src-256+r] if src >= 256 else st.rsgpr(src+r)] for f in [_f16(v&0xffff), _f16((v>>16)&0xffff)]] + mat_a, mat_b = read_f16_mat(src0), read_f16_mat(src1) # Read matrix C (16x16 f32) from lanes 0-31, VGPRs src2 to src2+7 - # Layout: element i is at lane (i % 32), VGPR (i // 32) + src2 - mat_c = [] - for i in range(256): - lane, reg = i % 32, i // 32 - val = st.vgpr[lane][src2 - 256 + reg] if src2 >= 256 else st.rsgpr(src2 + reg) - mat_c.append(_f32(val)) - + mat_c = [_f32(st.vgpr[i % 32][src2 - 256 + i // 32] if src2 >= 256 else st.rsgpr(src2 + i // 32)) for i in range(256)] # Compute D = A × B + C (16x16 matrix multiply) - mat_d = [0.0] * 256 - for row in range(16): - for col in range(16): - acc = 0.0 - for k in range(16): - a_val = mat_a[row * 16 + k] - b_val = mat_b[col * 16 + k] - acc += a_val * b_val - mat_d[row * 16 + col] = acc + mat_c[row * 16 + col] - - # Write result matrix D back - same layout as C + mat_d = [sum(mat_a[row*16+k] * mat_b[col*16+k] for k in range(16)) + mat_c[row*16+col] for row in range(16) for col in range(16)] + # Write result - f16 packed or f32 if op == VOP3POp.V_WMMA_F16_16X16X16_F16: - # Output is f16, pack 2 values per VGPR for i in range(0, 256, 2): - lane, reg = (i // 2) % 32, (i // 2) // 32 - lo = _i16(mat_d[i]) & 0xffff - hi = _i16(mat_d[i + 1]) & 0xffff - st.vgpr[lane][vdst + reg] = (hi << 16) | lo + st.vgpr[(i//2) % 32][vdst + (i//2)//32] = ((_i16(mat_d[i+1]) & 0xffff) << 16) | (_i16(mat_d[i]) & 0xffff) else: - # Output is f32 - for i in range(256): - lane, reg = i % 32, i // 32 - st.vgpr[lane][vdst + reg] = _i32(mat_d[i]) + for i in range(256): st.vgpr[i % 32][vdst + i//32] = _i32(mat_d[i]) # ═══════════════════════════════════════════════════════════════════════════════ # MAIN EXECUTION LOOP @@ -751,15 +497,11 @@ def step_wave(program: Program, st: WaveState, lds: bytearray, n_lanes: int) -> if delta == -2: st.pc += inst_words; return -2 # barrier st.pc += inst_words + delta else: - # V_READFIRSTLANE_B32 and V_READLANE_B32 write to SGPR, so they should only execute once per wave (lane 0) - is_readlane = (inst_type is VOP1 and inst.op == VOP1Op.V_READFIRSTLANE_B32) or \ - (inst_type is VOP3 and inst.op in (VOP3Op.V_READFIRSTLANE_B32, VOP3Op.V_READLANE_B32)) - if is_readlane: - exec_vector(st, inst, 0, lds) # Execute once with lane 0 - else: - exec_mask = st.exec_mask - for lane in range(n_lanes): - if exec_mask & (1 << lane): exec_vector(st, inst, lane, lds) + # V_READFIRSTLANE/V_READLANE write to SGPR, execute once; others execute per-lane with exec_mask + is_readlane = inst_type in (VOP1, VOP3) and hasattr(inst.op, 'name') and 'READLANE' in inst.op.name + exec_mask = 1 if is_readlane else st.exec_mask + for lane in range(1 if is_readlane else n_lanes): + if exec_mask & (1 << lane): exec_vector(st, inst, lane, lds) st.commit_pends() st.pc += inst_words return 0 @@ -780,31 +522,24 @@ def exec_workgroup(program: Program, workgroup_id: tuple[int, int, int], local_s n_lanes, st = min(WAVE_SIZE, total_threads - wave_start), WaveState() st.exec_mask = (1 << n_lanes) - 1 st.wsgpr64(0, args_ptr) - gx, gy, gz = workgroup_id # Set workgroup IDs in SGPRs based on USER_SGPR_COUNT and enable flags from COMPUTE_PGM_RSRC2 sgpr_idx = wg_id_sgpr_base - if wg_id_enables[0]: st.sgpr[sgpr_idx] = gx; sgpr_idx += 1 - if wg_id_enables[1]: st.sgpr[sgpr_idx] = gy; sgpr_idx += 1 - if wg_id_enables[2]: st.sgpr[sgpr_idx] = gz + for wg_id, enabled in zip(workgroup_id, wg_id_enables): + if enabled: st.sgpr[sgpr_idx] = wg_id; sgpr_idx += 1 + # Set workitem IDs in VGPR0 using packed method: v0 = (Z << 20) | (Y << 10) | X for i in range(n_lanes): tid = wave_start + i - st.vgpr[i][0] = tid if local_size == (lx, 1, 1) else ((tid // (lx * ly)) << 20) | (((tid // lx) % ly) << 10) | (tid % lx) + st.vgpr[i][0] = ((tid // (lx * ly)) << 20) | (((tid // lx) % ly) << 10) | (tid % lx) waves.append((st, n_lanes, wave_start)) has_barrier = any(isinstance(inst, SOPP) and inst.op == SOPPOp.S_BARRIER for inst in program.values()) for _ in range(2 if has_barrier else 1): for st, n_lanes, _ in waves: exec_wave(program, st, lds, n_lanes) def run_asm(lib: int, lib_sz: int, gx: int, gy: int, gz: int, lx: int, ly: int, lz: int, args_ptr: int, rsrc2: int = 0x19c) -> int: - data = (ctypes.c_char * lib_sz).from_address(lib).raw - program = decode_program(data) + program = decode_program((ctypes.c_char * lib_sz).from_address(lib).raw) if not program: return -1 - # Parse COMPUTE_PGM_RSRC2 for SGPR layout - user_sgpr_count = (rsrc2 >> 1) & 0x1f - enable_wg_id_x = bool((rsrc2 >> 7) & 1) - enable_wg_id_y = bool((rsrc2 >> 8) & 1) - enable_wg_id_z = bool((rsrc2 >> 9) & 1) - wg_id_enables = (enable_wg_id_x, enable_wg_id_y, enable_wg_id_z) + wg_id_enables = tuple(bool((rsrc2 >> (7+i)) & 1) for i in range(3)) for gidz in range(gz): for gidy in range(gy): - for gidx in range(gx): exec_workgroup(program, (gidx, gidy, gidz), (lx, ly, lz), args_ptr, user_sgpr_count, wg_id_enables) + for gidx in range(gx): exec_workgroup(program, (gidx, gidy, gidz), (lx, ly, lz), args_ptr, (rsrc2 >> 1) & 0x1f, wg_id_enables) return 0 diff --git a/extra/assembly/amd/pcode.py b/extra/assembly/amd/pcode.py index bac30bd6ad..65e1193f68 100644 --- a/extra/assembly/amd/pcode.py +++ b/extra/assembly/amd/pcode.py @@ -1,90 +1,42 @@ # DSL for RDNA3 pseudocode - makes pseudocode expressions work directly as Python -import struct, math, re +import struct, math +from extra.assembly.amd.dsl import MASK32, MASK64, _f32, _i32, _sext, _f16, _i16, _f64, _i64 # ═══════════════════════════════════════════════════════════════════════════════ -# HELPER FUNCTIONS (previously in helpers.py) +# HELPER FUNCTIONS # ═══════════════════════════════════════════════════════════════════════════════ -def _f32(i): return struct.unpack(" 0 else 0xff800000 - try: return struct.unpack(" 0 else 0xff800000 def _div(a, b): try: return a / b except ZeroDivisionError: if a == 0.0 or math.isnan(a): return float("nan") return math.copysign(float("inf"), a * b) if b == 0.0 else float("inf") if a > 0 else float("-inf") -def _sext(v, b): return v - (1 << b) if v & (1 << (b - 1)) else v -def _f16(i): return struct.unpack(" 0 else 0xfc00 - try: return struct.unpack(" 0 else 0xfc00 def _to_f16_bits(v): return v if isinstance(v, int) else _i16(v) -def _f64(i): return struct.unpack(" 0 else 0xfff0000000000000 - try: return struct.unpack(" 0 else 0xfff0000000000000 def _isnan(x): try: return math.isnan(float(x)) except (TypeError, ValueError): return False -def _isquietnan(x): - """Check if x is a quiet NaN. - f16: exponent=31, bit9=1, mantissa!=0 - f32: exponent=255, bit22=1, mantissa!=0 - f64: exponent=2047, bit51=1, mantissa!=0 - """ +def _check_nan_type(x, quiet_bit_expected, default): + """Check NaN type by examining quiet bit. Returns default if can't determine.""" try: if not math.isnan(float(x)): return False - # Get raw bits from TypedView or similar object with _reg attribute if hasattr(x, '_reg') and hasattr(x, '_bits'): bits = x._reg._val & ((1 << x._bits) - 1) - if x._bits == 16: - return ((bits >> 10) & 0x1f) == 31 and ((bits >> 9) & 1) == 1 and (bits & 0x3ff) != 0 - if x._bits == 32: - return ((bits >> 23) & 0xff) == 255 and ((bits >> 22) & 1) == 1 and (bits & 0x7fffff) != 0 - if x._bits == 64: - return ((bits >> 52) & 0x7ff) == 0x7ff and ((bits >> 51) & 1) == 1 and (bits & 0xfffffffffffff) != 0 - return True # Default to quiet NaN if we can't determine bit pattern - except (TypeError, ValueError): return False -def _issignalnan(x): - """Check if x is a signaling NaN. - f16: exponent=31, bit9=0, mantissa!=0 - f32: exponent=255, bit22=0, mantissa!=0 - f64: exponent=2047, bit51=0, mantissa!=0 - """ - try: - if not math.isnan(float(x)): return False - # Get raw bits from TypedView or similar object with _reg attribute - if hasattr(x, '_reg') and hasattr(x, '_bits'): - bits = x._reg._val & ((1 << x._bits) - 1) - if x._bits == 16: - return ((bits >> 10) & 0x1f) == 31 and ((bits >> 9) & 1) == 0 and (bits & 0x3ff) != 0 - if x._bits == 32: - return ((bits >> 23) & 0xff) == 255 and ((bits >> 22) & 1) == 0 and (bits & 0x7fffff) != 0 - if x._bits == 64: - return ((bits >> 52) & 0x7ff) == 0x7ff and ((bits >> 51) & 1) == 0 and (bits & 0xfffffffffffff) != 0 - return False # Default to not signaling if we can't determine bit pattern + # NaN format: exponent all 1s, quiet bit, mantissa != 0 + # f16: exp[14:10]=31, quiet=bit9, mant[8:0] | f32: exp[30:23]=255, quiet=bit22, mant[22:0] | f64: exp[62:52]=2047, quiet=bit51, mant[51:0] + exp_bits, quiet_pos, mant_mask = {16: (0x1f, 9, 0x3ff), 32: (0xff, 22, 0x7fffff), 64: (0x7ff, 51, 0xfffffffffffff)}.get(x._bits, (0,0,0)) + exp_shift = {16: 10, 32: 23, 64: 52}.get(x._bits, 0) + if exp_bits and ((bits >> exp_shift) & exp_bits) == exp_bits and (bits & mant_mask) != 0: + return ((bits >> quiet_pos) & 1) == quiet_bit_expected + return default except (TypeError, ValueError): return False +def _isquietnan(x): return _check_nan_type(x, 1, True) # quiet NaN has quiet bit = 1 +def _issignalnan(x): return _check_nan_type(x, 0, False) # signaling NaN has quiet bit = 0 def _gt_neg_zero(a, b): return (a > b) or (a == 0 and b == 0 and not math.copysign(1, a) < 0 and math.copysign(1, b) < 0) def _lt_neg_zero(a, b): return (a < b) or (a == 0 and b == 0 and math.copysign(1, a) < 0 and not math.copysign(1, b) < 0) def _fma(a, b, c): return a * b + c def _signext(v): return v -def trunc(x): - x = float(x) - return x if math.isnan(x) or math.isinf(x) else float(math.trunc(x)) -def floor(x): - x = float(x) - return x if math.isnan(x) or math.isinf(x) else float(math.floor(x)) -def ceil(x): - x = float(x) - return x if math.isnan(x) or math.isinf(x) else float(math.ceil(x)) +def _fpop(fn): return lambda x: (x := float(x), x if math.isnan(x) or math.isinf(x) else float(fn(x)))[1] +trunc, floor, ceil = _fpop(math.trunc), _fpop(math.floor), _fpop(math.ceil) class _SafeFloat(float): """Float subclass that uses _div for division to handle 0/inf correctly.""" def __truediv__(self, o): return _div(float(self), float(o)) @@ -92,20 +44,10 @@ class _SafeFloat(float): def sqrt(x): return _SafeFloat(math.sqrt(x)) if x >= 0 else _SafeFloat(float("nan")) def log2(x): return math.log2(x) if x > 0 else (float("-inf") if x == 0 else float("nan")) i32_to_f32 = u32_to_f32 = i32_to_f64 = u32_to_f64 = f32_to_f64 = f64_to_f32 = float -def f32_to_i32(f): - f = float(f) - if math.isnan(f): return 0 - if f >= 2147483647: return 2147483647 - if f <= -2147483648: return -2147483648 - return int(f) -def f32_to_u32(f): - f = float(f) - if math.isnan(f): return 0 - if f >= 4294967295: return 4294967295 - if f <= 0: return 0 - return int(f) -f64_to_i32 = f32_to_i32 -f64_to_u32 = f32_to_u32 +def _f_to_int(f, lo, hi): f = float(f); return 0 if math.isnan(f) else (hi if f >= hi else lo if f <= lo else int(f)) +def f32_to_i32(f): return _f_to_int(f, -2147483648, 2147483647) +def f32_to_u32(f): return _f_to_int(f, 0, 4294967295) +f64_to_i32, f64_to_u32 = f32_to_i32, f32_to_u32 def f32_to_f16(f): f = float(f) if math.isnan(f): return 0x7e00 # f16 NaN @@ -129,38 +71,26 @@ def isEven(x): return int(x) % 2 == 0 def fract(x): return x - math.floor(x) PI = math.pi -def sin(x): - # V_SIN_F32: pseudocode does sin(input * 2π), but hardware does frac on the input first - # So sin(1.0 * 2π) should be sin(frac(1.0) * 2π) = sin(0) = 0 +def _trig(fn, x): + # V_SIN/COS_F32: hardware does frac on input cycles before computing if math.isinf(x) or math.isnan(x): return float("nan") - # The input x is already multiplied by 2π in the pseudocode, so we need to - # extract the fractional cycle: frac(x / 2π) * 2π - cycles = x / (2 * math.pi) - frac_cycles = cycles - math.floor(cycles) - return math.sin(frac_cycles * 2 * math.pi) -def cos(x): - # V_COS_F32: same as sin, hardware does frac on input cycles - if math.isinf(x) or math.isnan(x): return float("nan") - cycles = x / (2 * math.pi) - frac_cycles = cycles - math.floor(cycles) - return math.cos(frac_cycles * 2 * math.pi) + frac_cycles = fract(x / (2 * math.pi)) + return fn(frac_cycles * 2 * math.pi) +def sin(x): return _trig(math.sin, x) +def cos(x): return _trig(math.cos, x) def pow(a, b): try: return a ** b except OverflowError: return float("inf") if b > 0 else 0.0 -def _brev32(v): return int(bin(v & 0xffffffff)[2:].zfill(32)[::-1], 2) -def _brev64(v): return int(bin(v & 0xffffffffffffffff)[2:].zfill(64)[::-1], 2) -def _ctz32(v): - v = int(v) & 0xffffffff - if v == 0: return 32 - n = 0 - while (v & 1) == 0: v >>= 1; n += 1 - return n -def _ctz64(v): - v = int(v) & 0xffffffffffffffff - if v == 0: return 64 - n = 0 +def _brev(v, bits): return int(bin(v & ((1 << bits) - 1))[2:].zfill(bits)[::-1], 2) +def _brev32(v): return _brev(v, 32) +def _brev64(v): return _brev(v, 64) +def _ctz(v, bits): + v, n = int(v) & ((1 << bits) - 1), 0 + if v == 0: return bits while (v & 1) == 0: v >>= 1; n += 1 return n +def _ctz32(v): return _ctz(v, 32) +def _ctz64(v): return _ctz(v, 64) def _exponent(f): # Handle TypedView (f16/f32/f64) to get correct exponent for that type if hasattr(f, '_bits') and hasattr(f, '_float') and f._float: @@ -184,34 +114,21 @@ def _is_denorm_f64(f): if math.isinf(f) or math.isnan(f) or f == 0.0: return False bits = struct.unpack("> 52) & 0x7ff == 0 -def v_min_f32(a, b): - if math.isnan(b): return a - if math.isnan(a): return b - return a if _lt_neg_zero(a, b) else b -def v_max_f32(a, b): - if math.isnan(b): return a - if math.isnan(a): return b - return a if _gt_neg_zero(a, b) else b -def v_min_i32(a, b): return min(a, b) -def v_max_i32(a, b): return max(a, b) -def v_min_u32(a, b): return min(a & 0xffffffff, b & 0xffffffff) -def v_max_u32(a, b): return max(a & 0xffffffff, b & 0xffffffff) -v_min_f16 = v_min_f32 -v_max_f16 = v_max_f32 -v_min_i16 = v_min_i32 -v_max_i16 = v_max_i32 +def v_min_f32(a, b): return a if math.isnan(b) else b if math.isnan(a) else (a if _lt_neg_zero(a, b) else b) +def v_max_f32(a, b): return a if math.isnan(b) else b if math.isnan(a) else (a if _gt_neg_zero(a, b) else b) +v_min_f16, v_max_f16 = v_min_f32, v_max_f32 +v_min_i32, v_max_i32 = min, max +v_min_i16, v_max_i16 = min, max +def v_min_u32(a, b): return min(a & MASK32, b & MASK32) +def v_max_u32(a, b): return max(a & MASK32, b & MASK32) def v_min_u16(a, b): return min(a & 0xffff, b & 0xffff) def v_max_u16(a, b): return max(a & 0xffff, b & 0xffff) def v_min3_f32(a, b, c): return v_min_f32(v_min_f32(a, b), c) def v_max3_f32(a, b, c): return v_max_f32(v_max_f32(a, b), c) -def v_min3_i32(a, b, c): return min(a, b, c) -def v_max3_i32(a, b, c): return max(a, b, c) -def v_min3_u32(a, b, c): return min(a & 0xffffffff, b & 0xffffffff, c & 0xffffffff) -def v_max3_u32(a, b, c): return max(a & 0xffffffff, b & 0xffffffff, c & 0xffffffff) -v_min3_f16 = v_min3_f32 -v_max3_f16 = v_max3_f32 -v_min3_i16 = v_min3_i32 -v_max3_i16 = v_max3_i32 +v_min3_f16, v_max3_f16 = v_min3_f32, v_max3_f32 +v_min3_i32, v_max3_i32, v_min3_i16, v_max3_i16 = min, max, min, max +def v_min3_u32(a, b, c): return min(a & MASK32, b & MASK32, c & MASK32) +def v_max3_u32(a, b, c): return max(a & MASK32, b & MASK32, c & MASK32) def v_min3_u16(a, b, c): return min(a & 0xffff, b & 0xffff, c & 0xffff) def v_max3_u16(a, b, c): return max(a & 0xffff, b & 0xffff, c & 0xffff) def ABSDIFF(a, b): return abs(int(a) - int(b)) @@ -295,7 +212,7 @@ def signext_from_bit(val, bit): __all__ = [ # Classes - 'Reg', 'SliceProxy', 'TypedView', 'ExecContext', 'compile_pseudocode', + 'Reg', 'SliceProxy', 'TypedView', # Pack functions '_pack', '_pack32', 'pack', 'pack32', # Constants @@ -381,8 +298,6 @@ ROUND_MODE = _RoundMode() def cvtToQuietNAN(x): return float('nan') DST = None # Placeholder, will be set in context -MASK32, MASK64 = 0xffffffff, 0xffffffffffffffff - # 2/PI with 1201 bits of precision for V_TRIG_PREOP_F64 # Computed as: int((2/pi) * 2^1201) - this is the fractional part of 2/pi scaled to integer # The MSB (bit 1200) corresponds to 2^0 position in the fraction 0.b1200 b1199 ... b1 b0 @@ -624,587 +539,4 @@ class Reg: def __eq__(s, o): return s._val == int(o) def __ne__(s, o): return s._val != int(o) -# ═══════════════════════════════════════════════════════════════════════════════ -# COMPILER: pseudocode -> Python (minimal transforms) -# ═══════════════════════════════════════════════════════════════════════════════ -def compile_pseudocode(pseudocode: str) -> str: - """Compile pseudocode to Python. Transforms are minimal - most syntax just works.""" - # Join continuation lines (lines ending with || or && or open paren) - raw_lines = pseudocode.strip().split('\n') - joined_lines: list[str] = [] - for line in raw_lines: - line = line.strip() - if joined_lines and (joined_lines[-1].rstrip().endswith(('||', '&&', '(', ',')) or - (joined_lines[-1].count('(') > joined_lines[-1].count(')'))): - joined_lines[-1] = joined_lines[-1].rstrip() + ' ' + line - else: - joined_lines.append(line) - - lines = [] - indent, need_pass, in_first_match_loop = 0, False, False - for line in joined_lines: - line = line.strip() - if not line or line.startswith('//'): continue - - # Control flow - only need pass before outdent (endif/endfor/else/elsif) - if line.startswith('if '): - lines.append(' ' * indent + f"if {_expr(line[3:].rstrip(' then'))}:") - indent += 1 - need_pass = True - elif line.startswith('elsif '): - if need_pass: lines.append(' ' * indent + "pass") - indent -= 1 - lines.append(' ' * indent + f"elif {_expr(line[6:].rstrip(' then'))}:") - indent += 1 - need_pass = True - elif line == 'else': - if need_pass: lines.append(' ' * indent + "pass") - indent -= 1 - lines.append(' ' * indent + "else:") - indent += 1 - need_pass = True - elif line.startswith('endif'): - if need_pass: lines.append(' ' * indent + "pass") - indent -= 1 - need_pass = False - elif line.startswith('endfor'): - if need_pass: lines.append(' ' * indent + "pass") - indent -= 1 - need_pass, in_first_match_loop = False, False - elif line.startswith('declare '): - pass - elif m := re.match(r'for (\w+) in (.+?)\s*:\s*(.+?) do', line): - start, end = _expr(m[2].strip()), _expr(m[3].strip()) - lines.append(' ' * indent + f"for {m[1]} in range({start}, int({end})+1):") - indent += 1 - need_pass, in_first_match_loop = True, True - elif '=' in line and not line.startswith('=='): - need_pass = False - line = line.rstrip(';') - # Handle tuple unpacking: { D1.u1, D0.u64 } = expr - if m := re.match(r'\{\s*D1\.[ui]1\s*,\s*D0\.[ui]64\s*\}\s*=\s*(.+)', line): - rhs = _expr(m[1]) - lines.append(' ' * indent + f"_full = {rhs}") - lines.append(' ' * indent + f"D0.u64 = int(_full) & 0xffffffffffffffff") - lines.append(' ' * indent + f"D1 = Reg((int(_full) >> 64) & 1)") - # Compound assignment - elif any(op in line for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^=')): - for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^='): - if op in line: - lhs, rhs = line.split(op, 1) - lines.append(' ' * indent + f"{lhs.strip()} {op} {_expr(rhs.strip())}") - break - else: - lhs, rhs = line.split('=', 1) - lhs_s, rhs_s = lhs.strip(), rhs.strip() - stmt = _assign(lhs_s, _expr(rhs_s)) - # CLZ/CTZ pattern: assignment of loop var to tmp/D0.i32 in first-match loop needs break - if in_first_match_loop and rhs_s == 'i' and (lhs_s == 'tmp' or lhs_s == 'D0.i32'): - stmt += "; break" - lines.append(' ' * indent + stmt) - # If we ended with a control statement that needs a body, add pass - if need_pass: lines.append(' ' * indent + "pass") - return '\n'.join(lines) - -def _assign(lhs: str, rhs: str) -> str: - """Generate assignment. Bare tmp/SCC/etc get wrapped in Reg().""" - if lhs in ('tmp', 'SCC', 'VCC', 'EXEC', 'D0', 'D1', 'saveexec', 'PC'): - return f"{lhs} = Reg({rhs})" - return f"{lhs} = {rhs}" - -def _expr(e: str) -> str: - """Expression transform: minimal - just fix syntax differences.""" - e = e.strip() - e = e.replace('&&', ' and ').replace('||', ' or ').replace('<>', ' != ') - e = re.sub(r'!([^=])', r' not \1', e) - - # Pack: { hi, lo } -> _pack(hi, lo) - e = re.sub(r'\{\s*(\w+\.u32)\s*,\s*(\w+\.u32)\s*\}', r'_pack32(\1, \2)', e) - def pack(m): - hi, lo = _expr(m[1].strip()), _expr(m[2].strip()) - return f'_pack({hi}, {lo})' - e = re.sub(r'\{\s*([^,{}]+)\s*,\s*([^,{}]+)\s*\}', pack, e) - - # Special constant: 1201'B(2.0 / PI) -> TWO_OVER_PI_1201 (precomputed 1201-bit 2/pi) - e = re.sub(r"1201'B\(2\.0\s*/\s*PI\)", "TWO_OVER_PI_1201", e) - - # Literals: 1'0U -> 0, 32'I(x) -> (x), B(x) -> (x) - e = re.sub(r"\d+'([0-9a-fA-Fx]+)[UuFf]*", r'\1', e) - e = re.sub(r"\d+'[FIBU]\(", "(", e) - e = re.sub(r'\bB\(', '(', e) # Bare B( without digit prefix - e = re.sub(r'([0-9a-fA-Fx])ULL\b', r'\1', e) - e = re.sub(r'([0-9a-fA-Fx])LL\b', r'\1', e) - e = re.sub(r'([0-9a-fA-Fx])U\b', r'\1', e) - e = re.sub(r'(\d\.?\d*)F\b', r'\1', e) - # Remove redundant type suffix after lane access: VCC.u64[laneId].u64 -> VCC.u64[laneId] - e = re.sub(r'(\[laneId\])\.[uib]\d+', r'\1', e) - - # Constants - INF is defined as an object supporting .f32/.f64 access - e = e.replace('+INF', 'INF').replace('-INF', '(-INF)') - e = re.sub(r'NAN\.f\d+', 'float("nan")', e) - - # Verilog bit slice syntax: [start +: width] -> extract width bits starting at start - # Convert to Python slice: [start + width - 1 : start] - def convert_verilog_slice(m): - start, width = m.group(1).strip(), m.group(2).strip() - # Convert to high:low slice format - return f'[({start}) + ({width}) - 1 : ({start})]' - e = re.sub(r'\[([^:\[\]]+)\s*\+:\s*([^:\[\]]+)\]', convert_verilog_slice, e) - - # Recursively process bracket contents to handle nested ternaries like S1.u32[x ? a : b] - def process_brackets(s): - result, i = [], 0 - while i < len(s): - if s[i] == '[': - # Find matching ] - depth, start = 1, i + 1 - j = start - while j < len(s) and depth > 0: - if s[j] == '[': depth += 1 - elif s[j] == ']': depth -= 1 - j += 1 - inner = _expr(s[start:j-1]) # Recursively process bracket content - result.append('[' + inner + ']') - i = j - else: - result.append(s[i]) - i += 1 - return ''.join(result) - e = process_brackets(e) - - # Ternary: a ? b : c -> (b if a else c) - while '?' in e: - depth, bracket, q = 0, 0, -1 - for i, c in enumerate(e): - if c == '(': depth += 1 - elif c == ')': depth -= 1 - elif c == '[': bracket += 1 - elif c == ']': bracket -= 1 - elif c == '?' and depth == 0 and bracket == 0: q = i; break - if q < 0: break - depth, bracket, col = 0, 0, -1 - for i in range(q + 1, len(e)): - if e[i] == '(': depth += 1 - elif e[i] == ')': depth -= 1 - elif e[i] == '[': bracket += 1 - elif e[i] == ']': bracket -= 1 - elif e[i] == ':' and depth == 0 and bracket == 0: col = i; break - if col < 0: break - cond, t, f = e[:q].strip(), e[q+1:col].strip(), e[col+1:].strip() - e = f'(({t}) if ({cond}) else ({f}))' - return e - -# ═══════════════════════════════════════════════════════════════════════════════ -# EXECUTION CONTEXT -# ═══════════════════════════════════════════════════════════════════════════════ - -class ExecContext: - """Context for running compiled pseudocode.""" - def __init__(self, s0=0, s1=0, s2=0, d0=0, scc=0, vcc=0, lane=0, exec_mask=MASK32, literal=0, vgprs=None, src0_idx=0, vdst_idx=0): - self.S0, self.S1, self.S2 = Reg(s0), Reg(s1), Reg(s2) - self.D0, self.D1 = Reg(d0), Reg(0) - self.SCC, self.VCC, self.EXEC = Reg(scc), Reg(vcc), Reg(exec_mask) - self.tmp, self.saveexec = Reg(0), Reg(exec_mask) - self.lane, self.laneId, self.literal = lane, lane, literal - self.SIMM16, self.SIMM32 = Reg(literal), Reg(literal) - self.VGPR = vgprs if vgprs is not None else {} - self.SRC0, self.VDST = Reg(src0_idx), Reg(vdst_idx) - - def run(self, code: str): - """Execute compiled code.""" - # Start with module globals (helpers, aliases), then add instance-specific bindings - ns = dict(globals()) - ns.update({ - 'S0': self.S0, 'S1': self.S1, 'S2': self.S2, 'D0': self.D0, 'D1': self.D1, - 'SCC': self.SCC, 'VCC': self.VCC, 'EXEC': self.EXEC, - 'EXEC_LO': SliceProxy(self.EXEC, 31, 0), 'EXEC_HI': SliceProxy(self.EXEC, 63, 32), - 'tmp': self.tmp, 'saveexec': self.saveexec, - 'lane': self.lane, 'laneId': self.laneId, 'literal': self.literal, - 'SIMM16': self.SIMM16, 'SIMM32': self.SIMM32, - 'VGPR': self.VGPR, 'SRC0': self.SRC0, 'VDST': self.VDST, - }) - exec(code, ns) - # Sync rebinds: if register was reassigned to new Reg or value, copy it back - def _sync(ctx_reg, ns_val): - if isinstance(ns_val, Reg): ctx_reg._val = ns_val._val - else: ctx_reg._val = int(ns_val) & MASK64 - if ns.get('SCC') is not self.SCC: _sync(self.SCC, ns['SCC']) - if ns.get('VCC') is not self.VCC: _sync(self.VCC, ns['VCC']) - if ns.get('EXEC') is not self.EXEC: _sync(self.EXEC, ns['EXEC']) - if ns.get('D0') is not self.D0: _sync(self.D0, ns['D0']) - if ns.get('D1') is not self.D1: _sync(self.D1, ns['D1']) - if ns.get('tmp') is not self.tmp: _sync(self.tmp, ns['tmp']) - if ns.get('saveexec') is not self.saveexec: _sync(self.saveexec, ns['saveexec']) - - def result(self) -> dict: - return {"d0": self.D0._val, "scc": self.SCC._val & 1} - -# ═══════════════════════════════════════════════════════════════════════════════ -# PDF EXTRACTION AND CODE GENERATION -# ═══════════════════════════════════════════════════════════════════════════════ - -from extra.assembly.amd.dsl import PDF_URLS -INST_PATTERN = re.compile(r'^([SV]_[A-Z0-9_]+)\s+(\d+)\s*$', re.M) - -# Patterns that can't be handled by the DSL (require special handling in emu.py) -UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS', - 'vscnt', 'vmcnt', 'expcnt', 'lgkmcnt', - 'CVT_OFF_TABLE', 'ThreadMask', - 'S1[i', 'C.i32', 'S[i]', 'in[', - 'if n.', 'DST.u32', 'addrd = DST', 'addr = DST'] # Malformed pseudocode from PDF - -def extract_pseudocode(text: str) -> str | None: - """Extract pseudocode from an instruction description snippet.""" - lines, result, depth, in_lambda = text.split('\n'), [], 0, 0 - for line in lines: - s = line.strip() - if not s: continue - if re.match(r'^\d+ of \d+$', s): continue - if re.match(r'^\d+\.\d+\..*Instructions', s): continue - # Skip document headers (RDNA or CDNA) - if s.startswith('"RDNA') or s.startswith('AMD ') or s.startswith('CDNA'): continue - if s.startswith('Notes') or s.startswith('Functional examples'): break - # Track lambda definitions (e.g., BYTE_PERMUTE = lambda(data, sel) (...)) - if '= lambda(' in s: in_lambda += 1; continue - if in_lambda > 0: - if s.endswith(');'): in_lambda -= 1 - continue - if s.startswith('if '): depth += 1 - elif s.startswith('endif'): depth = max(0, depth - 1) - if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue - if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue - is_code = ( - any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =']) or - any(p in s for p in ['D0[', 'D1[', 'S0[', 'S1[', 'S2[']) or - s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or - re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s) - ) - if is_code: result.append(s) - return '\n'.join(result) if result else None - -def _get_op_enums(arch: str) -> list: - """Dynamically load op enums from the arch-specific autogen module.""" - import importlib - autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}") - # Deterministic order: common enums first, then arch-specific - enums = [] - for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp']: - if hasattr(autogen, name): enums.append(getattr(autogen, name)) - return enums - -def _parse_pseudocode_from_single_pdf(url: str, defined_ops: dict, OP_ENUMS: list) -> dict: - """Parse pseudocode from a single PDF.""" - import pdfplumber - from tinygrad.helpers import fetch - - pdf = pdfplumber.open(fetch(url)) - total_pages = len(pdf.pages) - - page_cache = {} - def get_page_text(i): - if i not in page_cache: page_cache[i] = pdf.pages[i].extract_text() or '' - return page_cache[i] - - # Find the "Instructions" chapter - typically 10-40% through the document - instr_start = None - for i in range(int(total_pages * 0.1), int(total_pages * 0.5)): - if re.search(r'Chapter \d+\.\s+Instructions\b', get_page_text(i)): - instr_start = i - break - if instr_start is None: instr_start = total_pages // 3 # fallback - - # Find end - stop at "Microcode Formats" chapter (typically 60-70% through) - instr_end = total_pages - search_starts = [int(total_pages * 0.6), int(total_pages * 0.5), instr_start] - for start in search_starts: - for i in range(start, min(start + 100, total_pages)): - if re.search(r'Chapter \d+\.\s+Microcode Formats', get_page_text(i)): - instr_end = i - break - if instr_end < total_pages: break - - # Extract remaining pages (some already cached from chapter search) - all_text = '\n'.join(get_page_text(i) for i in range(instr_start, instr_end)) - matches = list(INST_PATTERN.finditer(all_text)) - instructions: dict = {cls: {} for cls in OP_ENUMS} - - for i, match in enumerate(matches): - name, opcode = match.group(1), int(match.group(2)) - key = (name, opcode) - if key not in defined_ops: continue - start = match.end() - end = matches[i + 1].start() if i + 1 < len(matches) else start + 2000 - snippet = all_text[start:end].strip() - if (pseudocode := extract_pseudocode(snippet)): - # Assign to all enums that have this op (e.g., both VOPCOp and VOP3AOp) - for enum_cls, enum_val in defined_ops[key]: - instructions[enum_cls][enum_val] = pseudocode - - return instructions - -def parse_pseudocode_from_pdf(arch: str = "rdna3") -> dict: - """Parse pseudocode from PDF(s) for all ops. Returns {enum_cls: {op: pseudocode}}.""" - OP_ENUMS = _get_op_enums(arch) - # Build a dict from (name, opcode) -> list of (enum_cls, op) tuples - # Multiple enums can have the same op (e.g., VOPCOp and VOP3AOp both have V_CMP_* ops) - defined_ops: dict[tuple, list] = {} - for enum_cls in OP_ENUMS: - for op in enum_cls: - if op.name.startswith(('S_', 'V_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op)) - - urls = PDF_URLS[arch] - if isinstance(urls, str): urls = [urls] - - # Parse all PDFs and merge (union of pseudocode) - # Reverse order so newer PDFs (RDNA3.5, CDNA4) take priority - instructions: dict = {cls: {} for cls in OP_ENUMS} - for url in reversed(urls): - result = _parse_pseudocode_from_single_pdf(url, defined_ops, OP_ENUMS) - for cls, ops in result.items(): - for op, pseudocode in ops.items(): - if op in instructions[cls]: - if instructions[cls][op] != pseudocode: - print(f" Ignoring {op.name} from older PDF:") - print(f" new: {instructions[cls][op]!r}") - print(f" old: {pseudocode!r}") - else: - instructions[cls][op] = pseudocode - - return instructions - -def generate_gen_pcode(output_path: str = "extra/assembly/amd/autogen/rdna3/gen_pcode.py", arch: str = "rdna3"): - """Generate gen_pcode.py - compiled pseudocode functions for the emulator.""" - from pathlib import Path - - OP_ENUMS = _get_op_enums(arch) - - print("Parsing pseudocode from PDF...") - by_cls = parse_pseudocode_from_pdf(arch) - - total_found, total_ops = 0, 0 - for enum_cls in OP_ENUMS: - total = sum(1 for op in enum_cls if op.name.startswith(('S_', 'V_'))) - found = len(by_cls.get(enum_cls, {})) - total_found += found - total_ops += total - print(f"{enum_cls.__name__}: {found}/{total} ({100*found//total if total else 0}%)") - print(f"Total: {total_found}/{total_ops} ({100*total_found//total_ops}%)") - - print("\nCompiling to pseudocode functions...") - # Build dynamic import line based on available enums - enum_names = [e.__name__ for e in OP_ENUMS] - lines = [f'''# autogenerated by pcode.py - do not edit -# to regenerate: python -m extra.assembly.amd.pcode --arch {arch} -# ruff: noqa: E501,F405,F403 -# mypy: ignore-errors -from extra.assembly.amd.autogen.{arch} import {", ".join(enum_names)} -from extra.assembly.amd.pcode import * -'''] - - compiled_count, skipped_count = 0, 0 - - for enum_cls in OP_ENUMS: - cls_name = enum_cls.__name__ - pseudocode_dict = by_cls.get(enum_cls, {}) - if not pseudocode_dict: continue - - fn_entries = [] - for op, pc in pseudocode_dict.items(): - if any(p in pc for p in UNSUPPORTED): - skipped_count += 1 - continue - - try: - code = compile_pseudocode(pc) - # NOTE: Do NOT add more code.replace() hacks here. Fix issues properly in the DSL - # (compile_pseudocode, helper functions, or Reg/TypedView classes) instead. - # V_DIV_FMAS_F32/F64: PDF page 449 says 2^32/2^64 but hardware behavior is more complex. - # The scale direction depends on S2 (the addend): if exponent(S2) > 127 (i.e., S2 >= 2.0), - # scale by 2^+64 (to unscale a numerator that was scaled). Otherwise scale by 2^-64 - # (to unscale a denominator that was scaled). - if op.name == 'V_DIV_FMAS_F32': - code = code.replace( - 'D0.f32 = 2.0 ** 32 * fma(S0.f32, S1.f32, S2.f32)', - 'D0.f32 = (2.0 ** 64 if exponent(S2.f32) > 127 else 2.0 ** -64) * fma(S0.f32, S1.f32, S2.f32)') - if op.name == 'V_DIV_FMAS_F64': - code = code.replace( - 'D0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)', - 'D0.f64 = (2.0 ** 128 if exponent(S2.f64) > 1023 else 2.0 ** -128) * fma(S0.f64, S1.f64, S2.f64)') - # V_DIV_SCALE_F32/F64: PDF page 463-464 has several bugs vs hardware behavior: - # 1. Zero case: hardware sets VCC=1 (PDF doesn't) - # 2. Denorm denom: hardware returns NaN (PDF says scale). VCC is set independently by exp diff check. - # 3. Tiny numer (exp<=23): hardware sets VCC=1 (PDF doesn't) - # 4. Result would be denorm: hardware doesn't scale, just sets VCC=1 - if op.name == 'V_DIV_SCALE_F32': - # Fix 1: Set VCC=1 when zero operands produce NaN - code = code.replace( - 'D0.f32 = float("nan")', - 'VCC = Reg(0x1); D0.f32 = float("nan")') - # Fix 2: Denorm denom returns NaN. Must check this AFTER all VCC-setting logic runs. - # Insert at end of all branches, before the final result is used - code = code.replace( - 'elif S1.f32 == DENORM.f32:\n D0.f32 = ldexp(S0.f32, 64)', - 'elif False:\n pass # denorm check moved to end') - # Add denorm check at the very end - this overrides D0 but preserves VCC - code += '\nif S1.f32 == DENORM.f32:\n D0.f32 = float("nan")' - # Fix 3: Tiny numer should set VCC=1 - code = code.replace( - 'elif exponent(S2.f32) <= 23:\n D0.f32 = ldexp(S0.f32, 64)', - 'elif exponent(S2.f32) <= 23:\n VCC = Reg(0x1); D0.f32 = ldexp(S0.f32, 64)') - # Fix 4: S2/S1 would be denorm - don't scale, just set VCC - code = code.replace( - 'elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)\n if S0.f32 == S2.f32:\n D0.f32 = ldexp(S0.f32, 64)', - 'elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)') - if op.name == 'V_DIV_SCALE_F64': - # Same fixes for f64 version - code = code.replace( - 'D0.f64 = float("nan")', - 'VCC = Reg(0x1); D0.f64 = float("nan")') - code = code.replace( - 'elif S1.f64 == DENORM.f64:\n D0.f64 = ldexp(S0.f64, 128)', - 'elif False:\n pass # denorm check moved to end') - code += '\nif S1.f64 == DENORM.f64:\n D0.f64 = float("nan")' - code = code.replace( - 'elif exponent(S2.f64) <= 52:\n D0.f64 = ldexp(S0.f64, 128)', - 'elif exponent(S2.f64) <= 52:\n VCC = Reg(0x1); D0.f64 = ldexp(S0.f64, 128)') - code = code.replace( - 'elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)\n if S0.f64 == S2.f64:\n D0.f64 = ldexp(S0.f64, 128)', - 'elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)') - # V_DIV_FIXUP_F32/F64: PDF doesn't check isNAN(S0), but hardware returns OVERFLOW if S0 is NaN. - # When division fails (e.g., due to denorm denom), S0 becomes NaN, and fixup should return ±inf. - if op.name == 'V_DIV_FIXUP_F32': - code = code.replace( - 'D0.f32 = ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))', - 'D0.f32 = ((-OVERFLOW_F32) if (sign_out) else (OVERFLOW_F32)) if isNAN(S0.f32) else ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))') - if op.name == 'V_DIV_FIXUP_F64': - code = code.replace( - 'D0.f64 = ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))', - 'D0.f64 = ((-OVERFLOW_F64) if (sign_out) else (OVERFLOW_F64)) if isNAN(S0.f64) else ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))') - # V_TRIG_PREOP_F64: AMD pseudocode uses (x << shift) & mask but mask needs to extract TOP bits. - # The PDF shows: result = 64'F((1201'B(2.0/PI)[1200:0] << shift) & 1201'0x1fffffffffffff) - # Issues to fix: - # 1. After left shift, the interesting bits are at the top, not bottom - need >> (1201-53) - # 2. shift.u32 fails because shift is a plain int after * 53 - use int(shift) - # 3. 64'F(...) means convert int to float (not interpret as bit pattern) - use float() - if op.name == 'V_TRIG_PREOP_F64': - code = code.replace( - 'result = F((TWO_OVER_PI_1201[1200 : 0] << shift.u32) & 0x1fffffffffffff)', - 'result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff)') - # Detect flags for result handling - is_64 = any(p in pc for p in ['D0.u64', 'D0.b64', 'D0.f64', 'D0.i64', 'D1.u64', 'D1.b64', 'D1.f64', 'D1.i64']) - has_d1 = '{ D1' in pc - if has_d1: is_64 = True - is_cmp = (cls_name == 'VOPCOp' or cls_name == 'VOP3Op') and 'D0.u64[laneId]' in pc - is_cmpx = (cls_name == 'VOPCOp' or cls_name == 'VOP3Op') and 'EXEC.u64[laneId]' in pc # V_CMPX writes to EXEC per-lane - # V_DIV_SCALE passes through S0 if no branch taken - is_div_scale = 'DIV_SCALE' in op.name - # VOP3SD instructions that write VCC per-lane (either via VCC.u64[laneId] or by setting VCC = 0/1) - has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale) - # Instructions that use/modify PC - has_pc = 'PC' in pc - - # Generate function with indented body - fn_name = f"_{cls_name}_{op.name}" - lines.append(f"def {fn_name}(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0):") - # Add original pseudocode as comment - for pc_line in pc.split('\n'): - lines.append(f" # {pc_line}") - # Only create Reg objects for registers actually used in the pseudocode - combined = code + pc - regs = [('S0', 'Reg(s0)'), ('S1', 'Reg(s1)'), ('S2', 'Reg(s2)'), - ('D0', 'Reg(s0)' if is_div_scale else 'Reg(d0)'), ('D1', 'Reg(0)'), - ('SCC', 'Reg(scc)'), ('VCC', 'Reg(vcc)'), ('EXEC', 'Reg(exec_mask)'), - ('tmp', 'Reg(0)'), ('saveexec', 'Reg(exec_mask)'), ('laneId', 'lane'), - ('SIMM16', 'Reg(literal)'), ('SIMM32', 'Reg(literal)'), - ('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)'), - ('PC', 'Reg(pc)')] # PC is passed in as byte address - used = {name for name, _ in regs if name in combined} - # EXEC_LO/EXEC_HI need EXEC - if 'EXEC_LO' in combined or 'EXEC_HI' in combined: used.add('EXEC') - # VCCZ/EXECZ need VCC/EXEC - if 'VCCZ' in combined: used.add('VCC') - if 'EXECZ' in combined: used.add('EXEC') - for name, init in regs: - if name in used: lines.append(f" {name} = {init}") - if 'EXEC_LO' in combined: lines.append(" EXEC_LO = SliceProxy(EXEC, 31, 0)") - if 'EXEC_HI' in combined: lines.append(" EXEC_HI = SliceProxy(EXEC, 63, 32)") - # VCCZ = 1 if VCC == 0, EXECZ = 1 if EXEC == 0 - if 'VCCZ' in combined: lines.append(" VCCZ = Reg(1 if VCC._val == 0 else 0)") - if 'EXECZ' in combined: lines.append(" EXECZ = Reg(1 if EXEC._val == 0 else 0)") - # Add compiled pseudocode with markers - lines.append(" # --- compiled pseudocode ---") - for line in code.split('\n'): - lines.append(f" {line}") - lines.append(" # --- end pseudocode ---") - # Generate result dict - use raw params if Reg wasn't created - d0_val = "D0._val" if 'D0' in used else "d0" - scc_val = "SCC._val & 1" if 'SCC' in used else "scc & 1" - lines.append(f" result = {{'d0': {d0_val}, 'scc': {scc_val}}}") - if has_sdst: - lines.append(" result['vcc_lane'] = (VCC._val >> lane) & 1") - elif 'VCC' in used: - lines.append(" if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1") - if is_cmpx: - lines.append(" result['exec_lane'] = (EXEC._val >> lane) & 1") - elif 'EXEC' in used: - lines.append(" if EXEC._val != exec_mask: result['exec'] = EXEC._val") - if is_cmp: - lines.append(" result['vcc_lane'] = (D0._val >> lane) & 1") - if is_64: - lines.append(" result['d0_64'] = True") - if has_d1: - lines.append(" result['d1'] = D1._val & 1") - if has_pc: - # Return new PC as absolute byte address, emulator will compute delta - # Handle negative values (backward jumps): PC._val is stored as unsigned, convert to signed - lines.append(" _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000") - lines.append(" result['new_pc'] = _pc # absolute byte address") - lines.append(" return result") - lines.append("") - - fn_entries.append((op, fn_name)) - compiled_count += 1 - except Exception as e: - print(f" Warning: Failed to compile {op.name}: {e}") - skipped_count += 1 - - if fn_entries: - lines.append(f'{cls_name}_FUNCTIONS = {{') - for op, fn_name in fn_entries: - lines.append(f" {cls_name}.{op.name}: {fn_name},") - lines.append('}') - lines.append('') - - # Add manually implemented V_WRITELANE_B32 (not in PDF pseudocode, requires special vgpr_write handling) - # Only add for architectures that have VOP3Op (RDNA) not VOP3AOp/VOP3BOp (CDNA) - if 'VOP3Op' in enum_names: - lines.append(''' -# V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) -def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): - wr_lane = s1 & 0x1f # lane select (5 bits for wave32) - return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)} -VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32 -''') - - lines.append('COMPILED_FUNCTIONS = {') - for enum_cls in OP_ENUMS: - cls_name = enum_cls.__name__ - if by_cls.get(enum_cls): lines.append(f' {cls_name}: {cls_name}_FUNCTIONS,') - lines.append('}') - lines.append('') - lines.append('def get_compiled_functions(): return COMPILED_FUNCTIONS') - - Path(output_path).write_text('\n'.join(lines)) - print(f"\nGenerated {output_path}: {compiled_count} compiled, {skipped_count} skipped") - -if __name__ == "__main__": - import argparse - parser = argparse.ArgumentParser(description="Generate pseudocode functions from AMD ISA PDF") - parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3", help="Target architecture (default: rdna3)") - args = parser.parse_args() - if args.arch == "all": - for arch in PDF_URLS.keys(): - generate_gen_pcode(output_path=f"extra/assembly/amd/autogen/{arch}/gen_pcode.py", arch=arch) - else: - generate_gen_pcode(output_path=f"extra/assembly/amd/autogen/{args.arch}/gen_pcode.py", arch=args.arch) diff --git a/extra/assembly/amd/pdf.py b/extra/assembly/amd/pdf.py new file mode 100644 index 0000000000..177820a459 --- /dev/null +++ b/extra/assembly/amd/pdf.py @@ -0,0 +1,623 @@ +# Generate AMD ISA autogen files from PDF documentation +# Combines format/enum generation (previously in dsl.py) and pseudocode compilation (previously in pcode.py) +# Usage: python -m extra.assembly.amd.pdf [--arch rdna3|rdna4|cdna|all] +import re, functools +from pathlib import Path +from concurrent.futures import ProcessPoolExecutor + +PDF_URLS = { + "rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content", + "rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content", + "cdna": ["https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf", + "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"], +} + +# Field type mappings and ordering +FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src', + 'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField', + 'VDATA': 'VGPRField', 'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField', + 'SIMM16': 'SImm', 'OFFSET': 'Imm', 'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src', + 'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'} +FIELD_ORDER = { + 'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'], + 'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'], + 'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'], + 'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'], + 'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'], + 'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'], + 'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'], + 'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'], + 'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'], + 'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'], + 'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'], + 'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'], + 'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'], + 'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']} +SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'} +FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO', + '4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'} +INST_PATTERN = re.compile(r'^([SV]_[A-Z0-9_]+)\s+(\d+)\s*$', re.M) + +# Patterns that can't be handled by the DSL (require special handling in emu.py) +UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS', + 'vscnt', 'vmcnt', 'expcnt', 'lgkmcnt', + 'CVT_OFF_TABLE', 'ThreadMask', + 'S1[i', 'C.i32', 'S[i]', 'in[', + 'if n.', 'DST.u32', 'addrd = DST', 'addr = DST'] # Malformed pseudocode from PDF + +# ═══════════════════════════════════════════════════════════════════════════════ +# COMPILER: pseudocode -> Python (minimal transforms) +# ═══════════════════════════════════════════════════════════════════════════════ + +def compile_pseudocode(pseudocode: str) -> str: + """Compile pseudocode to Python. Transforms are minimal - most syntax just works.""" + raw_lines = pseudocode.strip().split('\n') + joined_lines: list[str] = [] + for line in raw_lines: + line = line.strip() + if joined_lines and (joined_lines[-1].rstrip().endswith(('||', '&&', '(', ',')) or + (joined_lines[-1].count('(') > joined_lines[-1].count(')'))): + joined_lines[-1] = joined_lines[-1].rstrip() + ' ' + line + else: + joined_lines.append(line) + + lines = [] + indent, need_pass, in_first_match_loop = 0, False, False + for line in joined_lines: + line = line.strip() + if not line or line.startswith('//'): continue + if line.startswith('if '): + lines.append(' ' * indent + f"if {_expr(line[3:].rstrip(' then'))}:") + indent += 1 + need_pass = True + elif line.startswith('elsif '): + if need_pass: lines.append(' ' * indent + "pass") + indent -= 1 + lines.append(' ' * indent + f"elif {_expr(line[6:].rstrip(' then'))}:") + indent += 1 + need_pass = True + elif line == 'else': + if need_pass: lines.append(' ' * indent + "pass") + indent -= 1 + lines.append(' ' * indent + "else:") + indent += 1 + need_pass = True + elif line.startswith('endif'): + if need_pass: lines.append(' ' * indent + "pass") + indent -= 1 + need_pass = False + elif line.startswith('endfor'): + if need_pass: lines.append(' ' * indent + "pass") + indent -= 1 + need_pass, in_first_match_loop = False, False + elif line.startswith('declare '): + pass + elif m := re.match(r'for (\w+) in (.+?)\s*:\s*(.+?) do', line): + start, end = _expr(m[2].strip()), _expr(m[3].strip()) + lines.append(' ' * indent + f"for {m[1]} in range({start}, int({end})+1):") + indent += 1 + need_pass, in_first_match_loop = True, True + elif '=' in line and not line.startswith('=='): + need_pass = False + line = line.rstrip(';') + if m := re.match(r'\{\s*D1\.[ui]1\s*,\s*D0\.[ui]64\s*\}\s*=\s*(.+)', line): + rhs = _expr(m[1]) + lines.append(' ' * indent + f"_full = {rhs}") + lines.append(' ' * indent + f"D0.u64 = int(_full) & 0xffffffffffffffff") + lines.append(' ' * indent + f"D1 = Reg((int(_full) >> 64) & 1)") + elif any(op in line for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^=')): + for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^='): + if op in line: + lhs, rhs = line.split(op, 1) + lines.append(' ' * indent + f"{lhs.strip()} {op} {_expr(rhs.strip())}") + break + else: + lhs, rhs = line.split('=', 1) + lhs_s, rhs_s = lhs.strip(), rhs.strip() + stmt = _assign(lhs_s, _expr(rhs_s)) + if in_first_match_loop and rhs_s == 'i' and (lhs_s == 'tmp' or lhs_s == 'D0.i32'): + stmt += "; break" + lines.append(' ' * indent + stmt) + if need_pass: lines.append(' ' * indent + "pass") + return '\n'.join(lines) + +def _assign(lhs: str, rhs: str) -> str: + if lhs in ('tmp', 'SCC', 'VCC', 'EXEC', 'D0', 'D1', 'saveexec', 'PC'): + return f"{lhs} = Reg({rhs})" + return f"{lhs} = {rhs}" + +def _expr(e: str) -> str: + e = e.strip() + e = e.replace('&&', ' and ').replace('||', ' or ').replace('<>', ' != ') + e = re.sub(r'!([^=])', r' not \1', e) + e = re.sub(r'\{\s*(\w+\.u32)\s*,\s*(\w+\.u32)\s*\}', r'_pack32(\1, \2)', e) + def pack(m): + hi, lo = _expr(m[1].strip()), _expr(m[2].strip()) + return f'_pack({hi}, {lo})' + e = re.sub(r'\{\s*([^,{}]+)\s*,\s*([^,{}]+)\s*\}', pack, e) + e = re.sub(r"1201'B\(2\.0\s*/\s*PI\)", "TWO_OVER_PI_1201", e) + e = re.sub(r"\d+'([0-9a-fA-Fx]+)[UuFf]*", r'\1', e) + e = re.sub(r"\d+'[FIBU]\(", "(", e) + e = re.sub(r'\bB\(', '(', e) + e = re.sub(r'([0-9a-fA-Fx])ULL\b', r'\1', e) + e = re.sub(r'([0-9a-fA-Fx])LL\b', r'\1', e) + e = re.sub(r'([0-9a-fA-Fx])U\b', r'\1', e) + e = re.sub(r'(\d\.?\d*)F\b', r'\1', e) + e = re.sub(r'(\[laneId\])\.[uib]\d+', r'\1', e) + e = e.replace('+INF', 'INF').replace('-INF', '(-INF)') + e = re.sub(r'NAN\.f\d+', 'float("nan")', e) + def convert_verilog_slice(m): + start, width = m.group(1).strip(), m.group(2).strip() + return f'[({start}) + ({width}) - 1 : ({start})]' + e = re.sub(r'\[([^:\[\]]+)\s*\+:\s*([^:\[\]]+)\]', convert_verilog_slice, e) + def process_brackets(s): + result, i = [], 0 + while i < len(s): + if s[i] == '[': + depth, start = 1, i + 1 + j = start + while j < len(s) and depth > 0: + if s[j] == '[': depth += 1 + elif s[j] == ']': depth -= 1 + j += 1 + inner = _expr(s[start:j-1]) + result.append('[' + inner + ']') + i = j + else: + result.append(s[i]) + i += 1 + return ''.join(result) + e = process_brackets(e) + while '?' in e: + depth, bracket, q = 0, 0, -1 + for i, c in enumerate(e): + if c == '(': depth += 1 + elif c == ')': depth -= 1 + elif c == '[': bracket += 1 + elif c == ']': bracket -= 1 + elif c == '?' and depth == 0 and bracket == 0: q = i; break + if q < 0: break + depth, bracket, col = 0, 0, -1 + for i in range(q + 1, len(e)): + if e[i] == '(': depth += 1 + elif e[i] == ')': depth -= 1 + elif e[i] == '[': bracket += 1 + elif e[i] == ']': bracket -= 1 + elif e[i] == ':' and depth == 0 and bracket == 0: col = i; break + if col < 0: break + cond, t, f = e[:q].strip(), e[q+1:col].strip(), e[col+1:].strip() + e = f'(({t}) if ({cond}) else ({f}))' + return e + +# ═══════════════════════════════════════════════════════════════════════════════ +# PDF PARSING WITH PAGE CACHING +# ═══════════════════════════════════════════════════════════════════════════════ + +class CachedPDF: + """PDF wrapper with page text/table caching for faster repeated access.""" + def __init__(self, pdf): + self._pdf, self._text_cache, self._table_cache = pdf, {}, {} + def __len__(self): return len(self._pdf.pages) + def text(self, i): + if i not in self._text_cache: self._text_cache[i] = self._pdf.pages[i].extract_text() or '' + return self._text_cache[i] + def tables(self, i): + if i not in self._table_cache: self._table_cache[i] = [t.extract() for t in self._pdf.pages[i].find_tables()] + return self._table_cache[i] + +def _parse_bits(s: str) -> tuple[int, int] | None: + return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None + +def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]: + fields = [] + for row in table[1:]: + if not row or not row[0]: continue + name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip() + if not (bits := _parse_bits(bits_str)): continue + enc_val, hi, lo = None, bits[0], bits[1] + if name == 'ENCODING' and row[2]: + if m := re.search(r"(?:'b|Must be:\s*)([01_]+)", row[2]): + enc_bits = m.group(1).replace('_', '') + enc_val, declared_width, actual_width = int(enc_bits, 2), hi - lo + 1, len(enc_bits) + if actual_width > declared_width: lo = hi - actual_width + 1 + ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper()) + fields.append((name, hi, lo, enc_val, ftype)) + return fields + +def _parse_single_pdf(url: str): + """Parse a single PDF and return (formats, enums, src_enum, doc_name, instructions).""" + import pdfplumber + from tinygrad.helpers import fetch + + pdf = CachedPDF(pdfplumber.open(fetch(url))) + total_pages = len(pdf) + + # Auto-detect document type + first_page = pdf.text(0) + is_cdna4, is_cdna3 = 'CDNA4' in first_page or 'CDNA 4' in first_page, 'CDNA3' in first_page or 'MI300' in first_page + is_cdna, is_rdna4 = is_cdna3 or is_cdna4, 'RDNA4' in first_page or 'RDNA 4' in first_page + is_rdna35, is_rdna3 = 'RDNA3.5' in first_page or 'RDNA 3.5' in first_page, 'RDNA3' in first_page and 'RDNA3.5' not in first_page + doc_name = "CDNA4" if is_cdna4 else "CDNA3" if is_cdna3 else "RDNA4" if is_rdna4 else "RDNA3.5" if is_rdna35 else "RDNA3" if is_rdna3 else "Unknown" + + # Find Microcode Formats section (for formats/enums) + microcode_start = next((i for i in range(int(total_pages * 0.2), total_pages) + if re.search(r'\d+\.\d+\.\d+\.\s+SOP2\b|Chapter \d+\.\s+Microcode Formats', pdf.text(i))), int(total_pages * 0.9)) + # Find Instructions section (for pseudocode) + instr_start = next((i for i in range(int(total_pages * 0.1), int(total_pages * 0.5)) + if re.search(r'Chapter \d+\.\s+Instructions\b', pdf.text(i))), total_pages // 3) + instr_end = next((i for start in [int(total_pages * 0.6), int(total_pages * 0.5), instr_start] + for i in range(start, min(start + 100, total_pages)) + if re.search(r'Chapter \d+\.\s+Microcode Formats', pdf.text(i))), total_pages) + + # Parse src enum from SSRC encoding table + src_enum = dict(SRC_EXTRAS) + for i in range(microcode_start, min(microcode_start + 10, total_pages)): + text = pdf.text(i) + if 'SSRC0' in text and 'VCC_LO' in text: + for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M): + val, name = int(m.group(1)), m.group(2).rstrip('.:') + if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name] + elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name + break + + # Parse opcode tables + full_text = '\n'.join(pdf.text(i) for i in range(microcode_start, min(microcode_start + 50, total_pages))) + enums: dict[str, dict[int, str]] = {} + for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S): + if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}: + enums[m.group(1) + "Op"] = ops + if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S): + if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}: + enums["VOPDOp"] = ops + enum_names = set(enums.keys()) + + # Parse instruction formats + def is_fields_table(t): return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '') + def has_encoding(fields): return any(f[0] == 'ENCODING' for f in fields) + def has_header_before_fields(text): return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos])) + + format_headers = [] + for i in range(50): + if microcode_start + i >= total_pages: break + text = pdf.text(microcode_start + i) + for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start())) + for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text): + fmt_name = m.group(1) + if is_cdna and fmt_name.isupper() and len(fmt_name) >= 2: format_headers.append((fmt_name, i, m.start())) + elif m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < 50: + next_text = pdf.text(microcode_start + i + 1).lstrip() + if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]): + format_headers.append((fmt_name, i, m.start())) + + formats: dict[str, list] = {} + for fmt_name, rel_idx, header_pos in format_headers: + if fmt_name in formats: continue + page_idx = microcode_start + rel_idx + text = pdf.text(page_idx) + field_pos = text.find('Field Name', header_pos) + fields = None + for offset in range(3): + if page_idx + offset >= total_pages: break + if offset > 0 and has_header_before_fields(pdf.text(page_idx + offset)): break + for t in pdf.tables(page_idx + offset) if offset > 0 or field_pos > header_pos else []: + if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f): fields = f; break + if fields: break + if not fields and field_pos > header_pos: + for t in pdf.tables(page_idx): + if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)): fields = f; break + if not fields: continue + field_names = {f[0] for f in fields} + for pg_offset in range(1, 3): + if page_idx + pg_offset >= total_pages or has_header_before_fields(pdf.text(page_idx + pg_offset)): break + for t in pdf.tables(page_idx + pg_offset): + if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra): + for ef in extra: + if ef[0] not in field_names: fields.append(ef); field_names.add(ef[0]) + break + formats[fmt_name] = fields + + # Fix known PDF errors + if 'SMEM' in formats: + formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t) + for n, h, l, e, t in formats['SMEM']] + if doc_name in ('RDNA3', 'RDNA3.5'): + if 'SOPPOp' in enums: assert 8 not in enums['SOPPOp']; enums['SOPPOp'][8] = 'S_WAITCNT_DEPCTR' + if 'DSOp' in enums: + for k, v in {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'}.items(): + assert k not in enums['DSOp']; enums['DSOp'][k] = v + if 'FLATOp' in enums: + for k, v in {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}.items(): + assert k not in enums['FLATOp']; enums['FLATOp'][k] = v + + # Extract pseudocode for instructions + all_text = '\n'.join(pdf.text(i) for i in range(instr_start, instr_end)) + matches = list(INST_PATTERN.finditer(all_text)) + raw_pseudocode: dict[tuple[str, int], str] = {} + for i, match in enumerate(matches): + name, opcode = match.group(1), int(match.group(2)) + start, end = match.end(), matches[i + 1].start() if i + 1 < len(matches) else match.end() + 2000 + snippet = all_text[start:end].strip() + if pseudocode := _extract_pseudocode(snippet): raw_pseudocode[(name, opcode)] = pseudocode + + return {"formats": formats, "enums": enums, "src_enum": src_enum, "doc_name": doc_name, "pseudocode": raw_pseudocode, "is_cdna": is_cdna} + +def _extract_pseudocode(text: str) -> str | None: + """Extract pseudocode from an instruction description snippet.""" + lines, result, depth, in_lambda = text.split('\n'), [], 0, 0 + for line in lines: + s = line.strip() + if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue + if s.startswith(('Notes', 'Functional examples')): break + if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue + if '= lambda(' in s: in_lambda += 1; continue + if in_lambda > 0: + if s.endswith(');'): in_lambda -= 1 + continue + if s.startswith('if '): depth += 1 + elif s.startswith('endif'): depth = max(0, depth - 1) + if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue + if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue + is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =', + 'D0[', 'D1[', 'S0[', 'S1[', 'S2[']) or + s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or + re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s)) + if is_code: result.append(s) + return '\n'.join(result) if result else None + +def _merge_results(results: list[dict]) -> dict: + """Merge multiple PDF parse results into a superset.""" + merged = {"formats": {}, "enums": {}, "src_enum": dict(SRC_EXTRAS), "doc_names": [], "pseudocode": {}, "is_cdna": False} + for r in results: + merged["doc_names"].append(r["doc_name"]) + merged["is_cdna"] = merged["is_cdna"] or r["is_cdna"] + for val, name in r["src_enum"].items(): + if val in merged["src_enum"]: assert merged["src_enum"][val] == name + else: merged["src_enum"][val] = name + for enum_name, ops in r["enums"].items(): + if enum_name not in merged["enums"]: merged["enums"][enum_name] = {} + for val, name in ops.items(): + if val in merged["enums"][enum_name]: assert merged["enums"][enum_name][val] == name + else: merged["enums"][enum_name][val] = name + for fmt_name, fields in r["formats"].items(): + if fmt_name not in merged["formats"]: merged["formats"][fmt_name] = list(fields) + else: + existing = {f[0]: (f[1], f[2]) for f in merged["formats"][fmt_name]} + for f in fields: + if f[0] in existing: assert existing[f[0]] == (f[1], f[2]) + else: merged["formats"][fmt_name].append(f) + for key, pc in r["pseudocode"].items(): + if key not in merged["pseudocode"]: merged["pseudocode"][key] = pc + return merged + +# ═══════════════════════════════════════════════════════════════════════════════ +# CODE GENERATION +# ═══════════════════════════════════════════════════════════════════════════════ + +def _generate_init_py(formats, enums, src_enum, doc_name) -> str: + """Generate __init__.py content (instruction formats and enums).""" + def enum_lines(name, items): return [f"class {name}(IntEnum):"] + [f" {n} = {v}" for v, n in sorted(items.items())] + [""] + def field_key(f, order): return order.index(f[0].lower()) if f[0].lower() in order else 1000 + lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit", "from enum import IntEnum", "from typing import Annotated", + "from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField", + "import functools", ""] + lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], []) + format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}} + lines.append("# instruction formats") + for fmt_name, fields in sorted(formats.items()): + base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32" + order = FIELD_ORDER.get(fmt_name, []) + lines.append(f"class {fmt_name}({base}):") + if enc := next((f for f in fields if f[0] == 'ENCODING'), None): + lines.append(f" encoding = bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f" encoding = bits[{enc[1]}] == {enc[3]}") + if defaults := format_defaults.get(fmt_name): lines.append(f" _defaults = {defaults}") + for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=lambda f: field_key(f, order)): + ann = f":Annotated[BitField, {ftype}]" if ftype and ftype.endswith('Op') else f":{ftype}" if ftype else "" + lines.append(f" {name.lower()}{ann} = bits[{hi}]" if hi == lo else f" {name.lower()}{ann} = bits[{hi}:{lo}]") + lines.append("") + lines.append("# instruction helpers") + for cls_name, ops in sorted(enums.items()): + fmt = cls_name[:-2] + for op_val, name in sorted(ops.items()): + seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt, "") + tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}") + if fmt in formats or fmt in ("GLOBAL", "SCRATCH"): + suffix = "_e32" if fmt in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt == "VOP3" and op_val < 512 else "" + if name in ('V_FMAMK_F32', 'V_FMAMK_F16'): + lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)") + elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'): + lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)") + else: lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})") + src_names = {name for _, name in src_enum.items()} + lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in {'DPP8', 'DPP16'}] + if "NULL" in src_names: lines.append("OFF = NULL\n") + return '\n'.join(lines) + +def _generate_gen_pcode_py(enums, pseudocode, arch) -> str: + """Generate gen_pcode.py content (compiled pseudocode functions).""" + # Get op enums for this arch + import importlib + autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}") + OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp'] if hasattr(autogen, name)] + + # Build defined ops mapping + defined_ops: dict[tuple, list] = {} + for enum_cls in OP_ENUMS: + for op in enum_cls: + if op.name.startswith(('S_', 'V_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op)) + + enum_names = [e.__name__ for e in OP_ENUMS] + lines = [f'''# autogenerated by pdf.py - do not edit +# to regenerate: python -m extra.assembly.amd.pdf --arch {arch} +# ruff: noqa: E501,F405,F403 +# mypy: ignore-errors +from extra.assembly.amd.autogen.{arch} import {", ".join(enum_names)} +from extra.assembly.amd.pcode import * +'''] + + instructions: dict = {cls: {} for cls in OP_ENUMS} + for key, pc in pseudocode.items(): + if key in defined_ops: + for enum_cls, enum_val in defined_ops[key]: instructions[enum_cls][enum_val] = pc + + for enum_cls in OP_ENUMS: + cls_name = enum_cls.__name__ + if not instructions.get(enum_cls): continue + fn_entries = [] + for op, pc in instructions[enum_cls].items(): + if any(p in pc for p in UNSUPPORTED): continue + try: + code = compile_pseudocode(pc) + code = _apply_pseudocode_fixes(op, code) + fn_name, fn_code = _generate_function(cls_name, op, pc, code) + lines.append(fn_code) + fn_entries.append((op, fn_name)) + except Exception as e: print(f" Warning: Failed to compile {op.name}: {e}") + if fn_entries: + lines.append(f'{cls_name}_FUNCTIONS = {{') + for op, fn_name in fn_entries: lines.append(f" {cls_name}.{op.name}: {fn_name},") + lines.append('}\n') + + # Add V_WRITELANE_B32 if VOP3Op exists + if 'VOP3Op' in enum_names: + lines.append(''' +# V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) +def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): + wr_lane = s1 & 0x1f + return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)} +VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32 +''') + + lines.append('COMPILED_FUNCTIONS = {') + for enum_cls in OP_ENUMS: + if instructions.get(enum_cls): lines.append(f' {enum_cls.__name__}: {enum_cls.__name__}_FUNCTIONS,') + lines.append('}\n\ndef get_compiled_functions(): return COMPILED_FUNCTIONS') + return '\n'.join(lines) + +def _apply_pseudocode_fixes(op, code: str) -> str: + """Apply known fixes for PDF pseudocode bugs.""" + if op.name == 'V_DIV_FMAS_F32': + code = code.replace('D0.f32 = 2.0 ** 32 * fma(S0.f32, S1.f32, S2.f32)', + 'D0.f32 = (2.0 ** 64 if exponent(S2.f32) > 127 else 2.0 ** -64) * fma(S0.f32, S1.f32, S2.f32)') + if op.name == 'V_DIV_FMAS_F64': + code = code.replace('D0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)', + 'D0.f64 = (2.0 ** 128 if exponent(S2.f64) > 1023 else 2.0 ** -128) * fma(S0.f64, S1.f64, S2.f64)') + if op.name == 'V_DIV_SCALE_F32': + code = code.replace('D0.f32 = float("nan")', 'VCC = Reg(0x1); D0.f32 = float("nan")') + code = code.replace('elif S1.f32 == DENORM.f32:\n D0.f32 = ldexp(S0.f32, 64)', 'elif False:\n pass') + code += '\nif S1.f32 == DENORM.f32:\n D0.f32 = float("nan")' + code = code.replace('elif exponent(S2.f32) <= 23:\n D0.f32 = ldexp(S0.f32, 64)', 'elif exponent(S2.f32) <= 23:\n VCC = Reg(0x1); D0.f32 = ldexp(S0.f32, 64)') + code = code.replace('elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)\n if S0.f32 == S2.f32:\n D0.f32 = ldexp(S0.f32, 64)', 'elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)') + if op.name == 'V_DIV_SCALE_F64': + code = code.replace('D0.f64 = float("nan")', 'VCC = Reg(0x1); D0.f64 = float("nan")') + code = code.replace('elif S1.f64 == DENORM.f64:\n D0.f64 = ldexp(S0.f64, 128)', 'elif False:\n pass') + code += '\nif S1.f64 == DENORM.f64:\n D0.f64 = float("nan")' + code = code.replace('elif exponent(S2.f64) <= 52:\n D0.f64 = ldexp(S0.f64, 128)', 'elif exponent(S2.f64) <= 52:\n VCC = Reg(0x1); D0.f64 = ldexp(S0.f64, 128)') + code = code.replace('elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)\n if S0.f64 == S2.f64:\n D0.f64 = ldexp(S0.f64, 128)', 'elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)') + if op.name == 'V_DIV_FIXUP_F32': + code = code.replace('D0.f32 = ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))', + 'D0.f32 = ((-OVERFLOW_F32) if (sign_out) else (OVERFLOW_F32)) if isNAN(S0.f32) else ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))') + if op.name == 'V_DIV_FIXUP_F64': + code = code.replace('D0.f64 = ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))', + 'D0.f64 = ((-OVERFLOW_F64) if (sign_out) else (OVERFLOW_F64)) if isNAN(S0.f64) else ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))') + if op.name == 'V_TRIG_PREOP_F64': + code = code.replace('result = F((TWO_OVER_PI_1201[1200 : 0] << shift.u32) & 0x1fffffffffffff)', + 'result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff)') + return code + +def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]: + """Generate a single compiled pseudocode function.""" + is_64 = any(p in pc for p in ['D0.u64', 'D0.b64', 'D0.f64', 'D0.i64', 'D1.u64', 'D1.b64', 'D1.f64', 'D1.i64']) + has_d1 = '{ D1' in pc + if has_d1: is_64 = True + is_cmp = (cls_name in ('VOPCOp', 'VOP3Op')) and 'D0.u64[laneId]' in pc + is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc + is_div_scale = 'DIV_SCALE' in op.name + has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale) + has_pc = 'PC' in pc + combined = code + pc + + fn_name = f"_{cls_name}_{op.name}" + lines = [f"def {fn_name}(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0, pc=0):"] + for pc_line in pc.split('\n'): lines.append(f" # {pc_line}") + + regs = [('S0', 'Reg(s0)'), ('S1', 'Reg(s1)'), ('S2', 'Reg(s2)'), + ('D0', 'Reg(s0)' if is_div_scale else 'Reg(d0)'), ('D1', 'Reg(0)'), + ('SCC', 'Reg(scc)'), ('VCC', 'Reg(vcc)'), ('EXEC', 'Reg(exec_mask)'), + ('tmp', 'Reg(0)'), ('saveexec', 'Reg(exec_mask)'), ('laneId', 'lane'), + ('SIMM16', 'Reg(literal)'), ('SIMM32', 'Reg(literal)'), + ('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)'), ('PC', 'Reg(pc)')] + used = {name for name, _ in regs if name in combined} + if 'EXEC_LO' in combined or 'EXEC_HI' in combined: used.add('EXEC') + if 'VCCZ' in combined: used.add('VCC') + if 'EXECZ' in combined: used.add('EXEC') + for name, init in regs: + if name in used: lines.append(f" {name} = {init}") + if 'EXEC_LO' in combined: lines.append(" EXEC_LO = SliceProxy(EXEC, 31, 0)") + if 'EXEC_HI' in combined: lines.append(" EXEC_HI = SliceProxy(EXEC, 63, 32)") + if 'VCCZ' in combined: lines.append(" VCCZ = Reg(1 if VCC._val == 0 else 0)") + if 'EXECZ' in combined: lines.append(" EXECZ = Reg(1 if EXEC._val == 0 else 0)") + lines.append(" # --- compiled pseudocode ---") + for line in code.split('\n'): lines.append(f" {line}") + lines.append(" # --- end pseudocode ---") + d0_val, scc_val = ("D0._val" if 'D0' in used else "d0"), ("SCC._val & 1" if 'SCC' in used else "scc & 1") + lines.append(f" result = {{'d0': {d0_val}, 'scc': {scc_val}}}") + if has_sdst: lines.append(" result['vcc_lane'] = (VCC._val >> lane) & 1") + elif 'VCC' in used: lines.append(" if VCC._val != vcc: result['vcc_lane'] = (VCC._val >> lane) & 1") + if is_cmpx: lines.append(" result['exec_lane'] = (EXEC._val >> lane) & 1") + elif 'EXEC' in used: lines.append(" if EXEC._val != exec_mask: result['exec'] = EXEC._val") + if is_cmp: lines.append(" result['vcc_lane'] = (D0._val >> lane) & 1") + if is_64: lines.append(" result['d0_64'] = True") + if has_d1: lines.append(" result['d1'] = D1._val & 1") + if has_pc: + lines.append(" _pc = PC._val if PC._val < 0x8000000000000000 else PC._val - 0x10000000000000000") + lines.append(" result['new_pc'] = _pc") + lines.append(" return result\n") + return fn_name, '\n'.join(lines) + +# ═══════════════════════════════════════════════════════════════════════════════ +# MAIN GENERATION +# ═══════════════════════════════════════════════════════════════════════════════ + +def generate_arch(arch: str) -> dict: + """Generate both __init__.py and gen_pcode.py for a single architecture.""" + urls = PDF_URLS[arch] + if isinstance(urls, str): urls = [urls] + + print(f"\n{'='*60}\nGenerating {arch}...") + print(f"Parsing {len(urls)} PDF(s)...") + results = [_parse_single_pdf(url) for url in urls] + merged = _merge_results(results) if len(results) > 1 else results[0] + doc_name = "+".join(merged["doc_names"]) if len(results) > 1 else merged["doc_name"] + + # Write __init__.py + init_path = Path(f"extra/assembly/amd/autogen/{arch}/__init__.py") + init_path.parent.mkdir(parents=True, exist_ok=True) + init_content = _generate_init_py(merged["formats"], merged["enums"], merged["src_enum"], doc_name) + init_path.write_text(init_content) + print(f"Generated {init_path}: SrcEnum ({len(merged['src_enum'])}) + {len(merged['enums'])} enums + {len(merged['formats'])} formats") + + # Write gen_pcode.py (needs __init__.py to exist first for imports) + pcode_path = Path(f"extra/assembly/amd/autogen/{arch}/gen_pcode.py") + pcode_content = _generate_gen_pcode_py(merged["enums"], merged["pseudocode"], arch) + pcode_path.write_text(pcode_content) + print(f"Generated {pcode_path}: {len(merged['pseudocode'])} instructions") + + return merged + +def _generate_arch_wrapper(arch: str): + """Wrapper for multiprocessing - returns arch name for ordering.""" + generate_arch(arch) + return arch + +def generate_all(): + """Generate all architectures in parallel.""" + with ProcessPoolExecutor() as executor: + list(executor.map(_generate_arch_wrapper, PDF_URLS.keys())) + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="Generate AMD ISA autogen files from PDF documentation") + parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3") + args = parser.parse_args() + if args.arch == "all": generate_all() + else: generate_arch(args.arch) diff --git a/extra/assembly/amd/test/helpers.py b/extra/assembly/amd/test/helpers.py index cb98cd4968..cbfb1b1c73 100644 --- a/extra/assembly/amd/test/helpers.py +++ b/extra/assembly/amd/test/helpers.py @@ -22,3 +22,45 @@ def get_llvm_objdump(): for p in ['llvm-objdump', 'llvm-objdump-21', 'llvm-objdump-20']: if shutil.which(p): return p raise FileNotFoundError("llvm-objdump not found") + +# ═══════════════════════════════════════════════════════════════════════════════ +# EXECUTION CONTEXT (for testing compiled pseudocode) +# ═══════════════════════════════════════════════════════════════════════════════ + +class ExecContext: + """Context for running compiled pseudocode in tests.""" + def __init__(self, s0=0, s1=0, s2=0, d0=0, scc=0, vcc=0, lane=0, exec_mask=0xffffffff, literal=0, vgprs=None, src0_idx=0, vdst_idx=0): + from extra.assembly.amd.pcode import Reg, MASK32, MASK64, SliceProxy + self._Reg, self._MASK64, self._SliceProxy = Reg, MASK64, SliceProxy + self.S0, self.S1, self.S2 = Reg(s0), Reg(s1), Reg(s2) + self.D0, self.D1 = Reg(d0), Reg(0) + self.SCC, self.VCC, self.EXEC = Reg(scc), Reg(vcc), Reg(exec_mask) + self.tmp, self.saveexec = Reg(0), Reg(exec_mask) + self.lane, self.laneId, self.literal = lane, lane, literal + self.SIMM16, self.SIMM32 = Reg(literal), Reg(literal) + self.VGPR = vgprs if vgprs is not None else {} + self.SRC0, self.VDST = Reg(src0_idx), Reg(vdst_idx) + + def run(self, code: str): + """Execute compiled code.""" + import extra.assembly.amd.pcode as pcode + ns = {k: getattr(pcode, k) for k in dir(pcode) if not k.startswith('_')} + # Also include underscore-prefixed helpers that compiled pseudocode uses + for k in ['_pack', '_pack32']: + if hasattr(pcode, k): ns[k] = getattr(pcode, k) + ns.update({ + 'S0': self.S0, 'S1': self.S1, 'S2': self.S2, 'D0': self.D0, 'D1': self.D1, + 'SCC': self.SCC, 'VCC': self.VCC, 'EXEC': self.EXEC, + 'EXEC_LO': self._SliceProxy(self.EXEC, 31, 0), 'EXEC_HI': self._SliceProxy(self.EXEC, 63, 32), + 'tmp': self.tmp, 'saveexec': self.saveexec, + 'lane': self.lane, 'laneId': self.laneId, 'literal': self.literal, + 'SIMM16': self.SIMM16, 'SIMM32': self.SIMM32, 'VGPR': self.VGPR, 'SRC0': self.SRC0, 'VDST': self.VDST, + }) + exec(code, ns) + def _sync(ctx_reg, ns_val): + if isinstance(ns_val, self._Reg): ctx_reg._val = ns_val._val + else: ctx_reg._val = int(ns_val) & self._MASK64 + for name in ('SCC', 'VCC', 'EXEC', 'D0', 'D1', 'tmp', 'saveexec'): + if ns.get(name) is not getattr(self, name): _sync(getattr(self, name), ns[name]) + + def result(self) -> dict: return {"d0": self.D0._val, "scc": self.SCC._val & 1} diff --git a/extra/assembly/amd/test/test_emu.py b/extra/assembly/amd/test/test_emu.py index 3761ddf356..d16e2469e4 100644 --- a/extra/assembly/amd/test/test_emu.py +++ b/extra/assembly/amd/test/test_emu.py @@ -3813,3 +3813,40 @@ class TestVTrigPreopF64(unittest.TestCase): # Result should still be a valid float (not NaN or inf) self.assertFalse(math.isnan(result), "Result should not be NaN") self.assertFalse(math.isinf(result), "Result should not be inf") + + +class Test64BitLiterals(unittest.TestCase): + """Regression tests for 64-bit instruction literal encoding. + Tests verify that Inst.to_bytes() correctly encodes 64-bit literals.""" + + def test_64bit_literal_negative_encoding(self): + """Verify 64-bit instruction encodes negative literals correctly. + Regression test: -33 should encode as 0xffffffdf in the literal field, + NOT as 0xffffffff (which would happen with incorrect sign extension).""" + neg_val = -33 + expected_lit = neg_val & 0xffffffff # 0xffffffdf + inst = v_add_f64(v[2], v[0], neg_val) + # Check the literal is stored correctly (in high 32 bits for 64-bit ops) + self.assertIsNotNone(inst._literal, "Literal should be set") + # Literal is stored as (lit32 << 32) for 64-bit ops + actual_lit = (inst._literal >> 32) & 0xffffffff + self.assertEqual(actual_lit, expected_lit, f"Literal should be {expected_lit:#x}, got {actual_lit:#x}") + # Also verify the encoded bytes + code = inst.to_bytes() + # Literal is last 4 bytes + lit_bytes = code[-4:] + lit_val = int.from_bytes(lit_bytes, 'little') + self.assertEqual(lit_val, expected_lit, f"Encoded literal should be {expected_lit:#x}, got {lit_val:#x}") + + def test_64bit_literal_positive_encoding(self): + """Verify 64-bit instruction encodes large positive literals correctly.""" + large_val = 0x12345678 + inst = v_add_f64(v[2], v[0], large_val) + self.assertIsNotNone(inst._literal, "Literal should be set") + actual_lit = (inst._literal >> 32) & 0xffffffff + self.assertEqual(actual_lit, large_val, f"Literal should be {large_val:#x}, got {actual_lit:#x}") + # Verify encoded bytes + code = inst.to_bytes() + lit_bytes = code[-4:] + lit_val = int.from_bytes(lit_bytes, 'little') + self.assertEqual(lit_val, large_val, f"Encoded literal should be {large_val:#x}, got {lit_val:#x}") diff --git a/extra/assembly/amd/test/test_formats.py b/extra/assembly/amd/test/test_formats.py index dc4504ddb9..21fe926546 100644 --- a/extra/assembly/amd/test/test_formats.py +++ b/extra/assembly/amd/test/test_formats.py @@ -2,7 +2,8 @@ """Test MUBUF, MTBUF, MIMG, EXP, DS formats against LLVM.""" import unittest from extra.assembly.amd.autogen.rdna3 import * -from extra.assembly.amd.dsl import encode_src +from extra.assembly.amd.dsl import encode_src, RawImm +from extra.assembly.amd.asm import detect_format class TestMUBUF(unittest.TestCase): """Test MUBUF (buffer) instructions.""" @@ -328,5 +329,79 @@ class TestVOP3Literal(unittest.TestCase): self.assertEqual(len(inst.to_bytes()), 12) # 8 bytes + 4 byte literal +class TestDetectFormat(unittest.TestCase): + """Test detect_format uses encoding from autogen classes.""" + + def test_detect_sopp(self): + self.assertEqual(detect_format(s_endpgm().to_bytes()), SOPP) + self.assertEqual(detect_format(s_nop(0).to_bytes()), SOPP) + self.assertEqual(detect_format(s_barrier().to_bytes()), SOPP) + + def test_detect_sop1(self): + self.assertEqual(detect_format(s_mov_b32(s[0], 0).to_bytes()), SOP1) + self.assertEqual(detect_format(s_mov_b64(s[0:1], 0).to_bytes()), SOP1) + + def test_detect_sop2(self): + self.assertEqual(detect_format(s_add_u32(s[0], s[1], s[2]).to_bytes()), SOP2) + self.assertEqual(detect_format(s_mul_i32(s[0], s[1], s[2]).to_bytes()), SOP2) + + def test_detect_sopc(self): + self.assertEqual(detect_format(s_cmp_eq_i32(s[0], s[1]).to_bytes()), SOPC) + + def test_detect_sopk(self): + self.assertEqual(detect_format(s_movk_i32(s[0], 0x1234).to_bytes()), SOPK) + + def test_detect_vop1(self): + self.assertEqual(detect_format(v_mov_b32_e32(v[0], 0).to_bytes()), VOP1) + self.assertEqual(detect_format(v_rcp_f32_e32(v[0], v[1]).to_bytes()), VOP1) + + def test_detect_vop2(self): + self.assertEqual(detect_format(v_add_f32_e32(v[0], v[1], v[2]).to_bytes()), VOP2) + self.assertEqual(detect_format(v_mul_f32_e32(v[0], v[1], v[2]).to_bytes()), VOP2) + + def test_detect_vopc(self): + self.assertEqual(detect_format(v_cmp_eq_f32_e32(v[0], v[1]).to_bytes()), VOPC) + self.assertEqual(detect_format(v_cmp_lt_i32_e32(v[0], v[1]).to_bytes()), VOPC) + + def test_detect_vop3(self): + self.assertEqual(detect_format(v_add_f32_e64(v[0], v[1], v[2]).to_bytes()), VOP3) + self.assertEqual(detect_format(v_fma_f32(v[0], v[1], v[2], v[3]).to_bytes()), VOP3) + + def test_detect_vop3p(self): + self.assertEqual(detect_format(VOP3P(VOP3POp.V_PK_ADD_F16, v[0], v[1], v[2], v[3]).to_bytes()), VOP3P) + + def test_detect_smem(self): + self.assertEqual(detect_format(s_load_b32(s[0], s[2:3], 0).to_bytes()), SMEM) + self.assertEqual(detect_format(s_load_b64(s[0:1], s[2:3], s[5]).to_bytes()), SMEM) + + def test_detect_ds(self): + self.assertEqual(detect_format(ds_load_b32(v[0], v[1]).to_bytes()), DS) + self.assertEqual(detect_format(ds_store_b32(v[0], v[1]).to_bytes()), DS) + + def test_detect_flat(self): + self.assertEqual(detect_format(global_load_b32(v[0], v[1:3], RawImm(124)).to_bytes()), FLAT) + self.assertEqual(detect_format(global_store_b32(v[0:2], v[2], RawImm(124)).to_bytes()), FLAT) + + def test_detect_mubuf(self): + self.assertEqual(detect_format(buffer_load_b32(v[0], v[1], s[0:4], s[5]).to_bytes()), MUBUF) + + def test_detect_mtbuf(self): + self.assertEqual(detect_format(tbuffer_load_format_x(v[0], v[1], s[0:4], s[5], format=22).to_bytes()), MTBUF) + + def test_detect_mimg(self): + self.assertEqual(detect_format(image_load(v[0:4], v[4:6], s[0:8], dmask=0xf, dim=1).to_bytes()), MIMG) + + def test_detect_exp(self): + self.assertEqual(detect_format(EXP(en=0xf, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[2], vsrc3=v[3]).to_bytes()), EXP) + + def test_detect_vopd(self): + inst = VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=0, srcy0=0) + self.assertEqual(detect_format(inst.to_bytes()), VOPD) + + def test_detect_vinterp(self): + inst = VINTERP(VINTERPOp.V_INTERP_P10_F32, vdst=v[0], src0=v[1], src1=v[2], src2=v[3]) + self.assertEqual(detect_format(inst.to_bytes()), VINTERP) + + if __name__ == "__main__": unittest.main() diff --git a/extra/assembly/amd/test/test_pcode.py b/extra/assembly/amd/test/test_pcode.py index b848a48fe4..9fdc630c00 100644 --- a/extra/assembly/amd/test/test_pcode.py +++ b/extra/assembly/amd/test/test_pcode.py @@ -1,9 +1,11 @@ #!/usr/bin/env python3 """Tests for the RDNA3 pseudocode DSL.""" import unittest -from extra.assembly.amd.pcode import (Reg, TypedView, SliceProxy, ExecContext, compile_pseudocode, _expr, MASK32, MASK64, +from extra.assembly.amd.pcode import (Reg, TypedView, SliceProxy, MASK32, MASK64, _f32, _i32, _f16, _i16, f32_to_f16, _isnan, _bf16, _ibf16, bf16_to_f32, f32_to_bf16, BYTE_PERMUTE, v_sad_u8, v_msad_u8) +from extra.assembly.amd.pdf import compile_pseudocode, _expr +from extra.assembly.amd.test.helpers import ExecContext from extra.assembly.amd.autogen.rdna3.gen_pcode import _VOP3SDOp_V_DIV_SCALE_F32, _VOPCOp_V_CMP_CLASS_F32 class TestReg(unittest.TestCase): diff --git a/test/mockgpu/amd/amdgpu.py b/test/mockgpu/amd/amdgpu.py index c3fc27d705..3395f72998 100644 --- a/test/mockgpu/amd/amdgpu.py +++ b/test/mockgpu/amd/amdgpu.py @@ -187,7 +187,7 @@ class PM4Executor(AMDQueue): if st <= prg_addr < st+sz: prg_sz = sz - (prg_addr - st) assert prg_sz > 0, "Invalid prg ptr (not found in mapped ranges)" - # Pass valid memory ranges and rsrc2 to Python emulator for bounds checking and SGPR layout + # Pass valid memory ranges and rsrc2 to Python emulator for bounds checking and SGPR/VGPR layout if hasattr(remu, 'valid_mem_ranges'): remu.valid_mem_ranges = self.gpu.mapped_ranges if hasattr(remu, 'rsrc2'): remu.rsrc2 = rsrc2 err = remu.run_asm(prg_addr, prg_sz, *gl, *lc, args_addr)