* duration
* handwritten tests
* rdna3 pickle
* rdna4 pickle
* asserts
* rm that
* wmma work
* r4
* this shows the overlap well
* ohh okay it goes back
* are ds_load and ds_store different queues on RDNA4?
* print msg, v_mul_lo_u32 is 4 cycles?
* discover
* wmma something
* wmma comment
* less
* less
* better comments
* work
* inst st
* delay column
* better cli
* emit_alt
* update test_handwritten
* work
* viz: variable length rdna barriers
* work
* tiny changes
* simple wave simd test
* small wave sync test
* good multi barrier bug find
* simple fix
* wave_sync asserts
* rdna4 work
* more rdna4
* find more bugs in my model
* it's so much simpler
* wave_sync tests duration
* r4
* should just call this rdna4
* remove llvm requirement from amd
* tests pass
* test
* sink kernarg_size
* move stuff
* amd_asm_matmul to new style
* default type
* fix tests, simpler
* cu mode is faster and simpler
* darken