mirror of
https://github.com/tinygrad/tinygrad.git
synced 2026-01-14 01:18:26 -05:00
30bd6a619f
* start gpu * progress * fixes * read correct * libusb * libusb works * support asm24 * hmm * one access file * fix extra * start AMBar * works on am * back to usb * patch fw * full fast write into a bar * ugh, minus one gpus, next please * mute libusb for now * usb for asm24 * 63 * hmm * ops * rescan * and gpu shoudl be there * enumerate them? * usbgpu bus 4, 100% reliable (draft) * lil * works * comments * add DEBUG * cleaner * simplest * Revert "simplest" This reverts commit1d00354c16. * Revert "cleaner" This reverts commitc5662de956. * assert we find gpu * that's simpler * this back * simpler? * correcT * work * nonsense * works with more checks * this works * the 6s in the right place * reliable now * fix after reboot * set config * 1s timeouts * close to fw loading * streams * usbhub works * endpoints * fix * want to test tiny10 * move to tiny 10 * fix gpu * ugly speed * smth * mostly broken, but signals and dmas * do not reset gpu every time * changes to run kernels * ugh, not working * t10 * pg and sc files * some prog * um? * somehow it works * patched for 24 * some tries * minimal * moving * back to working * so sloooooow * move to controller * usb.py rewrite * rework * cleaner 1 * cleaner 2 * cleaner 3 * new abstractions * aft merge * init controller * cleaner 4 * cleaner 5 * patcher + tiny changes * ignore that * cleaner 6 * after rebase * cleaner 7 * bring it back * start linter war * linter 2 * autogen was missing * fix autogen * typing * better? * mypy * extra/legacy rename and cleaner * shuffle * better printing * tiny changes and tests --------- Co-authored-by: George Hotz <72895+geohot@users.noreply.github.com>
89 lines
4.0 KiB
Python
Executable File
89 lines
4.0 KiB
Python
Executable File
#!/usr/bin/env python3
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import sys
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import zlib
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def patch(input_filepath, output_filepath, patches):
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with open(input_filepath, 'rb') as infile: data = bytearray(infile.read())
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for offset, expected_bytes, new_bytes in patches:
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if len(expected_bytes) != len(new_bytes):
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print(len(expected_bytes), len(new_bytes))
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raise ValueError("Expected bytes and new bytes must be the same length")
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if offset + len(new_bytes) > len(data): return False
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current_bytes = data[offset:offset + len(expected_bytes)]
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assert bytes(current_bytes) == expected_bytes, f"Expected {expected_bytes} at offset {offset:x}, but got {current_bytes}"
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data[offset:offset + len(new_bytes)] = new_bytes
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checksum = sum(data[4:-6]) & 0xff
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crc32 = zlib.crc32(data[4:-6]).to_bytes(4, 'little')
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data[-5] = checksum
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data[-4] = crc32[0]
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data[-3] = crc32[1]
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data[-2] = crc32[2]
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data[-1] = crc32[3]
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with open(output_filepath, 'wb') as outfile:
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outfile.write(data)
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return True
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patches = [
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# (0x3903 + 1 + 4, b'\x8a', b'\x8b'),
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# (0x3cf9 + 1 + 4, b'\x8a', b'\x8b'), # this is the one which triggered...
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(0x2a0d + 1 + 4, b'\x0a', b'\x05'), # write handle exit with code 5 (?)
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# (0x40e1 + 4, b'\x90\x06\xe6\x04\xf0\x78\x0d\xe6\xfe\x24\x71\x12\x1b\x0b\x60\x0b\x74\x08', b'\x7f\x00\x12\x53\x21\x12\x1c\xfc\x74\x01\xf6\x90\x90\x94\x74\x10\xf0\x22')
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# (0x29ad + 1 + 4, b'\x09', b'\x05'), # write handle exit with code 5 (?)
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# (0x40ef + 0 + 4, b'\x60', b'\x70'), # jz -> jnz
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# (0x40e1 + 0 + 4, b'\x90', b'\x22'), # jmp -> ret
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# (0x40fa + 0 + 4, b'\x80', b'\x22'),
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# (0x40e1 + 0 + 4, b'\x90\x06\xe6\x04\xf0', b'\x7f\x00\x02\x41\x7c'), # jmp -> ret
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]
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next_traphandler = 0
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def add_traphandler(addr, sec):
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global next_traphandler, patches
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trap_addr = 0x6000 + next_traphandler * 0x20
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return_addr = addr + len(sec)
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cntr_addr = 0x3000 + next_traphandler
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patches += [
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(addr + 4, sec, b'\x02' + trap_addr.to_bytes(2, 'big') + b'\x22'*(len(sec)-3)),
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(trap_addr + 4, b'\x00' * (21 + len(sec)),
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b'\xc0\xe0\xc0\x82\xc0\x83\x90' + cntr_addr.to_bytes(2, 'big') + b'\xe0\x04\xf0\xd0\x83\xd0\x82\xd0\xe0' + sec + b'\x02' + return_addr.to_bytes(2, 'big')),
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]
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next_traphandler += 1
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# add_traphandler(0x0206, b'\xed\x54\x06') # fill_scsi_resp
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# add_traphandler(0x40d9, b'\x78\x6a\xe6') # fill_scsi_to_usb_transport
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# add_traphandler(0x4d44, b'\x78\x6a\xe6') # FUN_CODE_4d44
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# add_traphandler(0x4784, b'\x78\x6a\xe6') # FUN_CODE_4784
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# add_traphandler(0x3e81, b'\x90\xc5\x16') # FUN_CODE_3e81
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# add_traphandler(0x32a5, b'\x78\x6a\xe6') # FUN_CODE_32a5
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# add_traphandler(0x2a10, b'\x90\xc4\x51') # FUN_CODE_2a10
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# add_traphandler(0x2608, b'\x12\x16\x87') # FUN_CODE_2608
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# add_traphandler(0x0e78, b'\x90\xc8\x02') # main usb entry
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# add_traphandler(0x102f, b'\x12\x18\x0d') # possible scsi entry parser
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# add_traphandler(0x1198, b'\x12\x18\x0d') # close_to_scsi_parse_1_and_set_c47a_to_0xff caller to scsi
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# add_traphandler(0x180d, b'\x90\x0a\x7d') # close_to_scsi_parse
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# add_traphandler(0x1114, b'\x75\x37\x00') # entry into if ((DAT_EXTMEM_c802 >> 2 & 1) != 0) { in main usb entry
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# add_traphandler(0x113a, b'\x90\x90\x00') # exit from scsi parse loop
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# add_traphandler(0x117b, b'\xd0\x07\xd0\x06') # exit from main usb entry
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# add_traphandler(0x2f81, b'\x90\x0a\x59') # main loop? 8
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# add_traphandler(0xc7a7, b'\x90\x09\xfa') # call smth in write path 9
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# add_traphandler(0x2fcb, b'\x90\x0a\x59') # if ((DAT_EXTMEM_0ae2 != 0) && (DAT_EXTMEM_0ae2 != 0x10)) {
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# add_traphandler(0x2fc0, b'\x90\x0a\xe2') # submain loop 11
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# add_traphandler(0x30be, b'\x90\x0a\x5a') # aft sub loop 12
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# add_traphandler(0x3076, b'\x12\x03\x59') # call to call_wait_for_nvme??(); 13
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# add_traphandler(0x30ad, b'\x12\x04\xe4') # call to call_wait_for_nvme??(); 14
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# add_traphandler(0x2608, b'\x12\x16\x87') # FUN_CODE_2608
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# add_traphandler(0x10ee, b'\x90\x04\x64') # iniside trap handler
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# add_traphandler(0x10e0, b'\x90\xc8\x06') # iniside trap handler
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# add_traphandler(0x4977, b'\x90\x0a\xa8') # waiter for nvme???
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assert patch(sys.argv[1], sys.argv[2], patches) is True
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