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* assembly/amd: improve tests for asm * upd * skip * tests * re bug * more passing * cleanups * cdna fixups * improve tests, better CDNA parsing * fix CI * no defs * simpler * all pass * from pdf * regen
1679 lines
37 KiB
Python
1679 lines
37 KiB
Python
# autogenerated from AMD RDNA4 ISA PDF by pdf.py - do not edit
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from enum import IntEnum
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class SrcEnum(IntEnum):
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VCC_LO = 106
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VCC_HI = 107
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NULL = 124
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M0 = 125
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EXEC_LO = 126
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EXEC_HI = 127
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ZERO = 128
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DPP8 = 233
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DPP8FI = 234
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SHARED_BASE = 235
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SHARED_LIMIT = 236
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PRIVATE_BASE = 237
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PRIVATE_LIMIT = 238
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POS_HALF = 240
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NEG_HALF = 241
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POS_ONE = 242
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NEG_ONE = 243
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POS_TWO = 244
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NEG_TWO = 245
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POS_FOUR = 246
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NEG_FOUR = 247
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INV_2PI = 248
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DPP16 = 250
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VCCZ = 251
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EXECZ = 252
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SCC = 253
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LDS_DIRECT = 254
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class DSOp(IntEnum):
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DS_ADD_U32 = 0
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DS_SUB_U32 = 1
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DS_RSUB_U32 = 2
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DS_INC_U32 = 3
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DS_DEC_U32 = 4
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DS_MIN_I32 = 5
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DS_MAX_I32 = 6
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DS_MIN_U32 = 7
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DS_MAX_U32 = 8
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DS_AND_B32 = 9
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DS_OR_B32 = 10
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DS_XOR_B32 = 11
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DS_MSKOR_B32 = 12
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DS_STORE_B32 = 13
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DS_STORE_2ADDR_B32 = 14
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DS_STORE_2ADDR_STRIDE64_B32 = 15
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DS_CMPSTORE_B32 = 16
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DS_MIN_NUM_F32 = 18
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DS_MAX_NUM_F32 = 19
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DS_NOP = 20
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DS_ADD_F32 = 21
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DS_STORE_B8 = 30
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DS_STORE_B16 = 31
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DS_ADD_RTN_U32 = 32
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DS_SUB_RTN_U32 = 33
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DS_RSUB_RTN_U32 = 34
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DS_INC_RTN_U32 = 35
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DS_DEC_RTN_U32 = 36
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DS_MIN_RTN_I32 = 37
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DS_MAX_RTN_I32 = 38
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DS_MIN_RTN_U32 = 39
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DS_MAX_RTN_U32 = 40
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DS_AND_RTN_B32 = 41
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DS_OR_RTN_B32 = 42
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DS_XOR_RTN_B32 = 43
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DS_MSKOR_RTN_B32 = 44
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DS_STOREXCHG_RTN_B32 = 45
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DS_STOREXCHG_2ADDR_RTN_B32 = 46
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DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32 = 47
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DS_CMPSTORE_RTN_B32 = 48
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DS_MIN_NUM_RTN_F32 = 50
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DS_MAX_NUM_RTN_F32 = 51
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DS_SWIZZLE_B32 = 53
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DS_LOAD_B32 = 54
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DS_LOAD_2ADDR_B32 = 55
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DS_LOAD_2ADDR_STRIDE64_B32 = 56
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DS_LOAD_I8 = 57
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DS_LOAD_U8 = 58
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DS_LOAD_I16 = 59
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DS_LOAD_U16 = 60
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DS_CONSUME = 61
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DS_APPEND = 62
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DS_ADD_U64 = 64
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DS_SUB_U64 = 65
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DS_RSUB_U64 = 66
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DS_INC_U64 = 67
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DS_DEC_U64 = 68
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DS_MIN_I64 = 69
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DS_MAX_I64 = 70
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DS_MIN_U64 = 71
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DS_MAX_U64 = 72
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DS_AND_B64 = 73
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DS_OR_B64 = 74
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DS_XOR_B64 = 75
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DS_MSKOR_B64 = 76
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DS_STORE_B64 = 77
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DS_STORE_2ADDR_B64 = 78
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DS_STORE_2ADDR_STRIDE64_B64 = 79
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DS_CMPSTORE_B64 = 80
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DS_MIN_NUM_F64 = 82
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DS_MAX_NUM_F64 = 83
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DS_ADD_RTN_U64 = 96
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DS_SUB_RTN_U64 = 97
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DS_RSUB_RTN_U64 = 98
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DS_INC_RTN_U64 = 99
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DS_DEC_RTN_U64 = 100
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DS_MIN_RTN_I64 = 101
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DS_MAX_RTN_I64 = 102
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DS_MIN_RTN_U64 = 103
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DS_MAX_RTN_U64 = 104
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DS_AND_RTN_B64 = 105
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DS_OR_RTN_B64 = 106
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DS_XOR_RTN_B64 = 107
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DS_MSKOR_RTN_B64 = 108
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DS_STOREXCHG_RTN_B64 = 109
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DS_STOREXCHG_2ADDR_RTN_B64 = 110
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DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64 = 111
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DS_CMPSTORE_RTN_B64 = 112
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DS_MIN_NUM_RTN_F64 = 114
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DS_MAX_NUM_RTN_F64 = 115
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DS_LOAD_B64 = 118
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DS_LOAD_2ADDR_B64 = 119
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DS_LOAD_2ADDR_STRIDE64_B64 = 120
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DS_ADD_RTN_F32 = 121
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DS_CONDXCHG32_RTN_B64 = 126
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DS_COND_SUB_U32 = 152
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DS_SUB_CLAMP_U32 = 153
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DS_PK_ADD_F16 = 154
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DS_PK_ADD_BF16 = 155
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DS_STORE_B8_D16_HI = 160
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DS_STORE_B16_D16_HI = 161
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DS_LOAD_U8_D16 = 162
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DS_LOAD_U8_D16_HI = 163
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DS_LOAD_I8_D16 = 164
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DS_LOAD_I8_D16_HI = 165
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DS_LOAD_U16_D16 = 166
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DS_LOAD_U16_D16_HI = 167
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DS_COND_SUB_RTN_U32 = 168
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DS_SUB_CLAMP_RTN_U32 = 169
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DS_PK_ADD_RTN_F16 = 170
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DS_PK_ADD_RTN_BF16 = 171
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DS_STORE_ADDTID_B32 = 176
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DS_LOAD_ADDTID_B32 = 177
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DS_PERMUTE_B32 = 178
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DS_BPERMUTE_B32 = 179
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DS_BPERMUTE_FI_B32 = 205
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DS_STORE_B96 = 222
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DS_STORE_B128 = 223
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DS_BVH_STACK_PUSH4_POP1_RTN_B32 = 224
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DS_BVH_STACK_PUSH8_POP1_RTN_B32 = 225
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DS_BVH_STACK_PUSH8_POP2_RTN_B64 = 226
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DS_LOAD_B96 = 254
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DS_LOAD_B128 = 255
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class SMEMOp(IntEnum):
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S_LOAD_B32 = 0
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S_LOAD_B64 = 1
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S_LOAD_B128 = 2
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S_LOAD_B256 = 3
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S_LOAD_B512 = 4
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S_LOAD_B96 = 5
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S_LOAD_I8 = 8
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S_LOAD_U8 = 9
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S_LOAD_I16 = 10
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S_LOAD_U16 = 11
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S_BUFFER_LOAD_B32 = 16
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S_BUFFER_LOAD_B64 = 17
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S_BUFFER_LOAD_B128 = 18
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S_BUFFER_LOAD_B256 = 19
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S_BUFFER_LOAD_B512 = 20
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S_BUFFER_LOAD_B96 = 21
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S_BUFFER_LOAD_I8 = 24
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S_BUFFER_LOAD_U8 = 25
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S_BUFFER_LOAD_I16 = 26
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S_BUFFER_LOAD_U16 = 27
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S_DCACHE_INV = 33
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S_PREFETCH_INST = 36
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S_PREFETCH_INST_PC_REL = 37
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S_PREFETCH_DATA = 38
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S_BUFFER_PREFETCH_DATA = 39
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S_PREFETCH_DATA_PC_REL = 40
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class SOP1Op(IntEnum):
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S_MOV_B32 = 0
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S_MOV_B64 = 1
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S_CMOV_B32 = 2
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S_CMOV_B64 = 3
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S_BREV_B32 = 4
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S_BREV_B64 = 5
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S_CTZ_I32_B32 = 8
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S_CTZ_I32_B64 = 9
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S_CLZ_I32_U32 = 10
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S_CLZ_I32_U64 = 11
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S_CLS_I32 = 12
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S_CLS_I32_I64 = 13
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S_SEXT_I32_I8 = 14
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S_SEXT_I32_I16 = 15
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S_BITSET0_B32 = 16
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S_BITSET0_B64 = 17
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S_BITSET1_B32 = 18
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S_BITSET1_B64 = 19
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S_BITREPLICATE_B64_B32 = 20
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S_ABS_I32 = 21
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S_BCNT0_I32_B32 = 22
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S_BCNT0_I32_B64 = 23
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S_BCNT1_I32_B32 = 24
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S_BCNT1_I32_B64 = 25
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S_QUADMASK_B32 = 26
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S_QUADMASK_B64 = 27
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S_WQM_B32 = 28
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S_WQM_B64 = 29
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S_NOT_B32 = 30
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S_NOT_B64 = 31
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S_AND_SAVEEXEC_B32 = 32
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S_AND_SAVEEXEC_B64 = 33
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S_OR_SAVEEXEC_B32 = 34
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S_OR_SAVEEXEC_B64 = 35
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S_XOR_SAVEEXEC_B32 = 36
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S_XOR_SAVEEXEC_B64 = 37
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S_NAND_SAVEEXEC_B32 = 38
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S_NAND_SAVEEXEC_B64 = 39
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S_NOR_SAVEEXEC_B32 = 40
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S_NOR_SAVEEXEC_B64 = 41
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S_XNOR_SAVEEXEC_B32 = 42
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S_XNOR_SAVEEXEC_B64 = 43
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S_AND_NOT0_SAVEEXEC_B32 = 44
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S_AND_NOT0_SAVEEXEC_B64 = 45
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S_OR_NOT0_SAVEEXEC_B32 = 46
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S_OR_NOT0_SAVEEXEC_B64 = 47
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S_AND_NOT1_SAVEEXEC_B32 = 48
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S_AND_NOT1_SAVEEXEC_B64 = 49
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S_OR_NOT1_SAVEEXEC_B32 = 50
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S_OR_NOT1_SAVEEXEC_B64 = 51
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S_AND_NOT0_WREXEC_B32 = 52
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S_AND_NOT0_WREXEC_B64 = 53
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S_AND_NOT1_WREXEC_B32 = 54
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S_AND_NOT1_WREXEC_B64 = 55
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S_MOVRELS_B32 = 64
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S_MOVRELS_B64 = 65
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S_MOVRELD_B32 = 66
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S_MOVRELD_B64 = 67
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S_MOVRELSD_2_B32 = 68
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S_GETPC_B64 = 71
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S_SETPC_B64 = 72
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S_SWAPPC_B64 = 73
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S_RFE_B64 = 74
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S_SENDMSG_RTN_B32 = 76
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S_SENDMSG_RTN_B64 = 77
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S_BARRIER_SIGNAL = 78
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S_BARRIER_SIGNAL_ISFIRST = 79
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S_GET_BARRIER_STATE = 80
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S_ALLOC_VGPR = 83
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S_SLEEP_VAR = 88
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S_CEIL_F32 = 96
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S_FLOOR_F32 = 97
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S_TRUNC_F32 = 98
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S_RNDNE_F32 = 99
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S_CVT_F32_I32 = 100
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S_CVT_F32_U32 = 101
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S_CVT_I32_F32 = 102
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S_CVT_U32_F32 = 103
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S_CVT_F16_F32 = 104
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S_CVT_F32_F16 = 105
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S_CVT_HI_F32_F16 = 106
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S_CEIL_F16 = 107
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S_FLOOR_F16 = 108
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S_TRUNC_F16 = 109
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S_RNDNE_F16 = 110
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class SOP2Op(IntEnum):
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S_ADD_CO_U32 = 0
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S_SUB_CO_U32 = 1
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S_ADD_CO_I32 = 2
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S_SUB_CO_I32 = 3
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S_ADD_CO_CI_U32 = 4
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S_SUB_CO_CI_U32 = 5
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S_ABSDIFF_I32 = 6
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S_LSHL_B32 = 8
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S_LSHL_B64 = 9
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S_LSHR_B32 = 10
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S_LSHR_B64 = 11
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S_ASHR_I32 = 12
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S_ASHR_I64 = 13
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S_LSHL1_ADD_U32 = 14
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S_LSHL2_ADD_U32 = 15
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S_LSHL3_ADD_U32 = 16
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S_LSHL4_ADD_U32 = 17
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S_MIN_I32 = 18
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S_MIN_U32 = 19
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S_MAX_I32 = 20
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S_MAX_U32 = 21
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S_AND_B32 = 22
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S_AND_B64 = 23
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S_OR_B32 = 24
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S_OR_B64 = 25
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S_XOR_B32 = 26
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S_XOR_B64 = 27
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S_NAND_B32 = 28
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S_NAND_B64 = 29
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S_NOR_B32 = 30
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S_NOR_B64 = 31
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S_XNOR_B32 = 32
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S_XNOR_B64 = 33
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S_AND_NOT1_B32 = 34
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S_AND_NOT1_B64 = 35
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S_OR_NOT1_B32 = 36
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S_OR_NOT1_B64 = 37
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S_BFE_U32 = 38
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S_BFE_I32 = 39
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S_BFE_U64 = 40
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S_BFE_I64 = 41
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S_BFM_B32 = 42
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S_BFM_B64 = 43
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S_MUL_I32 = 44
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S_MUL_HI_U32 = 45
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S_MUL_HI_I32 = 46
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S_CSELECT_B32 = 48
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S_CSELECT_B64 = 49
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S_PACK_LL_B32_B16 = 50
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S_PACK_LH_B32_B16 = 51
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S_PACK_HH_B32_B16 = 52
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S_PACK_HL_B32_B16 = 53
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S_ADD_F32 = 64
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S_SUB_F32 = 65
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S_MIN_NUM_F32 = 66
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S_MAX_NUM_F32 = 67
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S_MUL_F32 = 68
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S_FMAAK_F32 = 69
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S_FMAMK_F32 = 70
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S_FMAC_F32 = 71
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S_CVT_PK_RTZ_F16_F32 = 72
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S_ADD_F16 = 73
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S_SUB_F16 = 74
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S_MIN_NUM_F16 = 75
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S_MAX_NUM_F16 = 76
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S_MUL_F16 = 77
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S_FMAC_F16 = 78
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S_MINIMUM_F32 = 79
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S_MAXIMUM_F32 = 80
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S_MINIMUM_F16 = 81
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S_MAXIMUM_F16 = 82
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S_ADD_NC_U64 = 83
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S_SUB_NC_U64 = 84
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S_MUL_U64 = 85
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class SOPCOp(IntEnum):
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S_CMP_EQ_I32 = 0
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S_CMP_LG_I32 = 1
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S_CMP_GT_I32 = 2
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S_CMP_GE_I32 = 3
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S_CMP_LT_I32 = 4
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S_CMP_LE_I32 = 5
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S_CMP_EQ_U32 = 6
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S_CMP_LG_U32 = 7
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S_CMP_GT_U32 = 8
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S_CMP_GE_U32 = 9
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S_CMP_LT_U32 = 10
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S_CMP_LE_U32 = 11
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S_BITCMP0_B32 = 12
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S_BITCMP1_B32 = 13
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S_BITCMP0_B64 = 14
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S_BITCMP1_B64 = 15
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S_CMP_EQ_U64 = 16
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S_CMP_LG_U64 = 17
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S_CMP_LT_F32 = 65
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S_CMP_EQ_F32 = 66
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S_CMP_LE_F32 = 67
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S_CMP_GT_F32 = 68
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S_CMP_LG_F32 = 69
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S_CMP_GE_F32 = 70
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S_CMP_O_F32 = 71
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S_CMP_U_F32 = 72
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S_CMP_NGE_F32 = 73
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S_CMP_NLG_F32 = 74
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S_CMP_NGT_F32 = 75
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S_CMP_NLE_F32 = 76
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S_CMP_NEQ_F32 = 77
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S_CMP_NLT_F32 = 78
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S_CMP_LT_F16 = 81
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S_CMP_EQ_F16 = 82
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S_CMP_LE_F16 = 83
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S_CMP_GT_F16 = 84
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S_CMP_LG_F16 = 85
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S_CMP_GE_F16 = 86
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S_CMP_O_F16 = 87
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S_CMP_U_F16 = 88
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S_CMP_NGE_F16 = 89
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S_CMP_NLG_F16 = 90
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S_CMP_NGT_F16 = 91
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S_CMP_NLE_F16 = 92
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S_CMP_NEQ_F16 = 93
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S_CMP_NLT_F16 = 94
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class SOPKOp(IntEnum):
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S_MOVK_I32 = 0
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S_VERSION = 1
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S_CMOVK_I32 = 2
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S_ADDK_CO_I32 = 15
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S_MULK_I32 = 16
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S_GETREG_B32 = 17
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S_SETREG_B32 = 18
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S_SETREG_IMM32_B32 = 19
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S_CALL_B64 = 20
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class SOPPOp(IntEnum):
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S_NOP = 0
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S_SETKILL = 1
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S_SETHALT = 2
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S_SLEEP = 3
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S_CLAUSE = 5
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S_DELAY_ALU = 7
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S_WAIT_ALU = 8
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S_WAITCNT = 9
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S_WAIT_IDLE = 10
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S_WAIT_EVENT = 11
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S_TRAP = 16
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S_ROUND_MODE = 17
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S_DENORM_MODE = 18
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S_BARRIER_WAIT = 20
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S_CODE_END = 31
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S_BRANCH = 32
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S_CBRANCH_SCC0 = 33
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S_CBRANCH_SCC1 = 34
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S_CBRANCH_VCCZ = 35
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S_CBRANCH_VCCNZ = 36
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S_CBRANCH_EXECZ = 37
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S_CBRANCH_EXECNZ = 38
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S_ENDPGM = 48
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S_ENDPGM_SAVED = 49
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S_WAKEUP = 52
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S_SETPRIO = 53
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S_SENDMSG = 54
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S_SENDMSGHALT = 55
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S_INCPERFLEVEL = 56
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S_DECPERFLEVEL = 57
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S_ICACHE_INV = 60
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S_WAIT_LOADCNT = 64
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S_WAIT_STORECNT = 65
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S_WAIT_SAMPLECNT = 66
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S_WAIT_BVHCNT = 67
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S_WAIT_EXPCNT = 68
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S_WAIT_DSCNT = 70
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S_WAIT_KMCNT = 71
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S_WAIT_LOADCNT_DSCNT = 72
|
|
S_WAIT_STORECNT_DSCNT = 73
|
|
|
|
class VBUFFEROp(IntEnum):
|
|
BUFFER_LOAD_FORMAT_X = 0
|
|
BUFFER_LOAD_FORMAT_XY = 1
|
|
BUFFER_LOAD_FORMAT_XYZ = 2
|
|
BUFFER_LOAD_FORMAT_XYZW = 3
|
|
BUFFER_STORE_FORMAT_X = 4
|
|
BUFFER_STORE_FORMAT_XY = 5
|
|
BUFFER_STORE_FORMAT_XYZ = 6
|
|
BUFFER_STORE_FORMAT_XYZW = 7
|
|
BUFFER_LOAD_D16_FORMAT_X = 8
|
|
BUFFER_LOAD_D16_FORMAT_XY = 9
|
|
BUFFER_LOAD_D16_FORMAT_XYZ = 10
|
|
BUFFER_LOAD_D16_FORMAT_XYZW = 11
|
|
BUFFER_STORE_D16_FORMAT_X = 12
|
|
BUFFER_STORE_D16_FORMAT_XY = 13
|
|
BUFFER_STORE_D16_FORMAT_XYZ = 14
|
|
BUFFER_STORE_D16_FORMAT_XYZW = 15
|
|
BUFFER_LOAD_U8 = 16
|
|
BUFFER_LOAD_I8 = 17
|
|
BUFFER_LOAD_U16 = 18
|
|
BUFFER_LOAD_I16 = 19
|
|
BUFFER_LOAD_B32 = 20
|
|
BUFFER_LOAD_B64 = 21
|
|
BUFFER_LOAD_B96 = 22
|
|
BUFFER_LOAD_B128 = 23
|
|
BUFFER_STORE_B8 = 24
|
|
BUFFER_STORE_B16 = 25
|
|
BUFFER_STORE_B32 = 26
|
|
BUFFER_STORE_B64 = 27
|
|
BUFFER_STORE_B96 = 28
|
|
BUFFER_STORE_B128 = 29
|
|
BUFFER_LOAD_D16_U8 = 30
|
|
BUFFER_LOAD_D16_I8 = 31
|
|
BUFFER_LOAD_D16_B16 = 32
|
|
BUFFER_LOAD_D16_HI_U8 = 33
|
|
BUFFER_LOAD_D16_HI_I8 = 34
|
|
BUFFER_LOAD_D16_HI_B16 = 35
|
|
BUFFER_STORE_D16_HI_B8 = 36
|
|
BUFFER_STORE_D16_HI_B16 = 37
|
|
BUFFER_LOAD_D16_HI_FORMAT_X = 38
|
|
BUFFER_STORE_D16_HI_FORMAT_X = 39
|
|
BUFFER_ATOMIC_SWAP_B32 = 51
|
|
BUFFER_ATOMIC_CMPSWAP_B32 = 52
|
|
BUFFER_ATOMIC_ADD_U32 = 53
|
|
BUFFER_ATOMIC_SUB_U32 = 54
|
|
BUFFER_ATOMIC_SUB_CLAMP_U32 = 55
|
|
BUFFER_ATOMIC_MIN_I32 = 56
|
|
BUFFER_ATOMIC_MIN_U32 = 57
|
|
BUFFER_ATOMIC_MAX_I32 = 58
|
|
BUFFER_ATOMIC_MAX_U32 = 59
|
|
BUFFER_ATOMIC_AND_B32 = 60
|
|
BUFFER_ATOMIC_OR_B32 = 61
|
|
BUFFER_ATOMIC_XOR_B32 = 62
|
|
BUFFER_ATOMIC_INC_U32 = 63
|
|
BUFFER_ATOMIC_DEC_U32 = 64
|
|
BUFFER_ATOMIC_SWAP_B64 = 65
|
|
BUFFER_ATOMIC_CMPSWAP_B64 = 66
|
|
BUFFER_ATOMIC_ADD_U64 = 67
|
|
BUFFER_ATOMIC_SUB_U64 = 68
|
|
BUFFER_ATOMIC_MIN_I64 = 69
|
|
BUFFER_ATOMIC_MIN_U64 = 70
|
|
BUFFER_ATOMIC_MAX_I64 = 71
|
|
BUFFER_ATOMIC_MAX_U64 = 72
|
|
BUFFER_ATOMIC_AND_B64 = 73
|
|
BUFFER_ATOMIC_OR_B64 = 74
|
|
BUFFER_ATOMIC_XOR_B64 = 75
|
|
BUFFER_ATOMIC_INC_U64 = 76
|
|
BUFFER_ATOMIC_DEC_U64 = 77
|
|
BUFFER_ATOMIC_COND_SUB_U32 = 80
|
|
BUFFER_ATOMIC_MIN_NUM_F32 = 81
|
|
BUFFER_ATOMIC_MAX_NUM_F32 = 82
|
|
BUFFER_ATOMIC_ADD_F32 = 86
|
|
BUFFER_ATOMIC_PK_ADD_F16 = 89
|
|
BUFFER_ATOMIC_PK_ADD_BF16 = 90
|
|
TBUFFER_LOAD_FORMAT_X = 128
|
|
TBUFFER_LOAD_FORMAT_XY = 129
|
|
TBUFFER_LOAD_FORMAT_XYZ = 130
|
|
TBUFFER_LOAD_FORMAT_XYZW = 131
|
|
TBUFFER_STORE_FORMAT_X = 132
|
|
TBUFFER_STORE_FORMAT_XY = 133
|
|
TBUFFER_STORE_FORMAT_XYZ = 134
|
|
TBUFFER_STORE_FORMAT_XYZW = 135
|
|
TBUFFER_LOAD_D16_FORMAT_X = 136
|
|
TBUFFER_LOAD_D16_FORMAT_XY = 137
|
|
TBUFFER_LOAD_D16_FORMAT_XYZ = 138
|
|
TBUFFER_LOAD_D16_FORMAT_XYZW = 139
|
|
TBUFFER_STORE_D16_FORMAT_X = 140
|
|
TBUFFER_STORE_D16_FORMAT_XY = 141
|
|
TBUFFER_STORE_D16_FORMAT_XYZ = 142
|
|
TBUFFER_STORE_D16_FORMAT_XYZW = 143
|
|
|
|
class VDSDIROp(IntEnum):
|
|
DS_PARAM_LOAD = 0
|
|
DS_DIRECT_LOAD = 1
|
|
|
|
class VFLATOp(IntEnum):
|
|
FLAT_LOAD_U8 = 16
|
|
FLAT_LOAD_I8 = 17
|
|
FLAT_LOAD_U16 = 18
|
|
FLAT_LOAD_I16 = 19
|
|
FLAT_LOAD_B32 = 20
|
|
FLAT_LOAD_B64 = 21
|
|
FLAT_LOAD_B96 = 22
|
|
FLAT_LOAD_B128 = 23
|
|
FLAT_STORE_B8 = 24
|
|
FLAT_STORE_B16 = 25
|
|
FLAT_STORE_B32 = 26
|
|
FLAT_STORE_B64 = 27
|
|
FLAT_STORE_B96 = 28
|
|
FLAT_STORE_B128 = 29
|
|
FLAT_LOAD_D16_U8 = 30
|
|
FLAT_LOAD_D16_I8 = 31
|
|
FLAT_LOAD_D16_B16 = 32
|
|
FLAT_LOAD_D16_HI_U8 = 33
|
|
FLAT_LOAD_D16_HI_I8 = 34
|
|
FLAT_LOAD_D16_HI_B16 = 35
|
|
FLAT_STORE_D16_HI_B8 = 36
|
|
FLAT_STORE_D16_HI_B16 = 37
|
|
FLAT_ATOMIC_SWAP_B32 = 51
|
|
FLAT_ATOMIC_CMPSWAP_B32 = 52
|
|
FLAT_ATOMIC_ADD_U32 = 53
|
|
FLAT_ATOMIC_SUB_U32 = 54
|
|
FLAT_ATOMIC_SUB_CLAMP_U32 = 55
|
|
FLAT_ATOMIC_MIN_I32 = 56
|
|
FLAT_ATOMIC_MIN_U32 = 57
|
|
FLAT_ATOMIC_MAX_I32 = 58
|
|
FLAT_ATOMIC_MAX_U32 = 59
|
|
FLAT_ATOMIC_AND_B32 = 60
|
|
FLAT_ATOMIC_OR_B32 = 61
|
|
FLAT_ATOMIC_XOR_B32 = 62
|
|
FLAT_ATOMIC_INC_U32 = 63
|
|
FLAT_ATOMIC_DEC_U32 = 64
|
|
FLAT_ATOMIC_SWAP_B64 = 65
|
|
FLAT_ATOMIC_CMPSWAP_B64 = 66
|
|
FLAT_ATOMIC_ADD_U64 = 67
|
|
FLAT_ATOMIC_SUB_U64 = 68
|
|
FLAT_ATOMIC_MIN_I64 = 69
|
|
FLAT_ATOMIC_MIN_U64 = 70
|
|
FLAT_ATOMIC_MAX_I64 = 71
|
|
FLAT_ATOMIC_MAX_U64 = 72
|
|
FLAT_ATOMIC_AND_B64 = 73
|
|
FLAT_ATOMIC_OR_B64 = 74
|
|
FLAT_ATOMIC_XOR_B64 = 75
|
|
FLAT_ATOMIC_INC_U64 = 76
|
|
FLAT_ATOMIC_DEC_U64 = 77
|
|
FLAT_ATOMIC_COND_SUB_U32 = 80
|
|
FLAT_ATOMIC_MIN_NUM_F32 = 81
|
|
FLAT_ATOMIC_MAX_NUM_F32 = 82
|
|
FLAT_ATOMIC_ADD_F32 = 86
|
|
FLAT_ATOMIC_PK_ADD_F16 = 89
|
|
FLAT_ATOMIC_PK_ADD_BF16 = 90
|
|
|
|
class VGLOBALOp(IntEnum):
|
|
GLOBAL_LOAD_U8 = 16
|
|
GLOBAL_LOAD_I8 = 17
|
|
GLOBAL_LOAD_U16 = 18
|
|
GLOBAL_LOAD_I16 = 19
|
|
GLOBAL_LOAD_B32 = 20
|
|
GLOBAL_LOAD_B64 = 21
|
|
GLOBAL_LOAD_B96 = 22
|
|
GLOBAL_LOAD_B128 = 23
|
|
GLOBAL_STORE_B8 = 24
|
|
GLOBAL_STORE_B16 = 25
|
|
GLOBAL_STORE_B32 = 26
|
|
GLOBAL_STORE_B64 = 27
|
|
GLOBAL_STORE_B96 = 28
|
|
GLOBAL_STORE_B128 = 29
|
|
GLOBAL_LOAD_D16_U8 = 30
|
|
GLOBAL_LOAD_D16_I8 = 31
|
|
GLOBAL_LOAD_D16_B16 = 32
|
|
GLOBAL_LOAD_D16_HI_U8 = 33
|
|
GLOBAL_LOAD_D16_HI_I8 = 34
|
|
GLOBAL_LOAD_D16_HI_B16 = 35
|
|
GLOBAL_STORE_D16_HI_B8 = 36
|
|
GLOBAL_STORE_D16_HI_B16 = 37
|
|
GLOBAL_LOAD_ADDTID_B32 = 40
|
|
GLOBAL_STORE_ADDTID_B32 = 41
|
|
GLOBAL_INV = 43
|
|
GLOBAL_WB = 44
|
|
GLOBAL_ATOMIC_SWAP_B32 = 51
|
|
GLOBAL_ATOMIC_CMPSWAP_B32 = 52
|
|
GLOBAL_ATOMIC_ADD_U32 = 53
|
|
GLOBAL_ATOMIC_SUB_U32 = 54
|
|
GLOBAL_ATOMIC_SUB_CLAMP_U32 = 55
|
|
GLOBAL_ATOMIC_MIN_I32 = 56
|
|
GLOBAL_ATOMIC_MIN_U32 = 57
|
|
GLOBAL_ATOMIC_MAX_I32 = 58
|
|
GLOBAL_ATOMIC_MAX_U32 = 59
|
|
GLOBAL_ATOMIC_AND_B32 = 60
|
|
GLOBAL_ATOMIC_OR_B32 = 61
|
|
GLOBAL_ATOMIC_XOR_B32 = 62
|
|
GLOBAL_ATOMIC_INC_U32 = 63
|
|
GLOBAL_ATOMIC_DEC_U32 = 64
|
|
GLOBAL_ATOMIC_SWAP_B64 = 65
|
|
GLOBAL_ATOMIC_CMPSWAP_B64 = 66
|
|
GLOBAL_ATOMIC_ADD_U64 = 67
|
|
GLOBAL_ATOMIC_SUB_U64 = 68
|
|
GLOBAL_ATOMIC_MIN_I64 = 69
|
|
GLOBAL_ATOMIC_MIN_U64 = 70
|
|
GLOBAL_ATOMIC_MAX_I64 = 71
|
|
GLOBAL_ATOMIC_MAX_U64 = 72
|
|
GLOBAL_ATOMIC_AND_B64 = 73
|
|
GLOBAL_ATOMIC_OR_B64 = 74
|
|
GLOBAL_ATOMIC_XOR_B64 = 75
|
|
GLOBAL_ATOMIC_INC_U64 = 76
|
|
GLOBAL_ATOMIC_DEC_U64 = 77
|
|
GLOBAL_WBINV = 79
|
|
GLOBAL_ATOMIC_COND_SUB_U32 = 80
|
|
GLOBAL_ATOMIC_MIN_NUM_F32 = 81
|
|
GLOBAL_ATOMIC_MAX_NUM_F32 = 82
|
|
GLOBAL_LOAD_BLOCK = 83
|
|
GLOBAL_STORE_BLOCK = 84
|
|
GLOBAL_ATOMIC_ADD_F32 = 86
|
|
GLOBAL_LOAD_TR_B128 = 87
|
|
GLOBAL_LOAD_TR_B64 = 88
|
|
GLOBAL_ATOMIC_PK_ADD_F16 = 89
|
|
GLOBAL_ATOMIC_PK_ADD_BF16 = 90
|
|
GLOBAL_ATOMIC_ORDERED_ADD_B64 = 115
|
|
|
|
class VIMAGEOp(IntEnum):
|
|
IMAGE_LOAD = 0
|
|
IMAGE_LOAD_MIP = 1
|
|
IMAGE_LOAD_PCK = 2
|
|
IMAGE_LOAD_PCK_SGN = 3
|
|
IMAGE_LOAD_MIP_PCK = 4
|
|
IMAGE_LOAD_MIP_PCK_SGN = 5
|
|
IMAGE_STORE = 6
|
|
IMAGE_STORE_MIP = 7
|
|
IMAGE_STORE_PCK = 8
|
|
IMAGE_STORE_MIP_PCK = 9
|
|
IMAGE_ATOMIC_SWAP = 10
|
|
IMAGE_ATOMIC_CMPSWAP = 11
|
|
IMAGE_ATOMIC_ADD_UINT = 12
|
|
IMAGE_ATOMIC_SUB_UINT = 13
|
|
IMAGE_ATOMIC_MIN_INT = 14
|
|
IMAGE_ATOMIC_MIN_UINT = 15
|
|
IMAGE_ATOMIC_MAX_INT = 16
|
|
IMAGE_ATOMIC_MAX_UINT = 17
|
|
IMAGE_ATOMIC_AND = 18
|
|
IMAGE_ATOMIC_OR = 19
|
|
IMAGE_ATOMIC_XOR = 20
|
|
IMAGE_ATOMIC_INC_UINT = 21
|
|
IMAGE_ATOMIC_DEC_UINT = 22
|
|
IMAGE_GET_RESINFO = 23
|
|
IMAGE_BVH_INTERSECT_RAY = 25
|
|
IMAGE_BVH64_INTERSECT_RAY = 26
|
|
IMAGE_BVH_DUAL_INTERSECT_RAY = 128
|
|
IMAGE_BVH8_INTERSECT_RAY = 129
|
|
IMAGE_ATOMIC_ADD_FLT = 131
|
|
IMAGE_ATOMIC_MIN_FLT = 132
|
|
IMAGE_ATOMIC_MAX_FLT = 133
|
|
IMAGE_ATOMIC_PK_ADD_F16 = 134
|
|
IMAGE_ATOMIC_PK_ADD_BF16 = 135
|
|
|
|
class VINTERPOp(IntEnum):
|
|
V_INTERP_P10_F32 = 0
|
|
V_INTERP_P2_F32 = 1
|
|
V_INTERP_P10_F16_F32 = 2
|
|
V_INTERP_P2_F16_F32 = 3
|
|
V_INTERP_P10_RTZ_F16_F32 = 4
|
|
V_INTERP_P2_RTZ_F16_F32 = 5
|
|
|
|
class VOP1Op(IntEnum):
|
|
V_NOP = 0
|
|
V_MOV_B32 = 1
|
|
V_READFIRSTLANE_B32 = 2
|
|
V_CVT_I32_F64 = 3
|
|
V_CVT_F64_I32 = 4
|
|
V_CVT_F32_I32 = 5
|
|
V_CVT_F32_U32 = 6
|
|
V_CVT_U32_F32 = 7
|
|
V_CVT_I32_F32 = 8
|
|
V_CVT_F16_F32 = 10
|
|
V_CVT_F32_F16 = 11
|
|
V_CVT_NEAREST_I32_F32 = 12
|
|
V_CVT_FLOOR_I32_F32 = 13
|
|
V_CVT_OFF_F32_I4 = 14
|
|
V_CVT_F32_F64 = 15
|
|
V_CVT_F64_F32 = 16
|
|
V_CVT_F32_UBYTE0 = 17
|
|
V_CVT_F32_UBYTE1 = 18
|
|
V_CVT_F32_UBYTE2 = 19
|
|
V_CVT_F32_UBYTE3 = 20
|
|
V_CVT_U32_F64 = 21
|
|
V_CVT_F64_U32 = 22
|
|
V_TRUNC_F64 = 23
|
|
V_CEIL_F64 = 24
|
|
V_RNDNE_F64 = 25
|
|
V_FLOOR_F64 = 26
|
|
V_PIPEFLUSH = 27
|
|
V_MOV_B16 = 28
|
|
V_FRACT_F32 = 32
|
|
V_TRUNC_F32 = 33
|
|
V_CEIL_F32 = 34
|
|
V_RNDNE_F32 = 35
|
|
V_FLOOR_F32 = 36
|
|
V_EXP_F32 = 37
|
|
V_LOG_F32 = 39
|
|
V_RCP_F32 = 42
|
|
V_RCP_IFLAG_F32 = 43
|
|
V_RSQ_F32 = 46
|
|
V_RCP_F64 = 47
|
|
V_RSQ_F64 = 49
|
|
V_SQRT_F32 = 51
|
|
V_SQRT_F64 = 52
|
|
V_SIN_F32 = 53
|
|
V_COS_F32 = 54
|
|
V_NOT_B32 = 55
|
|
V_BFREV_B32 = 56
|
|
V_CLZ_I32_U32 = 57
|
|
V_CTZ_I32_B32 = 58
|
|
V_CLS_I32 = 59
|
|
V_FREXP_EXP_I32_F64 = 60
|
|
V_FREXP_MANT_F64 = 61
|
|
V_FRACT_F64 = 62
|
|
V_FREXP_EXP_I32_F32 = 63
|
|
V_FREXP_MANT_F32 = 64
|
|
V_MOVRELD_B32 = 66
|
|
V_MOVRELS_B32 = 67
|
|
V_MOVRELSD_B32 = 68
|
|
V_MOVRELSD_2_B32 = 72
|
|
V_CVT_F16_U16 = 80
|
|
V_CVT_F16_I16 = 81
|
|
V_CVT_U16_F16 = 82
|
|
V_CVT_I16_F16 = 83
|
|
V_RCP_F16 = 84
|
|
V_SQRT_F16 = 85
|
|
V_RSQ_F16 = 86
|
|
V_LOG_F16 = 87
|
|
V_EXP_F16 = 88
|
|
V_FREXP_MANT_F16 = 89
|
|
V_FREXP_EXP_I16_F16 = 90
|
|
V_FLOOR_F16 = 91
|
|
V_CEIL_F16 = 92
|
|
V_TRUNC_F16 = 93
|
|
V_RNDNE_F16 = 94
|
|
V_FRACT_F16 = 95
|
|
V_SIN_F16 = 96
|
|
V_COS_F16 = 97
|
|
V_SAT_PK_U8_I16 = 98
|
|
V_CVT_NORM_I16_F16 = 99
|
|
V_CVT_NORM_U16_F16 = 100
|
|
V_SWAP_B32 = 101
|
|
V_SWAP_B16 = 102
|
|
V_PERMLANE64_B32 = 103
|
|
V_SWAPREL_B32 = 104
|
|
V_NOT_B16 = 105
|
|
V_CVT_I32_I16 = 106
|
|
V_CVT_U32_U16 = 107
|
|
V_CVT_F32_FP8 = 108
|
|
V_CVT_F32_BF8 = 109
|
|
V_CVT_PK_F32_FP8 = 110
|
|
V_CVT_PK_F32_BF8 = 111
|
|
|
|
class VOP2Op(IntEnum):
|
|
V_CNDMASK_B32 = 1
|
|
V_ADD_F64 = 2
|
|
V_ADD_F32 = 3
|
|
V_SUB_F32 = 4
|
|
V_SUBREV_F32 = 5
|
|
V_MUL_F64 = 6
|
|
V_MUL_DX9_ZERO_F32 = 7
|
|
V_MUL_F32 = 8
|
|
V_MUL_I32_I24 = 9
|
|
V_MUL_HI_I32_I24 = 10
|
|
V_MUL_U32_U24 = 11
|
|
V_MUL_HI_U32_U24 = 12
|
|
V_MIN_NUM_F64 = 13
|
|
V_MAX_NUM_F64 = 14
|
|
V_MIN_I32 = 17
|
|
V_MAX_I32 = 18
|
|
V_MIN_U32 = 19
|
|
V_MAX_U32 = 20
|
|
V_MIN_NUM_F32 = 21
|
|
V_MAX_NUM_F32 = 22
|
|
V_LSHLREV_B32 = 24
|
|
V_LSHRREV_B32 = 25
|
|
V_ASHRREV_I32 = 26
|
|
V_AND_B32 = 27
|
|
V_OR_B32 = 28
|
|
V_XOR_B32 = 29
|
|
V_XNOR_B32 = 30
|
|
V_LSHLREV_B64 = 31
|
|
V_ADD_CO_CI_U32 = 32
|
|
V_SUB_CO_CI_U32 = 33
|
|
V_SUBREV_CO_CI_U32 = 34
|
|
V_ADD_NC_U32 = 37
|
|
V_SUB_NC_U32 = 38
|
|
V_SUBREV_NC_U32 = 39
|
|
V_FMAC_F32 = 43
|
|
V_FMAMK_F32 = 44
|
|
V_FMAAK_F32 = 45
|
|
V_CVT_PK_RTZ_F16_F32 = 47
|
|
V_MIN_NUM_F16 = 48
|
|
V_MAX_NUM_F16 = 49
|
|
V_ADD_F16 = 50
|
|
V_SUB_F16 = 51
|
|
V_SUBREV_F16 = 52
|
|
V_MUL_F16 = 53
|
|
V_FMAC_F16 = 54
|
|
V_FMAMK_F16 = 55
|
|
V_FMAAK_F16 = 56
|
|
V_LDEXP_F16 = 59
|
|
V_PK_FMAC_F16 = 60
|
|
|
|
class VOP3Op(IntEnum):
|
|
V_CMP_LT_F16 = 1
|
|
V_CMP_EQ_F16 = 2
|
|
V_CMP_LE_F16 = 3
|
|
V_CMP_GT_F16 = 4
|
|
V_CMP_LG_F16 = 5
|
|
V_CMP_GE_F16 = 6
|
|
V_CMP_O_F16 = 7
|
|
V_CMP_U_F16 = 8
|
|
V_CMP_NGE_F16 = 9
|
|
V_CMP_NLG_F16 = 10
|
|
V_CMP_NGT_F16 = 11
|
|
V_CMP_NLE_F16 = 12
|
|
V_CMP_NEQ_F16 = 13
|
|
V_CMP_NLT_F16 = 14
|
|
V_CMP_LT_F32 = 17
|
|
V_CMP_EQ_F32 = 18
|
|
V_CMP_LE_F32 = 19
|
|
V_CMP_GT_F32 = 20
|
|
V_CMP_LG_F32 = 21
|
|
V_CMP_GE_F32 = 22
|
|
V_CMP_O_F32 = 23
|
|
V_CMP_U_F32 = 24
|
|
V_CMP_NGE_F32 = 25
|
|
V_CMP_NLG_F32 = 26
|
|
V_CMP_NGT_F32 = 27
|
|
V_CMP_NLE_F32 = 28
|
|
V_CMP_NEQ_F32 = 29
|
|
V_CMP_NLT_F32 = 30
|
|
V_CMP_LT_F64 = 33
|
|
V_CMP_EQ_F64 = 34
|
|
V_CMP_LE_F64 = 35
|
|
V_CMP_GT_F64 = 36
|
|
V_CMP_LG_F64 = 37
|
|
V_CMP_GE_F64 = 38
|
|
V_CMP_O_F64 = 39
|
|
V_CMP_U_F64 = 40
|
|
V_CMP_NGE_F64 = 41
|
|
V_CMP_NLG_F64 = 42
|
|
V_CMP_NGT_F64 = 43
|
|
V_CMP_NLE_F64 = 44
|
|
V_CMP_NEQ_F64 = 45
|
|
V_CMP_NLT_F64 = 46
|
|
V_CMP_LT_I16 = 49
|
|
V_CMP_EQ_I16 = 50
|
|
V_CMP_LE_I16 = 51
|
|
V_CMP_GT_I16 = 52
|
|
V_CMP_NE_I16 = 53
|
|
V_CMP_GE_I16 = 54
|
|
V_CMP_LT_U16 = 57
|
|
V_CMP_EQ_U16 = 58
|
|
V_CMP_LE_U16 = 59
|
|
V_CMP_GT_U16 = 60
|
|
V_CMP_NE_U16 = 61
|
|
V_CMP_GE_U16 = 62
|
|
V_CMP_LT_I32 = 65
|
|
V_CMP_EQ_I32 = 66
|
|
V_CMP_LE_I32 = 67
|
|
V_CMP_GT_I32 = 68
|
|
V_CMP_NE_I32 = 69
|
|
V_CMP_GE_I32 = 70
|
|
V_CMP_LT_U32 = 73
|
|
V_CMP_EQ_U32 = 74
|
|
V_CMP_LE_U32 = 75
|
|
V_CMP_GT_U32 = 76
|
|
V_CMP_NE_U32 = 77
|
|
V_CMP_GE_U32 = 78
|
|
V_CMP_LT_I64 = 81
|
|
V_CMP_EQ_I64 = 82
|
|
V_CMP_LE_I64 = 83
|
|
V_CMP_GT_I64 = 84
|
|
V_CMP_NE_I64 = 85
|
|
V_CMP_GE_I64 = 86
|
|
V_CMP_LT_U64 = 89
|
|
V_CMP_EQ_U64 = 90
|
|
V_CMP_LE_U64 = 91
|
|
V_CMP_GT_U64 = 92
|
|
V_CMP_NE_U64 = 93
|
|
V_CMP_GE_U64 = 94
|
|
V_CMP_CLASS_F16 = 125
|
|
V_CMP_CLASS_F32 = 126
|
|
V_CMP_CLASS_F64 = 127
|
|
V_CMPX_LT_F16 = 129
|
|
V_CMPX_EQ_F16 = 130
|
|
V_CMPX_LE_F16 = 131
|
|
V_CMPX_GT_F16 = 132
|
|
V_CMPX_LG_F16 = 133
|
|
V_CMPX_GE_F16 = 134
|
|
V_CMPX_O_F16 = 135
|
|
V_CMPX_U_F16 = 136
|
|
V_CMPX_NGE_F16 = 137
|
|
V_CMPX_NLG_F16 = 138
|
|
V_CMPX_NGT_F16 = 139
|
|
V_CMPX_NLE_F16 = 140
|
|
V_CMPX_NEQ_F16 = 141
|
|
V_CMPX_NLT_F16 = 142
|
|
V_CMPX_LT_F32 = 145
|
|
V_CMPX_EQ_F32 = 146
|
|
V_CMPX_LE_F32 = 147
|
|
V_CMPX_GT_F32 = 148
|
|
V_CMPX_LG_F32 = 149
|
|
V_CMPX_GE_F32 = 150
|
|
V_CMPX_O_F32 = 151
|
|
V_CMPX_U_F32 = 152
|
|
V_CMPX_NGE_F32 = 153
|
|
V_CMPX_NLG_F32 = 154
|
|
V_CMPX_NGT_F32 = 155
|
|
V_CMPX_NLE_F32 = 156
|
|
V_CMPX_NEQ_F32 = 157
|
|
V_CMPX_NLT_F32 = 158
|
|
V_CMPX_LT_F64 = 161
|
|
V_CMPX_EQ_F64 = 162
|
|
V_CMPX_LE_F64 = 163
|
|
V_CMPX_GT_F64 = 164
|
|
V_CMPX_LG_F64 = 165
|
|
V_CMPX_GE_F64 = 166
|
|
V_CMPX_O_F64 = 167
|
|
V_CMPX_U_F64 = 168
|
|
V_CMPX_NGE_F64 = 169
|
|
V_CMPX_NLG_F64 = 170
|
|
V_CMPX_NGT_F64 = 171
|
|
V_CMPX_NLE_F64 = 172
|
|
V_CMPX_NEQ_F64 = 173
|
|
V_CMPX_NLT_F64 = 174
|
|
V_CMPX_LT_I16 = 177
|
|
V_CMPX_EQ_I16 = 178
|
|
V_CMPX_LE_I16 = 179
|
|
V_CMPX_GT_I16 = 180
|
|
V_CMPX_NE_I16 = 181
|
|
V_CMPX_GE_I16 = 182
|
|
V_CMPX_LT_U16 = 185
|
|
V_CMPX_EQ_U16 = 186
|
|
V_CMPX_LE_U16 = 187
|
|
V_CMPX_GT_U16 = 188
|
|
V_CMPX_NE_U16 = 189
|
|
V_CMPX_GE_U16 = 190
|
|
V_CMPX_LT_I32 = 193
|
|
V_CMPX_EQ_I32 = 194
|
|
V_CMPX_LE_I32 = 195
|
|
V_CMPX_GT_I32 = 196
|
|
V_CMPX_NE_I32 = 197
|
|
V_CMPX_GE_I32 = 198
|
|
V_CMPX_LT_U32 = 201
|
|
V_CMPX_EQ_U32 = 202
|
|
V_CMPX_LE_U32 = 203
|
|
V_CMPX_GT_U32 = 204
|
|
V_CMPX_NE_U32 = 205
|
|
V_CMPX_GE_U32 = 206
|
|
V_CMPX_LT_I64 = 209
|
|
V_CMPX_EQ_I64 = 210
|
|
V_CMPX_LE_I64 = 211
|
|
V_CMPX_GT_I64 = 212
|
|
V_CMPX_NE_I64 = 213
|
|
V_CMPX_GE_I64 = 214
|
|
V_CMPX_LT_U64 = 217
|
|
V_CMPX_EQ_U64 = 218
|
|
V_CMPX_LE_U64 = 219
|
|
V_CMPX_GT_U64 = 220
|
|
V_CMPX_NE_U64 = 221
|
|
V_CMPX_GE_U64 = 222
|
|
V_CMPX_CLASS_F16 = 253
|
|
V_CMPX_CLASS_F32 = 254
|
|
V_CMPX_CLASS_F64 = 255
|
|
V_CNDMASK_B32 = 257
|
|
V_ADD_F64 = 258
|
|
V_ADD_F32 = 259
|
|
V_SUB_F32 = 260
|
|
V_SUBREV_F32 = 261
|
|
V_MUL_F64 = 262
|
|
V_MUL_DX9_ZERO_F32 = 263
|
|
V_MUL_F32 = 264
|
|
V_MUL_I32_I24 = 265
|
|
V_MUL_HI_I32_I24 = 266
|
|
V_MUL_U32_U24 = 267
|
|
V_MUL_HI_U32_U24 = 268
|
|
V_MIN_NUM_F64 = 269
|
|
V_MAX_NUM_F64 = 270
|
|
V_MIN_I32 = 273
|
|
V_MAX_I32 = 274
|
|
V_MIN_U32 = 275
|
|
V_MAX_U32 = 276
|
|
V_MIN_NUM_F32 = 277
|
|
V_MAX_NUM_F32 = 278
|
|
V_LSHLREV_B32 = 280
|
|
V_LSHRREV_B32 = 281
|
|
V_ASHRREV_I32 = 282
|
|
V_AND_B32 = 283
|
|
V_OR_B32 = 284
|
|
V_XOR_B32 = 285
|
|
V_XNOR_B32 = 286
|
|
V_LSHLREV_B64 = 287
|
|
V_ADD_NC_U32 = 293
|
|
V_SUB_NC_U32 = 294
|
|
V_SUBREV_NC_U32 = 295
|
|
V_FMAC_F32 = 299
|
|
V_CVT_PK_RTZ_F16_F32 = 303
|
|
V_MIN_NUM_F16 = 304
|
|
V_MAX_NUM_F16 = 305
|
|
V_ADD_F16 = 306
|
|
V_SUB_F16 = 307
|
|
V_SUBREV_F16 = 308
|
|
V_MUL_F16 = 309
|
|
V_FMAC_F16 = 310
|
|
V_LDEXP_F16 = 315
|
|
V_NOP = 384
|
|
V_MOV_B32 = 385
|
|
V_READFIRSTLANE_B32 = 386
|
|
V_CVT_I32_F64 = 387
|
|
V_CVT_F64_I32 = 388
|
|
V_CVT_F32_I32 = 389
|
|
V_CVT_F32_U32 = 390
|
|
V_CVT_U32_F32 = 391
|
|
V_CVT_I32_F32 = 392
|
|
V_CVT_F16_F32 = 394
|
|
V_CVT_F32_F16 = 395
|
|
V_CVT_NEAREST_I32_F32 = 396
|
|
V_CVT_FLOOR_I32_F32 = 397
|
|
V_CVT_OFF_F32_I4 = 398
|
|
V_CVT_F32_F64 = 399
|
|
V_CVT_F64_F32 = 400
|
|
V_CVT_F32_UBYTE0 = 401
|
|
V_CVT_F32_UBYTE1 = 402
|
|
V_CVT_F32_UBYTE2 = 403
|
|
V_CVT_F32_UBYTE3 = 404
|
|
V_CVT_U32_F64 = 405
|
|
V_CVT_F64_U32 = 406
|
|
V_TRUNC_F64 = 407
|
|
V_CEIL_F64 = 408
|
|
V_RNDNE_F64 = 409
|
|
V_FLOOR_F64 = 410
|
|
V_PIPEFLUSH = 411
|
|
V_MOV_B16 = 412
|
|
V_FRACT_F32 = 416
|
|
V_TRUNC_F32 = 417
|
|
V_CEIL_F32 = 418
|
|
V_RNDNE_F32 = 419
|
|
V_FLOOR_F32 = 420
|
|
V_EXP_F32 = 421
|
|
V_LOG_F32 = 423
|
|
V_RCP_F32 = 426
|
|
V_RCP_IFLAG_F32 = 427
|
|
V_RSQ_F32 = 430
|
|
V_RCP_F64 = 431
|
|
V_RSQ_F64 = 433
|
|
V_SQRT_F32 = 435
|
|
V_SQRT_F64 = 436
|
|
V_SIN_F32 = 437
|
|
V_COS_F32 = 438
|
|
V_NOT_B32 = 439
|
|
V_BFREV_B32 = 440
|
|
V_CLZ_I32_U32 = 441
|
|
V_CTZ_I32_B32 = 442
|
|
V_CLS_I32 = 443
|
|
V_FREXP_EXP_I32_F64 = 444
|
|
V_FREXP_MANT_F64 = 445
|
|
V_FRACT_F64 = 446
|
|
V_FREXP_EXP_I32_F32 = 447
|
|
V_FREXP_MANT_F32 = 448
|
|
V_MOVRELD_B32 = 450
|
|
V_MOVRELS_B32 = 451
|
|
V_MOVRELSD_B32 = 452
|
|
V_MOVRELSD_2_B32 = 456
|
|
V_CVT_F16_U16 = 464
|
|
V_CVT_F16_I16 = 465
|
|
V_CVT_U16_F16 = 466
|
|
V_CVT_I16_F16 = 467
|
|
V_RCP_F16 = 468
|
|
V_SQRT_F16 = 469
|
|
V_RSQ_F16 = 470
|
|
V_LOG_F16 = 471
|
|
V_EXP_F16 = 472
|
|
V_FREXP_MANT_F16 = 473
|
|
V_FREXP_EXP_I16_F16 = 474
|
|
V_FLOOR_F16 = 475
|
|
V_CEIL_F16 = 476
|
|
V_TRUNC_F16 = 477
|
|
V_RNDNE_F16 = 478
|
|
V_FRACT_F16 = 479
|
|
V_SIN_F16 = 480
|
|
V_COS_F16 = 481
|
|
V_SAT_PK_U8_I16 = 482
|
|
V_CVT_NORM_I16_F16 = 483
|
|
V_CVT_NORM_U16_F16 = 484
|
|
V_NOT_B16 = 489
|
|
V_CVT_I32_I16 = 490
|
|
V_CVT_U32_U16 = 491
|
|
V_CVT_F32_FP8 = 492
|
|
V_CVT_F32_BF8 = 493
|
|
V_CVT_PK_F32_FP8 = 494
|
|
V_CVT_PK_F32_BF8 = 495
|
|
V_FMA_DX9_ZERO_F32 = 521
|
|
V_MAD_I32_I24 = 522
|
|
V_MAD_U32_U24 = 523
|
|
V_CUBEID_F32 = 524
|
|
V_CUBESC_F32 = 525
|
|
V_CUBETC_F32 = 526
|
|
V_CUBEMA_F32 = 527
|
|
V_BFE_U32 = 528
|
|
V_BFE_I32 = 529
|
|
V_BFI_B32 = 530
|
|
V_FMA_F32 = 531
|
|
V_FMA_F64 = 532
|
|
V_LERP_U8 = 533
|
|
V_ALIGNBIT_B32 = 534
|
|
V_ALIGNBYTE_B32 = 535
|
|
V_MULLIT_F32 = 536
|
|
V_MIN3_I32 = 538
|
|
V_MIN3_U32 = 539
|
|
V_MAX3_I32 = 541
|
|
V_MAX3_U32 = 542
|
|
V_MED3_I32 = 544
|
|
V_MED3_U32 = 545
|
|
V_SAD_U8 = 546
|
|
V_SAD_HI_U8 = 547
|
|
V_SAD_U16 = 548
|
|
V_SAD_U32 = 549
|
|
V_CVT_PK_U8_F32 = 550
|
|
V_DIV_FIXUP_F32 = 551
|
|
V_DIV_FIXUP_F64 = 552
|
|
V_MIN3_NUM_F32 = 553
|
|
V_MAX3_NUM_F32 = 554
|
|
V_MIN3_NUM_F16 = 555
|
|
V_MAX3_NUM_F16 = 556
|
|
V_MINIMUM3_F32 = 557
|
|
V_MAXIMUM3_F32 = 558
|
|
V_MINIMUM3_F16 = 559
|
|
V_MAXIMUM3_F16 = 560
|
|
V_MED3_NUM_F32 = 561
|
|
V_MED3_NUM_F16 = 562
|
|
V_DIV_FMAS_F32 = 567
|
|
V_DIV_FMAS_F64 = 568
|
|
V_MSAD_U8 = 569
|
|
V_QSAD_PK_U16_U8 = 570
|
|
V_MQSAD_PK_U16_U8 = 571
|
|
V_MQSAD_U32_U8 = 573
|
|
V_XOR3_B32 = 576
|
|
V_MAD_U16 = 577
|
|
V_PERM_B32 = 580
|
|
V_XAD_U32 = 581
|
|
V_LSHL_ADD_U32 = 582
|
|
V_ADD_LSHL_U32 = 583
|
|
V_FMA_F16 = 584
|
|
V_MIN3_I16 = 586
|
|
V_MIN3_U16 = 587
|
|
V_MAX3_I16 = 589
|
|
V_MAX3_U16 = 590
|
|
V_MED3_I16 = 592
|
|
V_MED3_U16 = 593
|
|
V_MAD_I16 = 595
|
|
V_DIV_FIXUP_F16 = 596
|
|
V_ADD3_U32 = 597
|
|
V_LSHL_OR_B32 = 598
|
|
V_AND_OR_B32 = 599
|
|
V_OR3_B32 = 600
|
|
V_MAD_U32_U16 = 601
|
|
V_MAD_I32_I16 = 602
|
|
V_PERMLANE16_B32 = 603
|
|
V_PERMLANEX16_B32 = 604
|
|
V_CNDMASK_B16 = 605
|
|
V_MAXMIN_U32 = 610
|
|
V_MINMAX_U32 = 611
|
|
V_MAXMIN_I32 = 612
|
|
V_MINMAX_I32 = 613
|
|
V_DOT2_F16_F16 = 614
|
|
V_DOT2_BF16_BF16 = 615
|
|
V_MINMAX_NUM_F32 = 616
|
|
V_MAXMIN_NUM_F32 = 617
|
|
V_MINMAX_NUM_F16 = 618
|
|
V_MAXMIN_NUM_F16 = 619
|
|
V_MINIMUMMAXIMUM_F32 = 620
|
|
V_MAXIMUMMINIMUM_F32 = 621
|
|
V_MINIMUMMAXIMUM_F16 = 622
|
|
V_MAXIMUMMINIMUM_F16 = 623
|
|
V_S_EXP_F32 = 640
|
|
V_S_EXP_F16 = 641
|
|
V_S_LOG_F32 = 642
|
|
V_S_LOG_F16 = 643
|
|
V_S_RCP_F32 = 644
|
|
V_S_RCP_F16 = 645
|
|
V_S_RSQ_F32 = 646
|
|
V_S_RSQ_F16 = 647
|
|
V_S_SQRT_F32 = 648
|
|
V_S_SQRT_F16 = 649
|
|
V_ADD_NC_U16 = 771
|
|
V_SUB_NC_U16 = 772
|
|
V_MUL_LO_U16 = 773
|
|
V_CVT_PK_I16_F32 = 774
|
|
V_CVT_PK_U16_F32 = 775
|
|
V_MAX_U16 = 777
|
|
V_MAX_I16 = 778
|
|
V_MIN_U16 = 779
|
|
V_MIN_I16 = 780
|
|
V_ADD_NC_I16 = 781
|
|
V_SUB_NC_I16 = 782
|
|
V_PERMLANE16_VAR_B32 = 783
|
|
V_PERMLANEX16_VAR_B32 = 784
|
|
V_PACK_B32_F16 = 785
|
|
V_CVT_PK_NORM_I16_F16 = 786
|
|
V_CVT_PK_NORM_U16_F16 = 787
|
|
V_LDEXP_F32 = 796
|
|
V_BFM_B32 = 797
|
|
V_BCNT_U32_B32 = 798
|
|
V_MBCNT_LO_U32_B32 = 799
|
|
V_MBCNT_HI_U32_B32 = 800
|
|
V_CVT_PK_NORM_I16_F32 = 801
|
|
V_CVT_PK_NORM_U16_F32 = 802
|
|
V_CVT_PK_U16_U32 = 803
|
|
V_CVT_PK_I16_I32 = 804
|
|
V_SUB_NC_I32 = 805
|
|
V_ADD_NC_I32 = 806
|
|
V_LDEXP_F64 = 811
|
|
V_MUL_LO_U32 = 812
|
|
V_MUL_HI_U32 = 813
|
|
V_MUL_HI_I32 = 814
|
|
V_TRIG_PREOP_F64 = 815
|
|
V_LSHLREV_B16 = 824
|
|
V_LSHRREV_B16 = 825
|
|
V_ASHRREV_I16 = 826
|
|
V_LSHRREV_B64 = 829
|
|
V_ASHRREV_I64 = 830
|
|
V_MINIMUM_F64 = 833
|
|
V_MAXIMUM_F64 = 834
|
|
V_READLANE_B32 = 864
|
|
V_WRITELANE_B32 = 865
|
|
V_AND_B16 = 866
|
|
V_OR_B16 = 867
|
|
V_XOR_B16 = 868
|
|
V_MINIMUM_F32 = 869
|
|
V_MAXIMUM_F32 = 870
|
|
V_MINIMUM_F16 = 871
|
|
V_MAXIMUM_F16 = 872
|
|
V_CVT_PK_FP8_F32 = 873
|
|
V_CVT_PK_BF8_F32 = 874
|
|
V_CVT_SR_FP8_F32 = 875
|
|
V_CVT_SR_BF8_F32 = 876
|
|
|
|
class VOP3POp(IntEnum):
|
|
V_PK_MAD_I16 = 0
|
|
V_PK_MUL_LO_U16 = 1
|
|
V_PK_ADD_I16 = 2
|
|
V_PK_SUB_I16 = 3
|
|
V_PK_LSHLREV_B16 = 4
|
|
V_PK_LSHRREV_B16 = 5
|
|
V_PK_ASHRREV_I16 = 6
|
|
V_PK_MAX_I16 = 7
|
|
V_PK_MIN_I16 = 8
|
|
V_PK_MAD_U16 = 9
|
|
V_PK_ADD_U16 = 10
|
|
V_PK_SUB_U16 = 11
|
|
V_PK_MAX_U16 = 12
|
|
V_PK_MIN_U16 = 13
|
|
V_PK_FMA_F16 = 14
|
|
V_PK_ADD_F16 = 15
|
|
V_PK_MUL_F16 = 16
|
|
V_DOT2_F32_F16 = 19
|
|
V_DOT4_I32_IU8 = 22
|
|
V_DOT4_U32_U8 = 23
|
|
V_DOT8_I32_IU4 = 24
|
|
V_DOT8_U32_U4 = 25
|
|
V_DOT2_F32_BF16 = 26
|
|
V_PK_MIN_NUM_F16 = 27
|
|
V_PK_MAX_NUM_F16 = 28
|
|
V_PK_MINIMUM_F16 = 29
|
|
V_PK_MAXIMUM_F16 = 30
|
|
V_FMA_MIX_F32 = 32
|
|
V_FMA_MIXLO_F16 = 33
|
|
V_FMA_MIXHI_F16 = 34
|
|
V_DOT4_F32_FP8_BF8 = 36
|
|
V_DOT4_F32_BF8_FP8 = 37
|
|
V_DOT4_F32_FP8_FP8 = 38
|
|
V_DOT4_F32_BF8_BF8 = 39
|
|
V_WMMA_F32_16X16X16_F16 = 64
|
|
V_WMMA_F32_16X16X16_BF16 = 65
|
|
V_WMMA_F16_16X16X16_F16 = 66
|
|
V_WMMA_BF16_16X16X16_BF16 = 67
|
|
V_WMMA_I32_16X16X16_IU8 = 68
|
|
V_WMMA_I32_16X16X16_IU4 = 69
|
|
V_WMMA_F32_16X16X16_FP8_FP8 = 70
|
|
V_WMMA_F32_16X16X16_FP8_BF8 = 71
|
|
V_WMMA_F32_16X16X16_BF8_FP8 = 72
|
|
V_WMMA_F32_16X16X16_BF8_BF8 = 73
|
|
V_WMMA_I32_16X16X32_IU4 = 74
|
|
V_SWMMAC_F32_16X16X32_F16 = 80
|
|
V_SWMMAC_F32_16X16X32_BF16 = 81
|
|
V_SWMMAC_F16_16X16X32_F16 = 82
|
|
V_SWMMAC_BF16_16X16X32_BF16 = 83
|
|
V_SWMMAC_I32_16X16X32_IU8 = 84
|
|
V_SWMMAC_I32_16X16X32_IU4 = 85
|
|
V_SWMMAC_I32_16X16X64_IU4 = 86
|
|
V_SWMMAC_F32_16X16X32_FP8_FP8 = 87
|
|
V_SWMMAC_F32_16X16X32_FP8_BF8 = 88
|
|
V_SWMMAC_F32_16X16X32_BF8_FP8 = 89
|
|
V_SWMMAC_F32_16X16X32_BF8_BF8 = 90
|
|
|
|
class VOP3SDOp(IntEnum):
|
|
DWORD = 1
|
|
V_ADD_CO_CI_U32 = 288
|
|
V_SUB_CO_CI_U32 = 289
|
|
V_SUBREV_CO_CI_U32 = 290
|
|
V_DIV_SCALE_F32 = 764
|
|
V_DIV_SCALE_F64 = 765
|
|
V_MAD_CO_U64_U32 = 766
|
|
V_MAD_CO_I64_I32 = 767
|
|
V_ADD_CO_U32 = 768
|
|
V_SUB_CO_U32 = 769
|
|
V_SUBREV_CO_U32 = 770
|
|
|
|
class VOPCOp(IntEnum):
|
|
V_CMP_LT_F16 = 1
|
|
V_CMP_EQ_F16 = 2
|
|
V_CMP_LE_F16 = 3
|
|
V_CMP_GT_F16 = 4
|
|
V_CMP_LG_F16 = 5
|
|
V_CMP_GE_F16 = 6
|
|
V_CMP_O_F16 = 7
|
|
V_CMP_U_F16 = 8
|
|
V_CMP_NGE_F16 = 9
|
|
V_CMP_NLG_F16 = 10
|
|
V_CMP_NGT_F16 = 11
|
|
V_CMP_NLE_F16 = 12
|
|
V_CMP_NEQ_F16 = 13
|
|
V_CMP_NLT_F16 = 14
|
|
V_CMP_LT_F32 = 17
|
|
V_CMP_EQ_F32 = 18
|
|
V_CMP_LE_F32 = 19
|
|
V_CMP_GT_F32 = 20
|
|
V_CMP_LG_F32 = 21
|
|
V_CMP_GE_F32 = 22
|
|
V_CMP_O_F32 = 23
|
|
V_CMP_U_F32 = 24
|
|
V_CMP_NGE_F32 = 25
|
|
V_CMP_NLG_F32 = 26
|
|
V_CMP_NGT_F32 = 27
|
|
V_CMP_NLE_F32 = 28
|
|
V_CMP_NEQ_F32 = 29
|
|
V_CMP_NLT_F32 = 30
|
|
V_CMP_LT_F64 = 33
|
|
V_CMP_EQ_F64 = 34
|
|
V_CMP_LE_F64 = 35
|
|
V_CMP_GT_F64 = 36
|
|
V_CMP_LG_F64 = 37
|
|
V_CMP_GE_F64 = 38
|
|
V_CMP_O_F64 = 39
|
|
V_CMP_U_F64 = 40
|
|
V_CMP_NGE_F64 = 41
|
|
V_CMP_NLG_F64 = 42
|
|
V_CMP_NGT_F64 = 43
|
|
V_CMP_NLE_F64 = 44
|
|
V_CMP_NEQ_F64 = 45
|
|
V_CMP_NLT_F64 = 46
|
|
V_CMP_LT_I16 = 49
|
|
V_CMP_EQ_I16 = 50
|
|
V_CMP_LE_I16 = 51
|
|
V_CMP_GT_I16 = 52
|
|
V_CMP_NE_I16 = 53
|
|
V_CMP_GE_I16 = 54
|
|
V_CMP_LT_U16 = 57
|
|
V_CMP_EQ_U16 = 58
|
|
V_CMP_LE_U16 = 59
|
|
V_CMP_GT_U16 = 60
|
|
V_CMP_NE_U16 = 61
|
|
V_CMP_GE_U16 = 62
|
|
V_CMP_LT_I32 = 65
|
|
V_CMP_EQ_I32 = 66
|
|
V_CMP_LE_I32 = 67
|
|
V_CMP_GT_I32 = 68
|
|
V_CMP_NE_I32 = 69
|
|
V_CMP_GE_I32 = 70
|
|
V_CMP_LT_U32 = 73
|
|
V_CMP_EQ_U32 = 74
|
|
V_CMP_LE_U32 = 75
|
|
V_CMP_GT_U32 = 76
|
|
V_CMP_NE_U32 = 77
|
|
V_CMP_GE_U32 = 78
|
|
V_CMP_LT_I64 = 81
|
|
V_CMP_EQ_I64 = 82
|
|
V_CMP_LE_I64 = 83
|
|
V_CMP_GT_I64 = 84
|
|
V_CMP_NE_I64 = 85
|
|
V_CMP_GE_I64 = 86
|
|
V_CMP_LT_U64 = 89
|
|
V_CMP_EQ_U64 = 90
|
|
V_CMP_LE_U64 = 91
|
|
V_CMP_GT_U64 = 92
|
|
V_CMP_NE_U64 = 93
|
|
V_CMP_GE_U64 = 94
|
|
V_CMP_CLASS_F16 = 125
|
|
V_CMP_CLASS_F32 = 126
|
|
V_CMP_CLASS_F64 = 127
|
|
V_CMPX_LT_F16 = 129
|
|
V_CMPX_EQ_F16 = 130
|
|
V_CMPX_LE_F16 = 131
|
|
V_CMPX_GT_F16 = 132
|
|
V_CMPX_LG_F16 = 133
|
|
V_CMPX_GE_F16 = 134
|
|
V_CMPX_O_F16 = 135
|
|
V_CMPX_U_F16 = 136
|
|
V_CMPX_NGE_F16 = 137
|
|
V_CMPX_NLG_F16 = 138
|
|
V_CMPX_NGT_F16 = 139
|
|
V_CMPX_NLE_F16 = 140
|
|
V_CMPX_NEQ_F16 = 141
|
|
V_CMPX_NLT_F16 = 142
|
|
V_CMPX_LT_F32 = 145
|
|
V_CMPX_EQ_F32 = 146
|
|
V_CMPX_LE_F32 = 147
|
|
V_CMPX_GT_F32 = 148
|
|
V_CMPX_LG_F32 = 149
|
|
V_CMPX_GE_F32 = 150
|
|
V_CMPX_O_F32 = 151
|
|
V_CMPX_U_F32 = 152
|
|
V_CMPX_NGE_F32 = 153
|
|
V_CMPX_NLG_F32 = 154
|
|
V_CMPX_NGT_F32 = 155
|
|
V_CMPX_NLE_F32 = 156
|
|
V_CMPX_NEQ_F32 = 157
|
|
V_CMPX_NLT_F32 = 158
|
|
V_CMPX_LT_F64 = 161
|
|
V_CMPX_EQ_F64 = 162
|
|
V_CMPX_LE_F64 = 163
|
|
V_CMPX_GT_F64 = 164
|
|
V_CMPX_LG_F64 = 165
|
|
V_CMPX_GE_F64 = 166
|
|
V_CMPX_O_F64 = 167
|
|
V_CMPX_U_F64 = 168
|
|
V_CMPX_NGE_F64 = 169
|
|
V_CMPX_NLG_F64 = 170
|
|
V_CMPX_NGT_F64 = 171
|
|
V_CMPX_NLE_F64 = 172
|
|
V_CMPX_NEQ_F64 = 173
|
|
V_CMPX_NLT_F64 = 174
|
|
V_CMPX_LT_I16 = 177
|
|
V_CMPX_EQ_I16 = 178
|
|
V_CMPX_LE_I16 = 179
|
|
V_CMPX_GT_I16 = 180
|
|
V_CMPX_NE_I16 = 181
|
|
V_CMPX_GE_I16 = 182
|
|
V_CMPX_LT_U16 = 185
|
|
V_CMPX_EQ_U16 = 186
|
|
V_CMPX_LE_U16 = 187
|
|
V_CMPX_GT_U16 = 188
|
|
V_CMPX_NE_U16 = 189
|
|
V_CMPX_GE_U16 = 190
|
|
V_CMPX_LT_I32 = 193
|
|
V_CMPX_EQ_I32 = 194
|
|
V_CMPX_LE_I32 = 195
|
|
V_CMPX_GT_I32 = 196
|
|
V_CMPX_NE_I32 = 197
|
|
V_CMPX_GE_I32 = 198
|
|
V_CMPX_LT_U32 = 201
|
|
V_CMPX_EQ_U32 = 202
|
|
V_CMPX_LE_U32 = 203
|
|
V_CMPX_GT_U32 = 204
|
|
V_CMPX_NE_U32 = 205
|
|
V_CMPX_GE_U32 = 206
|
|
V_CMPX_LT_I64 = 209
|
|
V_CMPX_EQ_I64 = 210
|
|
V_CMPX_LE_I64 = 211
|
|
V_CMPX_GT_I64 = 212
|
|
V_CMPX_NE_I64 = 213
|
|
V_CMPX_GE_I64 = 214
|
|
V_CMPX_LT_U64 = 217
|
|
V_CMPX_EQ_U64 = 218
|
|
V_CMPX_LE_U64 = 219
|
|
V_CMPX_GT_U64 = 220
|
|
V_CMPX_NE_U64 = 221
|
|
V_CMPX_GE_U64 = 222
|
|
V_CMPX_CLASS_F16 = 253
|
|
V_CMPX_CLASS_F32 = 254
|
|
V_CMPX_CLASS_F64 = 255
|
|
|
|
class VOPDOp(IntEnum):
|
|
V_DUAL_FMAC_F32 = 0
|
|
V_DUAL_FMAAK_F32 = 1
|
|
V_DUAL_FMAMK_F32 = 2
|
|
V_DUAL_MUL_F32 = 3
|
|
V_DUAL_ADD_F32 = 4
|
|
V_DUAL_SUB_F32 = 5
|
|
V_DUAL_SUBREV_F32 = 6
|
|
V_DUAL_MUL_DX9_ZERO_F32 = 7
|
|
V_DUAL_MOV_B32 = 8
|
|
V_DUAL_CNDMASK_B32 = 9
|
|
V_DUAL_MAX_NUM_F32 = 10
|
|
V_DUAL_MIN_NUM_F32 = 11
|
|
V_DUAL_DOT2ACC_F32_F16 = 12
|
|
V_DUAL_DOT2ACC_F32_BF16 = 13
|
|
V_DUAL_ADD_NC_U32 = 16
|
|
V_DUAL_LSHLREV_B32 = 17
|
|
V_DUAL_AND_B32 = 18
|
|
|
|
class VSAMPLEOp(IntEnum):
|
|
IMAGE_MSAA_LOAD = 24
|
|
IMAGE_SAMPLE = 27
|
|
IMAGE_SAMPLE_D = 28
|
|
IMAGE_SAMPLE_L = 29
|
|
IMAGE_SAMPLE_B = 30
|
|
IMAGE_SAMPLE_LZ = 31
|
|
IMAGE_SAMPLE_C = 32
|
|
IMAGE_SAMPLE_C_D = 33
|
|
IMAGE_SAMPLE_C_L = 34
|
|
IMAGE_SAMPLE_C_B = 35
|
|
IMAGE_SAMPLE_C_LZ = 36
|
|
IMAGE_SAMPLE_O = 37
|
|
IMAGE_SAMPLE_D_O = 38
|
|
IMAGE_SAMPLE_L_O = 39
|
|
IMAGE_SAMPLE_B_O = 40
|
|
IMAGE_SAMPLE_LZ_O = 41
|
|
IMAGE_SAMPLE_C_O = 42
|
|
IMAGE_SAMPLE_C_D_O = 43
|
|
IMAGE_SAMPLE_C_L_O = 44
|
|
IMAGE_SAMPLE_C_B_O = 45
|
|
IMAGE_SAMPLE_C_LZ_O = 46
|
|
IMAGE_GATHER4 = 47
|
|
IMAGE_GATHER4_L = 48
|
|
IMAGE_GATHER4_B = 49
|
|
IMAGE_GATHER4_LZ = 50
|
|
IMAGE_GATHER4_C = 51
|
|
IMAGE_GATHER4_C_LZ = 52
|
|
IMAGE_GATHER4_O = 53
|
|
IMAGE_GATHER4_LZ_O = 54
|
|
IMAGE_GATHER4_C_LZ_O = 55
|
|
IMAGE_GET_LOD = 56
|
|
IMAGE_SAMPLE_D_G16 = 57
|
|
IMAGE_SAMPLE_C_D_G16 = 58
|
|
IMAGE_SAMPLE_D_O_G16 = 59
|
|
IMAGE_SAMPLE_C_D_O_G16 = 60
|
|
IMAGE_SAMPLE_CL = 64
|
|
IMAGE_SAMPLE_D_CL = 65
|
|
IMAGE_SAMPLE_B_CL = 66
|
|
IMAGE_SAMPLE_C_CL = 67
|
|
IMAGE_SAMPLE_C_D_CL = 68
|
|
IMAGE_SAMPLE_C_B_CL = 69
|
|
IMAGE_SAMPLE_CL_O = 70
|
|
IMAGE_SAMPLE_D_CL_O = 71
|
|
IMAGE_SAMPLE_B_CL_O = 72
|
|
IMAGE_SAMPLE_C_CL_O = 73
|
|
IMAGE_SAMPLE_C_D_CL_O = 74
|
|
IMAGE_SAMPLE_C_B_CL_O = 75
|
|
IMAGE_SAMPLE_C_D_CL_G16 = 84
|
|
IMAGE_SAMPLE_D_CL_O_G16 = 85
|
|
IMAGE_SAMPLE_C_D_CL_O_G16 = 86
|
|
IMAGE_SAMPLE_D_CL_G16 = 95
|
|
IMAGE_GATHER4_CL = 96
|
|
IMAGE_GATHER4_B_CL = 97
|
|
IMAGE_GATHER4_C_CL = 98
|
|
IMAGE_GATHER4_C_L = 99
|
|
IMAGE_GATHER4_C_B = 100
|
|
IMAGE_GATHER4_C_B_CL = 101
|
|
IMAGE_GATHER4H = 144
|
|
|
|
class VSCRATCHOp(IntEnum):
|
|
SCRATCH_LOAD_U8 = 16
|
|
SCRATCH_LOAD_I8 = 17
|
|
SCRATCH_LOAD_U16 = 18
|
|
SCRATCH_LOAD_I16 = 19
|
|
SCRATCH_LOAD_B32 = 20
|
|
SCRATCH_LOAD_B64 = 21
|
|
SCRATCH_LOAD_B96 = 22
|
|
SCRATCH_LOAD_B128 = 23
|
|
SCRATCH_STORE_B8 = 24
|
|
SCRATCH_STORE_B16 = 25
|
|
SCRATCH_STORE_B32 = 26
|
|
SCRATCH_STORE_B64 = 27
|
|
SCRATCH_STORE_B96 = 28
|
|
SCRATCH_STORE_B128 = 29
|
|
SCRATCH_LOAD_D16_U8 = 30
|
|
SCRATCH_LOAD_D16_I8 = 31
|
|
SCRATCH_LOAD_D16_B16 = 32
|
|
SCRATCH_LOAD_D16_HI_U8 = 33
|
|
SCRATCH_LOAD_D16_HI_I8 = 34
|
|
SCRATCH_LOAD_D16_HI_B16 = 35
|
|
SCRATCH_STORE_D16_HI_B8 = 36
|
|
SCRATCH_STORE_D16_HI_B16 = 37
|
|
SCRATCH_LOAD_BLOCK = 83
|
|
SCRATCH_STORE_BLOCK = 84
|
|
|
|
class BufFmt(IntEnum):
|
|
BUF_FMT_8_UNORM = 1
|
|
BUF_FMT_8_SNORM = 2
|
|
BUF_FMT_8_USCALED = 3
|
|
BUF_FMT_8_SSCALED = 4
|
|
BUF_FMT_8_UINT = 5
|
|
BUF_FMT_8_SINT = 6
|
|
BUF_FMT_16_UNORM = 7
|
|
BUF_FMT_16_SNORM = 8
|
|
BUF_FMT_16_USCALED = 9
|
|
BUF_FMT_16_SSCALED = 10
|
|
BUF_FMT_16_UINT = 11
|
|
BUF_FMT_16_SINT = 12
|
|
BUF_FMT_16_FLOAT = 13
|
|
BUF_FMT_8_8_UNORM = 14
|
|
BUF_FMT_8_8_SNORM = 15
|
|
BUF_FMT_8_8_USCALED = 16
|
|
BUF_FMT_8_8_SSCALED = 17
|
|
BUF_FMT_8_8_UINT = 18
|
|
BUF_FMT_8_8_SINT = 19
|
|
BUF_FMT_32_UINT = 20
|
|
BUF_FMT_32_SINT = 21
|
|
BUF_FMT_32_FLOAT = 22
|
|
BUF_FMT_16_16_UNORM = 23
|
|
BUF_FMT_10_10_10_2_UNORM = 32
|
|
BUF_FMT_10_10_10_2_SNORM = 33
|
|
BUF_FMT_10_10_10_2_UINT = 34
|
|
BUF_FMT_10_10_10_2_SINT = 35
|
|
BUF_FMT_2_10_10_10_UNORM = 36
|
|
BUF_FMT_2_10_10_10_SNORM = 37
|
|
BUF_FMT_2_10_10_10_USCALED = 38
|
|
BUF_FMT_2_10_10_10_SSCALED = 39
|
|
BUF_FMT_2_10_10_10_UINT = 40
|
|
BUF_FMT_2_10_10_10_SINT = 41
|
|
BUF_FMT_8_8_8_8_UNORM = 42
|
|
BUF_FMT_8_8_8_8_SNORM = 43
|
|
BUF_FMT_8_8_8_8_USCALED = 44
|
|
BUF_FMT_8_8_8_8_SSCALED = 45
|
|
BUF_FMT_8_8_8_8_UINT = 46
|
|
BUF_FMT_8_8_8_8_SINT = 47
|
|
BUF_FMT_32_32_UINT = 48
|
|
BUF_FMT_32_32_SINT = 49
|
|
BUF_FMT_32_32_FLOAT = 50
|
|
BUF_FMT_16_16_16_16_UNORM = 51
|
|
BUF_FMT_16_16_16_16_SNORM = 52
|
|
BUF_FMT_16_16_16_16_USCALED = 53
|
|
BUF_FMT_16_16_16_16_SSCALED = 54
|
|
BUF_FMT_16_16_16_16_UINT = 55
|