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49 lines
947 B
Verilog
49 lines
947 B
Verilog
module top (
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input clk_i,
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input [3:0] sw,
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output [11:0] led,
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output ser_tx,
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input ser_rx,
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);
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//assign led = {&sw, |sw, ^sw, ~^sw};
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reg clk50 = 1'b0;
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always @(posedge clk_i)
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clk50 <= ~clk50;
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wire clk;
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BUFGCTRL bufg_i (
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.I0(clk50),
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.CE0(1'b1),
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.S0(1'b1),
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.O(clk)
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);
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// wire clk = clk_i;
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//reg clkdiv;
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//reg [22:0] ctr;
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//always @(posedge clk) {clkdiv, ctr} <= ctr + 1'b1;
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wire [7:0] soc_led;
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attosoc soc_i(
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.clk(clk),
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.reset(sw[0]),
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.led(soc_led),
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.ser_tx(ser_tx),
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.ser_rx(ser_rx),
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);
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// this maps 2 bits to each LED
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generate
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genvar i;
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for (i = 0; i < 4; i++) begin
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assign led[0 + i] = soc_led[2 * i]; // R
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assign led[4 + i] = soc_led[(2 * i) + 1]; // G
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assign led[8 + i] = &soc_led[2 * i +: 2]; // B
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end
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endgenerate
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endmodule
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