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* assembly/amd: make pdf.py code shine * no merge * pdf2 is the future * something * regen enums * test * work * remove junk * write * pcode extraction * pdf2 passes all tests * simplify * simpler pdf * late filter * remove hacks * simplify pdf2.py * field type * remove defaults * don't export srcenum * simple pdf.py * simpler * cleaner * less hack in PDF
1590 lines
36 KiB
Python
1590 lines
36 KiB
Python
# autogenerated from AMD ISA PDF by pdf.py - do not edit
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from enum import IntEnum
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class DSOp(IntEnum):
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DS_ADD_U32 = 0
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DS_SUB_U32 = 1
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DS_RSUB_U32 = 2
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DS_INC_U32 = 3
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DS_DEC_U32 = 4
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DS_MIN_I32 = 5
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DS_MAX_I32 = 6
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DS_MIN_U32 = 7
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DS_MAX_U32 = 8
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DS_AND_B32 = 9
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DS_OR_B32 = 10
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DS_XOR_B32 = 11
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DS_MSKOR_B32 = 12
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DS_WRITE_B32 = 13
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DS_WRITE2_B32 = 14
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DS_WRITE2ST64_B32 = 15
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DS_CMPST_B32 = 16
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DS_CMPST_F32 = 17
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DS_MIN_F32 = 18
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DS_MAX_F32 = 19
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DS_NOP = 20
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DS_ADD_F32 = 21
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DS_PK_ADD_F16 = 23
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DS_PK_ADD_BF16 = 24
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DS_WRITE_ADDTID_B32 = 29
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DS_WRITE_B8 = 30
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DS_WRITE_B16 = 31
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DS_ADD_RTN_U32 = 32
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DS_SUB_RTN_U32 = 33
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DS_RSUB_RTN_U32 = 34
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DS_INC_RTN_U32 = 35
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DS_DEC_RTN_U32 = 36
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DS_MIN_RTN_I32 = 37
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DS_MAX_RTN_I32 = 38
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DS_MIN_RTN_U32 = 39
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DS_MAX_RTN_U32 = 40
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DS_AND_RTN_B32 = 41
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DS_OR_RTN_B32 = 42
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DS_XOR_RTN_B32 = 43
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DS_MSKOR_RTN_B32 = 44
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DS_WRXCHG_RTN_B32 = 45
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DS_WRXCHG2_RTN_B32 = 46
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DS_WRXCHG2ST64_RTN_B32 = 47
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DS_CMPST_RTN_B32 = 48
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DS_CMPST_RTN_F32 = 49
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DS_MIN_RTN_F32 = 50
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DS_MAX_RTN_F32 = 51
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DS_WRAP_RTN_B32 = 52
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DS_ADD_RTN_F32 = 53
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DS_READ_B32 = 54
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DS_READ2_B32 = 55
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DS_READ2ST64_B32 = 56
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DS_READ_I8 = 57
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DS_READ_U8 = 58
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DS_READ_I16 = 59
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DS_READ_U16 = 60
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DS_SWIZZLE_B32 = 61
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DS_PERMUTE_B32 = 62
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DS_BPERMUTE_B32 = 63
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DS_ADD_U64 = 64
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DS_SUB_U64 = 65
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DS_RSUB_U64 = 66
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DS_INC_U64 = 67
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DS_DEC_U64 = 68
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DS_MIN_I64 = 69
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DS_MAX_I64 = 70
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DS_MIN_U64 = 71
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DS_MAX_U64 = 72
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DS_AND_B64 = 73
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DS_OR_B64 = 74
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DS_XOR_B64 = 75
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DS_MSKOR_B64 = 76
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DS_WRITE_B64 = 77
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DS_WRITE2_B64 = 78
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DS_WRITE2ST64_B64 = 79
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DS_CMPST_B64 = 80
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DS_CMPST_F64 = 81
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DS_MIN_F64 = 82
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DS_MAX_F64 = 83
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DS_WRITE_B8_D16_HI = 84
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DS_WRITE_B16_D16_HI = 85
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DS_READ_U8_D16 = 86
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DS_READ_U8_D16_HI = 87
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DS_READ_I8_D16 = 88
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DS_READ_I8_D16_HI = 89
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DS_READ_U16_D16 = 90
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DS_READ_U16_D16_HI = 91
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DS_ADD_F64 = 92
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DS_ADD_RTN_U64 = 96
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DS_SUB_RTN_U64 = 97
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DS_RSUB_RTN_U64 = 98
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DS_INC_RTN_U64 = 99
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DS_DEC_RTN_U64 = 100
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DS_MIN_RTN_I64 = 101
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DS_MAX_RTN_I64 = 102
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DS_MIN_RTN_U64 = 103
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DS_MAX_RTN_U64 = 104
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DS_AND_RTN_B64 = 105
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DS_OR_RTN_B64 = 106
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DS_XOR_RTN_B64 = 107
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DS_MSKOR_RTN_B64 = 108
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DS_WRXCHG_RTN_B64 = 109
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DS_WRXCHG2_RTN_B64 = 110
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DS_WRXCHG2ST64_RTN_B64 = 111
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DS_CMPST_RTN_B64 = 112
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DS_CMPST_RTN_F64 = 113
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DS_MIN_RTN_F64 = 114
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DS_MAX_RTN_F64 = 115
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DS_READ_B64 = 118
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DS_READ2_B64 = 119
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DS_READ2ST64_B64 = 120
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DS_ADD_RTN_F64 = 124
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DS_CONDXCHG32_RTN_B64 = 126
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DS_READ_ADDTID_B32 = 182
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DS_PK_ADD_RTN_F16 = 183
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DS_PK_ADD_RTN_BF16 = 184
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DS_CONSUME = 189
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DS_APPEND = 190
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DS_WRITE_B96 = 222
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DS_WRITE_B128 = 223
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DS_READ_B64_TR_B4 = 224
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DS_READ_B96_TR_B6 = 225
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DS_READ_B64_TR_B8 = 226
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DS_READ_B64_TR_B16 = 227
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DS_READ_B96 = 254
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DS_READ_B128 = 255
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class FLATOp(IntEnum):
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FLAT_LOAD_UBYTE = 16
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FLAT_LOAD_SBYTE = 17
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FLAT_LOAD_USHORT = 18
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FLAT_LOAD_SSHORT = 19
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FLAT_LOAD_DWORD = 20
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FLAT_LOAD_DWORDX2 = 21
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FLAT_LOAD_DWORDX3 = 22
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FLAT_LOAD_DWORDX4 = 23
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FLAT_STORE_BYTE = 24
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FLAT_STORE_BYTE_D16_HI = 25
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FLAT_STORE_SHORT = 26
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FLAT_STORE_SHORT_D16_HI = 27
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FLAT_STORE_DWORD = 28
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FLAT_STORE_DWORDX2 = 29
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FLAT_STORE_DWORDX3 = 30
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FLAT_STORE_DWORDX4 = 31
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FLAT_LOAD_UBYTE_D16 = 32
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FLAT_LOAD_UBYTE_D16_HI = 33
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FLAT_LOAD_SBYTE_D16 = 34
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FLAT_LOAD_SBYTE_D16_HI = 35
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FLAT_LOAD_SHORT_D16 = 36
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FLAT_LOAD_SHORT_D16_HI = 37
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FLAT_ATOMIC_SWAP = 64
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FLAT_ATOMIC_CMPSWAP = 65
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FLAT_ATOMIC_ADD = 66
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FLAT_ATOMIC_SUB = 67
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FLAT_ATOMIC_SMIN = 68
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FLAT_ATOMIC_UMIN = 69
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FLAT_ATOMIC_SMAX = 70
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FLAT_ATOMIC_UMAX = 71
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FLAT_ATOMIC_AND = 72
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FLAT_ATOMIC_OR = 73
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FLAT_ATOMIC_XOR = 74
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FLAT_ATOMIC_INC = 75
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FLAT_ATOMIC_DEC = 76
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FLAT_ATOMIC_ADD_F32 = 77
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FLAT_ATOMIC_PK_ADD_F16 = 78
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FLAT_ATOMIC_ADD_F64 = 79
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FLAT_ATOMIC_MIN_F64 = 80
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FLAT_ATOMIC_MAX_F64 = 81
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FLAT_ATOMIC_PK_ADD_BF16 = 82
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FLAT_ATOMIC_SWAP_X2 = 96
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FLAT_ATOMIC_CMPSWAP_X2 = 97
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FLAT_ATOMIC_ADD_X2 = 98
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FLAT_ATOMIC_SUB_X2 = 99
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FLAT_ATOMIC_SMIN_X2 = 100
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FLAT_ATOMIC_UMIN_X2 = 101
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FLAT_ATOMIC_SMAX_X2 = 102
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FLAT_ATOMIC_UMAX_X2 = 103
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FLAT_ATOMIC_AND_X2 = 104
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FLAT_ATOMIC_OR_X2 = 105
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FLAT_ATOMIC_XOR_X2 = 106
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FLAT_ATOMIC_INC_X2 = 107
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FLAT_ATOMIC_DEC_X2 = 108
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class GLOBALOp(IntEnum):
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GLOBAL_LOAD_UBYTE = 16
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GLOBAL_LOAD_SBYTE = 17
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GLOBAL_LOAD_USHORT = 18
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GLOBAL_LOAD_SSHORT = 19
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GLOBAL_LOAD_DWORD = 20
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GLOBAL_LOAD_DWORDX2 = 21
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GLOBAL_LOAD_DWORDX3 = 22
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GLOBAL_LOAD_DWORDX4 = 23
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GLOBAL_STORE_BYTE = 24
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GLOBAL_STORE_BYTE_D16_HI = 25
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GLOBAL_STORE_SHORT = 26
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GLOBAL_STORE_SHORT_D16_HI = 27
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GLOBAL_STORE_DWORD = 28
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GLOBAL_STORE_DWORDX2 = 29
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GLOBAL_STORE_DWORDX3 = 30
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GLOBAL_STORE_DWORDX4 = 31
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GLOBAL_LOAD_UBYTE_D16 = 32
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GLOBAL_LOAD_UBYTE_D16_HI = 33
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GLOBAL_LOAD_SBYTE_D16 = 34
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GLOBAL_LOAD_SBYTE_D16_HI = 35
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GLOBAL_LOAD_SHORT_D16 = 36
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GLOBAL_LOAD_SHORT_D16_HI = 37
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GLOBAL_LOAD_LDS_UBYTE = 38
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GLOBAL_LOAD_LDS_SBYTE = 39
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GLOBAL_LOAD_LDS_USHORT = 40
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GLOBAL_LOAD_LDS_SSHORT = 41
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GLOBAL_LOAD_LDS_DWORD = 42
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GLOBAL_ATOMIC_SWAP = 64
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GLOBAL_ATOMIC_CMPSWAP = 65
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GLOBAL_ATOMIC_ADD = 66
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GLOBAL_ATOMIC_SUB = 67
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GLOBAL_ATOMIC_SMIN = 68
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GLOBAL_ATOMIC_UMIN = 69
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GLOBAL_ATOMIC_SMAX = 70
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GLOBAL_ATOMIC_UMAX = 71
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GLOBAL_ATOMIC_AND = 72
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GLOBAL_ATOMIC_OR = 73
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GLOBAL_ATOMIC_XOR = 74
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GLOBAL_ATOMIC_INC = 75
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GLOBAL_ATOMIC_DEC = 76
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GLOBAL_ATOMIC_ADD_F32 = 77
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GLOBAL_ATOMIC_PK_ADD_F16 = 78
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GLOBAL_ATOMIC_ADD_F64 = 79
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GLOBAL_ATOMIC_MIN_F64 = 80
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GLOBAL_ATOMIC_MAX_F64 = 81
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GLOBAL_ATOMIC_PK_ADD_BF16 = 82
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GLOBAL_ATOMIC_SWAP_X2 = 96
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GLOBAL_ATOMIC_CMPSWAP_X2 = 97
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GLOBAL_ATOMIC_ADD_X2 = 98
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GLOBAL_ATOMIC_SUB_X2 = 99
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GLOBAL_ATOMIC_SMIN_X2 = 100
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GLOBAL_ATOMIC_UMIN_X2 = 101
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GLOBAL_ATOMIC_SMAX_X2 = 102
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GLOBAL_ATOMIC_UMAX_X2 = 103
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GLOBAL_ATOMIC_AND_X2 = 104
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GLOBAL_ATOMIC_OR_X2 = 105
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GLOBAL_ATOMIC_XOR_X2 = 106
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GLOBAL_ATOMIC_INC_X2 = 107
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GLOBAL_ATOMIC_DEC_X2 = 108
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GLOBAL_LOAD_LDS_DWORDX4 = 125
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GLOBAL_LOAD_LDS_DWORDX3 = 126
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class MTBUFOp(IntEnum):
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TBUFFER_LOAD_FORMAT_X = 0
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TBUFFER_LOAD_FORMAT_XY = 1
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TBUFFER_LOAD_FORMAT_XYZ = 2
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TBUFFER_LOAD_FORMAT_XYZW = 3
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TBUFFER_STORE_FORMAT_X = 4
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TBUFFER_STORE_FORMAT_XY = 5
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TBUFFER_STORE_FORMAT_XYZ = 6
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TBUFFER_STORE_FORMAT_XYZW = 7
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TBUFFER_LOAD_FORMAT_D16_X = 8
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TBUFFER_LOAD_FORMAT_D16_XY = 9
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TBUFFER_LOAD_FORMAT_D16_XYZ = 10
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TBUFFER_LOAD_FORMAT_D16_XYZW = 11
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TBUFFER_STORE_FORMAT_D16_X = 12
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TBUFFER_STORE_FORMAT_D16_XY = 13
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TBUFFER_STORE_FORMAT_D16_XYZ = 14
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TBUFFER_STORE_FORMAT_D16_XYZW = 15
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class MUBUFOp(IntEnum):
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BUFFER_LOAD_FORMAT_X = 0
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BUFFER_LOAD_FORMAT_XY = 1
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BUFFER_LOAD_FORMAT_XYZ = 2
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BUFFER_LOAD_FORMAT_XYZW = 3
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BUFFER_STORE_FORMAT_X = 4
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BUFFER_STORE_FORMAT_XY = 5
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BUFFER_STORE_FORMAT_XYZ = 6
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BUFFER_STORE_FORMAT_XYZW = 7
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BUFFER_LOAD_FORMAT_D16_X = 8
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BUFFER_LOAD_FORMAT_D16_XY = 9
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BUFFER_LOAD_FORMAT_D16_XYZ = 10
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BUFFER_LOAD_FORMAT_D16_XYZW = 11
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BUFFER_STORE_FORMAT_D16_X = 12
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BUFFER_STORE_FORMAT_D16_XY = 13
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BUFFER_STORE_FORMAT_D16_XYZ = 14
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BUFFER_STORE_FORMAT_D16_XYZW = 15
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BUFFER_LOAD_UBYTE = 16
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BUFFER_LOAD_SBYTE = 17
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BUFFER_LOAD_USHORT = 18
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BUFFER_LOAD_SSHORT = 19
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BUFFER_LOAD_DWORD = 20
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BUFFER_LOAD_DWORDX2 = 21
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BUFFER_LOAD_DWORDX3 = 22
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BUFFER_LOAD_DWORDX4 = 23
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BUFFER_STORE_BYTE = 24
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BUFFER_STORE_BYTE_D16_HI = 25
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BUFFER_STORE_SHORT = 26
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BUFFER_STORE_SHORT_D16_HI = 27
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BUFFER_STORE_DWORD = 28
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BUFFER_STORE_DWORDX2 = 29
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BUFFER_STORE_DWORDX3 = 30
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BUFFER_STORE_DWORDX4 = 31
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BUFFER_LOAD_UBYTE_D16 = 32
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BUFFER_LOAD_UBYTE_D16_HI = 33
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BUFFER_LOAD_SBYTE_D16 = 34
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BUFFER_LOAD_SBYTE_D16_HI = 35
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BUFFER_LOAD_SHORT_D16 = 36
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BUFFER_LOAD_SHORT_D16_HI = 37
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BUFFER_LOAD_FORMAT_D16_HI_X = 38
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BUFFER_STORE_FORMAT_D16_HI_X = 39
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BUFFER_WBL2 = 40
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BUFFER_INV = 41
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BUFFER_ATOMIC_SWAP = 64
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BUFFER_ATOMIC_CMPSWAP = 65
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BUFFER_ATOMIC_ADD = 66
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BUFFER_ATOMIC_SUB = 67
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BUFFER_ATOMIC_SMIN = 68
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BUFFER_ATOMIC_UMIN = 69
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BUFFER_ATOMIC_SMAX = 70
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BUFFER_ATOMIC_UMAX = 71
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BUFFER_ATOMIC_AND = 72
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BUFFER_ATOMIC_OR = 73
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BUFFER_ATOMIC_XOR = 74
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BUFFER_ATOMIC_INC = 75
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BUFFER_ATOMIC_DEC = 76
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BUFFER_ATOMIC_ADD_F32 = 77
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BUFFER_ATOMIC_PK_ADD_F16 = 78
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BUFFER_ATOMIC_ADD_F64 = 79
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BUFFER_ATOMIC_MIN_F64 = 80
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BUFFER_ATOMIC_MAX_F64 = 81
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BUFFER_ATOMIC_PK_ADD_BF16 = 82
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BUFFER_ATOMIC_SWAP_X2 = 96
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BUFFER_ATOMIC_CMPSWAP_X2 = 97
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BUFFER_ATOMIC_ADD_X2 = 98
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BUFFER_ATOMIC_SUB_X2 = 99
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BUFFER_ATOMIC_SMIN_X2 = 100
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BUFFER_ATOMIC_UMIN_X2 = 101
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BUFFER_ATOMIC_SMAX_X2 = 102
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BUFFER_ATOMIC_UMAX_X2 = 103
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BUFFER_ATOMIC_AND_X2 = 104
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BUFFER_ATOMIC_OR_X2 = 105
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BUFFER_ATOMIC_XOR_X2 = 106
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BUFFER_ATOMIC_INC_X2 = 107
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BUFFER_ATOMIC_DEC_X2 = 108
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class SCRATCHOp(IntEnum):
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SCRATCH_LOAD_UBYTE = 16
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SCRATCH_LOAD_SBYTE = 17
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SCRATCH_LOAD_USHORT = 18
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SCRATCH_LOAD_SSHORT = 19
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SCRATCH_LOAD_DWORD = 20
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SCRATCH_LOAD_DWORDX2 = 21
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SCRATCH_LOAD_DWORDX3 = 22
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SCRATCH_LOAD_DWORDX4 = 23
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SCRATCH_STORE_BYTE = 24
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SCRATCH_STORE_BYTE_D16_HI = 25
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SCRATCH_STORE_SHORT = 26
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SCRATCH_STORE_SHORT_D16_HI = 27
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SCRATCH_STORE_DWORD = 28
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SCRATCH_STORE_DWORDX2 = 29
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SCRATCH_STORE_DWORDX3 = 30
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SCRATCH_STORE_DWORDX4 = 31
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SCRATCH_LOAD_UBYTE_D16 = 32
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SCRATCH_LOAD_UBYTE_D16_HI = 33
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SCRATCH_LOAD_SBYTE_D16 = 34
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SCRATCH_LOAD_SBYTE_D16_HI = 35
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SCRATCH_LOAD_SHORT_D16 = 36
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SCRATCH_LOAD_SHORT_D16_HI = 37
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SCRATCH_LOAD_LDS_UBYTE = 38
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SCRATCH_LOAD_LDS_SBYTE = 39
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SCRATCH_LOAD_LDS_USHORT = 40
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SCRATCH_LOAD_LDS_SSHORT = 41
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SCRATCH_LOAD_LDS_DWORD = 42
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class SMEMOp(IntEnum):
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S_LOAD_DWORD = 0
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S_LOAD_DWORDX2 = 1
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S_LOAD_DWORDX4 = 2
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S_LOAD_DWORDX8 = 3
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S_LOAD_DWORDX16 = 4
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S_SCRATCH_LOAD_DWORD = 5
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S_SCRATCH_LOAD_DWORDX2 = 6
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S_SCRATCH_LOAD_DWORDX4 = 7
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S_BUFFER_LOAD_DWORD = 8
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S_BUFFER_LOAD_DWORDX2 = 9
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S_BUFFER_LOAD_DWORDX4 = 10
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S_BUFFER_LOAD_DWORDX8 = 11
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S_BUFFER_LOAD_DWORDX16 = 12
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S_STORE_DWORD = 16
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S_STORE_DWORDX2 = 17
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S_STORE_DWORDX4 = 18
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S_SCRATCH_STORE_DWORD = 21
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S_SCRATCH_STORE_DWORDX2 = 22
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S_SCRATCH_STORE_DWORDX4 = 23
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S_BUFFER_STORE_DWORD = 24
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S_BUFFER_STORE_DWORDX2 = 25
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S_BUFFER_STORE_DWORDX4 = 26
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S_DCACHE_INV = 32
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S_DCACHE_WB = 33
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S_DCACHE_INV_VOL = 34
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S_DCACHE_WB_VOL = 35
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S_MEMTIME = 36
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S_MEMREALTIME = 37
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S_DCACHE_DISCARD = 40
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S_DCACHE_DISCARD_X2 = 41
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S_BUFFER_ATOMIC_SWAP = 64
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S_BUFFER_ATOMIC_CMPSWAP = 65
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S_BUFFER_ATOMIC_ADD = 66
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S_BUFFER_ATOMIC_SUB = 67
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S_BUFFER_ATOMIC_SMIN = 68
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S_BUFFER_ATOMIC_UMIN = 69
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S_BUFFER_ATOMIC_SMAX = 70
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S_BUFFER_ATOMIC_UMAX = 71
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S_BUFFER_ATOMIC_AND = 72
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S_BUFFER_ATOMIC_OR = 73
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S_BUFFER_ATOMIC_XOR = 74
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S_BUFFER_ATOMIC_INC = 75
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S_BUFFER_ATOMIC_DEC = 76
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S_BUFFER_ATOMIC_SWAP_X2 = 96
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S_BUFFER_ATOMIC_CMPSWAP_X2 = 97
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S_BUFFER_ATOMIC_ADD_X2 = 98
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S_BUFFER_ATOMIC_SUB_X2 = 99
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S_BUFFER_ATOMIC_SMIN_X2 = 100
|
|
S_BUFFER_ATOMIC_UMIN_X2 = 101
|
|
S_BUFFER_ATOMIC_SMAX_X2 = 102
|
|
S_BUFFER_ATOMIC_UMAX_X2 = 103
|
|
S_BUFFER_ATOMIC_AND_X2 = 104
|
|
S_BUFFER_ATOMIC_OR_X2 = 105
|
|
S_BUFFER_ATOMIC_XOR_X2 = 106
|
|
S_BUFFER_ATOMIC_INC_X2 = 107
|
|
S_BUFFER_ATOMIC_DEC_X2 = 108
|
|
S_ATOMIC_SWAP = 128
|
|
S_ATOMIC_CMPSWAP = 129
|
|
S_ATOMIC_ADD = 130
|
|
S_ATOMIC_SUB = 131
|
|
S_ATOMIC_SMIN = 132
|
|
S_ATOMIC_UMIN = 133
|
|
S_ATOMIC_SMAX = 134
|
|
S_ATOMIC_UMAX = 135
|
|
S_ATOMIC_AND = 136
|
|
S_ATOMIC_OR = 137
|
|
S_ATOMIC_XOR = 138
|
|
S_ATOMIC_INC = 139
|
|
S_ATOMIC_DEC = 140
|
|
S_ATOMIC_SWAP_X2 = 160
|
|
S_ATOMIC_CMPSWAP_X2 = 161
|
|
S_ATOMIC_ADD_X2 = 162
|
|
S_ATOMIC_SUB_X2 = 163
|
|
S_ATOMIC_SMIN_X2 = 164
|
|
S_ATOMIC_UMIN_X2 = 165
|
|
S_ATOMIC_SMAX_X2 = 166
|
|
S_ATOMIC_UMAX_X2 = 167
|
|
S_ATOMIC_AND_X2 = 168
|
|
S_ATOMIC_OR_X2 = 169
|
|
S_ATOMIC_XOR_X2 = 170
|
|
S_ATOMIC_INC_X2 = 171
|
|
S_ATOMIC_DEC_X2 = 172
|
|
|
|
class SOP1Op(IntEnum):
|
|
S_MOV_B32 = 0
|
|
S_MOV_B64 = 1
|
|
S_CMOV_B32 = 2
|
|
S_CMOV_B64 = 3
|
|
S_NOT_B32 = 4
|
|
S_NOT_B64 = 5
|
|
S_WQM_B32 = 6
|
|
S_WQM_B64 = 7
|
|
S_BREV_B32 = 8
|
|
S_BREV_B64 = 9
|
|
S_BCNT0_I32_B32 = 10
|
|
S_BCNT0_I32_B64 = 11
|
|
S_BCNT1_I32_B32 = 12
|
|
S_BCNT1_I32_B64 = 13
|
|
S_FF0_I32_B32 = 14
|
|
S_FF0_I32_B64 = 15
|
|
S_FF1_I32_B32 = 16
|
|
S_FF1_I32_B64 = 17
|
|
S_FLBIT_I32_B32 = 18
|
|
S_FLBIT_I32_B64 = 19
|
|
S_FLBIT_I32 = 20
|
|
S_FLBIT_I32_I64 = 21
|
|
S_SEXT_I32_I8 = 22
|
|
S_SEXT_I32_I16 = 23
|
|
S_BITSET0_B32 = 24
|
|
S_BITSET0_B64 = 25
|
|
S_BITSET1_B32 = 26
|
|
S_BITSET1_B64 = 27
|
|
S_GETPC_B64 = 28
|
|
S_SETPC_B64 = 29
|
|
S_SWAPPC_B64 = 30
|
|
S_RFE_B64 = 31
|
|
S_AND_SAVEEXEC_B64 = 32
|
|
S_OR_SAVEEXEC_B64 = 33
|
|
S_XOR_SAVEEXEC_B64 = 34
|
|
S_ANDN2_SAVEEXEC_B64 = 35
|
|
S_ORN2_SAVEEXEC_B64 = 36
|
|
S_NAND_SAVEEXEC_B64 = 37
|
|
S_NOR_SAVEEXEC_B64 = 38
|
|
S_XNOR_SAVEEXEC_B64 = 39
|
|
S_QUADMASK_B32 = 40
|
|
S_QUADMASK_B64 = 41
|
|
S_MOVRELS_B32 = 42
|
|
S_MOVRELS_B64 = 43
|
|
S_MOVRELD_B32 = 44
|
|
S_MOVRELD_B64 = 45
|
|
S_CBRANCH_JOIN = 46
|
|
S_ABS_I32 = 48
|
|
S_SET_GPR_IDX_IDX = 50
|
|
S_ANDN1_SAVEEXEC_B64 = 51
|
|
S_ORN1_SAVEEXEC_B64 = 52
|
|
S_ANDN1_WREXEC_B64 = 53
|
|
S_ANDN2_WREXEC_B64 = 54
|
|
S_BITREPLICATE_B64_B32 = 55
|
|
|
|
class SOP2Op(IntEnum):
|
|
S_ADD_U32 = 0
|
|
S_SUB_U32 = 1
|
|
S_ADD_I32 = 2
|
|
S_SUB_I32 = 3
|
|
S_ADDC_U32 = 4
|
|
S_SUBB_U32 = 5
|
|
S_MIN_I32 = 6
|
|
S_MIN_U32 = 7
|
|
S_MAX_I32 = 8
|
|
S_MAX_U32 = 9
|
|
S_CSELECT_B32 = 10
|
|
S_CSELECT_B64 = 11
|
|
S_AND_B32 = 12
|
|
S_AND_B64 = 13
|
|
S_OR_B32 = 14
|
|
S_OR_B64 = 15
|
|
S_XOR_B32 = 16
|
|
S_XOR_B64 = 17
|
|
S_ANDN2_B32 = 18
|
|
S_ANDN2_B64 = 19
|
|
S_ORN2_B32 = 20
|
|
S_ORN2_B64 = 21
|
|
S_NAND_B32 = 22
|
|
S_NAND_B64 = 23
|
|
S_NOR_B32 = 24
|
|
S_NOR_B64 = 25
|
|
S_XNOR_B32 = 26
|
|
S_XNOR_B64 = 27
|
|
S_LSHL_B32 = 28
|
|
S_LSHL_B64 = 29
|
|
S_LSHR_B32 = 30
|
|
S_LSHR_B64 = 31
|
|
S_ASHR_I32 = 32
|
|
S_ASHR_I64 = 33
|
|
S_BFM_B32 = 34
|
|
S_BFM_B64 = 35
|
|
S_MUL_I32 = 36
|
|
S_BFE_U32 = 37
|
|
S_BFE_I32 = 38
|
|
S_BFE_U64 = 39
|
|
S_BFE_I64 = 40
|
|
S_CBRANCH_G_FORK = 41
|
|
S_ABSDIFF_I32 = 42
|
|
S_MUL_HI_U32 = 44
|
|
S_MUL_HI_I32 = 45
|
|
S_LSHL1_ADD_U32 = 46
|
|
S_LSHL2_ADD_U32 = 47
|
|
S_LSHL3_ADD_U32 = 48
|
|
S_LSHL4_ADD_U32 = 49
|
|
S_PACK_LL_B32_B16 = 50
|
|
S_PACK_LH_B32_B16 = 51
|
|
S_PACK_HH_B32_B16 = 52
|
|
|
|
class SOPCOp(IntEnum):
|
|
S_CMP_EQ_I32 = 0
|
|
S_CMP_LG_I32 = 1
|
|
S_CMP_GT_I32 = 2
|
|
S_CMP_GE_I32 = 3
|
|
S_CMP_LT_I32 = 4
|
|
S_CMP_LE_I32 = 5
|
|
S_CMP_EQ_U32 = 6
|
|
S_CMP_LG_U32 = 7
|
|
S_CMP_GT_U32 = 8
|
|
S_CMP_GE_U32 = 9
|
|
S_CMP_LT_U32 = 10
|
|
S_CMP_LE_U32 = 11
|
|
S_BITCMP0_B32 = 12
|
|
S_BITCMP1_B32 = 13
|
|
S_BITCMP0_B64 = 14
|
|
S_BITCMP1_B64 = 15
|
|
S_SETVSKIP = 16
|
|
S_SET_GPR_IDX_ON = 17
|
|
S_CMP_EQ_U64 = 18
|
|
S_CMP_LG_U64 = 19
|
|
|
|
class SOPKOp(IntEnum):
|
|
S_MOVK_I32 = 0
|
|
S_CMOVK_I32 = 1
|
|
S_CMPK_EQ_I32 = 2
|
|
S_CMPK_LG_I32 = 3
|
|
S_CMPK_GT_I32 = 4
|
|
S_CMPK_GE_I32 = 5
|
|
S_CMPK_LT_I32 = 6
|
|
S_CMPK_LE_I32 = 7
|
|
S_CMPK_EQ_U32 = 8
|
|
S_CMPK_LG_U32 = 9
|
|
S_CMPK_GT_U32 = 10
|
|
S_CMPK_GE_U32 = 11
|
|
S_CMPK_LT_U32 = 12
|
|
S_CMPK_LE_U32 = 13
|
|
S_ADDK_I32 = 14
|
|
S_MULK_I32 = 15
|
|
S_CBRANCH_I_FORK = 16
|
|
S_GETREG_B32 = 17
|
|
S_SETREG_B32 = 18
|
|
S_SETREG_IMM32_B32 = 20
|
|
S_CALL_B64 = 21
|
|
|
|
class SOPPOp(IntEnum):
|
|
S_NOP = 0
|
|
S_ENDPGM = 1
|
|
S_BRANCH = 2
|
|
S_WAKEUP = 3
|
|
S_CBRANCH_SCC0 = 4
|
|
S_CBRANCH_SCC1 = 5
|
|
S_CBRANCH_VCCZ = 6
|
|
S_CBRANCH_VCCNZ = 7
|
|
S_CBRANCH_EXECZ = 8
|
|
S_CBRANCH_EXECNZ = 9
|
|
S_BARRIER = 10
|
|
S_SETKILL = 11
|
|
S_WAITCNT = 12
|
|
S_SETHALT = 13
|
|
S_SLEEP = 14
|
|
S_SETPRIO = 15
|
|
S_SENDMSG = 16
|
|
S_SENDMSGHALT = 17
|
|
S_TRAP = 18
|
|
S_ICACHE_INV = 19
|
|
S_INCPERFLEVEL = 20
|
|
S_DECPERFLEVEL = 21
|
|
S_TTRACEDATA = 22
|
|
S_CBRANCH_CDBGSYS = 23
|
|
S_CBRANCH_CDBGUSER = 24
|
|
S_CBRANCH_CDBGSYS_OR_USER = 25
|
|
S_CBRANCH_CDBGSYS_AND_USER = 26
|
|
S_ENDPGM_SAVED = 27
|
|
S_SET_GPR_IDX_OFF = 28
|
|
S_SET_GPR_IDX_MODE = 29
|
|
|
|
class VOP1Op(IntEnum):
|
|
V_NOP = 0
|
|
V_MOV_B32 = 1
|
|
V_READFIRSTLANE_B32 = 2
|
|
V_CVT_I32_F64 = 3
|
|
V_CVT_F64_I32 = 4
|
|
V_CVT_F32_I32 = 5
|
|
V_CVT_F32_U32 = 6
|
|
V_CVT_U32_F32 = 7
|
|
V_CVT_I32_F32 = 8
|
|
V_CVT_F16_F32 = 10
|
|
V_CVT_F32_F16 = 11
|
|
V_CVT_RPI_I32_F32 = 12
|
|
V_CVT_FLR_I32_F32 = 13
|
|
V_CVT_OFF_F32_I4 = 14
|
|
V_CVT_F32_F64 = 15
|
|
V_CVT_F64_F32 = 16
|
|
V_CVT_F32_UBYTE0 = 17
|
|
V_CVT_F32_UBYTE1 = 18
|
|
V_CVT_F32_UBYTE2 = 19
|
|
V_CVT_F32_UBYTE3 = 20
|
|
V_CVT_U32_F64 = 21
|
|
V_CVT_F64_U32 = 22
|
|
V_TRUNC_F64 = 23
|
|
V_CEIL_F64 = 24
|
|
V_RNDNE_F64 = 25
|
|
V_FLOOR_F64 = 26
|
|
V_FRACT_F32 = 27
|
|
V_TRUNC_F32 = 28
|
|
V_CEIL_F32 = 29
|
|
V_RNDNE_F32 = 30
|
|
V_FLOOR_F32 = 31
|
|
V_EXP_F32 = 32
|
|
V_LOG_F32 = 33
|
|
V_RCP_F32 = 34
|
|
V_RCP_IFLAG_F32 = 35
|
|
V_RSQ_F32 = 36
|
|
V_RCP_F64 = 37
|
|
V_RSQ_F64 = 38
|
|
V_SQRT_F32 = 39
|
|
V_SQRT_F64 = 40
|
|
V_SIN_F32 = 41
|
|
V_COS_F32 = 42
|
|
V_NOT_B32 = 43
|
|
V_BFREV_B32 = 44
|
|
V_FFBH_U32 = 45
|
|
V_FFBL_B32 = 46
|
|
V_FFBH_I32 = 47
|
|
V_FREXP_EXP_I32_F64 = 48
|
|
V_FREXP_MANT_F64 = 49
|
|
V_FRACT_F64 = 50
|
|
V_FREXP_EXP_I32_F32 = 51
|
|
V_FREXP_MANT_F32 = 52
|
|
V_CLREXCP = 53
|
|
V_MOV_B64 = 56
|
|
V_CVT_F16_U16 = 57
|
|
V_CVT_F16_I16 = 58
|
|
V_CVT_U16_F16 = 59
|
|
V_CVT_I16_F16 = 60
|
|
V_RCP_F16 = 61
|
|
V_SQRT_F16 = 62
|
|
V_RSQ_F16 = 63
|
|
V_LOG_F16 = 64
|
|
V_EXP_F16 = 65
|
|
V_FREXP_MANT_F16 = 66
|
|
V_FREXP_EXP_I16_F16 = 67
|
|
V_FLOOR_F16 = 68
|
|
V_CEIL_F16 = 69
|
|
V_TRUNC_F16 = 70
|
|
V_RNDNE_F16 = 71
|
|
V_FRACT_F16 = 72
|
|
V_SIN_F16 = 73
|
|
V_COS_F16 = 74
|
|
V_CVT_NORM_I16_F16 = 77
|
|
V_CVT_NORM_U16_F16 = 78
|
|
V_SAT_PK_U8_I16 = 79
|
|
V_SWAP_B32 = 81
|
|
V_ACCVGPR_MOV_B32 = 82
|
|
V_CVT_F32_FP8 = 84
|
|
V_CVT_F32_BF8 = 85
|
|
V_CVT_PK_F32_FP8 = 86
|
|
V_CVT_PK_F32_BF8 = 87
|
|
V_PRNG_B32 = 88
|
|
V_PERMLANE16_SWAP_B32 = 89
|
|
V_PERMLANE32_SWAP_B32 = 90
|
|
V_CVT_F32_BF16 = 91
|
|
|
|
class VOP2Op(IntEnum):
|
|
V_CNDMASK_B32 = 0
|
|
V_ADD_F32 = 1
|
|
V_SUB_F32 = 2
|
|
V_SUBREV_F32 = 3
|
|
V_FMAC_F64 = 4
|
|
V_MUL_F32 = 5
|
|
V_MUL_I32_I24 = 6
|
|
V_MUL_HI_I32_I24 = 7
|
|
V_MUL_U32_U24 = 8
|
|
V_MUL_HI_U32_U24 = 9
|
|
V_MIN_F32 = 10
|
|
V_MAX_F32 = 11
|
|
V_MIN_I32 = 12
|
|
V_MAX_I32 = 13
|
|
V_MIN_U32 = 14
|
|
V_MAX_U32 = 15
|
|
V_LSHRREV_B32 = 16
|
|
V_ASHRREV_I32 = 17
|
|
V_LSHLREV_B32 = 18
|
|
V_AND_B32 = 19
|
|
V_OR_B32 = 20
|
|
V_XOR_B32 = 21
|
|
V_DOT2C_F32_BF16 = 22
|
|
V_FMAMK_F32 = 23
|
|
V_FMAAK_F32 = 24
|
|
V_ADD_CO_U32 = 25
|
|
V_SUB_CO_U32 = 26
|
|
V_SUBREV_CO_U32 = 27
|
|
V_ADDC_CO_U32 = 28
|
|
V_SUBB_CO_U32 = 29
|
|
V_SUBBREV_CO_U32 = 30
|
|
V_ADD_F16 = 31
|
|
V_SUB_F16 = 32
|
|
V_SUBREV_F16 = 33
|
|
V_MUL_F16 = 34
|
|
V_MAC_F16 = 35
|
|
V_MADMK_F16 = 36
|
|
V_MADAK_F16 = 37
|
|
V_ADD_U16 = 38
|
|
V_SUB_U16 = 39
|
|
V_SUBREV_U16 = 40
|
|
V_MUL_LO_U16 = 41
|
|
V_LSHLREV_B16 = 42
|
|
V_LSHRREV_B16 = 43
|
|
V_ASHRREV_I16 = 44
|
|
V_MAX_F16 = 45
|
|
V_MIN_F16 = 46
|
|
V_MAX_U16 = 47
|
|
V_MAX_I16 = 48
|
|
V_MIN_U16 = 49
|
|
V_MIN_I16 = 50
|
|
V_LDEXP_F16 = 51
|
|
V_ADD_U32 = 52
|
|
V_SUB_U32 = 53
|
|
V_SUBREV_U32 = 54
|
|
V_DOT2C_F32_F16 = 55
|
|
V_DOT2C_I32_I16 = 56
|
|
V_DOT4C_I32_I8 = 57
|
|
V_DOT8C_I32_I4 = 58
|
|
V_FMAC_F32 = 59
|
|
V_PK_FMAC_F16 = 60
|
|
V_XNOR_B32 = 61
|
|
|
|
class VOP3AOp(IntEnum):
|
|
V_CMP_CLASS_F32 = 16
|
|
V_CMPX_CLASS_F32 = 17
|
|
V_CMP_CLASS_F64 = 18
|
|
V_CMPX_CLASS_F64 = 19
|
|
V_CMP_CLASS_F16 = 20
|
|
V_CMPX_CLASS_F16 = 21
|
|
V_CMP_F_F16 = 32
|
|
V_CMP_LT_F16 = 33
|
|
V_CMP_EQ_F16 = 34
|
|
V_CMP_LE_F16 = 35
|
|
V_CMP_GT_F16 = 36
|
|
V_CMP_LG_F16 = 37
|
|
V_CMP_GE_F16 = 38
|
|
V_CMP_O_F16 = 39
|
|
V_CMP_U_F16 = 40
|
|
V_CMP_NGE_F16 = 41
|
|
V_CMP_NLG_F16 = 42
|
|
V_CMP_NGT_F16 = 43
|
|
V_CMP_NLE_F16 = 44
|
|
V_CMP_NEQ_F16 = 45
|
|
V_CMP_NLT_F16 = 46
|
|
V_CMP_TRU_F16 = 47
|
|
V_CMPX_F_F16 = 48
|
|
V_CMPX_LT_F16 = 49
|
|
V_CMPX_EQ_F16 = 50
|
|
V_CMPX_LE_F16 = 51
|
|
V_CMPX_GT_F16 = 52
|
|
V_CMPX_LG_F16 = 53
|
|
V_CMPX_GE_F16 = 54
|
|
V_CMPX_O_F16 = 55
|
|
V_CMPX_U_F16 = 56
|
|
V_CMPX_NGE_F16 = 57
|
|
V_CMPX_NLG_F16 = 58
|
|
V_CMPX_NGT_F16 = 59
|
|
V_CMPX_NLE_F16 = 60
|
|
V_CMPX_NEQ_F16 = 61
|
|
V_CMPX_NLT_F16 = 62
|
|
V_CMPX_TRU_F16 = 63
|
|
V_CMP_F_F32 = 64
|
|
V_CMP_LT_F32 = 65
|
|
V_CMP_EQ_F32 = 66
|
|
V_CMP_LE_F32 = 67
|
|
V_CMP_GT_F32 = 68
|
|
V_CMP_LG_F32 = 69
|
|
V_CMP_GE_F32 = 70
|
|
V_CMP_O_F32 = 71
|
|
V_CMP_U_F32 = 72
|
|
V_CMP_NGE_F32 = 73
|
|
V_CMP_NLG_F32 = 74
|
|
V_CMP_NGT_F32 = 75
|
|
V_CMP_NLE_F32 = 76
|
|
V_CMP_NEQ_F32 = 77
|
|
V_CMP_NLT_F32 = 78
|
|
V_CMP_TRU_F32 = 79
|
|
V_CMPX_F_F32 = 80
|
|
V_CMPX_LT_F32 = 81
|
|
V_CMPX_EQ_F32 = 82
|
|
V_CMPX_LE_F32 = 83
|
|
V_CMPX_GT_F32 = 84
|
|
V_CMPX_LG_F32 = 85
|
|
V_CMPX_GE_F32 = 86
|
|
V_CMPX_O_F32 = 87
|
|
V_CMPX_U_F32 = 88
|
|
V_CMPX_NGE_F32 = 89
|
|
V_CMPX_NLG_F32 = 90
|
|
V_CMPX_NGT_F32 = 91
|
|
V_CMPX_NLE_F32 = 92
|
|
V_CMPX_NEQ_F32 = 93
|
|
V_CMPX_NLT_F32 = 94
|
|
V_CMPX_TRU_F32 = 95
|
|
V_CMP_F_F64 = 96
|
|
V_CMP_LT_F64 = 97
|
|
V_CMP_EQ_F64 = 98
|
|
V_CMP_LE_F64 = 99
|
|
V_CMP_GT_F64 = 100
|
|
V_CMP_LG_F64 = 101
|
|
V_CMP_GE_F64 = 102
|
|
V_CMP_O_F64 = 103
|
|
V_CMP_U_F64 = 104
|
|
V_CMP_NGE_F64 = 105
|
|
V_CMP_NLG_F64 = 106
|
|
V_CMP_NGT_F64 = 107
|
|
V_CMP_NLE_F64 = 108
|
|
V_CMP_NEQ_F64 = 109
|
|
V_CMP_NLT_F64 = 110
|
|
V_CMP_TRU_F64 = 111
|
|
V_CMPX_F_F64 = 112
|
|
V_CMPX_LT_F64 = 113
|
|
V_CMPX_EQ_F64 = 114
|
|
V_CMPX_LE_F64 = 115
|
|
V_CMPX_GT_F64 = 116
|
|
V_CMPX_LG_F64 = 117
|
|
V_CMPX_GE_F64 = 118
|
|
V_CMPX_O_F64 = 119
|
|
V_CMPX_U_F64 = 120
|
|
V_CMPX_NGE_F64 = 121
|
|
V_CMPX_NLG_F64 = 122
|
|
V_CMPX_NGT_F64 = 123
|
|
V_CMPX_NLE_F64 = 124
|
|
V_CMPX_NEQ_F64 = 125
|
|
V_CMPX_NLT_F64 = 126
|
|
V_CMPX_TRU_F64 = 127
|
|
V_CMP_F_I16 = 160
|
|
V_CMP_LT_I16 = 161
|
|
V_CMP_EQ_I16 = 162
|
|
V_CMP_LE_I16 = 163
|
|
V_CMP_GT_I16 = 164
|
|
V_CMP_NE_I16 = 165
|
|
V_CMP_GE_I16 = 166
|
|
V_CMP_T_I16 = 167
|
|
V_CMP_F_U16 = 168
|
|
V_CMP_LT_U16 = 169
|
|
V_CMP_EQ_U16 = 170
|
|
V_CMP_LE_U16 = 171
|
|
V_CMP_GT_U16 = 172
|
|
V_CMP_NE_U16 = 173
|
|
V_CMP_GE_U16 = 174
|
|
V_CMP_T_U16 = 175
|
|
V_CMPX_F_I16 = 176
|
|
V_CMPX_LT_I16 = 177
|
|
V_CMPX_EQ_I16 = 178
|
|
V_CMPX_LE_I16 = 179
|
|
V_CMPX_GT_I16 = 180
|
|
V_CMPX_NE_I16 = 181
|
|
V_CMPX_GE_I16 = 182
|
|
V_CMPX_T_I16 = 183
|
|
V_CMPX_F_U16 = 184
|
|
V_CMPX_LT_U16 = 185
|
|
V_CMPX_EQ_U16 = 186
|
|
V_CMPX_LE_U16 = 187
|
|
V_CMPX_GT_U16 = 188
|
|
V_CMPX_NE_U16 = 189
|
|
V_CMPX_GE_U16 = 190
|
|
V_CMPX_T_U16 = 191
|
|
V_CMP_F_I32 = 192
|
|
V_CMP_LT_I32 = 193
|
|
V_CMP_EQ_I32 = 194
|
|
V_CMP_LE_I32 = 195
|
|
V_CMP_GT_I32 = 196
|
|
V_CMP_NE_I32 = 197
|
|
V_CMP_GE_I32 = 198
|
|
V_CMP_T_I32 = 199
|
|
V_CMP_F_U32 = 200
|
|
V_CMP_LT_U32 = 201
|
|
V_CMP_EQ_U32 = 202
|
|
V_CMP_LE_U32 = 203
|
|
V_CMP_GT_U32 = 204
|
|
V_CMP_NE_U32 = 205
|
|
V_CMP_GE_U32 = 206
|
|
V_CMP_T_U32 = 207
|
|
V_CMPX_F_I32 = 208
|
|
V_CMPX_LT_I32 = 209
|
|
V_CMPX_EQ_I32 = 210
|
|
V_CMPX_LE_I32 = 211
|
|
V_CMPX_GT_I32 = 212
|
|
V_CMPX_NE_I32 = 213
|
|
V_CMPX_GE_I32 = 214
|
|
V_CMPX_T_I32 = 215
|
|
V_CMPX_F_U32 = 216
|
|
V_CMPX_LT_U32 = 217
|
|
V_CMPX_EQ_U32 = 218
|
|
V_CMPX_LE_U32 = 219
|
|
V_CMPX_GT_U32 = 220
|
|
V_CMPX_NE_U32 = 221
|
|
V_CMPX_GE_U32 = 222
|
|
V_CMPX_T_U32 = 223
|
|
V_CMP_F_I64 = 224
|
|
V_CMP_LT_I64 = 225
|
|
V_CMP_EQ_I64 = 226
|
|
V_CMP_LE_I64 = 227
|
|
V_CMP_GT_I64 = 228
|
|
V_CMP_NE_I64 = 229
|
|
V_CMP_GE_I64 = 230
|
|
V_CMP_T_I64 = 231
|
|
V_CMP_F_U64 = 232
|
|
V_CMP_LT_U64 = 233
|
|
V_CMP_EQ_U64 = 234
|
|
V_CMP_LE_U64 = 235
|
|
V_CMP_GT_U64 = 236
|
|
V_CMP_NE_U64 = 237
|
|
V_CMP_GE_U64 = 238
|
|
V_CMP_T_U64 = 239
|
|
V_CMPX_F_I64 = 240
|
|
V_CMPX_LT_I64 = 241
|
|
V_CMPX_EQ_I64 = 242
|
|
V_CMPX_LE_I64 = 243
|
|
V_CMPX_GT_I64 = 244
|
|
V_CMPX_NE_I64 = 245
|
|
V_CMPX_GE_I64 = 246
|
|
V_CMPX_T_I64 = 247
|
|
V_CMPX_F_U64 = 248
|
|
V_CMPX_LT_U64 = 249
|
|
V_CMPX_EQ_U64 = 250
|
|
V_CMPX_LE_U64 = 251
|
|
V_CMPX_GT_U64 = 252
|
|
V_CMPX_NE_U64 = 253
|
|
V_CMPX_GE_U64 = 254
|
|
V_CMPX_T_U64 = 255
|
|
V_CNDMASK_B32 = 256
|
|
V_ADD_F32 = 257
|
|
V_SUB_F32 = 258
|
|
V_SUBREV_F32 = 259
|
|
V_FMAC_F64 = 260
|
|
V_MUL_F32 = 261
|
|
V_MUL_I32_I24 = 262
|
|
V_MUL_HI_I32_I24 = 263
|
|
V_MUL_U32_U24 = 264
|
|
V_MUL_HI_U32_U24 = 265
|
|
V_MIN_F32 = 266
|
|
V_MAX_F32 = 267
|
|
V_MIN_I32 = 268
|
|
V_MAX_I32 = 269
|
|
V_MIN_U32 = 270
|
|
V_MAX_U32 = 271
|
|
V_LSHRREV_B32 = 272
|
|
V_ASHRREV_I32 = 273
|
|
V_LSHLREV_B32 = 274
|
|
V_AND_B32 = 275
|
|
V_OR_B32 = 276
|
|
V_XOR_B32 = 277
|
|
V_DOT2C_F32_BF16 = 278
|
|
V_ADD_F16 = 287
|
|
V_SUB_F16 = 288
|
|
V_SUBREV_F16 = 289
|
|
V_MUL_F16 = 290
|
|
V_MAC_F16 = 291
|
|
V_ADD_U16 = 294
|
|
V_SUB_U16 = 295
|
|
V_SUBREV_U16 = 296
|
|
V_MUL_LO_U16 = 297
|
|
V_LSHLREV_B16 = 298
|
|
V_LSHRREV_B16 = 299
|
|
V_ASHRREV_I16 = 300
|
|
V_MAX_F16 = 301
|
|
V_MIN_F16 = 302
|
|
V_MAX_U16 = 303
|
|
V_MAX_I16 = 304
|
|
V_MIN_U16 = 305
|
|
V_MIN_I16 = 306
|
|
V_LDEXP_F16 = 307
|
|
V_ADD_U32 = 308
|
|
V_SUB_U32 = 309
|
|
V_SUBREV_U32 = 310
|
|
V_DOT2C_F32_F16 = 311
|
|
V_DOT2C_I32_I16 = 312
|
|
V_DOT4C_I32_I8 = 313
|
|
V_DOT8C_I32_I4 = 314
|
|
V_FMAC_F32 = 315
|
|
V_PK_FMAC_F16 = 316
|
|
V_XNOR_B32 = 317
|
|
V_NOP = 384
|
|
V_MOV_B32 = 385
|
|
V_READFIRSTLANE_B32 = 386
|
|
V_CVT_I32_F64 = 387
|
|
V_CVT_F64_I32 = 388
|
|
V_CVT_F32_I32 = 389
|
|
V_CVT_F32_U32 = 390
|
|
V_CVT_U32_F32 = 391
|
|
V_CVT_I32_F32 = 392
|
|
V_CVT_F16_F32 = 394
|
|
V_CVT_F32_F16 = 395
|
|
V_CVT_RPI_I32_F32 = 396
|
|
V_CVT_FLR_I32_F32 = 397
|
|
V_CVT_OFF_F32_I4 = 398
|
|
V_CVT_F32_F64 = 399
|
|
V_CVT_F64_F32 = 400
|
|
V_CVT_F32_UBYTE0 = 401
|
|
V_CVT_F32_UBYTE1 = 402
|
|
V_CVT_F32_UBYTE2 = 403
|
|
V_CVT_F32_UBYTE3 = 404
|
|
V_CVT_U32_F64 = 405
|
|
V_CVT_F64_U32 = 406
|
|
V_TRUNC_F64 = 407
|
|
V_CEIL_F64 = 408
|
|
V_RNDNE_F64 = 409
|
|
V_FLOOR_F64 = 410
|
|
V_FRACT_F32 = 411
|
|
V_TRUNC_F32 = 412
|
|
V_CEIL_F32 = 413
|
|
V_RNDNE_F32 = 414
|
|
V_FLOOR_F32 = 415
|
|
V_EXP_F32 = 416
|
|
V_LOG_F32 = 417
|
|
V_RCP_F32 = 418
|
|
V_RCP_IFLAG_F32 = 419
|
|
V_RSQ_F32 = 420
|
|
V_RCP_F64 = 421
|
|
V_RSQ_F64 = 422
|
|
V_SQRT_F32 = 423
|
|
V_SQRT_F64 = 424
|
|
V_SIN_F32 = 425
|
|
V_COS_F32 = 426
|
|
V_NOT_B32 = 427
|
|
V_BFREV_B32 = 428
|
|
V_FFBH_U32 = 429
|
|
V_FFBL_B32 = 430
|
|
V_FFBH_I32 = 431
|
|
V_FREXP_EXP_I32_F64 = 432
|
|
V_FREXP_MANT_F64 = 433
|
|
V_FRACT_F64 = 434
|
|
V_FREXP_EXP_I32_F32 = 435
|
|
V_FREXP_MANT_F32 = 436
|
|
V_CLREXCP = 437
|
|
V_MOV_B64 = 440
|
|
V_CVT_F16_U16 = 441
|
|
V_CVT_F16_I16 = 442
|
|
V_CVT_U16_F16 = 443
|
|
V_CVT_I16_F16 = 444
|
|
V_RCP_F16 = 445
|
|
V_SQRT_F16 = 446
|
|
V_RSQ_F16 = 447
|
|
V_LOG_F16 = 448
|
|
V_EXP_F16 = 449
|
|
V_MAD_I32_I24 = 450
|
|
V_MAD_U32_U24 = 451
|
|
V_CUBEID_F32 = 452
|
|
V_CUBESC_F32 = 453
|
|
V_CUBETC_F32 = 454
|
|
V_CUBEMA_F32 = 455
|
|
V_BFE_U32 = 456
|
|
V_BFE_I32 = 457
|
|
V_BFI_B32 = 458
|
|
V_FMA_F32 = 459
|
|
V_FMA_F64 = 460
|
|
V_LERP_U8 = 461
|
|
V_ALIGNBIT_B32 = 462
|
|
V_ALIGNBYTE_B32 = 463
|
|
V_MIN3_F32 = 464
|
|
V_MIN3_I32 = 465
|
|
V_MIN3_U32 = 466
|
|
V_MAX3_F32 = 467
|
|
V_MAX3_I32 = 468
|
|
V_MAX3_U32 = 469
|
|
V_MED3_F32 = 470
|
|
V_MED3_I32 = 471
|
|
V_MED3_U32 = 472
|
|
V_SAD_U8 = 473
|
|
V_SAD_HI_U8 = 474
|
|
V_SAD_U16 = 475
|
|
V_SAD_U32 = 476
|
|
V_CVT_PK_U8_F32 = 477
|
|
V_DIV_FIXUP_F32 = 478
|
|
V_DIV_FIXUP_F64 = 479
|
|
V_DIV_FMAS_F32 = 482
|
|
V_DIV_FMAS_F64 = 483
|
|
V_MSAD_U8 = 484
|
|
V_QSAD_PK_U16_U8 = 485
|
|
V_MQSAD_PK_U16_U8 = 486
|
|
V_MQSAD_U32_U8 = 487
|
|
V_MAD_LEGACY_F16 = 490
|
|
V_MAD_LEGACY_U16 = 491
|
|
V_MAD_LEGACY_I16 = 492
|
|
V_PERM_B32 = 493
|
|
V_FMA_LEGACY_F16 = 494
|
|
V_DIV_FIXUP_LEGACY_F16 = 495
|
|
V_CVT_PKACCUM_U8_F32 = 496
|
|
V_MAD_U32_U16 = 497
|
|
V_MAD_I32_I16 = 498
|
|
V_XAD_U32 = 499
|
|
V_MIN3_F16 = 500
|
|
V_MIN3_I16 = 501
|
|
V_MIN3_U16 = 502
|
|
V_MAX3_F16 = 503
|
|
V_MAX3_I16 = 504
|
|
V_MAX3_U16 = 505
|
|
V_MED3_F16 = 506
|
|
V_MED3_I16 = 507
|
|
V_MED3_U16 = 508
|
|
V_LSHL_ADD_U32 = 509
|
|
V_ADD_LSHL_U32 = 510
|
|
V_ADD3_U32 = 511
|
|
V_LSHL_OR_B32 = 512
|
|
V_AND_OR_B32 = 513
|
|
V_OR3_B32 = 514
|
|
V_MAD_F16 = 515
|
|
V_MAD_U16 = 516
|
|
V_MAD_I16 = 517
|
|
V_FMA_F16 = 518
|
|
V_DIV_FIXUP_F16 = 519
|
|
V_LSHL_ADD_U64 = 520
|
|
V_BITOP3_B16 = 563
|
|
V_BITOP3_B32 = 564
|
|
V_CVT_SCALEF32_PK_FP8_F32 = 565
|
|
V_CVT_SCALEF32_PK_BF8_F32 = 566
|
|
V_CVT_SCALEF32_SR_FP8_F32 = 567
|
|
V_CVT_SCALEF32_SR_BF8_F32 = 568
|
|
V_CVT_SCALEF32_PK_F32_FP8 = 569
|
|
V_CVT_SCALEF32_PK_F32_BF8 = 570
|
|
V_CVT_SCALEF32_F32_FP8 = 571
|
|
V_CVT_SCALEF32_F32_BF8 = 572
|
|
V_CVT_SCALEF32_PK_FP4_F32 = 573
|
|
V_CVT_SCALEF32_SR_PK_FP4_F32 = 574
|
|
V_CVT_SCALEF32_PK_F32_FP4 = 575
|
|
V_CVT_SCALEF32_PK_FP8_F16 = 576
|
|
V_CVT_SCALEF32_PK_BF8_F16 = 577
|
|
V_CVT_SCALEF32_SR_FP8_F16 = 578
|
|
V_CVT_SCALEF32_SR_BF8_F16 = 579
|
|
V_CVT_SCALEF32_PK_FP8_BF16 = 580
|
|
V_CVT_SCALEF32_PK_BF8_BF16 = 581
|
|
V_CVT_SCALEF32_SR_FP8_BF16 = 582
|
|
V_CVT_SCALEF32_SR_BF8_BF16 = 583
|
|
V_CVT_SCALEF32_PK_F16_FP8 = 584
|
|
V_CVT_SCALEF32_PK_F16_BF8 = 585
|
|
V_CVT_SCALEF32_F16_FP8 = 586
|
|
V_CVT_SCALEF32_F16_BF8 = 587
|
|
V_CVT_SCALEF32_PK_FP4_F16 = 588
|
|
V_CVT_SCALEF32_PK_FP4_BF16 = 589
|
|
V_CVT_SCALEF32_SR_PK_FP4_F16 = 590
|
|
V_CVT_SCALEF32_SR_PK_FP4_BF16 = 591
|
|
V_CVT_SCALEF32_PK_F16_FP4 = 592
|
|
V_CVT_SCALEF32_PK_BF16_FP4 = 593
|
|
V_CVT_SCALEF32_2XPK16_FP6_F32 = 594
|
|
V_CVT_SCALEF32_2XPK16_BF6_F32 = 595
|
|
V_CVT_SCALEF32_SR_PK32_FP6_F32 = 596
|
|
V_CVT_SCALEF32_SR_PK32_BF6_F32 = 597
|
|
V_CVT_SCALEF32_PK32_F32_FP6 = 598
|
|
V_CVT_SCALEF32_PK32_F32_BF6 = 599
|
|
V_CVT_SCALEF32_PK32_FP6_F16 = 600
|
|
V_CVT_SCALEF32_PK32_FP6_BF16 = 601
|
|
V_CVT_SCALEF32_PK32_BF6_F16 = 602
|
|
V_CVT_SCALEF32_PK32_BF6_BF16 = 603
|
|
V_CVT_SCALEF32_SR_PK32_FP6_F16 = 604
|
|
V_CVT_SCALEF32_SR_PK32_FP6_BF16 = 605
|
|
V_CVT_SCALEF32_SR_PK32_BF6_F16 = 606
|
|
V_CVT_SCALEF32_SR_PK32_BF6_BF16 = 607
|
|
V_CVT_SCALEF32_PK32_F16_FP6 = 608
|
|
V_CVT_SCALEF32_PK32_BF16_FP6 = 609
|
|
V_CVT_SCALEF32_PK32_F16_BF6 = 610
|
|
V_CVT_SCALEF32_PK32_BF16_BF6 = 611
|
|
V_ASHR_PK_I8_I32 = 613
|
|
V_ASHR_PK_U8_I32 = 614
|
|
V_CVT_PK_F16_F32 = 615
|
|
V_CVT_PK_BF16_F32 = 616
|
|
V_CVT_SCALEF32_PK_BF16_FP8 = 617
|
|
V_CVT_SCALEF32_PK_BF16_BF8 = 618
|
|
V_ADD_F64 = 640
|
|
V_MUL_F64 = 641
|
|
V_MIN_F64 = 642
|
|
V_MAX_F64 = 643
|
|
V_LDEXP_F64 = 644
|
|
V_MUL_LO_U32 = 645
|
|
V_MUL_HI_U32 = 646
|
|
V_MUL_HI_I32 = 647
|
|
V_LDEXP_F32 = 648
|
|
V_READLANE_B32 = 649
|
|
V_WRITELANE_B32 = 650
|
|
V_BCNT_U32_B32 = 651
|
|
V_MBCNT_LO_U32_B32 = 652
|
|
V_MBCNT_HI_U32_B32 = 653
|
|
V_LSHLREV_B64 = 655
|
|
V_LSHRREV_B64 = 656
|
|
V_ASHRREV_I64 = 657
|
|
V_TRIG_PREOP_F64 = 658
|
|
V_BFM_B32 = 659
|
|
V_CVT_PKNORM_I16_F32 = 660
|
|
V_CVT_PKNORM_U16_F32 = 661
|
|
V_CVT_PKRTZ_F16_F32 = 662
|
|
V_CVT_PK_U16_U32 = 663
|
|
V_CVT_PK_I16_I32 = 664
|
|
V_CVT_PKNORM_I16_F16 = 665
|
|
V_CVT_PKNORM_U16_F16 = 666
|
|
V_ADD_I32 = 668
|
|
V_SUB_I32 = 669
|
|
V_ADD_I16 = 670
|
|
V_SUB_I16 = 671
|
|
V_PACK_B32_F16 = 672
|
|
V_MUL_LEGACY_F32 = 673
|
|
V_CVT_PK_FP8_F32 = 674
|
|
V_CVT_PK_BF8_F32 = 675
|
|
V_CVT_SR_FP8_F32 = 676
|
|
V_CVT_SR_BF8_F32 = 677
|
|
V_CVT_SR_F16_F32 = 678
|
|
V_CVT_SR_BF16_F32 = 679
|
|
V_MINIMUM3_F32 = 680
|
|
V_MAXIMUM3_F32 = 681
|
|
|
|
class VOP3BOp(IntEnum):
|
|
V_ADD_CO_U32 = 281
|
|
V_SUB_CO_U32 = 282
|
|
V_SUBREV_CO_U32 = 283
|
|
V_ADDC_CO_U32 = 284
|
|
V_SUBB_CO_U32 = 285
|
|
V_SUBBREV_CO_U32 = 286
|
|
V_DIV_SCALE_F32 = 480
|
|
V_DIV_SCALE_F64 = 481
|
|
V_MAD_U64_U32 = 488
|
|
V_MAD_I64_I32 = 489
|
|
|
|
class VOP3POp(IntEnum):
|
|
V_PK_MAD_I16 = 0
|
|
V_PK_MUL_LO_U16 = 1
|
|
V_PK_ADD_I16 = 2
|
|
V_PK_SUB_I16 = 3
|
|
V_PK_LSHLREV_B16 = 4
|
|
V_PK_LSHRREV_B16 = 5
|
|
V_PK_ASHRREV_I16 = 6
|
|
V_PK_MAX_I16 = 7
|
|
V_PK_MIN_I16 = 8
|
|
V_PK_MAD_U16 = 9
|
|
V_PK_ADD_U16 = 10
|
|
V_PK_SUB_U16 = 11
|
|
V_PK_MAX_U16 = 12
|
|
V_PK_MIN_U16 = 13
|
|
V_PK_FMA_F16 = 14
|
|
V_PK_ADD_F16 = 15
|
|
V_PK_MUL_F16 = 16
|
|
V_PK_MIN_F16 = 17
|
|
V_PK_MAX_F16 = 18
|
|
V_DOT2_F32_BF16 = 26
|
|
V_PK_MINIMUM3_F16 = 27
|
|
V_PK_MAXIMUM3_F16 = 28
|
|
V_MAD_MIX_F32 = 32
|
|
V_MAD_MIXLO_F16 = 33
|
|
V_MAD_MIXHI_F16 = 34
|
|
V_DOT2_F32_F16 = 35
|
|
V_DOT2_I32_I16 = 38
|
|
V_DOT2_U32_U16 = 39
|
|
V_DOT4_I32_I8 = 40
|
|
V_DOT4_U32_U8 = 41
|
|
V_DOT8_I32_I4 = 42
|
|
V_DOT8_U32_U4 = 43
|
|
V_MFMA_F32_16X16X128_F8F6F4 = 45
|
|
V_MFMA_F32_32X32X64_F8F6F4 = 46
|
|
V_PK_FMA_F32 = 48
|
|
V_PK_MUL_F32 = 49
|
|
V_PK_ADD_F32 = 50
|
|
V_PK_MOV_B32 = 51
|
|
V_MFMA_F32_16X16X32_BF16 = 53
|
|
V_MFMA_I32_16X16X64_I8 = 54
|
|
V_MFMA_F32_32X32X16_BF16 = 55
|
|
V_MFMA_I32_32X32X32_I8 = 56
|
|
V_SMFMAC_F32_16X16X64_BF16 = 57
|
|
V_SMFMAC_I32_16X16X128_I8 = 58
|
|
V_SMFMAC_F32_16X16X128_BF8_BF8 = 59
|
|
V_SMFMAC_F32_16X16X128_BF8_FP8 = 60
|
|
V_SMFMAC_F32_16X16X128_FP8_BF8 = 61
|
|
V_MFMA_F32_32X32X1_2B_F32 = 64
|
|
V_MFMA_F32_16X16X1_4B_F32 = 65
|
|
V_MFMA_F32_4X4X1_16B_F32 = 66
|
|
V_SMFMAC_F32_16X16X128_FP8_FP8 = 67
|
|
V_MFMA_F32_32X32X2_F32 = 68
|
|
V_MFMA_F32_16X16X4_F32 = 69
|
|
V_SMFMAC_F32_32X32X32_BF16 = 70
|
|
V_SMFMAC_I32_32X32X64_I8 = 71
|
|
V_MFMA_F32_32X32X4_2B_F16 = 72
|
|
V_MFMA_F32_16X16X4_4B_F16 = 73
|
|
V_MFMA_F32_4X4X4_16B_F16 = 74
|
|
V_SMFMAC_F32_32X32X64_BF8_BF8 = 75
|
|
V_MFMA_F32_32X32X8_F16 = 76
|
|
V_MFMA_F32_16X16X16_F16 = 77
|
|
V_SMFMAC_F32_32X32X64_BF8_FP8 = 78
|
|
V_SMFMAC_F32_32X32X64_FP8_BF8 = 79
|
|
V_MFMA_I32_32X32X4_2B_I8 = 80
|
|
V_MFMA_I32_16X16X4_4B_I8 = 81
|
|
V_MFMA_I32_4X4X4_16B_I8 = 82
|
|
V_SMFMAC_F32_32X32X64_FP8_FP8 = 83
|
|
V_MFMA_F32_16X16X32_F16 = 84
|
|
V_MFMA_F32_32X32X16_F16 = 85
|
|
V_MFMA_I32_32X32X16_I8 = 86
|
|
V_MFMA_I32_16X16X32_I8 = 87
|
|
V_ACCVGPR_READ = 88
|
|
V_ACCVGPR_WRITE = 89
|
|
V_SMFMAC_F32_16X16X64_F16 = 90
|
|
V_SMFMAC_F32_32X32X32_F16 = 91
|
|
V_MFMA_F32_32X32X4_2B_BF16 = 93
|
|
V_MFMA_F32_16X16X4_4B_BF16 = 94
|
|
V_MFMA_F32_4X4X4_16B_BF16 = 95
|
|
V_MFMA_F32_32X32X8_BF16 = 96
|
|
V_MFMA_F32_16X16X16_BF16 = 97
|
|
V_SMFMAC_F32_16X16X32_F16 = 98
|
|
V_SMFMAC_F32_32X32X16_F16 = 100
|
|
V_SMFMAC_F32_16X16X32_BF16 = 102
|
|
V_SMFMAC_F32_32X32X16_BF16 = 104
|
|
V_SMFMAC_I32_16X16X64_I8 = 106
|
|
V_SMFMAC_I32_32X32X32_I8 = 108
|
|
V_MFMA_F64_16X16X4_F64 = 110
|
|
V_MFMA_F64_4X4X4_4B_F64 = 111
|
|
V_MFMA_F32_16X16X32_BF8_BF8 = 112
|
|
V_MFMA_F32_16X16X32_BF8_FP8 = 113
|
|
V_MFMA_F32_16X16X32_FP8_BF8 = 114
|
|
V_MFMA_F32_16X16X32_FP8_FP8 = 115
|
|
V_MFMA_F32_32X32X16_BF8_BF8 = 116
|
|
V_MFMA_F32_32X32X16_BF8_FP8 = 117
|
|
V_MFMA_F32_32X32X16_FP8_BF8 = 118
|
|
V_MFMA_F32_32X32X16_FP8_FP8 = 119
|
|
V_SMFMAC_F32_16X16X64_BF8_BF8 = 120
|
|
V_SMFMAC_F32_16X16X64_BF8_FP8 = 121
|
|
V_SMFMAC_F32_16X16X64_FP8_BF8 = 122
|
|
V_SMFMAC_F32_16X16X64_FP8_FP8 = 123
|
|
V_SMFMAC_F32_32X32X32_BF8_BF8 = 124
|
|
V_SMFMAC_F32_32X32X32_BF8_FP8 = 125
|
|
V_SMFMAC_F32_32X32X32_FP8_BF8 = 126
|
|
V_SMFMAC_F32_32X32X32_FP8_FP8 = 127
|
|
|
|
class VOPCOp(IntEnum):
|
|
V_CMP_CLASS_F32 = 16
|
|
V_CMPX_CLASS_F32 = 17
|
|
V_CMP_CLASS_F64 = 18
|
|
V_CMPX_CLASS_F64 = 19
|
|
V_CMP_CLASS_F16 = 20
|
|
V_CMPX_CLASS_F16 = 21
|
|
V_CMP_F_F16 = 32
|
|
V_CMP_LT_F16 = 33
|
|
V_CMP_EQ_F16 = 34
|
|
V_CMP_LE_F16 = 35
|
|
V_CMP_GT_F16 = 36
|
|
V_CMP_LG_F16 = 37
|
|
V_CMP_GE_F16 = 38
|
|
V_CMP_O_F16 = 39
|
|
V_CMP_U_F16 = 40
|
|
V_CMP_NGE_F16 = 41
|
|
V_CMP_NLG_F16 = 42
|
|
V_CMP_NGT_F16 = 43
|
|
V_CMP_NLE_F16 = 44
|
|
V_CMP_NEQ_F16 = 45
|
|
V_CMP_NLT_F16 = 46
|
|
V_CMP_TRU_F16 = 47
|
|
V_CMPX_F_F16 = 48
|
|
V_CMPX_LT_F16 = 49
|
|
V_CMPX_EQ_F16 = 50
|
|
V_CMPX_LE_F16 = 51
|
|
V_CMPX_GT_F16 = 52
|
|
V_CMPX_LG_F16 = 53
|
|
V_CMPX_GE_F16 = 54
|
|
V_CMPX_O_F16 = 55
|
|
V_CMPX_U_F16 = 56
|
|
V_CMPX_NGE_F16 = 57
|
|
V_CMPX_NLG_F16 = 58
|
|
V_CMPX_NGT_F16 = 59
|
|
V_CMPX_NLE_F16 = 60
|
|
V_CMPX_NEQ_F16 = 61
|
|
V_CMPX_NLT_F16 = 62
|
|
V_CMPX_TRU_F16 = 63
|
|
V_CMP_F_F32 = 64
|
|
V_CMP_LT_F32 = 65
|
|
V_CMP_EQ_F32 = 66
|
|
V_CMP_LE_F32 = 67
|
|
V_CMP_GT_F32 = 68
|
|
V_CMP_LG_F32 = 69
|
|
V_CMP_GE_F32 = 70
|
|
V_CMP_O_F32 = 71
|
|
V_CMP_U_F32 = 72
|
|
V_CMP_NGE_F32 = 73
|
|
V_CMP_NLG_F32 = 74
|
|
V_CMP_NGT_F32 = 75
|
|
V_CMP_NLE_F32 = 76
|
|
V_CMP_NEQ_F32 = 77
|
|
V_CMP_NLT_F32 = 78
|
|
V_CMP_TRU_F32 = 79
|
|
V_CMPX_F_F32 = 80
|
|
V_CMPX_LT_F32 = 81
|
|
V_CMPX_EQ_F32 = 82
|
|
V_CMPX_LE_F32 = 83
|
|
V_CMPX_GT_F32 = 84
|
|
V_CMPX_LG_F32 = 85
|
|
V_CMPX_GE_F32 = 86
|
|
V_CMPX_O_F32 = 87
|
|
V_CMPX_U_F32 = 88
|
|
V_CMPX_NGE_F32 = 89
|
|
V_CMPX_NLG_F32 = 90
|
|
V_CMPX_NGT_F32 = 91
|
|
V_CMPX_NLE_F32 = 92
|
|
V_CMPX_NEQ_F32 = 93
|
|
V_CMPX_NLT_F32 = 94
|
|
V_CMPX_TRU_F32 = 95
|
|
V_CMP_F_F64 = 96
|
|
V_CMP_LT_F64 = 97
|
|
V_CMP_EQ_F64 = 98
|
|
V_CMP_LE_F64 = 99
|
|
V_CMP_GT_F64 = 100
|
|
V_CMP_LG_F64 = 101
|
|
V_CMP_GE_F64 = 102
|
|
V_CMP_O_F64 = 103
|
|
V_CMP_U_F64 = 104
|
|
V_CMP_NGE_F64 = 105
|
|
V_CMP_NLG_F64 = 106
|
|
V_CMP_NGT_F64 = 107
|
|
V_CMP_NLE_F64 = 108
|
|
V_CMP_NEQ_F64 = 109
|
|
V_CMP_NLT_F64 = 110
|
|
V_CMP_TRU_F64 = 111
|
|
V_CMPX_F_F64 = 112
|
|
V_CMPX_LT_F64 = 113
|
|
V_CMPX_EQ_F64 = 114
|
|
V_CMPX_LE_F64 = 115
|
|
V_CMPX_GT_F64 = 116
|
|
V_CMPX_LG_F64 = 117
|
|
V_CMPX_GE_F64 = 118
|
|
V_CMPX_O_F64 = 119
|
|
V_CMPX_U_F64 = 120
|
|
V_CMPX_NGE_F64 = 121
|
|
V_CMPX_NLG_F64 = 122
|
|
V_CMPX_NGT_F64 = 123
|
|
V_CMPX_NLE_F64 = 124
|
|
V_CMPX_NEQ_F64 = 125
|
|
V_CMPX_NLT_F64 = 126
|
|
V_CMPX_TRU_F64 = 127
|
|
V_CMP_F_I16 = 160
|
|
V_CMP_LT_I16 = 161
|
|
V_CMP_EQ_I16 = 162
|
|
V_CMP_LE_I16 = 163
|
|
V_CMP_GT_I16 = 164
|
|
V_CMP_NE_I16 = 165
|
|
V_CMP_GE_I16 = 166
|
|
V_CMP_T_I16 = 167
|
|
V_CMP_F_U16 = 168
|
|
V_CMP_LT_U16 = 169
|
|
V_CMP_EQ_U16 = 170
|
|
V_CMP_LE_U16 = 171
|
|
V_CMP_GT_U16 = 172
|
|
V_CMP_NE_U16 = 173
|
|
V_CMP_GE_U16 = 174
|
|
V_CMP_T_U16 = 175
|
|
V_CMPX_F_I16 = 176
|
|
V_CMPX_LT_I16 = 177
|
|
V_CMPX_EQ_I16 = 178
|
|
V_CMPX_LE_I16 = 179
|
|
V_CMPX_GT_I16 = 180
|
|
V_CMPX_NE_I16 = 181
|
|
V_CMPX_GE_I16 = 182
|
|
V_CMPX_T_I16 = 183
|
|
V_CMPX_F_U16 = 184
|
|
V_CMPX_LT_U16 = 185
|
|
V_CMPX_EQ_U16 = 186
|
|
V_CMPX_LE_U16 = 187
|
|
V_CMPX_GT_U16 = 188
|
|
V_CMPX_NE_U16 = 189
|
|
V_CMPX_GE_U16 = 190
|
|
V_CMPX_T_U16 = 191
|
|
V_CMP_F_I32 = 192
|
|
V_CMP_LT_I32 = 193
|
|
V_CMP_EQ_I32 = 194
|
|
V_CMP_LE_I32 = 195
|
|
V_CMP_GT_I32 = 196
|
|
V_CMP_NE_I32 = 197
|
|
V_CMP_GE_I32 = 198
|
|
V_CMP_T_I32 = 199
|
|
V_CMP_F_U32 = 200
|
|
V_CMP_LT_U32 = 201
|
|
V_CMP_EQ_U32 = 202
|
|
V_CMP_LE_U32 = 203
|
|
V_CMP_GT_U32 = 204
|
|
V_CMP_NE_U32 = 205
|
|
V_CMP_GE_U32 = 206
|
|
V_CMP_T_U32 = 207
|
|
V_CMPX_F_I32 = 208
|
|
V_CMPX_LT_I32 = 209
|
|
V_CMPX_EQ_I32 = 210
|
|
V_CMPX_LE_I32 = 211
|
|
V_CMPX_GT_I32 = 212
|
|
V_CMPX_NE_I32 = 213
|
|
V_CMPX_GE_I32 = 214
|
|
V_CMPX_T_I32 = 215
|
|
V_CMPX_F_U32 = 216
|
|
V_CMPX_LT_U32 = 217
|
|
V_CMPX_EQ_U32 = 218
|
|
V_CMPX_LE_U32 = 219
|
|
V_CMPX_GT_U32 = 220
|
|
V_CMPX_NE_U32 = 221
|
|
V_CMPX_GE_U32 = 222
|
|
V_CMPX_T_U32 = 223
|
|
V_CMP_F_I64 = 224
|
|
V_CMP_LT_I64 = 225
|
|
V_CMP_EQ_I64 = 226
|
|
V_CMP_LE_I64 = 227
|
|
V_CMP_GT_I64 = 228
|
|
V_CMP_NE_I64 = 229
|
|
V_CMP_GE_I64 = 230
|
|
V_CMP_T_I64 = 231
|
|
V_CMP_F_U64 = 232
|
|
V_CMP_LT_U64 = 233
|
|
V_CMP_EQ_U64 = 234
|
|
V_CMP_LE_U64 = 235
|
|
V_CMP_GT_U64 = 236
|
|
V_CMP_NE_U64 = 237
|
|
V_CMP_GE_U64 = 238
|
|
V_CMP_T_U64 = 239
|
|
V_CMPX_F_I64 = 240
|
|
V_CMPX_LT_I64 = 241
|
|
V_CMPX_EQ_I64 = 242
|
|
V_CMPX_LE_I64 = 243
|
|
V_CMPX_GT_I64 = 244
|
|
V_CMPX_NE_I64 = 245
|
|
V_CMPX_GE_I64 = 246
|
|
V_CMPX_T_I64 = 247
|
|
V_CMPX_F_U64 = 248
|
|
V_CMPX_LT_U64 = 249
|
|
V_CMPX_EQ_U64 = 250
|
|
V_CMPX_LE_U64 = 251
|
|
V_CMPX_GT_U64 = 252
|
|
V_CMPX_NE_U64 = 253
|
|
V_CMPX_GE_U64 = 254
|
|
V_CMPX_T_U64 = 255
|