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b913c910c5
* test_roundtrip on different archs * failing tests * take RDNA4 xml changes from the emu branch * work * min diff to disasm flat * test_add passes, rdna4 first * correct vgpr field for the multi dword store stuff * amdllvm * recompile in roundtrip, get sources from emulator * amdllvm, 2 * clean clean * note, don't rely on that os.environ --------- Co-authored-by: George Hotz <geohot@gmail.com>
68 lines
4.2 KiB
Python
68 lines
4.2 KiB
Python
# Instruction format detection and decoding
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from __future__ import annotations
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from extra.assembly.amd.dsl import Inst, FixedBitField, EnumBitField
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# SDWA/DPP variant detection: src0 field (bits 0-8) encodes the variant
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# 0xf9 (249) = SDWA, 0xfa (250) = DPP16 for CDNA (GFX9)
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_VARIANT_SRC0 = {"_SDWA_SDST": 0xf9, "_SDWA": 0xf9, "_DPP16": 0xfa}
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def _matches(data: bytes, cls: type[Inst]) -> bool:
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"""Check if data matches all FixedBitFields and op is in allowed."""
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for _, field in cls._fields:
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dword_idx = field.lo // 32
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if len(data) < (dword_idx + 1) * 4: return False
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word = int.from_bytes(data[dword_idx*4:(dword_idx+1)*4], 'little')
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field_lo = field.lo % 32
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if isinstance(field, FixedBitField):
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if ((word >> field_lo) & field.mask) != field.default: return False
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if isinstance(field, EnumBitField) and field.allowed is not None:
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try: opcode = field.decode((word >> field_lo) & field.mask)
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except ValueError: return False # opcode not in enum
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if opcode not in field.allowed: return False
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# Check SDWA/DPP variant based on src0 field (bits 0-8) - only for variant classes
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name = cls.__name__
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word = int.from_bytes(data[:4], 'little')
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for suffix, expected_src0 in _VARIANT_SRC0.items():
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if name.endswith(suffix): return (word & 0x1ff) == expected_src0
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return True
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# Import instruction classes for each architecture
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from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP1_SDST, VOP1_LIT, VOP2, VOP2_LIT, VOP3, VOP3_SDST, VOP3SD, VOP3P, VOPC, VOPD, VINTERP,
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SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, SMEM, DS, FLAT, GLOBAL, SCRATCH)
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from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP1_SDST as R4_VOP1_SDST, VOP1_LIT as R4_VOP1_LIT,
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VOP2 as R4_VOP2, VOP2_LIT as R4_VOP2_LIT, VOP3 as R4_VOP3, VOP3_SDST as R4_VOP3_SDST, VOP3SD as R4_VOP3SD, VOP3P as R4_VOP3P,
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VOPC as R4_VOPC, VOPD as R4_VOPD, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP1_LIT as R4_SOP1_LIT,
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SOP2 as R4_SOP2, SOP2_LIT as R4_SOP2_LIT, SOPC as R4_SOPC, SOPC_LIT as R4_SOPC_LIT,
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SOPK as R4_SOPK, SOPK_LIT as R4_SOPK_LIT, SOPP as R4_SOPP,
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SMEM as R4_SMEM, DS as R4_DS, VFLAT as R4_FLAT, VGLOBAL as R4_GLOBAL, VSCRATCH as R4_SCRATCH)
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from extra.assembly.amd.autogen.cdna.ins import (VOP1 as C_VOP1, VOP1_SDWA as C_VOP1_SDWA, VOP1_DPP16 as C_VOP1_DPP16,
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VOP2 as C_VOP2, VOP2_LIT as C_VOP2_LIT, VOP2_SDWA as C_VOP2_SDWA, VOP2_DPP16 as C_VOP2_DPP16,
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VOPC as C_VOPC, VOPC_SDWA_SDST as C_VOPC_SDWA_SDST,
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VOP3 as C_VOP3, VOP3_SDST as C_VOP3_SDST, VOP3SD as C_VOP3SD, VOP3P as C_VOP3P, VOP3PX2 as C_VOP3PX2,
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SOP1 as C_SOP1, SOP2 as C_SOP2, SOPC as C_SOPC, SOPK as C_SOPK, SOPK_LIT as C_SOPK_LIT, SOPP as C_SOPP, SMEM as C_SMEM, DS as C_DS,
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FLAT as C_FLAT, GLOBAL as C_GLOBAL, SCRATCH as C_SCRATCH, MUBUF as C_MUBUF)
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# Order matters: more specific encodings first, catch-alls (SOP2, VOP2) last
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# Order: base before _LIT (base matches regular ops, _LIT catches lit-only ops excluded from base)
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_FORMATS = {
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"rdna3": [VOPD, VOP3P, VINTERP, VOP3SD, VOP3_SDST, VOP3, DS, GLOBAL, SCRATCH, FLAT, SMEM,
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SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, VOPC, VOP1_SDST, VOP1, VOP1_LIT, VOP2, VOP2_LIT],
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"rdna4": [R4_VOPD, R4_VOP3P, R4_VINTERP, R4_VOP3SD, R4_VOP3_SDST, R4_VOP3, R4_DS, R4_GLOBAL, R4_SCRATCH, R4_FLAT, R4_SMEM,
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R4_SOP1, R4_SOP1_LIT, R4_SOPC, R4_SOPC_LIT, R4_SOPP, R4_SOPK, R4_SOPK_LIT, R4_VOPC, R4_VOP1_SDST, R4_VOP1, R4_VOP1_LIT,
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R4_SOP2, R4_SOP2_LIT, R4_VOP2, R4_VOP2_LIT],
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"cdna": [C_VOP3PX2, C_VOP3P, C_VOP3SD, C_VOP3_SDST, C_VOP3, C_DS, C_GLOBAL, C_SCRATCH, C_FLAT, C_MUBUF, C_SMEM,
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C_SOP1, C_SOPC, C_SOPP, C_SOPK, C_SOPK_LIT, C_VOPC_SDWA_SDST, C_VOPC,
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C_VOP1_DPP16, C_VOP1_SDWA, C_VOP1, C_VOP2_DPP16, C_VOP2_SDWA, C_SOP2, C_VOP2, C_VOP2_LIT],
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}
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def detect_format(data: bytes, arch: str = "rdna3") -> type[Inst]:
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"""Detect instruction format from machine code bytes."""
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assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
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for cls in _FORMATS[arch]:
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if _matches(data, cls): return cls
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raise ValueError(f"unknown {arch} format word={int.from_bytes(data[:4], 'little'):#010x}")
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def decode_inst(data: bytes, arch: str = "rdna3") -> Inst:
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"""Decode machine code bytes into an instruction."""
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return detect_format(data, arch).from_bytes(data)
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