From 65a805ab3d444c123c4f3d20095689da666dbd47 Mon Sep 17 00:00:00 2001 From: Dzmitry Malyshau Date: Thu, 2 Dec 2021 11:01:27 -0500 Subject: [PATCH] hal: exclude COPY_DST from ordered sync usages --- wgpu-hal/src/lib.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wgpu-hal/src/lib.rs b/wgpu-hal/src/lib.rs index bfd5da180d..ffc79300c1 100644 --- a/wgpu-hal/src/lib.rs +++ b/wgpu-hal/src/lib.rs @@ -649,7 +649,7 @@ bitflags::bitflags! { /// The combination of all usages that the are guaranteed to be be ordered by the hardware. /// If a usage is not ordered, then even if it doesn't change between draw calls, there /// still need to be pipeline barriers inserted for synchronization. - const ORDERED = Self::INCLUSIVE.bits | Self::MAP_WRITE.bits | Self::COPY_DST.bits; + const ORDERED = Self::INCLUSIVE.bits | Self::MAP_WRITE.bits; } } @@ -672,7 +672,7 @@ bitflags::bitflags! { /// The combination of all usages that the are guaranteed to be be ordered by the hardware. /// If a usage is not ordered, then even if it doesn't change between draw calls, there /// still need to be pipeline barriers inserted for synchronization. - const ORDERED = Self::INCLUSIVE.bits | Self::COPY_DST.bits | Self::COLOR_TARGET.bits | Self::DEPTH_STENCIL_WRITE.bits | Self::STORAGE_READ.bits; + const ORDERED = Self::INCLUSIVE.bits | Self::COLOR_TARGET.bits | Self::DEPTH_STENCIL_WRITE.bits | Self::STORAGE_READ.bits; //TODO: remove this const UNINITIALIZED = 0xFFFF; }