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precision_
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.. meta::
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:description: Supported data types in ROCm
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:keywords: int8, float8, float8 (E4M3), float8 (E5M2), bfloat8, float16, half, bfloat16, tensorfloat32, float,
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float32, float64, double, AMD, ROCm, AMDGPU
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:description: Supported data types of AMD GPUs and libraries in ROCm.
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:keywords: precision, data types, HIP types, int8, float8, float8 (E4M3),
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float8 (E5M2), bfloat8, float16, half, bfloat16, tensorfloat32,
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float, float32, float64, double, AMD data types, HIP data types,
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ROCm precision, ROCm data types
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*************************************************************
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Precision support
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Data types and precision support
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*************************************************************
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Use the following sections to identify data types and HIP types ROCm™ supports.
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This topic lists the supported data types of AMD GPUs and ROCm libraries.
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Corresponding :doc:`HIP <hip:index>` data types are also noted.
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Integral types
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==========================================
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The signed and unsigned integral types that are supported by ROCm are listed in the following table,
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together with their corresponding HIP type and a short description.
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The signed and unsigned integral types supported by ROCm are listed in
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the following table, along with their corresponding HIP type and a short
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description.
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.. list-table::
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@@ -46,8 +50,8 @@ together with their corresponding HIP type and a short description.
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Floating-point types
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==========================================
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The floating-point types that are supported by ROCm are listed in the following table, together with
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their corresponding HIP type and a short description.
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The floating-point types supported by ROCm are listed in the following
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table, along with their corresponding HIP type and a short description.
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.. image:: ../data/about/compatibility/floating-point-data-types.png
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:alt: Supported floating-point types
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@@ -63,43 +67,62 @@ their corresponding HIP type and a short description.
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*
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- float8 (E4M3)
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- ``-``
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- An 8-bit floating-point number that mostly follows IEEE-754 conventions and **S1E4M3** bit layout, as described in `8-bit Numerical Formats for Deep Neural Networks <https://arxiv.org/abs/2206.02915>`_ , with expanded range and with no infinity or signed zero. NaN is represented as negative zero.
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- An 8-bit floating-point number that mostly follows IEEE-754 conventions
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and **S1E4M3** bit layout, as described in `8-bit Numerical Formats for Deep Neural Networks <https://arxiv.org/abs/2206.02915>`_ ,
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with expanded range and no infinity or signed zero. NaN is
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represented as negative zero.
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*
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- float8 (E5M2)
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- ``-``
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- An 8-bit floating-point number mostly following IEEE-754 conventions and **S1E5M2** bit layout, as described in `8-bit Numerical Formats for Deep Neural Networks <https://arxiv.org/abs/2206.02915>`_ , with expanded range and with no infinity or signed zero. NaN is represented as negative zero.
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- An 8-bit floating-point number mostly following IEEE-754 conventions and
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**S1E5M2** bit layout, as described in `8-bit Numerical Formats for Deep Neural Networks <https://arxiv.org/abs/2206.02915>`_ ,
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with expanded range and no infinity or signed zero. NaN is
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represented as negative zero.
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*
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- float16
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- ``half``
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- A 16-bit floating-point number that conforms to the IEEE 754-2008 half-precision storage format.
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- A 16-bit floating-point number that conforms to the IEEE 754-2008
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half-precision storage format.
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*
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- bfloat16
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- ``bfloat16``
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- A shortened 16-bit version of the IEEE 754 single-precision storage format.
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- A shortened 16-bit version of the IEEE 754 single-precision storage
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format.
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*
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- tensorfloat32
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- ``-``
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- A floating-point number that occupies 32 bits or less of storage, providing improved range compared to half (16-bit) format, at (potentially) greater throughput than single-precision (32-bit) formats.
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- A floating-point number that occupies 32 bits or less of storage,
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providing improved range compared to half (16-bit) format, at
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(potentially) greater throughput than single-precision (32-bit) formats.
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*
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- float32
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- ``float``
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- A 32-bit floating-point number that conforms to the IEEE 754 single-precision storage format.
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- A 32-bit floating-point number that conforms to the IEEE 754
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single-precision storage format.
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*
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- float64
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- ``double``
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- A 64-bit floating-point number that conforms to the IEEE 754 double-precision storage format.
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- A 64-bit floating-point number that conforms to the IEEE 754
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double-precision storage format.
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.. note::
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* The float8 and tensorfloat32 types are internal types used in calculations in Matrix Cores and can be stored in any type of the same size.
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* The encodings for FP8 (E5M2) and FP8 (E4M3) that are natively supported by MI300 differ from the FP8 (E5M2) and FP8 (E4M3) encodings used in H100 (`FP8 Formats for Deep Learning <https://arxiv.org/abs/2209.05433>`_).
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* The float8 and tensorfloat32 types are internal types used in calculations
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in Matrix Cores and can be stored in any type of the same size.
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* The encodings for FP8 (E5M2) and FP8 (E4M3) that the
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MI300 series natively supports differ from the FP8 (E5M2) and FP8 (E4M3)
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encodings used in NVIDIA H100
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(`FP8 Formats for Deep Learning <https://arxiv.org/abs/2209.05433>`_).
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* In some AMD documents and articles, float8 (E5M2) is referred to as bfloat8.
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ROCm support icons
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==========================================
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In the following sections, we use icons to represent the level of support. These icons, described in the
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following table, are also used on the library data type support pages.
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In the following sections, icons represent the level of support. These
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icons, described in the following table, are also used in the library data type
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support pages.
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.. list-table::
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:header-rows: 1
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@@ -121,14 +144,27 @@ following table, are also used on the library data type support pages.
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.. note::
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* Full support means that the type is supported natively or with hardware emulation.
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* Native support means that the operations for that type are implemented in hardware. Types that are not natively supported are emulated with the available hardware. The performance of non-natively supported types can differ from the full instruction throughput rate. For example, 16-bit integer operations can be performed on the 32-bit integer ALUs at full rate; however, 64-bit integer operations might need several instructions on the 32-bit integer ALUs.
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* Any type can be emulated by software, but this page does not cover such cases.
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* Full support means that the type is supported natively or with hardware
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emulation.
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Hardware type support
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* Native support means that the operations for that type are implemented in
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hardware. Types that are not natively supported are emulated with the
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available hardware. The performance of non-natively supported types can
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differ from the full instruction throughput rate. For example, 16-bit
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integer operations can be performed on the 32-bit integer ALUs at full rate;
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however, 64-bit integer operations might need several instructions on the
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32-bit integer ALUs.
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* Any type can be emulated by software, but this page does not cover such
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cases.
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Hardware data type support
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==========================================
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AMD GPU hardware support for data types is listed in the following tables.
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The following tables provide information about AMD Instinct accelerators support
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for various data types. The MI200 series GPUs, which include MI210, MI250, and
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MI250X, are based on the CDNA2 architecture. The MI300 series GPUs, consisting
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of MI300A, MI300X, and MI325X, are built on the CDNA3 architecture.
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Compute units support
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-------------------------------------------------------------------------------
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@@ -375,21 +411,23 @@ The following table lists data type support for atomic operations.
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.. note::
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For cases that are not natively supported, you can emulate atomic operations using software.
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Software-emulated atomic operations have high negative performance impact when they frequently
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access the same memory address.
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You can emulate atomic operations using software for cases that are not
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natively supported. Software-emulated atomic operations have a high negative
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performance impact when they frequently access the same memory address.
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Data Type support in ROCm Libraries
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Data type support in ROCm libraries
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==========================================
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ROCm library support for int8, float8 (E4M3), float8 (E5M2), int16, float16, bfloat16, int32,
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tensorfloat32, float32, int64, and float64 is listed in the following tables.
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ROCm library support for int8, float8 (E4M3), float8 (E5M2), int16, float16,
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bfloat16, int32, tensorfloat32, float32, int64, and float64 is listed in the
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following tables.
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Libraries input/output type support
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-------------------------------------------------------------------------------
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The following tables list ROCm library support for specific input and output data types. For a detailed
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description, refer to the corresponding library data type support page.
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The following tables list ROCm library support for specific input and output
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data types. Refer to the corresponding library data type support page for a
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detailed description.
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.. tab-set::
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@@ -516,8 +554,9 @@ description, refer to the corresponding library data type support page.
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Libraries internal calculations type support
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-------------------------------------------------------------------------------
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The following tables list ROCm library support for specific internal data types. For a detailed
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description, refer to the corresponding library data type support page.
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The following tables list ROCm library support for specific internal data types.
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Refer to the corresponding library data type support page for a detailed
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description.
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.. tab-set::
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Reference in New Issue
Block a user