[docs/7.0-alpha] Add pointers to latest documentation (#5384 )

* add beta to version history * Update preview versions list * add pointers to latest docs
[docs/7.0-alpha] Update preview versions list (#5171 )
2026-01-10 15:18:11 -05:00 · 2025-09-18 12:21:22 -04:00 · 2025-08-08 10:11:30 -04:00 · 2025-07-24 17:42:51 -04:00 · 2025-07-23 14:53:05 -04:00 · 2025-07-11 18:46:50 -04:00
254 changed files with 584 additions and 27488 deletions
--- a/.wordlist.txt
+++ b/.wordlist.txt
@@ -1,3 +1,4 @@
+SGLang
 Datacenter
 GST
 IET
@@ -13,6 +14,7 @@ demangled
 inlined
 microscaling
 roofline
+torchtitan
 AAC
 ABI
 ACE
--- a/docs/about/license.md
+++ b/docs/about/license.md
@@ -1,149 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="ROCm licensing terms">
-  <meta name="keywords" content="license, licensing terms">
-</head>
-
-# ROCm license
-
-```{include} ../../LICENSE
-```
-
-:::{note}
-The preceding license applies to the [ROCm repository](https://github.com/ROCm/ROCm), which
-primarily contains documentation. For licenses related to other ROCm components, refer to the
-following section.
-:::
-
-## ROCm component licenses
-
-ROCm is released by Advanced Micro Devices, Inc. (AMD) and is licensed per component separately.
-The following table is a list of ROCm components with links to their respective license
-terms. These components may include third party components subject to
-additional licenses. Please review individual repositories for more information.
-
-<!-- spellcheck-disable -->
-| Component | License |
-|:---------------------|:-------------------------|
-| [AMD Compute Language Runtime (CLR)](https://github.com/ROCm/clr) | [MIT](https://github.com/ROCm/clr/blob/amd-staging/LICENSE.txt) |
-| [AMD SMI](https://github.com/ROCm/amdsmi) | [MIT](https://github.com/ROCm/amdsmi/blob/amd-staging/LICENSE) |
-| [aomp](https://github.com/ROCm/aomp/) | [Apache 2.0](https://github.com/ROCm/aomp/blob/aomp-dev/LICENSE) |
-| [aomp-extras](https://github.com/ROCm/aomp-extras/) | [MIT](https://github.com/ROCm/aomp-extras/blob/aomp-dev/LICENSE) |
-| [Code Object Manager (Comgr)](https://github.com/ROCm/llvm-project/tree/amd-staging/amd/comgr) | [The University of Illinois/NCSA](https://github.com/ROCm/llvm-project/blob/amd-staging/amd/comgr/LICENSE.txt) |
-| [Composable Kernel](https://github.com/ROCm/composable_kernel) | [MIT](https://github.com/ROCm/composable_kernel/blob/develop/LICENSE) |
-| [half](https://github.com/ROCm/half/) | [MIT](https://github.com/ROCm/half/blob/rocm/LICENSE.txt) |
-| [HIP](https://github.com/ROCm/HIP/) | [MIT](https://github.com/ROCm/HIP/blob/amd-staging/LICENSE.txt) |
-| [hipamd](https://github.com/ROCm/clr/tree/amd-staging/hipamd) | [MIT](https://github.com/ROCm/clr/blob/amd-staging/hipamd/LICENSE.txt) |
-| [hipBLAS](https://github.com/ROCm/hipBLAS/) | [MIT](https://github.com/ROCm/hipBLAS/blob/develop/LICENSE.md) |
-| [hipBLASLt](https://github.com/ROCm/hipBLASLt/) | [MIT](https://github.com/ROCm/hipBLASLt/blob/develop/LICENSE.md) |
-| [HIPCC](https://github.com/ROCm/llvm-project/tree/amd-staging/amd/hipcc) | [MIT](https://github.com/ROCm/llvm-project/blob/amd-staging/amd/hipcc/LICENSE.txt) |
-| [hipCUB](https://github.com/ROCm/hipCUB/) | [Custom](https://github.com/ROCm/hipCUB/blob/develop/LICENSE.txt) |
-| [hipFFT](https://github.com/ROCm/hipFFT/) | [MIT](https://github.com/ROCm/hipFFT/blob/develop/LICENSE.md) |
-| [hipfort](https://github.com/ROCm/hipfort/) | [MIT](https://github.com/ROCm/hipfort/blob/develop/LICENSE) |
-| [HIPIFY](https://github.com/ROCm/HIPIFY/) | [MIT](https://github.com/ROCm/HIPIFY/blob/amd-staging/LICENSE.txt) |
-| [hipRAND](https://github.com/ROCm/hipRAND/) | [MIT](https://github.com/ROCm/hipRAND/blob/develop/LICENSE.txt) |
-| [hipSOLVER](https://github.com/ROCm/hipSOLVER/) | [MIT](https://github.com/ROCm/hipSOLVER/blob/develop/LICENSE.md) |
-| [hipSPARSE](https://github.com/ROCm/hipSPARSE/) | [MIT](https://github.com/ROCm/hipSPARSE/blob/develop/LICENSE.md) |
-| [hipSPARSELt](https://github.com/ROCm/hipSPARSELt/) | [MIT](https://github.com/ROCm/hipSPARSELt/blob/develop/LICENSE.md) |
-| [hipTensor](https://github.com/ROCm/hipTensor) | [MIT](https://github.com/ROCm/hipTensor/blob/develop/LICENSE) |
-| hsa-amd-aqlprofile | [AMD Software EULA](https://www.amd.com/en/legal/eula/amd-software-eula.html) |
-| [llvm-project](https://github.com/ROCm/llvm-project/) | [Apache](https://github.com/ROCm/llvm-project/blob/amd-staging/LICENSE.TXT) |
-| [llvm-project/flang](https://github.com/ROCm/llvm-project/tree/amd-staging/flang) | [Apache 2.0](https://github.com/ROCm/llvm-project/blob/amd-staging/flang/LICENSE.TXT) |
-| [MIGraphX](https://github.com/ROCm/AMDMIGraphX/) | [MIT](https://github.com/ROCm/AMDMIGraphX/blob/develop/LICENSE) |
-| [MIOpen](https://github.com/ROCm/MIOpen/) | [MIT](https://github.com/ROCm/MIOpen/blob/develop/LICENSE.txt) |
-| [MIVisionX](https://github.com/ROCm/MIVisionX/) | [MIT](https://github.com/ROCm/MIVisionX/blob/develop/LICENSE.txt) |
-| [rocAL](https://github.com/ROCm/rocAL) | [MIT](https://github.com/ROCm/rocAL/blob/develop/LICENSE.txt) |
-| [rocALUTION](https://github.com/ROCm/rocALUTION/) | [MIT](https://github.com/ROCm/rocALUTION/blob/develop/LICENSE.md) |
-| [rocBLAS](https://github.com/ROCm/rocBLAS/) | [MIT](https://github.com/ROCm/rocBLAS/blob/develop/LICENSE.md) |
-| [ROCdbgapi](https://github.com/ROCm/ROCdbgapi/) | [MIT](https://github.com/ROCm/ROCdbgapi/blob/amd-staging/LICENSE.txt) |
-| [rocDecode](https://github.com/ROCm/rocDecode) | [MIT](https://github.com/ROCm/rocDecode/blob/develop/LICENSE) |
-| [rocFFT](https://github.com/ROCm/rocFFT/) | [MIT](https://github.com/ROCm/rocFFT/blob/develop/LICENSE.md) |
-| [ROCgdb](https://github.com/ROCm/ROCgdb/) | [GNU General Public License v3.0](https://github.com/ROCm/ROCgdb/blob/amd-staging/COPYING3) |
-| [rocJPEG](https://github.com/ROCm/rocJPEG/) | [MIT](https://github.com/ROCm/rocJPEG/blob/develop/LICENSE) |
-| [ROCK-Kernel-Driver](https://github.com/ROCm/ROCK-Kernel-Driver/) | [GPL 2.0 WITH Linux-syscall-note](https://github.com/ROCm/ROCK-Kernel-Driver/blob/master/COPYING) |
-| [rocminfo](https://github.com/ROCm/rocminfo/) | [The University of Illinois/NCSA](https://github.com/ROCm/rocminfo/blob/amd-staging/License.txt) |
-| [ROCm Bandwidth Test](https://github.com/ROCm/rocm_bandwidth_test/) | [MIT](https://github.com/ROCm/rocm_bandwidth_test/blob/master/LICENSE.txt) |
-| [ROCm CMake](https://github.com/ROCm/rocm-cmake/) | [MIT](https://github.com/ROCm/rocm-cmake/blob/develop/LICENSE) |
-| [ROCm Communication Collectives Library (RCCL)](https://github.com/ROCm/rccl/) | [Custom](https://github.com/ROCm/rccl/blob/develop/LICENSE.txt) |
-| [ROCm-Core](https://github.com/ROCm/rocm-core) | [MIT](https://github.com/ROCm/rocm-core/blob/master/copyright) |
-| [ROCm Compute Profiler](https://github.com/ROCm/rocprofiler-compute) | [MIT](https://github.com/ROCm/rocprofiler-compute/blob/amd-staging/LICENSE) |
-| [ROCm Data Center (RDC)](https://github.com/ROCm/rdc/) | [MIT](https://github.com/ROCm/rdc/blob/amd-staging/LICENSE) |
-| [ROCm-Device-Libs](https://github.com/ROCm/llvm-project/tree/amd-staging/amd/device-libs) | [The University of Illinois/NCSA](https://github.com/ROCm/llvm-project/blob/amd-staging/amd/device-libs/LICENSE.TXT) |
-| [ROCm-OpenCL-Runtime](https://github.com/ROCm/clr/tree/amd-staging/opencl) | [MIT](https://github.com/ROCm/clr/blob/amd-staging/opencl/LICENSE.txt) |
-| [ROCm Performance Primitives (RPP)](https://github.com/ROCm/rpp) | [MIT](https://github.com/ROCm/rpp/blob/develop/LICENSE) |
-| [ROCm SMI Lib](https://github.com/ROCm/rocm_smi_lib/) | [MIT](https://github.com/ROCm/rocm_smi_lib/blob/amd-staging/License.txt) |
-| [ROCm Systems Profiler](https://github.com/ROCm/rocprofiler-systems) | [MIT](https://github.com/ROCm/rocprofiler-systems/blob/amd-staging/LICENSE) |
-| [ROCm Validation Suite](https://github.com/ROCm/ROCmValidationSuite/) | [MIT](https://github.com/ROCm/ROCmValidationSuite/blob/master/LICENSE) |
-| [rocPRIM](https://github.com/ROCm/rocPRIM/) | [MIT](https://github.com/ROCm/rocPRIM/blob/develop/LICENSE.txt) |
-| [ROCProfiler](https://github.com/ROCm/rocprofiler/) | [MIT](https://github.com/ROCm/rocprofiler/blob/amd-staging/LICENSE) |
-| [ROCprofiler-SDK](https://github.com/ROCm/rocprofiler-sdk) | [MIT](https://github.com/ROCm/rocprofiler-sdk/blob/amd-mainline/LICENSE) |
-| [rocPyDecode](https://github.com/ROCm/rocPyDecode) | [MIT](https://github.com/ROCm/rocPyDecode/blob/develop/LICENSE.txt) |
-| [rocRAND](https://github.com/ROCm/rocRAND/) | [MIT](https://github.com/ROCm/rocRAND/blob/develop/LICENSE.txt) |
-| [ROCr Debug Agent](https://github.com/ROCm/rocr_debug_agent/) | [The University of Illinois/NCSA](https://github.com/ROCm/rocr_debug_agent/blob/amd-staging/LICENSE.txt) |
-| [ROCR-Runtime](https://github.com/ROCm/ROCR-Runtime/) | [The University of Illinois/NCSA](https://github.com/ROCm/ROCR-Runtime/blob/amd-staging/LICENSE.txt) |
-| [rocSHMEM](https://github.com/ROCm/rocSHMEM/) | [MIT](https://github.com/ROCm/rocSHMEM/blob/develop/LICENSE.md) |
-| [rocSOLVER](https://github.com/ROCm/rocSOLVER/) | [BSD-2-Clause](https://github.com/ROCm/rocSOLVER/blob/develop/LICENSE.md) |
-| [rocSPARSE](https://github.com/ROCm/rocSPARSE/) | [MIT](https://github.com/ROCm/rocSPARSE/blob/develop/LICENSE.md) |
-| [rocThrust](https://github.com/ROCm/rocThrust/) | [Apache 2.0](https://github.com/ROCm/rocThrust/blob/develop/LICENSE) |
-| [ROCTracer](https://github.com/ROCm/roctracer/) | [MIT](https://github.com/ROCm/roctracer/blob/amd-master/LICENSE) |
-| [rocWMMA](https://github.com/ROCm/rocWMMA/) | [MIT](https://github.com/ROCm/rocWMMA/blob/develop/LICENSE.md) |
-| [Tensile](https://github.com/ROCm/Tensile/) | [MIT](https://github.com/ROCm/Tensile/blob/develop/LICENSE.md) |
-| [TransferBench](https://github.com/ROCm/TransferBench) | [MIT](https://github.com/ROCm/TransferBench/blob/develop/LICENSE.md) |
-
-Open sourced ROCm components are released via public GitHub
-repositories, packages on [https://repo.radeon.com](https://repo.radeon.com) and other distribution channels.
-Proprietary products are only available on [https://repo.radeon.com](https://repo.radeon.com).
-Proprietary components are organized in a proprietary subdirectory in the package
-repositories to distinguish from open sourced packages.
-
-```{note}
-The following additional terms and conditions apply to your use of ROCm technical documentation.
-```
-
-©2023 - 2025 Advanced Micro Devices, Inc. All rights reserved.
-
-The information presented in this document is for informational purposes only
-and may contain technical inaccuracies, omissions, and typographical errors. The
-information contained herein is subject to change and may be rendered inaccurate
-for many reasons, including but not limited to product and roadmap changes,
-component and motherboard version changes, new model and/or product releases,
-product differences between differing manufacturers, software changes, BIOS
-flashes, firmware upgrades, or the like. Any computer system has risks of
-security vulnerabilities that cannot be completely prevented or mitigated. AMD
-assumes no obligation to update or otherwise correct or revise this information.
-However, AMD reserves the right to revise this information and to make changes
-from time to time to the content hereof without obligation of AMD to notify any
-person of such revisions or changes.
-
-THIS INFORMATION IS PROVIDED “AS IS.” AMD MAKES NO REPRESENTATIONS OR WARRANTIES
-WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY
-INACCURACIES, ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD
-SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
-MERCHANTABILITY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE
-LIABLE TO ANY PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER
-CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN,
-EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-
-AMD, the AMD Arrow logo, ROCm, and combinations thereof are trademarks of
-Advanced Micro Devices, Inc. Other product names used in this publication are
-for identification purposes only and may be trademarks of their respective
-companies.
-
-### Package licensing
-
-:::{attention}
-AQL Profiler and AOCC CPU optimization are both provided in binary form, each
-subject to the license agreement enclosed in the directory for the binary available
-in `/opt/rocm/share/doc/hsa-amd-aqlprofile/EULA`. By using, installing,
-copying or distributing AQL Profiler and/or AOCC CPU Optimizations, you agree to
-the terms and conditions of this license agreement. If you do not agree to the
-terms of this agreement, do not install, copy or use the AQL Profiler and/or the
-AOCC CPU Optimizations.
-:::
-
-For the rest of the ROCm packages, you can find the licensing information at the
-following location: `/opt/rocm/share/doc/<component-name>/` or in the locations
-specified in the preceding table.
-
-For example, you can fetch the licensing information of the `amd_comgr`
-component (Code Object Manager) from the `/opt/rocm/share/doc/amd_comgr/LICENSE.txt` file.
--- a/docs/compatibility/compatibility-matrix-historical-6.0.csv
+++ b/docs/compatibility/compatibility-matrix-historical-6.0.csv
@@ -1,126 +0,0 @@
-ROCm Version,6.4.1,6.4.0,6.3.3,6.3.2,6.3.1,6.3.0,6.2.4,6.2.2,6.2.1,6.2.0, 6.1.5, 6.1.2, 6.1.1, 6.1.0, 6.0.2, 6.0.0
-      :ref:`Operating systems & kernels <OS-kernel-versions>`,Ubuntu 24.04.2,Ubuntu 24.04.2,Ubuntu 24.04.2,Ubuntu 24.04.2,Ubuntu 24.04.2,Ubuntu 24.04.2,"Ubuntu 24.04.1, 24.04","Ubuntu 24.04.1, 24.04","Ubuntu 24.04.1, 24.04",Ubuntu 24.04,,,,,,
-      ,Ubuntu 22.04.5,Ubuntu 22.04.5,Ubuntu 22.04.5,Ubuntu 22.04.5,Ubuntu 22.04.5,Ubuntu 22.04.5,"Ubuntu 22.04.5, 22.04.4","Ubuntu 22.04.5, 22.04.4","Ubuntu 22.04.5, 22.04.4","Ubuntu 22.04.5, 22.04.4","Ubuntu 22.04.5, 22.04.4, 22.04.3","Ubuntu 22.04.4, 22.04.3","Ubuntu 22.04.4, 22.04.3","Ubuntu 22.04.4, 22.04.3","Ubuntu 22.04.4, 22.04.3, 22.04.2","Ubuntu 22.04.4, 22.04.3, 22.04.2"
-      ,,,,,,,,,,,"Ubuntu 20.04.6, 20.04.5","Ubuntu 20.04.6, 20.04.5","Ubuntu 20.04.6, 20.04.5","Ubuntu 20.04.6, 20.04.5","Ubuntu 20.04.6, 20.04.5","Ubuntu 20.04.6, 20.04.5"
-      ,"RHEL 9.6, 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.4, 9.3","RHEL 9.4, 9.3","RHEL 9.4, 9.3","RHEL 9.4, 9.3","RHEL 9.4, 9.3, 9.2","RHEL 9.4, 9.3, 9.2","RHEL 9.4, 9.3, 9.2","RHEL 9.4, 9.3, 9.2","RHEL 9.3, 9.2","RHEL 9.3, 9.2"
-      ,RHEL 8.10,RHEL 8.10,RHEL 8.10,RHEL 8.10,RHEL 8.10,RHEL 8.10,"RHEL 8.10, 8.9","RHEL 8.10, 8.9","RHEL 8.10, 8.9","RHEL 8.10, 8.9","RHEL 8.9, 8.8","RHEL 8.9, 8.8","RHEL 8.9, 8.8","RHEL 8.9, 8.8","RHEL 8.9, 8.8","RHEL 8.9, 8.8"
-      ,SLES 15 SP6,SLES 15 SP6,"SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP6, SP5","SLES 15 SP5, SP4","SLES 15 SP5, SP4","SLES 15 SP5, SP4","SLES 15 SP5, SP4","SLES 15 SP5, SP4","SLES 15 SP5, SP4"
-      ,,,,,,,,,,,,CentOS 7.9,CentOS 7.9,CentOS 7.9,CentOS 7.9,CentOS 7.9
-      ,"Oracle Linux 9, 8 [#mi300x-past-60]_","Oracle Linux 9, 8 [#mi300x-past-60]_",Oracle Linux 8.10 [#mi300x-past-60]_,Oracle Linux 8.10 [#mi300x-past-60]_,Oracle Linux 8.10 [#mi300x-past-60]_,Oracle Linux 8.10 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,Oracle Linux 8.9 [#mi300x-past-60]_,,,
-      ,Debian 12 [#single-node-past-60]_,Debian 12 [#single-node-past-60]_,Debian 12 [#single-node-past-60]_,Debian 12 [#single-node-past-60]_,Debian 12 [#single-node-past-60]_,,,,,,,,,,,
-      ,Azure Linux 3.0 [#mi300x-past-60]_,Azure Linux 3.0 [#mi300x-past-60]_,Azure Linux 3.0 [#mi300x-past-60]_,Azure Linux 3.0 [#mi300x-past-60]_,,,,,,,,,,,,
-      ,.. _architecture-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`Architecture <rocm-install-on-linux:reference/system-requirements>`,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3,CDNA3
-      ,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2,CDNA2
-      ,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA,CDNA
-      ,RDNA4,,,,,,,,,,,,,,,
-      ,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3,RDNA3
-      ,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2,RDNA2
-      ,.. _gpu-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`GPU / LLVM target <rocm-install-on-linux:reference/system-requirements>`,gfx1201 [#RDNA-OS-past-60]_,,,,,,,,,,,,,,,
-      ,gfx1200 [#RDNA-OS-past-60]_,,,,,,,,,,,,,,,
-,gfx1101 [#RDNA-OS-past-60]_,,,,,,,,,,,,,,,
-      ,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100,gfx1100
-      ,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030,gfx1030
-      ,gfx942,gfx942,gfx942,gfx942,gfx942,gfx942,gfx942 [#mi300_624-past-60]_,gfx942 [#mi300_622-past-60]_,gfx942 [#mi300_621-past-60]_,gfx942 [#mi300_620-past-60]_, gfx942 [#mi300_612-past-60]_, gfx942 [#mi300_612-past-60]_, gfx942 [#mi300_611-past-60]_, gfx942 [#mi300_610-past-60]_, gfx942 [#mi300_602-past-60]_, gfx942 [#mi300_600-past-60]_
-      ,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a,gfx90a
-      ,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908,gfx908
-,,,,,,,,,,,,,,,,
-      FRAMEWORK SUPPORT,.. _framework-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`PyTorch <../compatibility/ml-compatibility/pytorch-compatibility>`,"2.6, 2.5, 2.4, 2.3","2.6, 2.5, 2.4, 2.3","2.4, 2.3, 2.2, 1.13","2.4, 2.3, 2.2, 1.13","2.4, 2.3, 2.2, 1.13","2.4, 2.3, 2.2, 2.1, 2.0, 1.13","2.3, 2.2, 2.1, 2.0, 1.13","2.3, 2.2, 2.1, 2.0, 1.13","2.3, 2.2, 2.1, 2.0, 1.13","2.3, 2.2, 2.1, 2.0, 1.13","2.1, 2.0, 1.13","2.1, 2.0, 1.13","2.1, 2.0, 1.13","2.1, 2.0, 1.13","2.1, 2.0, 1.13","2.1, 2.0, 1.13"
-      :doc:`TensorFlow <../compatibility/ml-compatibility/tensorflow-compatibility>`,"2.18.1, 2.17.1, 2.16.2","2.18.1, 2.17.1, 2.16.2","2.17.0, 2.16.2, 2.15.1","2.17.0, 2.16.2, 2.15.1","2.17.0, 2.16.2, 2.15.1","2.17.0, 2.16.2, 2.15.1","2.16.1, 2.15.1, 2.14.1","2.16.1, 2.15.1, 2.14.1","2.16.1, 2.15.1, 2.14.1","2.16.1, 2.15.1, 2.14.1","2.15.0, 2.14.0, 2.13.1","2.15.0, 2.14.0, 2.13.1","2.15.0, 2.14.0, 2.13.1","2.15.0, 2.14.0, 2.13.1","2.14.0, 2.13.1, 2.12.1","2.14.0, 2.13.1, 2.12.1"
-      :doc:`JAX <../compatibility/ml-compatibility/jax-compatibility>`,0.4.35,0.4.35,0.4.31,0.4.31,0.4.31,0.4.31,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26,0.4.26
-      `ONNX Runtime <https://onnxruntime.ai/docs/build/eps.html#amd-migraphx>`_,1.2,1.2,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.17.3,1.14.1,1.14.1
-,,,,,,,,,,,,,,,,
-      ,,,,,,,,,,,,,,,,
-      THIRD PARTY COMMS,.. _thirdpartycomms-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      `UCC <https://github.com/ROCm/ucc>`_,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.3.0,>=1.2.0,>=1.2.0
-      `UCX <https://github.com/ROCm/ucx>`_,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.15.0,>=1.14.1,>=1.14.1,>=1.14.1,>=1.14.1,>=1.14.1,>=1.14.1
-      ,,,,,,,,,,,,,,,,
-      THIRD PARTY ALGORITHM,.. _thirdpartyalgorithm-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      Thrust,2.5.0,2.5.0,2.3.2,2.3.2,2.3.2,2.3.2,2.2.0,2.2.0,2.2.0,2.2.0,2.1.0,2.1.0,2.1.0,2.1.0,2.0.1,2.0.1
-      CUB,2.5.0,2.5.0,2.3.2,2.3.2,2.3.2,2.3.2,2.2.0,2.2.0,2.2.0,2.2.0,2.1.0,2.1.0,2.1.0,2.1.0,2.0.1,2.0.1
-,,,,,,,,,,,,,,,,
-      KMD & USER SPACE [#kfd_support-past-60]_,.. _kfd-userspace-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`KMD versions <rocm-install-on-linux:reference/user-kernel-space-compat-matrix>`,"6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x, 5.7.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x, 5.7.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x, 5.7.x","6.4.x, 6.3.x, 6.2.x, 6.1.x, 6.0.x, 5.7.x","6.2.x, 6.1.x, 6.0.x, 5.7.x, 5.6.x","6.2.x, 6.1.x, 6.0.x, 5.7.x, 5.6.x"
-      ,,,,,,,,,,,,,,,,
-      ML & COMPUTER VISION,.. _mllibs-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`Composable Kernel <composable_kernel:index>`,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0
-      :doc:`MIGraphX <amdmigraphx:index>`,2.12.0,2.12.0,2.11.0,2.11.0,2.11.0,2.11.0,2.10.0,2.10.0,2.10.0,2.10.0,2.9.0,2.9.0,2.9.0,2.9.0,2.8.0,2.8.0
-      :doc:`MIOpen <miopen:index>`,3.4.0,3.4.0,3.3.0,3.3.0,3.3.0,3.3.0,3.2.0,3.2.0,3.2.0,3.2.0,3.1.0,3.1.0,3.1.0,3.1.0,3.0.0,3.0.0
-      :doc:`MIVisionX <mivisionx:index>`,3.2.0,3.2.0,3.1.0,3.1.0,3.1.0,3.1.0,3.0.0,3.0.0,3.0.0,3.0.0,2.5.0,2.5.0,2.5.0,2.5.0,2.5.0,2.5.0
-      :doc:`rocAL <rocal:index>`,2.2.0,2.2.0,2.1.0,2.1.0,2.1.0,2.1.0,2.0.0,2.0.0,2.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0
-      :doc:`rocDecode <rocdecode:index>`,0.10.0,0.10.0,0.8.0,0.8.0,0.8.0,0.8.0,0.6.0,0.6.0,0.6.0,0.6.0,0.6.0,0.6.0,0.5.0,0.5.0,N/A,N/A
-      :doc:`rocJPEG <rocjpeg:index>`,0.8.0,0.8.0,0.6.0,0.6.0,0.6.0,0.6.0,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
-      :doc:`rocPyDecode <rocpydecode:index>`,0.3.1,0.3.1,0.2.0,0.2.0,0.2.0,0.2.0,0.1.0,0.1.0,0.1.0,0.1.0,N/A,N/A,N/A,N/A,N/A,N/A
-      :doc:`RPP <rpp:index>`,1.9.10,1.9.10,1.9.1,1.9.1,1.9.1,1.9.1,1.8.0,1.8.0,1.8.0,1.8.0,1.5.0,1.5.0,1.5.0,1.5.0,1.4.0,1.4.0
-      ,,,,,,,,,,,,,,,,
-      COMMUNICATION,.. _commlibs-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`RCCL <rccl:index>`,2.22.3,2.22.3,2.21.5,2.21.5,2.21.5,2.21.5,2.20.5,2.20.5,2.20.5,2.20.5,2.18.6,2.18.6,2.18.6,2.18.6,2.18.3,2.18.3
-      :doc:`rocSHMEM <rocshmem:index>`,2.0.0,2.0.0,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
-      ,,,,,,,,,,,,,,,,
-      MATH LIBS,.. _mathlibs-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      `half <https://github.com/ROCm/half>`_ ,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0,1.12.0
-      :doc:`hipBLAS <hipblas:index>`,2.4.0,2.4.0,2.3.0,2.3.0,2.3.0,2.3.0,2.2.0,2.2.0,2.2.0,2.2.0,2.1.0,2.1.0,2.1.0,2.1.0,2.0.0,2.0.0
-      :doc:`hipBLASLt <hipblaslt:index>`,0.12.1,0.12.0,0.10.0,0.10.0,0.10.0,0.10.0,0.8.0,0.8.0,0.8.0,0.8.0,0.7.0,0.7.0,0.7.0,0.7.0,0.6.0,0.6.0
-      :doc:`hipFFT <hipfft:index>`,1.0.18,1.0.18,1.0.17,1.0.17,1.0.17,1.0.17,1.0.16,1.0.15,1.0.15,1.0.14,1.0.14,1.0.14,1.0.14,1.0.14,1.0.13,1.0.13
-      :doc:`hipfort <hipfort:index>`,0.6.0,0.6.0,0.5.1,0.5.1,0.5.0,0.5.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0
-      :doc:`hipRAND <hiprand:index>`,2.12.0,2.12.0,2.11.1,2.11.1,2.11.1,2.11.0,2.11.1,2.11.0,2.11.0,2.11.0,2.10.16,2.10.16,2.10.16,2.10.16,2.10.16,2.10.16
-      :doc:`hipSOLVER <hipsolver:index>`,2.4.0,2.4.0,2.3.0,2.3.0,2.3.0,2.3.0,2.2.0,2.2.0,2.2.0,2.2.0,2.1.1,2.1.1,2.1.1,2.1.0,2.0.0,2.0.0
-      :doc:`hipSPARSE <hipsparse:index>`,3.2.0,3.2.0,3.1.2,3.1.2,3.1.2,3.1.2,3.1.1,3.1.1,3.1.1,3.1.1,3.0.1,3.0.1,3.0.1,3.0.1,3.0.0,3.0.0
-      :doc:`hipSPARSELt <hipsparselt:index>`,0.2.3,0.2.3,0.2.2,0.2.2,0.2.2,0.2.2,0.2.1,0.2.1,0.2.1,0.2.1,0.2.0,0.2.0,0.1.0,0.1.0,0.1.0,0.1.0
-      :doc:`rocALUTION <rocalution:index>`,3.2.3,3.2.2,3.2.1,3.2.1,3.2.1,3.2.1,3.2.1,3.2.0,3.2.0,3.2.0,3.1.1,3.1.1,3.1.1,3.1.1,3.0.3,3.0.3
-      :doc:`rocBLAS <rocblas:index>`,4.4.0,4.4.0,4.3.0,4.3.0,4.3.0,4.3.0,4.2.4,4.2.1,4.2.1,4.2.0,4.1.2,4.1.2,4.1.0,4.1.0,4.0.0,4.0.0
-      :doc:`rocFFT <rocfft:index>`,1.0.32,1.0.32,1.0.31,1.0.31,1.0.31,1.0.31,1.0.30,1.0.29,1.0.29,1.0.28,1.0.27,1.0.27,1.0.27,1.0.26,1.0.25,1.0.23
-      :doc:`rocRAND <rocrand:index>`,3.3.0,3.3.0,3.2.0,3.2.0,3.2.0,3.2.0,3.1.1,3.1.0,3.1.0,3.1.0,3.0.1,3.0.1,3.0.1,3.0.1,3.0.0,2.10.17
-      :doc:`rocSOLVER <rocsolver:index>`,3.28.0,3.28.0,3.27.0,3.27.0,3.27.0,3.27.0,3.26.2,3.26.0,3.26.0,3.26.0,3.25.0,3.25.0,3.25.0,3.25.0,3.24.0,3.24.0
-      :doc:`rocSPARSE <rocsparse:index>`,3.4.0,3.4.0,3.3.0,3.3.0,3.3.0,3.3.0,3.2.1,3.2.0,3.2.0,3.2.0,3.1.2,3.1.2,3.1.2,3.1.2,3.0.2,3.0.2
-      :doc:`rocWMMA <rocwmma:index>`,1.7.0,1.7.0,1.6.0,1.6.0,1.6.0,1.6.0,1.5.0,1.5.0,1.5.0,1.5.0,1.4.0,1.4.0,1.4.0,1.4.0,1.3.0,1.3.0
-      :doc:`Tensile <tensile:src/index>`,4.43.0,4.43.0,4.42.0,4.42.0,4.42.0,4.42.0,4.41.0,4.41.0,4.41.0,4.41.0,4.40.0,4.40.0,4.40.0,4.40.0,4.39.0,4.39.0
-      ,,,,,,,,,,,,,,,,
-      PRIMITIVES,.. _primitivelibs-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`hipCUB <hipcub:index>`,3.4.0,3.4.0,3.3.0,3.3.0,3.3.0,3.3.0,3.2.1,3.2.0,3.2.0,3.2.0,3.1.0,3.1.0,3.1.0,3.1.0,3.0.0,3.0.0
-      :doc:`hipTensor <hiptensor:index>`,1.5.0,1.5.0,1.4.0,1.4.0,1.4.0,1.4.0,1.3.0,1.3.0,1.3.0,1.3.0,1.2.0,1.2.0,1.2.0,1.2.0,1.1.0,1.1.0
-      :doc:`rocPRIM <rocprim:index>`,3.4.0,3.4.0,3.3.0,3.3.0,3.3.0,3.3.0,3.2.2,3.2.0,3.2.0,3.2.0,3.1.0,3.1.0,3.1.0,3.1.0,3.0.0,3.0.0
-      :doc:`rocThrust <rocthrust:index>`,3.3.0,3.3.0,3.3.0,3.3.0,3.3.0,3.3.0,3.1.1,3.1.0,3.1.0,3.0.1,3.0.1,3.0.1,3.0.1,3.0.1,3.0.0,3.0.0
-      ,,,,,,,,,,,,,,,,
-      SUPPORT LIBS,,,,,,,,,,,,,,,,
-      `hipother <https://github.com/ROCm/hipother>`_,6.4.43483,6.4.43482,6.3.42134,6.3.42134,6.3.42133,6.3.42131,6.2.41134,6.2.41134,6.2.41134,6.2.41133,6.1.40093,6.1.40093,6.1.40092,6.1.40091,6.1.32831,6.1.32830
-      `rocm-core <https://github.com/ROCm/rocm-core>`_,6.4.1,6.4.0,6.3.3,6.3.2,6.3.1,6.3.0,6.2.4,6.2.2,6.2.1,6.2.0,6.1.5,6.1.2,6.1.1,6.1.0,6.0.2,6.0.0
-      `ROCT-Thunk-Interface <https://github.com/ROCm/ROCT-Thunk-Interface>`_,N/A [#ROCT-rocr-past-60]_,N/A [#ROCT-rocr-past-60]_,N/A [#ROCT-rocr-past-60]_,N/A [#ROCT-rocr-past-60]_,N/A [#ROCT-rocr-past-60]_,N/A [#ROCT-rocr-past-60]_,20240607.5.7,20240607.5.7,20240607.4.05,20240607.1.4246,20240125.5.08,20240125.5.08,20240125.5.08,20240125.3.30,20231016.2.245,20231016.2.245
-      ,,,,,,,,,,,,,,,,
-      SYSTEM MGMT TOOLS,.. _tools-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`AMD SMI <amdsmi:index>`,25.4.2,25.3.0,24.7.1,24.7.1,24.7.1,24.7.1,24.6.3,24.6.3,24.6.3,24.6.2,24.5.1,24.5.1,24.5.1,24.4.1,23.4.2,23.4.2
-      :doc:`ROCm Data Center Tool <rdc:index>`,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0,0.3.0
-      :doc:`rocminfo <rocminfo:index>`,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0
-      :doc:`ROCm SMI <rocm_smi_lib:index>`,7.5.0,7.5.0,7.4.0,7.4.0,7.4.0,7.4.0,7.3.0,7.3.0,7.3.0,7.3.0,7.2.0,7.2.0,7.0.0,7.0.0,6.0.2,6.0.0
-      :doc:`ROCm Validation Suite <rocmvalidationsuite:index>`,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.1.0,1.0.60204,1.0.60202,1.0.60201,1.0.60200,1.0.60105,1.0.60102,1.0.60101,1.0.60100,1.0.60002,1.0.60000
-      ,,,,,,,,,,,,,,,,
-      PERFORMANCE TOOLS,,,,,,,,,,,,,,,,
-      :doc:`ROCm Bandwidth Test <rocm_bandwidth_test:index>`,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0,1.4.0
-      :doc:`ROCm Compute Profiler <rocprofiler-compute:index>`,3.1.0,3.1.0,3.0.0,3.0.0,3.0.0,3.0.0,2.0.1,2.0.1,2.0.1,2.0.1,N/A,N/A,N/A,N/A,N/A,N/A
-      :doc:`ROCm Systems Profiler <rocprofiler-systems:index>`,1.0.1,1.0.0,0.1.2,0.1.1,0.1.0,0.1.0,1.11.2,1.11.2,1.11.2,1.11.2,N/A,N/A,N/A,N/A,N/A,N/A
-      :doc:`ROCProfiler <rocprofiler:index>`,2.0.60401,2.0.60400,2.0.60303,2.0.60302,2.0.60301,2.0.60300,2.0.60204,2.0.60202,2.0.60201,2.0.60200,2.0.60105,2.0.60102,2.0.60101,2.0.60100,2.0.60002,2.0.60000
-      :doc:`ROCprofiler-SDK <rocprofiler-sdk:index>`,0.6.0,0.6.0,0.5.0,0.5.0,0.5.0,0.5.0,0.4.0,0.4.0,0.4.0,0.4.0,N/A,N/A,N/A,N/A,N/A,N/A
-      :doc:`ROCTracer <roctracer:index>`,4.1.60401,4.1.60400,4.1.60303,4.1.60302,4.1.60301,4.1.60300,4.1.60204,4.1.60202,4.1.60201,4.1.60200,4.1.60105,4.1.60102,4.1.60101,4.1.60100,4.1.60002,4.1.60000
-      ,,,,,,,,,,,,,,,,
-      DEVELOPMENT TOOLS,,,,,,,,,,,,,,,,
-      :doc:`HIPIFY <hipify:index>`,19.0.0,19.0.0,18.0.0.25012,18.0.0.25012,18.0.0.24491,18.0.0.24455,18.0.0.24392,18.0.0.24355,18.0.0.24355,18.0.0.24232,17.0.0.24193,17.0.0.24193,17.0.0.24154,17.0.0.24103,17.0.0.24012,17.0.0.23483
-      :doc:`ROCm CMake <rocmcmakebuildtools:index>`,0.14.0,0.14.0,0.14.0,0.14.0,0.14.0,0.14.0,0.13.0,0.13.0,0.13.0,0.13.0,0.12.0,0.12.0,0.12.0,0.12.0,0.11.0,0.11.0
-      :doc:`ROCdbgapi <rocdbgapi:index>`,0.77.2,0.77.2,0.77.0,0.77.0,0.77.0,0.77.0,0.76.0,0.76.0,0.76.0,0.76.0,0.71.0,0.71.0,0.71.0,0.71.0,0.71.0,0.71.0
-      :doc:`ROCm Debugger (ROCgdb) <rocgdb:index>`,15.2.0,15.2.0,15.2.0,15.2.0,15.2.0,15.2.0,14.2.0,14.2.0,14.2.0,14.2.0,14.1.0,14.1.0,14.1.0,14.1.0,13.2.0,13.2.0
-      `rocprofiler-register <https://github.com/ROCm/rocprofiler-register>`_,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.4.0,0.3.0,0.3.0,0.3.0,0.3.0,N/A,N/A
-      :doc:`ROCr Debug Agent <rocr_debug_agent:index>`,2.0.4,2.0.4,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3,2.0.3
-      ,,,,,,,,,,,,,,,,
-      COMPILERS,.. _compilers-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      `clang-ocl <https://github.com/ROCm/clang-ocl>`_,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,0.5.0,0.5.0,0.5.0,0.5.0,0.5.0,0.5.0
-      :doc:`hipCC <hipcc:index>`,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.1.1,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0,1.0.0
-      `Flang <https://github.com/ROCm/flang>`_,19.0.0.25184,19.0.0.25133,18.0.0.25012,18.0.0.25012,18.0.0.24491,18.0.0.24455,18.0.0.24392,18.0.0.24355,18.0.0.24355,18.0.0.24232,17.0.0.24193,17.0.0.24193,17.0.0.24154,17.0.0.24103,17.0.0.24012,17.0.0.23483
-      :doc:`llvm-project <llvm-project:index>`,19.0.0.25184,19.0.0.25133,18.0.0.25012,18.0.0.25012,18.0.0.24491,18.0.0.24491,18.0.0.24392,18.0.0.24355,18.0.0.24355,18.0.0.24232,17.0.0.24193,17.0.0.24193,17.0.0.24154,17.0.0.24103,17.0.0.24012,17.0.0.23483
-      `OpenMP <https://github.com/ROCm/llvm-project/tree/amd-staging/openmp>`_,19.0.0.25184,19.0.0.25133,18.0.0.25012,18.0.0.25012,18.0.0.24491,18.0.0.24491,18.0.0.24392,18.0.0.24355,18.0.0.24355,18.0.0.24232,17.0.0.24193,17.0.0.24193,17.0.0.24154,17.0.0.24103,17.0.0.24012,17.0.0.23483
-,,,,,,,,,,,,,,,,
-      RUNTIMES,.. _runtime-support-compatibility-matrix-past-60:,,,,,,,,,,,,,,,
-      :doc:`AMD CLR <hip:understand/amd_clr>`,6.4.43483,6.4.43482,6.3.42134,6.3.42134,6.3.42133,6.3.42131,6.2.41134,6.2.41134,6.2.41134,6.2.41133,6.1.40093,6.1.40093,6.1.40092,6.1.40091,6.1.32831,6.1.32830
-      :doc:`HIP <hip:index>`,6.4.43483,6.4.43482,6.3.42134,6.3.42134,6.3.42133,6.3.42131,6.2.41134,6.2.41134,6.2.41134,6.2.41133,6.1.40093,6.1.40093,6.1.40092,6.1.40091,6.1.32831,6.1.32830
-      `OpenCL Runtime <https://github.com/ROCm/clr/tree/develop/opencl>`_,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0,2.0.0
-      :doc:`ROCr Runtime <rocr-runtime:index>`,1.15.0,1.15.0,1.14.0,1.14.0,1.14.0,1.14.0,1.14.0,1.14.0,1.14.0,1.13.0,1.13.0,1.13.0,1.13.0,1.13.0,1.12.0,1.12.0
--- a/docs/compatibility/compatibility-matrix.rst
+++ b/docs/compatibility/compatibility-matrix.rst
@@ -1,240 +0,0 @@
-.. meta::
-    :description: ROCm compatibility matrix
-    :keywords: GPU, architecture, hardware, compatibility, system, requirements, components, libraries
-
-**************************************************************************************
-Compatibility matrix
-**************************************************************************************
-
-Use this matrix to view the ROCm compatibility and system requirements across successive major and minor releases.
-
-You can also refer to the :ref:`past versions of ROCm compatibility matrix<past-rocm-compatibility-matrix>`.
-
-Accelerators and GPUs listed in the following table support compute workloads (no display
-information or graphics). If you’re using ROCm with AMD Radeon or Radeon Pro GPUs for graphics
-workloads, see the `Use ROCm on Radeon GPU documentation
-<https://rocm.docs.amd.com/projects/radeon/en/latest/docs/compatibility.html>`_ to verify
-compatibility and system requirements.
-
-.. |br| raw:: html
-
-   <br/>
-
-.. container:: format-big-table
-
-  .. csv-table::
-      :header: "ROCm Version", "6.4.1", "6.4.0", "6.3.0"
-      :stub-columns: 1
-
-      :ref:`Operating systems & kernels <OS-kernel-versions>`,Ubuntu 24.04.2,Ubuntu 24.04.2,Ubuntu 24.04.2
-      ,Ubuntu 22.04.5,Ubuntu 22.04.5,Ubuntu 22.04.5
-      ,"RHEL 9.6, 9.5, 9.4","RHEL 9.5, 9.4","RHEL 9.5, 9.4"
-      ,RHEL 8.10,RHEL 8.10,RHEL 8.10
-      ,SLES 15 SP6,SLES 15 SP6,"SLES 15 SP6, SP5"
-      ,"Oracle Linux 9, 8 [#mi300x]_","Oracle Linux 9, 8 [#mi300x]_",Oracle Linux 8.10 [#mi300x]_
-      ,Debian 12 [#single-node]_,Debian 12 [#single-node]_,
-      ,Azure Linux 3.0 [#mi300x]_,Azure Linux 3.0 [#mi300x]_,
-      ,.. _architecture-support-compatibility-matrix:,,
-      :doc:`Architecture <rocm-install-on-linux:reference/system-requirements>`,CDNA3,CDNA3,CDNA3
-      ,CDNA2,CDNA2,CDNA2
-      ,CDNA,CDNA,CDNA
-      ,RDNA4,,
-      ,RDNA3,RDNA3,RDNA3
-      ,RDNA2,RDNA2,RDNA2
-      ,.. _gpu-support-compatibility-matrix:,,
-      :doc:`GPU / LLVM target <rocm-install-on-linux:reference/system-requirements>`,gfx1201 [#RDNA-OS]_,,
-      ,gfx1200 [#RDNA-OS]_,,
-      ,gfx1101 [#RDNA-OS]_,,
-      ,gfx1100,gfx1100,gfx1100
-      ,gfx1030,gfx1030,gfx1030
-      ,gfx942,gfx942,gfx942
-      ,gfx90a,gfx90a,gfx90a
-      ,gfx908,gfx908,gfx908
-      ,,,
-      FRAMEWORK SUPPORT,.. _framework-support-compatibility-matrix:,,
-      :doc:`PyTorch <../compatibility/ml-compatibility/pytorch-compatibility>`,"2.6, 2.5, 2.4, 2.3","2.6, 2.5, 2.4, 2.3","2.4, 2.3, 2.2, 2.1, 2.0, 1.13"
-      :doc:`TensorFlow <../compatibility/ml-compatibility/tensorflow-compatibility>`,"2.18.1, 2.17.1, 2.16.2","2.18.1, 2.17.1, 2.16.2","2.17.0, 2.16.2, 2.15.1"
-      :doc:`JAX <../compatibility/ml-compatibility/jax-compatibility>`,0.4.35,0.4.35,0.4.31
-      `ONNX Runtime <https://onnxruntime.ai/docs/build/eps.html#amd-migraphx>`_,1.2,1.2,1.17.3
-      ,,,
-      THIRD PARTY COMMS,.. _thirdpartycomms-support-compatibility-matrix:,,
-      `UCC <https://github.com/ROCm/ucc>`_,>=1.3.0,>=1.3.0,>=1.3.0
-      `UCX <https://github.com/ROCm/ucx>`_,>=1.15.0,>=1.15.0,>=1.15.0
-      ,,,
-      THIRD PARTY ALGORITHM,.. _thirdpartyalgorithm-support-compatibility-matrix:,,
-      Thrust,2.5.0,2.5.0,2.3.2
-      CUB,2.5.0,2.5.0,2.3.2
-      ,,,
-      KMD & USER SPACE [#kfd_support]_,.. _kfd-userspace-support-compatibility-matrix:,,
-      :doc:`KMD versions <rocm-install-on-linux:reference/user-kernel-space-compat-matrix>`,"6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x","6.4.x, 6.3.x, 6.2.x, 6.1.x"
-      ,,,
-      ML & COMPUTER VISION,.. _mllibs-support-compatibility-matrix:,,
-      :doc:`Composable Kernel <composable_kernel:index>`,1.1.0,1.1.0,1.1.0
-      :doc:`MIGraphX <amdmigraphx:index>`,2.12.0,2.12.0,2.11.0
-      :doc:`MIOpen <miopen:index>`,3.4.0,3.4.0,3.3.0
-      :doc:`MIVisionX <mivisionx:index>`,3.2.0,3.2.0,3.1.0
-      :doc:`rocAL <rocal:index>`,2.2.0,2.2.0,2.1.0
-      :doc:`rocDecode <rocdecode:index>`,0.10.0,0.10.0,0.8.0
-      :doc:`rocJPEG <rocjpeg:index>`,0.8.0,0.8.0,0.6.0
-      :doc:`rocPyDecode <rocpydecode:index>`,0.3.1,0.3.1,0.2.0
-      :doc:`RPP <rpp:index>`,1.9.10,1.9.10,1.9.1
-      ,,,
-      COMMUNICATION,.. _commlibs-support-compatibility-matrix:,,
-      :doc:`RCCL <rccl:index>`,2.22.3,2.22.3,2.21.5
-      :doc:`rocSHMEM <rocshmem:index>`,2.0.0,2.0.0,N/A
-      ,,,
-      MATH LIBS,.. _mathlibs-support-compatibility-matrix:,,
-      `half <https://github.com/ROCm/half>`_ ,1.12.0,1.12.0,1.12.0
-      :doc:`hipBLAS <hipblas:index>`,2.4.0,2.4.0,2.3.0
-      :doc:`hipBLASLt <hipblaslt:index>`,0.12.1,0.12.0,0.10.0
-      :doc:`hipFFT <hipfft:index>`,1.0.18,1.0.18,1.0.17
-      :doc:`hipfort <hipfort:index>`,0.6.0,0.6.0,0.5.0
-      :doc:`hipRAND <hiprand:index>`,2.12.0,2.12.0,2.11.0
-      :doc:`hipSOLVER <hipsolver:index>`,2.4.0,2.4.0,2.3.0
-      :doc:`hipSPARSE <hipsparse:index>`,3.2.0,3.2.0,3.1.2
-      :doc:`hipSPARSELt <hipsparselt:index>`,0.2.3,0.2.3,0.2.2
-      :doc:`rocALUTION <rocalution:index>`,3.2.3,3.2.2,3.2.1
-      :doc:`rocBLAS <rocblas:index>`,4.4.0,4.4.0,4.3.0
-      :doc:`rocFFT <rocfft:index>`,1.0.32,1.0.32,1.0.31
-      :doc:`rocRAND <rocrand:index>`,3.3.0,3.3.0,3.2.0
-      :doc:`rocSOLVER <rocsolver:index>`,3.28.0,3.28.0,3.27.0
-      :doc:`rocSPARSE <rocsparse:index>`,3.4.0,3.4.0,3.3.0
-      :doc:`rocWMMA <rocwmma:index>`,1.7.0,1.7.0,1.6.0
-      :doc:`Tensile <tensile:src/index>`,4.43.0,4.43.0,4.42.0
-      ,,,
-      PRIMITIVES,.. _primitivelibs-support-compatibility-matrix:,,
-      :doc:`hipCUB <hipcub:index>`,3.4.0,3.4.0,3.3.0
-      :doc:`hipTensor <hiptensor:index>`,1.5.0,1.5.0,1.4.0
-      :doc:`rocPRIM <rocprim:index>`,3.4.0,3.4.0,3.3.0
-      :doc:`rocThrust <rocthrust:index>`,3.3.0,3.3.0,3.3.0
-      ,,,
-      SUPPORT LIBS,,,
-      `hipother <https://github.com/ROCm/hipother>`_,6.4.43483,6.4.43482,6.3.42131
-      `rocm-core <https://github.com/ROCm/rocm-core>`_,6.4.1,6.4.0,6.3.0
-      `ROCT-Thunk-Interface <https://github.com/ROCm/ROCT-Thunk-Interface>`_,N/A [#ROCT-rocr]_,N/A [#ROCT-rocr]_,N/A [#ROCT-rocr]_
-      ,,,
-      SYSTEM MGMT TOOLS,.. _tools-support-compatibility-matrix:,,
-      :doc:`AMD SMI <amdsmi:index>`,25.4.2,25.3.0,24.7.1
-      :doc:`ROCm Data Center Tool <rdc:index>`,0.3.0,0.3.0,0.3.0
-      :doc:`rocminfo <rocminfo:index>`,1.0.0,1.0.0,1.0.0
-      :doc:`ROCm SMI <rocm_smi_lib:index>`,7.5.0,7.5.0,7.4.0
-      :doc:`ROCm Validation Suite <rocmvalidationsuite:index>`,1.1.0,1.1.0,1.1.0
-      ,,,
-      PERFORMANCE TOOLS,,,
-      :doc:`ROCm Bandwidth Test <rocm_bandwidth_test:index>`,1.4.0,1.4.0,1.4.0
-      :doc:`ROCm Compute Profiler <rocprofiler-compute:index>`,3.1.0,3.1.0,3.0.0
-      :doc:`ROCm Systems Profiler <rocprofiler-systems:index>`,1.0.1,1.0.0,0.1.0
-      :doc:`ROCProfiler <rocprofiler:index>`,2.0.60401,2.0.60400,2.0.60300
-      :doc:`ROCprofiler-SDK <rocprofiler-sdk:index>`,0.6.0,0.6.0,0.5.0
-      :doc:`ROCTracer <roctracer:index>`,4.1.60401,4.1.60400,4.1.60300
-      ,,,
-      DEVELOPMENT TOOLS,,,
-      :doc:`HIPIFY <hipify:index>`,19.0.0,19.0.0,18.0.0.24455
-      :doc:`ROCm CMake <rocmcmakebuildtools:index>`,0.14.0,0.14.0,0.14.0
-      :doc:`ROCdbgapi <rocdbgapi:index>`,0.77.2,0.77.2,0.77.0
-      :doc:`ROCm Debugger (ROCgdb) <rocgdb:index>`,15.2.0,15.2.0,15.2.0
-      `rocprofiler-register <https://github.com/ROCm/rocprofiler-register>`_,0.4.0,0.4.0,0.4.0
-      :doc:`ROCr Debug Agent <rocr_debug_agent:index>`,2.0.4,2.0.4,2.0.3
-      ,,,
-      COMPILERS,.. _compilers-support-compatibility-matrix:,,
-      `clang-ocl <https://github.com/ROCm/clang-ocl>`_,N/A,N/A,N/A
-      :doc:`hipCC <hipcc:index>`,1.1.1,1.1.1,1.1.1
-      `Flang <https://github.com/ROCm/flang>`_,19.0.0.25184,19.0.0.25133,18.0.0.24455
-      :doc:`llvm-project <llvm-project:index>`,19.0.0.25184,19.0.0.25133,18.0.0.24491
-      `OpenMP <https://github.com/ROCm/llvm-project/tree/amd-staging/openmp>`_,19.0.0.25184,19.0.0.25133,18.0.0.24491
-      ,,,
-      RUNTIMES,.. _runtime-support-compatibility-matrix:,,
-      :doc:`AMD CLR <hip:understand/amd_clr>`,6.4.43483,6.4.43482,6.3.42131
-      :doc:`HIP <hip:index>`,6.4.43483,6.4.43482,6.3.42131
-      `OpenCL Runtime <https://github.com/ROCm/clr/tree/develop/opencl>`_,2.0.0,2.0.0,2.0.0
-      :doc:`ROCr Runtime <rocr-runtime:index>`,1.15.0,1.15.0,1.14.0
-
-
-.. rubric:: Footnotes
-
-.. [#mi300x] Oracle Linux and Azure Linux are supported only on AMD Instinct MI300X.
-.. [#single-node] Debian 12 is supported only on AMD Instinct MI300X for single-node functionality. 
-.. [#mi300_620] **For ROCm 6.2.0** - MI300X (gfx942) is supported on listed operating systems *except* Ubuntu 22.04.5 [6.8 HWE] and Ubuntu 22.04.4 [6.5 HWE].
-.. [#kfd_support] Starting from ROCm 6.4.0, forward and backward compatibility between the AMD Kernel-mode GPU Driver (KMD) and its user space software is provided up to a year apart (assuming hardware support is available in both). For earlier ROCm releases, the compatibility is provided for +/- 2 releases. These are the compatibility combinations that are currently supported.
-.. [#ROCT-rocr] Starting from ROCm 6.3.0, the ROCT Thunk Interface is included as part of the ROCr runtime package.
-.. [#RDNA-OS] Radeon AI PRO R9700, Radeon RX 9070 XT (gfx1201), Radeon RX 9060 XT (gfx1200), Radeon PRO W7700 (gfx1101), and Radeon RX 7800 XT (gfx1101) are supported only on Ubuntu 24.04.2, Ubuntu 22.04.5, RHEL 9.6, RHEL 9.5, and RHEL 9.4.
-
-.. _OS-kernel-versions:
-
-Operating systems, kernel and Glibc versions
-*********************************************
-
-Use this lookup table to confirm which operating system and kernel versions are supported with ROCm.
-
-.. csv-table::
-   :header: "OS", "Version", "Kernel", "Glibc"
-   :widths: 40, 20, 30, 20
-   :stub-columns: 1
-
-   `Ubuntu <https://ubuntu.com/about/release-cycle#ubuntu-kernel-release-cycle>`_, 24.04.2, "6.8 GA, 6.11 HWE", 2.39
-   ,,
-   `Ubuntu <https://ubuntu.com/about/release-cycle#ubuntu-kernel-release-cycle>`_, 22.04.5, "5.15 GA, 6.8 HWE", 2.35
-   ,,
-   `Red Hat Enterprise Linux (RHEL 9) <https://access.redhat.com/articles/3078#RHEL9>`_, 9.6, 5.14+, 2.34
-   , 9.5, 5.14+, 2.34
-   ,9.4, 5.14+, 2.34
-   ,9.3, 5.14+, 2.34
-   ,,
-   `Red Hat Enterprise Linux (RHEL 8) <https://access.redhat.com/articles/3078#RHEL8>`_, 8.10, 4.18.0+, 2.28
-   ,8.9, 4.18.0, 2.28
-   ,,
-   `SUSE Linux Enterprise Server (SLES) <https://www.suse.com/support/kb/doc/?id=000019587#SLE15SP4>`_, 15 SP6, "6.5.0+, 6.4.0", 2.38
-   ,15 SP5, 5.14.21, 2.31
-   ,,
-   `Oracle Linux <https://blogs.oracle.com/scoter/post/oracle-linux-and-unbreakable-enterprise-kernel-uek-releases>`_, 9, 5.15.0 (UEK), 2.35
-   ,8, 5.15.0 (UEK), 2.28
-   ,,
-   `Debian <https://www.debian.org/download>`_,12, 6.1, 2.36
-   ,,
-   `Azure Linux <https://techcommunity.microsoft.com/blog/linuxandopensourceblog/azure-linux-3-0-now-in-preview-on-azure-kubernetes-service-v1-31/4287229>`_,3.0, 6.6.60, 2.38
-   ,,
-
-.. note::
-
-  * See `Red Hat Enterprise Linux Release Dates <https://access.redhat.com/articles/3078>`_ to learn about the specific kernel versions supported on Red Hat Enterprise Linux (RHEL).
-  * See `List of SUSE Linux Enterprise Server kernel <https://www.suse.com/support/kb/doc/?id=000019587>`_ to learn about the specific kernel version supported on SUSE Linux Enterprise Server (SLES).
-..
-   Footnotes and ref anchors in below historical tables should be appended with "-past-60", to differentiate from the
-   footnote references in the above, latest, compatibility matrix.  It also allows to easily find & replace.
-   An easy way to work is to download the historical.CSV file, and update open it in excel. Then when content is ready,
-   delete the columns you don't need, to build the current compatibility matrix to use in above table.  Find & replace all
-   instances of "-past-60" to make it ready for above table.
-
-
-.. _past-rocm-compatibility-matrix:
-
-Past versions of ROCm compatibility matrix
-***************************************************
-
-Expand for full historical view of:
-
-.. dropdown:: ROCm 6.0 - Present
-
-   You can `download the entire .csv <../downloads/compatibility-matrix-historical-6.0.csv>`_ for offline reference.
-
-   .. csv-table::
-      :file: compatibility-matrix-historical-6.0.csv
-      :header-rows: 1
-      :stub-columns: 1
-
-   .. rubric:: Footnotes
-
-   .. [#mi300x-past-60] Oracle Linux and Azure Linux are supported only on AMD Instinct MI300X.
-   .. [#single-node-past-60] Debian 12 is supported only on AMD Instinct MI300X for single-node functionality. 
-   .. [#mi300_624-past-60] **For ROCm 6.2.4** - MI300X (gfx942) is supported on listed operating systems *except* Ubuntu 22.04.5 [6.8 HWE] and Ubuntu 22.04.4 [6.5 HWE].
-   .. [#mi300_622-past-60] **For ROCm 6.2.2** - MI300X (gfx942) is supported on listed operating systems *except* Ubuntu 22.04.5 [6.8 HWE] and Ubuntu 22.04.4 [6.5 HWE].
-   .. [#mi300_621-past-60] **For ROCm 6.2.1** - MI300X (gfx942) is supported on listed operating systems *except* Ubuntu 22.04.5 [6.8 HWE] and Ubuntu 22.04.4 [6.5 HWE].
-   .. [#mi300_620-past-60] **For ROCm 6.2.0** - MI300X (gfx942) is supported on listed operating systems *except* Ubuntu 22.04.5 [6.8 HWE] and Ubuntu 22.04.4 [6.5 HWE].
-   .. [#mi300_612-past-60] **For ROCm 6.1.2** - MI300A (gfx942) is supported on Ubuntu 22.04.4, RHEL 9.4, RHEL 9.3, RHEL 8.9, and SLES 15 SP5. MI300X (gfx942) is only supported on Ubuntu 22.04.4 and Oracle Linux.
-   .. [#mi300_611-past-60] **For ROCm 6.1.1** - MI300A (gfx942) is supported on Ubuntu 22.04.4, RHEL 9.4, RHEL 9.3, RHEL 8.9, and SLES 15 SP5. MI300X (gfx942) is only supported on Ubuntu 22.04.4 and Oracle Linux.
-   .. [#mi300_610-past-60] **For ROCm 6.1.0** - MI300A (gfx942) is supported on Ubuntu 22.04.4, RHEL 9.4, RHEL 9.3, RHEL 8.9, and SLES 15 SP5. MI300X (gfx942) is only supported on Ubuntu 22.04.4.
-   .. [#mi300_602-past-60] **For ROCm 6.0.2** - MI300A (gfx942) is supported on Ubuntu 22.04.3, RHEL 8.9, and SLES 15 SP5. MI300X (gfx942) is only supported on Ubuntu 22.04.3.
-   .. [#mi300_600-past-60] **For ROCm 6.0.0** - MI300A (gfx942) is supported on Ubuntu 22.04.3, RHEL 8.9, and SLES 15 SP5. MI300X (gfx942) is only supported on Ubuntu 22.04.3.
-   .. [#kfd_support-past-60] Starting from ROCm 6.4.0, forward and backward compatibility between the AMD Kernel-mode GPU Driver (KMD) and its user space software is provided up to a year apart (assuming hardware support is available in both). For earlier ROCm releases, the compatibility is provided for +/- 2 releases. These are the compatibility combinations that are currently supported.
-   .. [#ROCT-rocr-past-60] Starting from ROCm 6.3.0, the ROCT Thunk Interface is included as part of the ROCr runtime package.
-   .. [#RDNA-OS-past-60] Radeon AI PRO R9700, Radeon RX 9070 XT (gfx1201), Radeon RX 9060 XT (gfx1200), Radeon PRO W7700 (gfx1101), and Radeon RX 7800 XT (gfx1101) are supported only on Ubuntu 24.04.2, Ubuntu 22.04.5, RHEL 9.6, RHEL 9.5, and RHEL 9.4.
--- a/docs/compatibility/ml-compatibility/jax-compatibility.rst
+++ b/docs/compatibility/ml-compatibility/jax-compatibility.rst
@@ -1,519 +0,0 @@
-:orphan:
-
-.. meta::
-   :description: JAX compatibility
-   :keywords: GPU, JAX compatibility
-
-.. version-set:: rocm_version latest
-
-*******************************************************************************
-JAX compatibility
-*******************************************************************************
-
-JAX provides a NumPy-like API, which combines automatic differentiation and the
-Accelerated Linear Algebra (XLA) compiler to achieve high-performance machine
-learning at scale.
-
-JAX uses composable transformations of Python and NumPy through just-in-time
-(JIT) compilation, automatic vectorization, and parallelization. To learn about
-JAX, including profiling and optimizations, see the official `JAX documentation
-<https://jax.readthedocs.io/en/latest/notebooks/quickstart.html>`_.
-
-ROCm support for JAX is upstreamed, and users can build the official source code
-with ROCm support:
-
- ROCm JAX release:
-
-  - Offers AMD-validated and community :ref:`Docker images <jax-docker-compat>`
-    with ROCm and JAX preinstalled.
-
-  - ROCm JAX repository: `ROCm/jax <https://github.com/ROCm/jax>`_
-
-  - See the :doc:`ROCm JAX installation guide <rocm-install-on-linux:install/3rd-party/jax-install>`
-    to get started.
-
- Official JAX release:
-
-  - Official JAX repository: `jax-ml/jax <https://github.com/jax-ml/jax>`_
-
-  - See the `AMD GPU (Linux) installation section
-    <https://jax.readthedocs.io/en/latest/installation.html#amd-gpu-linux>`_ in
-    the JAX documentation.
-
-.. note::
-
-   AMD releases official `ROCm JAX Docker images <https://hub.docker.com/r/rocm/jax>`_
-   quarterly alongside new ROCm releases. These images undergo full AMD testing.
-   `Community ROCm JAX Docker images <https://hub.docker.com/r/rocm/jax-community>`_
-   follow upstream JAX releases and use the latest available ROCm version.
-
-Use cases and recommendations
-================================================================================
-
-* The `nanoGPT in JAX <https://rocm.blogs.amd.com/artificial-intelligence/nanoGPT-JAX/README.html>`_
-  blog explores the implementation and training of a Generative Pre-trained
-  Transformer (GPT) model in JAX, inspired by Andrej Karpathy’s JAX-based
-  nanoGPT. Comparing how essential GPT components—such as self-attention 
-  mechanisms and optimizers—are realized in JAX and JAX, also highlights
-  JAX’s unique features.
-
-* The `Optimize GPT Training: Enabling Mixed Precision Training in JAX using
-  ROCm on AMD GPUs <https://rocm.blogs.amd.com/artificial-intelligence/jax-mixed-precision/README.html>`_
-  blog post provides a comprehensive guide on enhancing the training efficiency
-  of GPT models by implementing mixed precision techniques in JAX, specifically
-  tailored for AMD GPUs utilizing the ROCm platform.
-
-* The `Supercharging JAX with Triton Kernels on AMD GPUs <https://rocm.blogs.amd.com/artificial-intelligence/jax-triton/README.html>`_
-  blog demonstrates how to develop a custom fused dropout-activation kernel for
-  matrices using Triton, integrate it with JAX, and benchmark its performance
-  using ROCm.
-
-* The `Distributed fine-tuning with JAX on AMD GPUs <https://rocm.blogs.amd.com/artificial-intelligence/distributed-sft-jax/README.html>`_
-  outlines the process of fine-tuning a Bidirectional Encoder Representations
-  from Transformers (BERT)-based large language model (LLM) using JAX for a text
-  classification task. The blog post discuss techniques for parallelizing the
-  fine-tuning across multiple AMD GPUs and assess the model's performance on a
-  holdout dataset. During the fine-tuning, a BERT-base-cased transformer model
-  and the General Language Understanding Evaluation (GLUE) benchmark dataset was
-  used on a multi-GPU setup.
-
-* The `MI300X workload optimization guide <https://rocm.docs.amd.com/en/latest/how-to/tuning-guides/mi300x/workload.html>`_
-  provides detailed guidance on optimizing workloads for the AMD Instinct MI300X
-  accelerator using ROCm. The page is aimed at helping users achieve optimal
-  performance for deep learning and other high-performance computing tasks on
-  the MI300X GPU.
-
-For more use cases and recommendations, see `ROCm JAX blog posts <https://rocm.blogs.amd.com/blog/tag/jax.html>`_.
-
-.. _jax-docker-compat:
-
-Docker image compatibility
-================================================================================
-
-.. |docker-icon| raw:: html
-
-   <i class="fab fa-docker"></i>
-
-AMD validates and publishes ready-made `ROCm JAX Docker images <https://hub.docker.com/r/rocm/jax>`_
-with ROCm backends on Docker Hub. The following Docker image tags and
-associated inventories represent the latest JAX version from the official Docker Hub and are validated for
-`ROCm 6.4.1 <https://repo.radeon.com/rocm/apt/6.4.1/>`_. Click the |docker-icon|
-icon to view the image on Docker Hub.
-
-.. list-table:: JAX Docker image components
-    :header-rows: 1
-
-    * - Docker image
-      - JAX
-      - Linux
-      - Python
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/jax/rocm6.4.1-jax0.4.35-py3.12/images/sha256-7a0745a2a2758bdf86397750bac00e9086cbf67d170cfdbb08af73f7c7d18a6a"><i class="fab fa-docker fa-lg"></i> rocm/jax</a>
-
-      - `0.4.35 <https://github.com/ROCm/jax/releases/tag/rocm-jax-v0.4.35>`_
-      - Ubuntu 24.04
-      - `3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/jax/rocm6.4.1-jax0.4.35-py3.10/images/sha256-5f9e8d6e6e69fdc9a1a3f2ba3b1234c3f46c53b7468538c07fd18b00899da54f"><i class="fab fa-docker fa-lg"></i> rocm/jax</a>
-
-      - `0.4.35 <https://github.com/ROCm/jax/releases/tag/rocm-jax-v0.4.35>`_
-      - Ubuntu 22.04
-      - `3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-
-AMD publishes `Community ROCm JAX Docker images <https://hub.docker.com/r/rocm/jax-community>`_
-with ROCm backends on Docker Hub. The following Docker image tags and
-associated inventories are tested for `ROCm 6.3.2 <https://repo.radeon.com/rocm/apt/6.3.2/>`_.
-
-.. list-table:: JAX community Docker image components
-    :header-rows: 1
-
-    * - Docker image
-      - JAX
-      - Linux
-      - Python
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/jax-community/rocm6.3.2-jax0.5.0-py3.12.8/images/sha256-25dfaa0183e274bd0a3554a309af3249c6f16a1793226cb5373f418e39d3146a"><i class="fab fa-docker fa-lg"></i> rocm/jax-community</a>
-
-      - `0.5.0 <https://github.com/ROCm/jax/releases/tag/rocm-jax-v0.5.0>`_
-      - Ubuntu 22.04
-      - `3.12.8 <https://www.python.org/downloads/release/python-3128/>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/jax-community/rocm6.3.2-jax0.5.0-py3.11.11/images/sha256-ff9baeca9067d13e6c279c911e5a9e5beed0817d24fafd424367cc3d5bd381d7"><i class="fab fa-docker fa-lg"></i> rocm/jax-community</a>
-
-      - `0.5.0 <https://github.com/ROCm/jax/releases/tag/rocm-jax-v0.5.0>`_
-      - Ubuntu 22.04
-      - `3.11.11 <https://www.python.org/downloads/release/python-31111/>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/jax-community/rocm6.3.2-jax0.5.0-py3.10.16/images/sha256-8bab484be1713655f74da51a191ed824bb9d03db1104fd63530a1ac3c37cf7b1"><i class="fab fa-docker fa-lg"></i> rocm/jax-community</a>
-
-      - `0.5.0 <https://github.com/ROCm/jax/releases/tag/rocm-jax-v0.5.0>`_
-      - Ubuntu 22.04
-      - `3.10.16 <https://www.python.org/downloads/release/python-31016/>`_
-
-Key ROCm libraries for JAX
-================================================================================
-
-JAX functionality on ROCm is determined by its underlying library
-dependencies. These ROCm components affect the capabilities, performance, and
-feature set available to developers.
-
-.. list-table::
-    :header-rows: 1
-
-    * - ROCm library
-      - Version
-      - Purpose
-      - Used in
-    * - `hipBLAS <https://github.com/ROCm/hipBLAS>`_
-      - :version-ref:`hipBLAS rocm_version`
-      - Provides GPU-accelerated Basic Linear Algebra Subprograms (BLAS) for
-        matrix and vector operations.
-      - Matrix multiplication in ``jax.numpy.matmul``, ``jax.lax.dot`` and
-        ``jax.lax.dot_general``, operations like ``jax.numpy.dot``, which
-        involve vector and matrix computations and batch matrix multiplications
-        ``jax.numpy.einsum`` with matrix-multiplication patterns algebra
-        operations.
-    * - `hipBLASLt <https://github.com/ROCm/hipBLASLt>`_
-      - :version-ref:`hipBLASLt rocm_version`
-      - hipBLASLt is an extension of hipBLAS, providing additional
-        features like epilogues fused into the matrix multiplication kernel or
-        use of integer tensor cores.
-      - Matrix multiplication in ``jax.numpy.matmul`` or ``jax.lax.dot``, and
-        the XLA (Accelerated Linear Algebra) use hipBLASLt for optimized matrix
-        operations, mixed-precision support, and hardware-specific
-        optimizations.
-    * - `hipCUB <https://github.com/ROCm/hipCUB>`_
-      - :version-ref:`hipCUB rocm_version`
-      - Provides a C++ template library for parallel algorithms for reduction,
-        scan, sort and select.
-      - Reduction functions (``jax.numpy.sum``, ``jax.numpy.mean``,
-        ``jax.numpy.prod``, ``jax.numpy.max`` and ``jax.numpy.min``), prefix sum
-        (``jax.numpy.cumsum``, ``jax.numpy.cumprod``) and sorting
-        (``jax.numpy.sort``, ``jax.numpy.argsort``).
-    * - `hipFFT <https://github.com/ROCm/hipFFT>`_
-      - :version-ref:`hipFFT rocm_version`
-      - Provides GPU-accelerated Fast Fourier Transform (FFT) operations.
-      - Used in functions like ``jax.numpy.fft``.
-    * - `hipRAND <https://github.com/ROCm/hipRAND>`_
-      - :version-ref:`hipRAND rocm_version`
-      - Provides fast random number generation for GPUs.
-      - The ``jax.random.uniform``, ``jax.random.normal``,
-        ``jax.random.randint`` and ``jax.random.split``.
-    * - `hipSOLVER <https://github.com/ROCm/hipSOLVER>`_
-      - :version-ref:`hipSOLVER rocm_version`
-      - Provides GPU-accelerated solvers for linear systems, eigenvalues, and
-        singular value decompositions (SVD).
-      - Solving linear systems (``jax.numpy.linalg.solve``), matrix
-        factorizations, SVD (``jax.numpy.linalg.svd``) and eigenvalue problems
-        (``jax.numpy.linalg.eig``).
-    * - `hipSPARSE <https://github.com/ROCm/hipSPARSE>`_
-      - :version-ref:`hipSPARSE rocm_version`
-      - Accelerates operations on sparse matrices, such as sparse matrix-vector
-        or matrix-matrix products.
-      - Sparse matrix multiplication (``jax.numpy.matmul``), sparse
-        matrix-vector and matrix-matrix products
-        (``jax.experimental.sparse.dot``), sparse linear system solvers and
-        sparse data handling.
-    * - `hipSPARSELt <https://github.com/ROCm/hipSPARSELt>`_
-      - :version-ref:`hipSPARSELt rocm_version`
-      - Accelerates operations on sparse matrices, such as sparse matrix-vector
-        or matrix-matrix products.
-      - Sparse matrix multiplication (``jax.numpy.matmul``), sparse
-        matrix-vector and matrix-matrix products
-        (``jax.experimental.sparse.dot``) and sparse linear system solvers.
-    * - `MIOpen <https://github.com/ROCm/MIOpen>`_
-      - :version-ref:`MIOpen rocm_version`
-      - Optimized for deep learning primitives such as convolutions, pooling,
-        normalization, and activation functions.
-      - Speeds up convolutional neural networks (CNNs), recurrent neural
-        networks (RNNs), and other layers. Used in operations like
-        ``jax.nn.conv``, ``jax.nn.relu``, and ``jax.nn.batch_norm``.
-    * - `RCCL <https://github.com/ROCm/rccl>`_
-      - :version-ref:`RCCL rocm_version`
-      - Optimized for multi-GPU communication for operations like  all-reduce,
-        broadcast, and scatter.
-      - Distribute computations across multiple GPU with ``pmap`` and
-        ``jax.distributed``. XLA automatically uses rccl when executing
-        operations across multiple GPUs on AMD hardware.
-    * - `rocThrust <https://github.com/ROCm/rocThrust>`_
-      - :version-ref:`rocThrust rocm_version`
-      - Provides a C++ template library for parallel algorithms like sorting,
-        reduction, and scanning.
-      - Reduction operations like ``jax.numpy.sum``, ``jax.pmap`` for
-        distributed training, which involves parallel reductions or
-        operations like ``jax.numpy.cumsum`` can use rocThrust.
-
-Supported features
-===============================================================================
-
-The following table maps the public JAX API modules to their supported
-ROCm and JAX versions.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Module
-      - Description
-      - As of JAX
-      - As of ROCm
-    * - ``jax.numpy``
-      - Implements the NumPy API, using the primitives in ``jax.lax``.
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy``
-      - Provides GPU-accelerated and differentiable implementations of many
-        functions from the SciPy library, leveraging JAX's transformations
-        (e.g., ``grad``, ``jit``, ``vmap``).
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.lax``
-      - A library of primitives operations that underpins libraries such as
-        ``jax.numpy.`` Transformation rules, such as Jacobian-vector product
-        (JVP) and batching rules, are typically defined as transformations on
-        ``jax.lax`` primitives.
-      - 0.1.57
-      - 5.0.0
-    * - ``jax.random``
-      - Provides a number of routines for deterministic generation of sequences
-        of pseudorandom numbers.
-      - 0.1.58
-      - 5.0.0
-    * - ``jax.sharding``
-      - Allows to define partitioning and distributing arrays across multiple
-        devices.
-      - 0.3.20
-      - 5.1.0
-    * - ``jax.distributed``
-      - Enables the scaling of computations across multiple devices on a single
-        machine or across multiple machines.
-      - 0.1.74
-      - 5.0.0
-    * - ``jax.image``
-      - Contains image manipulation functions like resize, scale and translation.
-      - 0.1.57
-      - 5.0.0
-    * - ``jax.nn``
-      - Contains common functions for neural network libraries.
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.ops``
-      - Computes the minimum, maximum, sum or product within segments of an
-        array.
-      - 0.1.57
-      - 5.0.0
-    * - ``jax.stages``
-      - Contains interfaces to stages of the compiled execution process.
-      - 0.3.4
-      - 5.0.0
-    * - ``jax.extend``
-      - Provides modules for access to JAX internal machinery module. The
-        ``jax.extend`` module defines a library view of some of JAX’s internal
-        components.
-      - 0.4.15
-      - 5.5.0
-    * - ``jax.example_libraries``
-      - Serves as a collection of example code and libraries that demonstrate
-        various capabilities of JAX.
-      - 0.1.74
-      - 5.0.0
-    * - ``jax.experimental``
-      - Namespace for experimental features and APIs that are in development or
-        are not yet fully stable for production use.
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.lib``
-      - Set of internal tools and types for bridging between JAX’s Python
-        frontend and its XLA backend.
-      - 0.4.6
-      - 5.3.0
-    * - ``jax_triton``
-      - Library that integrates the Triton deep learning compiler with JAX.
-      - jax_triton 0.2.0
-      - 6.2.4
-
-jax.scipy module
-------------------------------------------------------------------------------
-
-A SciPy-like API for scientific computing.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Module
-      - As of JAX
-      - As of ROCm
-    * - ``jax.scipy.cluster``
-      - 0.3.11
-      - 5.1.0
-    * - ``jax.scipy.fft``
-      - 0.1.71
-      - 5.0.0
-    * - ``jax.scipy.integrate``
-      - 0.4.15
-      - 5.5.0
-    * - ``jax.scipy.interpolate``
-      - 0.1.76
-      - 5.0.0
-    * - ``jax.scipy.linalg``
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy.ndimage``
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy.optimize``
-      - 0.1.57
-      - 5.0.0
-    * - ``jax.scipy.signal``
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy.spatial.transform``
-      - 0.4.12
-      - 5.4.0
-    * - ``jax.scipy.sparse.linalg``
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy.special``
-      - 0.1.56
-      - 5.0.0
-    * - ``jax.scipy.stats``
-      - 0.1.56
-      - 5.0.0
-
-jax.scipy.stats module
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. list-table::
-   :header-rows: 1
-
-   * - Module
-     - As of JAX
-     - As of ROCm
-   * - ``jax.scipy.stats.bernouli``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.beta``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.betabinom``
-     - 0.1.61
-     - 5.0.0
-   * - ``jax.scipy.stats.binom``
-     - 0.4.14
-     - 5.4.0
-   * - ``jax.scipy.stats.cauchy``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.chi2``
-     - 0.1.61
-     - 5.0.0
-   * - ``jax.scipy.stats.dirichlet``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.expon``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.gamma``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.gennorm``
-     - 0.3.15
-     - 5.2.0
-   * - ``jax.scipy.stats.geom``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.laplace``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.logistic``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.multinomial``
-     - 0.3.18
-     - 5.1.0
-   * - ``jax.scipy.stats.multivariate_normal``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.nbinom``
-     - 0.1.72
-     - 5.0.0
-   * - ``jax.scipy.stats.norm``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.pareto``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.poisson``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.t``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.truncnorm``
-     - 0.4.0
-     - 5.3.0
-   * - ``jax.scipy.stats.uniform``
-     - 0.1.56
-     - 5.0.0
-   * - ``jax.scipy.stats.vonmises``
-     - 0.4.2
-     - 5.3.0
-   * - ``jax.scipy.stats.wrapcauchy``
-     - 0.4.20
-     - 5.6.0
-
-jax.extend module
-------------------------------------------------------------------------------
-
-Modules for JAX extensions.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Module
-      - As of JAX
-      - As of ROCm
-    * - ``jax.extend.ffi``
-      - 0.4.30
-      - 6.0.0
-    * - ``jax.extend.linear_util``
-      - 0.4.17
-      - 5.6.0
-    * - ``jax.extend.mlir``
-      - 0.4.26
-      - 5.6.0
-    * - ``jax.extend.random``
-      - 0.4.15
-      - 5.5.0
-
-Unsupported JAX features
-===============================================================================
-
-The following GPU-accelerated JAX features are not supported by ROCm for
-the listed supported JAX versions.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-
-    * - Mixed Precision with TF32
-      - Mixed precision with TF32 is used for matrix multiplications,
-        convolutions, and other linear algebra operations, particularly in
-        deep learning workloads like CNNs and transformers.
-
-    * - XLA int4 support
-      - 4-bit integer (int4) precision in the XLA compiler.
-
-    * - MOSAIC (GPU)
-      - Mosaic is a library of kernel-building abstractions for JAX's Pallas system
--- a/docs/compatibility/ml-compatibility/pytorch-compatibility.rst
+++ b/docs/compatibility/ml-compatibility/pytorch-compatibility.rst
@@ -1,938 +0,0 @@
-:orphan:
-
-.. meta::
-    :description: PyTorch compatibility
-    :keywords: GPU, PyTorch compatibility
-
-.. version-set:: rocm_version latest
-
-********************************************************************************
-PyTorch compatibility
-********************************************************************************
-
-`PyTorch <https://pytorch.org/>`_ is an open-source tensor library designed for
-deep learning. PyTorch on ROCm provides mixed-precision and large-scale training
-using `MIOpen <https://github.com/ROCm/MIOpen>`_ and
-`RCCL <https://github.com/ROCm/rccl>`_ libraries.
-
-ROCm support for PyTorch is upstreamed into the official PyTorch repository. Due
-to independent compatibility considerations, this results in two distinct
-release cycles for PyTorch on ROCm:
-
- ROCm PyTorch release:
-
-  - Provides the latest version of ROCm but might not necessarily support the
-    latest stable PyTorch version.
-
-  - Offers :ref:`Docker images <pytorch-docker-compat>` with ROCm and PyTorch
-    preinstalled.
-
-  - ROCm PyTorch repository: `<https://github.com/ROCm/pytorch>`_
-
-  - See the :doc:`ROCm PyTorch installation guide <rocm-install-on-linux:install/3rd-party/pytorch-install>`
-    to get started.
-
- Official PyTorch release:
-
-  - Provides the latest stable version of PyTorch  but might not necessarily
-    support the latest ROCm version.
-
-  - Official PyTorch repository: `<https://github.com/pytorch/pytorch>`_
-
-  - See the `Nightly and latest stable version installation guide <https://pytorch.org/get-started/locally/>`_
-    or `Previous versions <https://pytorch.org/get-started/previous-versions/>`_
-    to get started.
-
-PyTorch includes tooling that generates HIP source code from the CUDA backend.
-This approach allows PyTorch to support ROCm without requiring manual code
-modifications. For more information, see :doc:`HIPIFY <hipify:index>`.
-
-ROCm development is aligned with the stable release of PyTorch, while upstream
-PyTorch testing uses the stable release of ROCm to maintain consistency.
-
-.. _pytorch-recommendations:
-
-Use cases and recommendations
-================================================================================
-
-* :doc:`Using ROCm for AI: training a model </how-to/rocm-for-ai/training/benchmark-docker/pytorch-training>`
-  guides how to leverage the ROCm platform for training AI models. It covers the
-  steps, tools, and best practices for optimizing training workflows on AMD GPUs
-  using PyTorch features.
-
-* :doc:`Single-GPU fine-tuning and inference </how-to/rocm-for-ai/fine-tuning/single-gpu-fine-tuning-and-inference>`
-  describes and demonstrates how to use the ROCm platform for the fine-tuning
-  and inference of machine learning models, particularly large language models
-  (LLMs), on systems with a single GPU. This topic provides a detailed guide for
-  setting up, optimizing, and executing fine-tuning and inference workflows in
-  such environments.
-
-* :doc:`Multi-GPU fine-tuning and inference optimization </how-to/rocm-for-ai/fine-tuning/multi-gpu-fine-tuning-and-inference>`
-  describes and demonstrates the fine-tuning and inference of machine learning
-  models on systems with multiple GPUs.
-
-* The :doc:`Instinct MI300X workload optimization guide </how-to/rocm-for-ai/inference-optimization/workload>`
-  provides detailed guidance on optimizing workloads for the AMD Instinct MI300X
-  accelerator using ROCm. This guide helps users achieve optimal performance for
-  deep learning and other high-performance computing tasks on the MI300X
-  accelerator.
-
-* The :doc:`Inception with PyTorch documentation </conceptual/ai-pytorch-inception>`
-  describes how PyTorch integrates with ROCm for AI workloads It outlines the
-  use of PyTorch on the ROCm platform and focuses on efficiently leveraging AMD
-  GPU hardware for training and inference tasks in AI applications.
-
-For more use cases and recommendations, see `ROCm PyTorch blog posts <https://rocm.blogs.amd.com/blog/tag/pytorch.html>`_.
-
-.. _pytorch-docker-compat:
-
-Docker image compatibility
-================================================================================
-
-.. |docker-icon| raw:: html
-
-   <i class="fab fa-docker"></i>
-
-AMD validates and publishes `PyTorch images <https://hub.docker.com/r/rocm/pytorch>`_
-with ROCm backends on Docker Hub. The following Docker image tags and associated
-inventories were tested on `ROCm 6.4.1 <https://repo.radeon.com/rocm/apt/6.4.1/>`_.
-Click |docker-icon| to view the image on Docker Hub.
-
-.. list-table:: PyTorch Docker image components
-    :header-rows: 1
-    :class: docker-image-compatibility
-
-    * - Docker
-      - PyTorch
-      - Ubuntu
-      - Python
-      - Apex
-      - torchvision
-      - TensorBoard
-      - MAGMA
-      - UCX
-      - OMPI
-      - OFED
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu24.04_py3.12_pytorch_release_2.6.0/images/sha256-c76af9bfb1c25b0f40d4c29e8652105c57250bf018d23ff595b06bd79666fdd7"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.6.0 <https://github.com/ROCm/pytorch/tree/release/2.6>`_
-      - 24.04
-      - `3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `1.6.0 <https://github.com/ROCm/apex/tree/release/1.6.0>`_
-      - `0.21.0 <https://github.com/pytorch/vision/tree/v0.21.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.16.0 <https://github.com/openucx/ucx/tree/v1.16.0>`_
-      - `4.1.6-7ubuntu2 <https://github.com/open-mpi/ompi/tree/v4.1.6>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu22.04_py3.10_pytorch_release_2.6.0/images/sha256-f9d226135d51831c810dcb1251636ec61f85c65fcdda03e188c053a5d4f6585b"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.6.0 <https://github.com/ROCm/pytorch/tree/release/2.6>`_
-      - 22.04
-      - `3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `1.6.0 <https://github.com/ROCm/apex/tree/release/1.6.0>`_
-      - `0.21.0 <https://github.com/pytorch/vision/tree/v0.21.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.12.1~rc2-1 <https://github.com/openucx/ucx/tree/v1.12.1>`_
-      - `4.1.2-2ubuntu1 <https://github.com/open-mpi/ompi/tree/v4.1.2>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu24.04_py3.12_pytorch_release_2.5.1/images/sha256-3490e74d4f43dcdb3351dd334108d1ccd47e5a687c0523a2424ac1bcdd3dd6dd"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.5.1 <https://github.com/ROCm/pytorch/tree/release/2.5>`_
-      - 24.04
-      - `3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `1.5.0 <https://github.com/ROCm/apex/tree/release/1.5.0>`_
-      - `0.20.1 <https://github.com/pytorch/vision/tree/v0.20.1>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.16.0+ds-5ubuntu1 <https://github.com/openucx/ucx/tree/v1.10.0>`_
-      - `4.1.6-7ubuntu2 <https://github.com/open-mpi/ompi/tree/v4.1.6>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu22.04_py3.10_pytorch_release_2.5.1/images/sha256-26c5dfffb4a54625884abca83166940f17dd27bc75f1b24f6e80fbcb7d4e9afb"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.5.1 <https://github.com/ROCm/pytorch/tree/release/2.5>`_
-      - 22.04
-      - `3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `1.5.0 <https://github.com/ROCm/apex/tree/release/1.5.0>`_
-      - `0.20.1 <https://github.com/pytorch/vision/tree/v0.20.1>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.12.1~rc2-1 <https://github.com/openucx/ucx/tree/v1.12.1>`_
-      - `4.1.2-2ubuntu1 <https://github.com/open-mpi/ompi/tree/v4.1.2>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu24.04_py3.12_pytorch_release_2.4.1/images/sha256-f378a24561fa6efc178b6dc93fc7d82e5b93653ecd59c89d4476674d29e1284d"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.4.1 <https://github.com/ROCm/pytorch/tree/release/2.4>`_
-      - 24.04
-      - `3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `1.4.0 <https://github.com/ROCm/apex/tree/release/1.4.0>`_
-      - `0.19.0 <https://github.com/pytorch/vision/tree/v0.19.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.16.0+ds-5ubuntu1 <https://github.com/openucx/ucx/tree/v1.16.0>`_
-      - `4.1.6-7ubuntu2 <https://github.com/open-mpi/ompi/tree/v4.1.6>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu22.04_py3.10_pytorch_release_2.4.1/images/sha256-2308dbd0e650b7bf8d548575cbb6e2bdc021f9386384ce570da16d58ee684d22"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.4.1 <https://github.com/ROCm/pytorch/tree/release/2.4>`_
-      - 22.04
-      - `3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `1.4.0 <https://github.com/ROCm/apex/tree/release/1.4.0>`_
-      - `0.19.0 <https://github.com/pytorch/vision/tree/v0.19.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13.0>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.12.1~rc2-1 <https://github.com/openucx/ucx/tree/v1.12.1>`_
-      - `4.1.2-2ubuntu1 <https://github.com/open-mpi/ompi/tree/v4.1.2>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu24.04_py3.12_pytorch_release_2.3.0/images/sha256-eefd2ab019728f91f94c5e6a9463cb0ea900b3011458d18fe5d88e50c0b57d86"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.3.0 <https://github.com/ROCm/pytorch/tree/release/2.3>`_
-      - 24.04
-      - `3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `1.3.0 <https://github.com/ROCm/apex/tree/release/1.3.0>`_
-      - `0.18.0 <https://github.com/pytorch/vision/tree/v0.18.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.16.0+ds-5ubuntu1 <https://github.com/openucx/ucx/tree/v1.16.0>`_
-      - `4.1.6-7ubuntu2 <https://github.com/open-mpi/ompi/tree/v4.1.6>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/pytorch/rocm6.4.1_ubuntu22.04_py3.10_pytorch_release_2.3.0/images/sha256-473643226ab0e93a04720b256ed772619878abf9c42b9f84828cefed522696fd"><i class="fab fa-docker fa-lg"></i></a>
-
-      - `2.3.0 <https://github.com/ROCm/pytorch/tree/release/2.3>`_
-      - 22.04
-      - `3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `1.3.0 <https://github.com/ROCm/apex/tree/release/1.3.0>`_
-      - `0.18.0 <https://github.com/pytorch/vision/tree/v0.18.0>`_
-      - `2.13.0 <https://github.com/tensorflow/tensorboard/tree/2.13>`_
-      - `master <https://bitbucket.org/icl/magma/src/master/>`_
-      - `1.12.1~rc2-1 <https://github.com/openucx/ucx/tree/v1.12.1>`_
-      - `4.1.2-2ubuntu1 <https://github.com/open-mpi/ompi/tree/v4.1.2>`_
-      - `5.3-1.0.5.0 <https://content.mellanox.com/ofed/MLNX_OFED-5.3-1.0.5.0/MLNX_OFED_LINUX-5.3-1.0.5.0-ubuntu20.04-x86_64.tgz>`_
-
-Key ROCm libraries for PyTorch
-================================================================================
-
-PyTorch functionality on ROCm is determined by its underlying library
-dependencies. These ROCm components affect the capabilities, performance, and
-feature set available to developers.
-
-.. list-table::
-    :header-rows: 1
-
-    * - ROCm library
-      - Version
-      - Purpose
-      - Used in
-    * - `Composable Kernel <https://github.com/ROCm/composable_kernel>`_
-      - :version-ref:`"Composable Kernel" rocm_version`
-      - Enables faster execution of core operations like matrix multiplication
-        (GEMM), convolutions and transformations.
-      - Speeds up ``torch.permute``, ``torch.view``, ``torch.matmul``,
-        ``torch.mm``, ``torch.bmm``, ``torch.nn.Conv2d``, ``torch.nn.Conv3d``
-        and ``torch.nn.MultiheadAttention``.
-    * - `hipBLAS <https://github.com/ROCm/hipBLAS>`_
-      - :version-ref:`hipBLAS rocm_version`
-      - Provides GPU-accelerated Basic Linear Algebra Subprograms (BLAS) for
-        matrix and vector operations.
-      - Supports operations such as matrix multiplication, matrix-vector
-        products, and tensor contractions. Utilized in both dense and batched
-        linear algebra operations.
-    * - `hipBLASLt <https://github.com/ROCm/hipBLASLt>`_
-      - :version-ref:`hipBLASLt rocm_version`
-      - hipBLASLt is an extension of the hipBLAS library, providing additional
-        features like epilogues fused into the matrix multiplication kernel or
-        use of integer tensor cores.
-      - Accelerates operations such as ``torch.matmul``, ``torch.mm``, and the
-        matrix multiplications used in convolutional and linear layers.
-    * - `hipCUB <https://github.com/ROCm/hipCUB>`_
-      - :version-ref:`hipCUB rocm_version`
-      - Provides a C++ template library for parallel algorithms for reduction,
-        scan, sort and select.
-      - Supports operations such as ``torch.sum``, ``torch.cumsum``,
-        ``torch.sort`` irregular shapes often involve scanning, sorting, and
-        filtering, which hipCUB handles efficiently.
-    * - `hipFFT <https://github.com/ROCm/hipFFT>`_
-      - :version-ref:`hipFFT rocm_version`
-      - Provides GPU-accelerated Fast Fourier Transform (FFT) operations.
-      - Used in functions like the ``torch.fft`` module.
-    * - `hipRAND <https://github.com/ROCm/hipRAND>`_
-      - :version-ref:`hipRAND rocm_version`
-      - Provides fast random number generation for GPUs.
-      - The ``torch.rand``, ``torch.randn``, and stochastic layers like
-        ``torch.nn.Dropout`` rely on hipRAND.
-    * - `hipSOLVER <https://github.com/ROCm/hipSOLVER>`_
-      - :version-ref:`hipSOLVER rocm_version`
-      - Provides GPU-accelerated solvers for linear systems, eigenvalues, and
-        singular value decompositions (SVD).
-      - Supports functions like ``torch.linalg.solve``,
-        ``torch.linalg.eig``, and ``torch.linalg.svd``.
-    * - `hipSPARSE <https://github.com/ROCm/hipSPARSE>`_
-      - :version-ref:`hipSPARSE rocm_version`
-      - Accelerates operations on sparse matrices, such as sparse matrix-vector
-        or matrix-matrix products.
-      - Sparse tensor operations ``torch.sparse``.
-    * - `hipSPARSELt <https://github.com/ROCm/hipSPARSELt>`_
-      - :version-ref:`hipSPARSELt rocm_version`
-      - Accelerates operations on sparse matrices, such as sparse matrix-vector
-        or matrix-matrix products.
-      - Sparse tensor operations ``torch.sparse``.
-    * - `hipTensor <https://github.com/ROCm/hipTensor>`_
-      - :version-ref:`hipTensor rocm_version`
-      - Optimizes for high-performance tensor operations, such as contractions.
-      - Accelerates tensor algebra, especially in deep learning and scientific
-        computing.
-    * - `MIOpen <https://github.com/ROCm/MIOpen>`_
-      - :version-ref:`MIOpen rocm_version`
-      - Optimizes deep learning primitives such as convolutions, pooling,
-        normalization, and activation functions.
-      - Speeds up convolutional neural networks (CNNs), recurrent neural
-        networks (RNNs), and other layers. Used in operations like
-        ``torch.nn.Conv2d``, ``torch.nn.ReLU``, and ``torch.nn.LSTM``.
-    * - `MIGraphX <https://github.com/ROCm/AMDMIGraphX>`_
-      - :version-ref:`MIGraphX rocm_version`
-      - Adds graph-level optimizations, ONNX models and mixed precision support
-        and enable Ahead-of-Time (AOT) Compilation.
-      - Speeds up inference models and executes ONNX models for
-        compatibility with other frameworks.
-        ``torch.nn.Conv2d``, ``torch.nn.ReLU``, and ``torch.nn.LSTM``.
-    * - `MIVisionX <https://github.com/ROCm/MIVisionX>`_
-      - :version-ref:`MIVisionX rocm_version`
-      - Optimizes acceleration for computer vision and AI workloads like
-        preprocessing, augmentation, and inferencing.
-      - Faster data preprocessing and augmentation pipelines for datasets like
-        ImageNet or COCO and easy to integrate into PyTorch's ``torch.utils.data``
-        and ``torchvision`` workflows.
-    * - `rocAL <https://github.com/ROCm/rocAL>`_
-      - :version-ref:`rocAL rocm_version`
-      - Accelerates the data pipeline by offloading intensive preprocessing and
-        augmentation tasks. rocAL is part of MIVisionX.
-      - Easy to integrate into PyTorch's ``torch.utils.data`` and
-        ``torchvision`` data load workloads.
-    * - `RCCL <https://github.com/ROCm/rccl>`_
-      - :version-ref:`RCCL rocm_version`
-      - Optimizes for multi-GPU communication for operations like AllReduce and
-        Broadcast.
-      - Distributed data parallel training (``torch.nn.parallel.DistributedDataParallel``).
-        Handles communication in multi-GPU setups.
-    * - `rocDecode <https://github.com/ROCm/rocDecode>`_
-      - :version-ref:`rocDecode rocm_version`
-      - Provides hardware-accelerated data decoding capabilities, particularly
-        for image, video, and other dataset formats.
-      - Can be integrated in ``torch.utils.data``, ``torchvision.transforms``
-        and ``torch.distributed``.
-    * - `rocJPEG <https://github.com/ROCm/rocJPEG>`_
-      - :version-ref:`rocJPEG rocm_version`
-      - Provides hardware-accelerated JPEG image decoding and encoding.
-      - GPU accelerated ``torchvision.io.decode_jpeg`` and
-        ``torchvision.io.encode_jpeg`` and can be integrated in
-        ``torch.utils.data`` and ``torchvision``.
-    * - `RPP <https://github.com/ROCm/RPP>`_
-      - :version-ref:`RPP rocm_version`
-      - Speeds up data augmentation, transformation, and other preprocessing steps.
-      - Easy to integrate into PyTorch's ``torch.utils.data`` and
-        ``torchvision`` data load workloads to speed up data processing.
-    * - `rocThrust <https://github.com/ROCm/rocThrust>`_
-      - :version-ref:`rocThrust rocm_version`
-      - Provides a C++ template library for parallel algorithms like sorting,
-        reduction, and scanning.
-      - Utilized in backend operations for tensor computations requiring
-        parallel processing.
-    * - `rocWMMA <https://github.com/ROCm/rocWMMA>`_
-      - :version-ref:`rocWMMA rocm_version`
-      - Accelerates warp-level matrix-multiply and matrix-accumulate to speed up matrix
-        multiplication (GEMM) and accumulation operations with mixed precision
-        support.
-      - Linear layers (``torch.nn.Linear``), convolutional layers
-        (``torch.nn.Conv2d``), attention layers, general tensor operations that
-        involve matrix products, such as ``torch.matmul``, ``torch.bmm``, and
-        more.
-
-Supported features
-================================================================================
-
-This section maps GPU-accelerated PyTorch features to their supported ROCm and
-PyTorch versions.
-
-torch
--------------------------------------------------------------------------------
-
-`torch <https://pytorch.org/docs/stable/index.html>`_ is the central module of
-PyTorch, providing data structures for multi-dimensional tensors and
-implementing mathematical operations on them. It also includes utilities for
-efficient serialization of tensors and arbitrary data types and other tools.
-
-Tensor data types
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The tensor data type is specified using the ``dtype`` attribute or argument. 
-PyTorch supports many data types for different use cases.
-
-The following table lists `torch.Tensor <https://pytorch.org/docs/stable/tensors.html>`_
-single data types:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Data type
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - ``torch.float8_e4m3fn``
-      - 8-bit floating point, e4m3
-      - 2.3
-      - 5.5
-    * - ``torch.float8_e5m2``
-      - 8-bit floating point, e5m2
-      - 2.3
-      - 5.5
-    * - ``torch.float16`` or ``torch.half``
-      - 16-bit floating point
-      - 0.1.6
-      - 2.0
-    * - ``torch.bfloat16``
-      - 16-bit floating point
-      - 1.6
-      - 2.6
-    * - ``torch.float32`` or ``torch.float``
-      - 32-bit floating point
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.float64`` or ``torch.double``
-      - 64-bit floating point
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.complex32`` or ``torch.chalf``
-      - PyTorch provides native support for 32-bit complex numbers
-      - 1.6
-      - 2.0
-    * - ``torch.complex64`` or ``torch.cfloat``
-      - PyTorch provides native support for 64-bit complex numbers
-      - 1.6
-      - 2.0
-    * - ``torch.complex128`` or ``torch.cdouble``
-      - PyTorch provides native support for 128-bit complex numbers
-      - 1.6
-      - 2.0
-    * - ``torch.uint8``
-      - 8-bit integer (unsigned)
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.uint16``
-      - 16-bit integer (unsigned)
-      - 2.3
-      - Not natively supported
-    * - ``torch.uint32``
-      - 32-bit integer (unsigned)
-      - 2.3
-      - Not natively supported
-    * - ``torch.uint64``
-      - 32-bit integer (unsigned)
-      - 2.3
-      - Not natively supported
-    * - ``torch.int8``
-      - 8-bit integer (signed)
-      - 1.12
-      - 5.0
-    * - ``torch.int16`` or ``torch.short``
-      - 16-bit integer (signed)
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.int32`` or ``torch.int``
-      - 32-bit integer (signed)
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.int64`` or ``torch.long``
-      - 64-bit integer (signed)
-      - 0.1.12_2
-      - 2.0
-    * - ``torch.bool``
-      - Boolean
-      - 1.2
-      - 2.0
-    * - ``torch.quint8``
-      - Quantized 8-bit integer (unsigned)
-      - 1.8
-      - 5.0
-    * - ``torch.qint8``
-      - Quantized 8-bit integer (signed)
-      - 1.8
-      - 5.0
-    * - ``torch.qint32``
-      - Quantized 32-bit integer (signed)
-      - 1.8
-      - 5.0
-    * - ``torch.quint4x2``
-      - Quantized 4-bit integer (unsigned)
-      - 1.8
-      - 5.0
-
-.. note::
-
-  Unsigned types except ``uint8`` have limited support in eager mode. They
-  primarily exist to assist usage with ``torch.compile``.
-
-  See :doc:`ROCm precision support <rocm:reference/precision-support>` for the
-  native hardware support of data types.
-
-torch.cuda
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-``torch.cuda`` in PyTorch is a module that provides utilities and functions for
-managing and utilizing AMD and NVIDIA GPUs. It enables GPU-accelerated
-computations, memory management, and efficient execution of tensor operations,
-leveraging ROCm and CUDA as the underlying frameworks.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - Device management
-      - Utilities for managing and interacting with GPUs.
-      - 0.4.0
-      - 3.8
-    * - Tensor operations on GPU
-      - Performs tensor operations such as addition and matrix multiplications on
-        the GPU.
-      - 0.4.0
-      - 3.8
-    * - Streams and events
-      - Streams allow overlapping computation and communication for optimized
-        performance. Events enable synchronization.
-      - 1.6.0
-      - 3.8
-    * - Memory management
-      - Functions to manage and inspect memory usage like
-        ``torch.cuda.memory_allocated()``, ``torch.cuda.max_memory_allocated()``,
-        ``torch.cuda.memory_reserved()`` and ``torch.cuda.empty_cache()``.
-      - 0.3.0
-      - 1.9.2
-    * - Running process lists of memory management
-      - Returns a human-readable printout of the running processes and their GPU
-        memory use for a given device with functions like
-        ``torch.cuda.memory_stats()`` and ``torch.cuda.memory_summary()``.
-      - 1.8.0
-      - 4.0
-    * - Communication collectives
-      - Set of APIs that enable efficient communication between multiple GPUs,
-        allowing for distributed computing and data parallelism.
-      - 1.9.0
-      - 5.0
-    * - ``torch.cuda.CUDAGraph``
-      - Graphs capture sequences of GPU operations to minimize kernel launch
-        overhead and improve performance.
-      - 1.10.0
-      - 5.3
-    * - TunableOp
-      - A mechanism that allows certain operations to be more flexible and
-        optimized for performance. It enables automatic tuning of kernel
-        configurations and other settings to achieve the best possible
-        performance based on the specific hardware (GPU) and workload.
-      - 2.0
-      - 5.4
-    * - NVIDIA Tools Extension (NVTX)
-      - Integration with NVTX for profiling and debugging GPU performance using
-        NVIDIA's Nsight tools.
-      - 1.8.0
-      - ❌
-    * - Lazy loading NVRTC
-      - Delays JIT compilation with NVRTC until the code is explicitly needed.
-      - 1.13.0
-      - ❌
-    * - Jiterator (beta)
-      - Jiterator allows asynchronous data streaming into computation streams
-        during training loops.
-      - 1.13.0
-      - 5.2
-
-.. Need to validate and extend.
-
-torch.backends.cuda
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-``torch.backends.cuda`` is a PyTorch module that provides configuration options
-and flags to control the behavior of ROCm or CUDA operations. It is part of the
-PyTorch backend configuration system, which allows users to fine-tune how
-PyTorch interacts with the ROCm or CUDA environment.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - ``cufft_plan_cache``
-      - Manages caching of GPU FFT plans to optimize repeated FFT computations.
-      - 1.7.0
-      - 5.0
-    * - ``matmul.allow_tf32``
-      - Enables or disables the use of TensorFloat-32 (TF32) precision for
-        faster matrix multiplications on GPUs with Tensor Cores.
-      - 1.10.0
-      - ❌
-    * - ``matmul.allow_fp16_reduced_precision_reduction``
-      - Reduced precision reductions (e.g., with fp16 accumulation type) are
-        allowed with fp16 GEMMs.
-      - 2.0
-      - ❌
-    * - ``matmul.allow_bf16_reduced_precision_reduction``
-      - Reduced precision reductions are allowed with bf16 GEMMs.
-      - 2.0
-      - ❌
-    * - ``enable_cudnn_sdp``
-      - Globally enables cuDNN SDPA's kernels within SDPA.
-      - 2.0
-      - ❌
-    * - ``enable_flash_sdp``
-      - Globally enables or disables FlashAttention for SDPA.
-      - 2.1
-      - ❌
-    * - ``enable_mem_efficient_sdp``
-      - Globally enables or disables Memory-Efficient Attention for SDPA.
-      - 2.1
-      - ❌
-    * - ``enable_math_sdp``
-      - Globally enables or disables the PyTorch C++ implementation within SDPA.
-      - 2.1
-      - ❌
-
-.. Need to validate and extend.
-
-torch.backends.cudnn
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Supported ``torch`` options include:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Option
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - ``allow_tf32``
-      - TensorFloat-32 tensor cores may be used in cuDNN convolutions on NVIDIA
-        Ampere or newer GPUs.
-      - 1.12.0
-      - ❌
-    * - ``deterministic``
-      - A bool that, if True, causes cuDNN to only use deterministic
-        convolution algorithms.
-      - 1.12.0
-      - 6.0
-
-Automatic mixed precision: torch.amp
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-PyTorch automates the process of using both 16-bit (half-precision, float16) and
-32-bit (single-precision, float32) floating-point types in model training and
-inference.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - Autocasting
-      - Autocast instances serve as context managers or decorators that allow
-        regions of your script to run in mixed precision.
-      - 1.9
-      - 2.5
-    * - Gradient scaling
-      - To prevent underflow, “gradient scaling” multiplies the network’s
-        loss by a scale factor and invokes a backward pass on the scaled
-        loss. The same factor then scales gradients flowing backward through
-        the network. In other words, gradient values have a larger magnitude so
-        that they don’t flush to zero.
-      - 1.9
-      - 2.5
-    * - CUDA op-specific behavior
-      - These ops always go through autocasting whether they are invoked as part
-        of a ``torch.nn.Module``, as a function, or as a ``torch.Tensor`` method. If
-        functions are exposed in multiple namespaces, they go through
-        autocasting regardless of the namespace.
-      - 1.9
-      - 2.5
-
-Distributed library features
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-PyTorch distributed library includes a collective of parallelism modules, a
-communications layer, and infrastructure for launching and debugging large
-training jobs. See :ref:`rocm-for-ai-pytorch-distributed` for more information.
-
-The Distributed Library feature in PyTorch provides tools and APIs for building
-and running distributed machine learning workflows. It allows training models
-across multiple processes, GPUs, or nodes in a cluster, enabling efficient use
-of computational resources and scalability for large-scale tasks.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - TensorPipe
-      - A point-to-point communication library integrated into
-        PyTorch for distributed training. It handles tensor data transfers
-        efficiently between different processes or devices, including those on
-        separate machines.
-      - 1.8
-      - 5.4
-    * - Gloo
-      - Designed for multi-machine and multi-GPU setups, enabling
-        efficient communication and synchronization between processes. Gloo is
-        one of the default backends for PyTorch's Distributed Data Parallel
-        (DDP) and RPC frameworks, alongside other backends like NCCL and MPI.
-      - 1.0
-      - 2.0
-
-torch.compiler
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-      - As of ROCm
-    * - ``torch.compiler`` (AOT Autograd)
-      - Autograd captures not only the user-level code, but also backpropagation,
-        which results in capturing the backwards pass “ahead-of-time”. This
-        enables acceleration of both forwards and backwards pass using
-        ``TorchInductor``.
-      - 2.0
-      - 5.3
-    * - ``torch.compiler`` (TorchInductor)
-      - The default ``torch.compile`` deep learning compiler that generates fast
-        code for multiple accelerators and backends. You need to use a backend
-        compiler to make speedups through ``torch.compile`` possible. For AMD,
-        NVIDIA, and Intel GPUs, it leverages OpenAI Triton as the key building block.
-      - 2.0
-      - 5.3
-
-torchaudio
--------------------------------------------------------------------------------
-
-The `torchaudio <https://pytorch.org/audio/stable/index.html>`_ library provides
-utilities for processing audio data in PyTorch, such as audio loading,
-transformations, and feature extraction.
-
-To ensure GPU-acceleration with ``torchaudio.transforms``, you need to
-explicitly move audio data (waveform tensor) to GPU using ``.to('cuda')``.
-
-The following ``torchaudio`` features are GPU-accelerated.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of torchaudio version
-      - As of ROCm
-    * - ``torchaudio.transforms.Spectrogram``
-      - Generate a spectrogram of an input waveform using STFT.
-      - 0.6.0
-      - 4.5
-    * - ``torchaudio.transforms.MelSpectrogram``
-      - Generates the mel-scale spectrogram of raw audio signals.
-      - 0.9.0
-      - 4.5
-    * - ``torchaudio.transforms.MFCC``
-      - Extract of MFCC features.
-      - 0.9.0
-      - 4.5
-    * - ``torchaudio.transforms.Resample``
-      - Resamples a signal from one frequency to another.
-      - 0.9.0
-      - 4.5
-
-torchvision
--------------------------------------------------------------------------------
-
-The `torchvision <https://pytorch.org/vision/stable/index.html>`_ library
-provides datasets, model architectures, and common image transformations for
-computer vision.
-
-The following ``torchvision`` features are GPU-accelerated.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of torchvision version
-      - As of ROCm
-    * - ``torchvision.transforms.functional``
-      - Provides GPU-compatible transformations for image preprocessing like
-        resize, normalize, rotate and crop.
-      - 0.2.0
-      - 4.0
-    * - ``torchvision.ops``
-      - GPU-accelerated operations for object detection and segmentation tasks.
-        ``torchvision.ops.roi_align``, ``torchvision.ops.nms`` and
-        ``box_convert``.
-      - 0.6.0
-      - 3.3
-    * - ``torchvision.models`` with ``.to('cuda')``
-      - ``torchvision`` provides several pre-trained models (ResNet, Faster
-        R-CNN, Mask R-CNN, ...) that can run on CUDA for faster inference and
-        training.
-      - 0.1.6
-      - 2.x
-    * - ``torchvision.io``
-      - Enables video decoding and frame extraction using GPU acceleration with NVIDIA’s
-        NVDEC and nvJPEG (rocJPEG) on CUDA-enabled GPUs.
-      - 0.4.0
-      - 6.3
-
-torchtext
--------------------------------------------------------------------------------
-
-The `torchtext <https://pytorch.org/text/stable/index.html>`_ library provides
-utilities for processing and working with text data in PyTorch, including
-tokenization, vocabulary management, and text embeddings. torchtext supports
-preprocessing pipelines and integration with PyTorch models, simplifying the
-implementation of natural language processing (NLP) tasks.
-
-To leverage GPU acceleration in torchtext, you need to move tensors
-explicitly to the GPU using ``.to('cuda')``.
-
-* torchtext does not implement its own kernels. ROCm support is enabled by linking against ROCm libraries.
-
-* Only official release exists.
-
-torchtune
--------------------------------------------------------------------------------
-
-The `torchtune <https://pytorch.org/torchtune/stable/index.html>`_ library for
-authoring, fine-tuning and experimenting with LLMs.
-
-* Usage: Enabling developers to fine-tune ROCm PyTorch solutions.
-
-* Only official release exists.
-
-torchserve
--------------------------------------------------------------------------------
-
-The `torchserve <https://pytorch.org/serve/>`_ is a PyTorch domain library
-for common sparsity and parallelism primitives needed for large-scale recommender
-systems.
-
-* torchtext does not implement its own kernels. ROCm support is enabled by
-  linking against ROCm libraries.
-
-* Only official release exists.
-
-torchrec
--------------------------------------------------------------------------------
-
-The `torchrec <https://pytorch.org/torchrec/>`_ is a PyTorch domain library for
-common sparsity and parallelism primitives needed for large-scale recommender
-systems.
-
-* torchrec does not implement its own kernels. ROCm support is enabled by
-  linking against ROCm libraries.
-
-* Only official release exists.
-
-Unsupported PyTorch features
-================================================================================
-
-The following GPU-accelerated PyTorch features are not supported by ROCm for
-the listed supported PyTorch versions.
-
-.. list-table::
-    :widths: 30, 60, 10
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - As of PyTorch
-    * - APEX batch norm
-      - Use APEX batch norm instead of PyTorch batch norm.
-      - 1.6.0
-    * - ``torch.backends.cuda`` / ``matmul.allow_tf32``
-      - A bool that controls whether TensorFloat-32 tensor cores may be used in
-        matrix multiplications.
-      - 1.7
-    * - ``torch.cuda`` / NVIDIA Tools Extension (NVTX)
-      - Integration with NVTX for profiling and debugging GPU performance using
-        NVIDIA's Nsight tools.
-      - 1.7.0
-    * - ``torch.cuda`` / Lazy loading NVRTC
-      - Delays JIT compilation with NVRTC until the code is explicitly needed.
-      - 1.8.0
-    * - ``torch-tensorrt``
-      - Integrate TensorRT library for optimizing and deploying PyTorch models.
-        ROCm does not have equialent library for TensorRT.
-      - 1.9.0
-    * - ``torch.backends`` / ``cudnn.allow_tf32``
-      - TensorFloat-32 tensor cores may be used in cuDNN convolutions.
-      - 1.10.0
-    * - ``torch.backends.cuda`` / ``matmul.allow_fp16_reduced_precision_reduction``
-      - Reduced precision reductions with fp16 accumulation type are
-        allowed with fp16 GEMMs.
-      - 2.0
-    * - ``torch.backends.cuda`` / ``matmul.allow_bf16_reduced_precision_reduction``
-      - Reduced precision reductions are allowed with bf16 GEMMs.
-      - 2.0
-    * - ``torch.nn.functional`` / ``scaled_dot_product_attention``
-      - Flash attention backend for SDPA to accelerate attention computation in
-        transformer-based models.
-      - 2.0
-    * - ``torch.backends.cuda`` / ``enable_cudnn_sdp``
-      - Globally enables cuDNN SDPA's kernels within SDPA.
-      - 2.0
-    * - ``torch.backends.cuda`` / ``enable_flash_sdp``
-      - Globally enables or disables FlashAttention for SDPA.
-      - 2.1
-    * - ``torch.backends.cuda`` / ``enable_mem_efficient_sdp``
-      - Globally enables or disables Memory-Efficient Attention for SDPA.
-      - 2.1
-    * - ``torch.backends.cuda`` / ``enable_math_sdp``
-      - Globally enables or disables the PyTorch C++ implementation within SDPA.
-      - 2.1
-    * - Dynamic parallelism
-      - PyTorch itself does not directly expose dynamic parallelism as a core
-        feature. Dynamic parallelism allow GPU threads to launch additional
-        threads which can be reached using custom operations via the
-        ``torch.utils.cpp_extension`` module.
-      - Not a core feature
-    * - Unified memory support in PyTorch
-      - Unified Memory is not directly exposed in PyTorch's core API, it can be
-        utilized effectively through custom CUDA extensions or advanced
-        workflows.
-      - Not a core feature
--- a/docs/compatibility/ml-compatibility/tensorflow-compatibility.rst
+++ b/docs/compatibility/ml-compatibility/tensorflow-compatibility.rst
@@ -1,571 +0,0 @@
-:orphan:
-
-.. meta::
-    :description: TensorFlow compatibility
-    :keywords: GPU, TensorFlow compatibility
-
-.. version-set:: rocm_version latest
-
-*******************************************************************************
-TensorFlow compatibility
-*******************************************************************************
-
-`TensorFlow <https://www.tensorflow.org/>`_ is an open-source library for
-solving machine learning, deep learning, and AI problems. It can solve many
-problems across different sectors and industries but primarily focuses on
-neural network training and inference. It is one of the most popular and
-in-demand frameworks and is very active in open-source contribution and
-development.
-
-The `official TensorFlow repository <http://github.com/tensorflow/tensorflow>`_
-includes full ROCm support. AMD maintains a TensorFlow `ROCm repository
-<http://github.com/rocm/tensorflow-upstream>`_ in order to quickly add bug
-fixes, updates, and support for the latest ROCM versions.
-
- ROCm TensorFlow release:
-
-  - Offers :ref:`Docker images <tensorflow-docker-compat>` with
-    ROCm and TensorFlow pre-installed.
-
-  - ROCm TensorFlow repository: `<https://github.com/ROCm/tensorflow-upstream>`_
-
-  - See the :doc:`ROCm TensorFlow installation guide <rocm-install-on-linux:install/3rd-party/tensorflow-install>`
-    to get started.
-
- Official TensorFlow release:
-
-  - Official TensorFlow repository: `<https://github.com/tensorflow/tensorflow>`_
-
-  - See the `TensorFlow API versions <https://www.tensorflow.org/versions>`_ list.
-
-  .. note::
-
-     The official TensorFlow documentation does not cover ROCm support. Use the
-     ROCm documentation for installation instructions for Tensorflow on ROCm.
-     See :doc:`rocm-install-on-linux:install/3rd-party/tensorflow-install`.
-
-.. _tensorflow-docker-compat:
-
-Docker image compatibility
-===============================================================================
-
-.. |docker-icon| raw:: html
-
-   <i class="fab fa-docker"></i>
-
-AMD validates and publishes ready-made `TensorFlow images
-<https://hub.docker.com/r/rocm/tensorflow>`_ with ROCm backends on
-Docker Hub. The following Docker image tags and associated inventories are
-validated for `ROCm 6.4.1 <https://repo.radeon.com/rocm/apt/6.4.1/>`_. Click
-the |docker-icon| icon to view the image on Docker Hub.
-
-.. list-table:: TensorFlow Docker image components
-    :header-rows: 1
-
-    * - Docker image
-      - TensorFlow
-      - Ubuntu
-      - Dev
-      - Python
-      - TensorBoard
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4-py3.12-tf2.18-dev/images/sha256-fa9cf5fa6c6079a7118727531ccd0056c6e3224a42c3d6e78a49e7781daafff4"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.18.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.18.1-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - dev
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `TensorBoard 2.18.0 <https://github.com/tensorflow/tensorboard/tree/2.18.0>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.12-tf2.18-runtime/images/sha256-d14d8c4989e7c9a60f4e72461b9e349de72347c6162dcd6897e6f4f80ffbb440"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.18.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.18.1-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `TensorBoard 2.18.0 <https://github.com/tensorflow/tensorboard/tree/2.18.0>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.18-dev/images/sha256-081e5bd6615a5dc17247ebd2ccc26895c3feeff086720400fa39b477e60a77c0"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.18.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.18.1-cp310-cp310-manylinux_2_28_x86_64.whl>`__
-      - dev
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.18.0 <https://github.com/tensorflow/tensorboard/tree/2.18.0>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.18-runtime/images/sha256-bf369637378264f4af6ddad5ca8b8611d3e372ffbea9ab7a06f1e122f0a0867b"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.18.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.18.1-cp310-cp310-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.18.0 <https://github.com/tensorflow/tensorboard/tree/2.18.0>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.12-tf2.17-dev/images/sha256-5a502008c50d0b6508e6027f911bdff070a7493700ae064bed74e1d22b91ed50"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.17.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4/tensorflow_rocm-2.17.1-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - dev
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `TensorBoard 2.17.1 <https://github.com/tensorflow/tensorboard/tree/2.17.1>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.12-tf2.17-runtime/images/sha256-1ee5dfffceb71ac66617ada33de3a10de0cb74199cc4b82441192e5e92fa2ddf"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.18.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4/tensorflow_rocm-2.17.1-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-3124/>`_
-      - `TensorBoard 2.17.1 <https://github.com/tensorflow/tensorboard/tree/2.17.1>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.17-dev/images/sha256-109218ad92bfae83bbd2710475f7502166e1ed54ca0b9748a9cbc3f5a1d75af1"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.17.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.17.1-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - dev
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.17.1 <https://github.com/tensorflow/tensorboard/tree/2.17.1>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.17-runtime/images/sha256-5d78bd5918d394f92263daa2990e88d695d27200dd90ed83ec64d20c7661c9c1"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.17.1 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.17.1-cp310-cp310-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.17.1 <https://github.com/tensorflow/tensorboard/tree/2.17.1>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.12-tf2.16-dev/images/sha256-b09b1ad921c09c687b7c916141051e9fcf15539a5686e5aa67c689195a522719"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.16.2 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.16.2-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - dev
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `TensorBoard 2.16.2 <https://github.com/tensorflow/tensorboard/tree/2.16.2>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.12-tf2.16-runtime/images/sha256-20dbd824e85558abfe33fc9283cc547d88cde3c623fe95322743a5082f883a64"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.16.2 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.16.2-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 24.04
-      - `Python 3.12.10 <https://www.python.org/downloads/release/python-31210/>`_
-      - `TensorBoard 2.16.2 <https://github.com/tensorflow/tensorboard/tree/2.16.2>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.16-dev/images/sha256-36c4fa047c86e2470ac473ec1429aea6d4b8934b90ffeb34d1afab40e7e5b377"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.16.2 <https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.16-dev/images/sha256-36c4fa047c86e2470ac473ec1429aea6d4b8934b90ffeb34d1afab40e7e5b377>`__
-      - dev
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.16.2 <https://github.com/tensorflow/tensorboard/tree/2.16.2>`_
-
-    * - .. raw:: html
-
-           <a href="https://hub.docker.com/layers/rocm/tensorflow/rocm6.4.1-py3.10-tf2.16-runtime/images/sha256-a94150ffb81365234ebfa34e764db5474bc6ab7d141b56495eac349778dafcf3"><i class="fab fa-docker fa-lg"></i> rocm/tensorflow</a>
-
-      - `tensorflow-rocm 2.16.2 <https://repo.radeon.com/rocm/manylinux/rocm-rel-6.4.1/tensorflow_rocm-2.16.2-cp312-cp312-manylinux_2_28_x86_64.whl>`__
-      - runtime
-      - 22.04
-      - `Python 3.10.17 <https://www.python.org/downloads/release/python-31017/>`_
-      - `TensorBoard 2.16.2 <https://github.com/tensorflow/tensorboard/tree/2.16.2>`_
-
-
-Critical ROCm libraries for TensorFlow
-===============================================================================
-
-TensorFlow depends on multiple components and the supported features of those
-components can affect the TensorFlow ROCm supported feature set. The versions
-in the following table refer to the first TensorFlow version where the ROCm
-library was introduced as a dependency. The versions described
-are available in ROCm :version:`rocm_version`.
-
-.. list-table::
-    :widths: 25, 10, 35, 30
-    :header-rows: 1
-
-    * - ROCm library
-      - Version
-      - Purpose
-      - Used in
-    * - `hipBLAS <https://github.com/ROCm/hipBLAS>`_
-      - :version-ref:`hipBLAS rocm_version`
-      - Provides GPU-accelerated Basic Linear Algebra Subprograms (BLAS) for
-        matrix and vector operations.
-      - Accelerates operations like ``tf.matmul``, ``tf.linalg.matmul``, and
-        other matrix multiplications commonly used in neural network layers.
-    * - `hipBLASLt <https://github.com/ROCm/hipBLASLt>`_
-      - :version-ref:`hipBLASLt rocm_version`
-      - Extends hipBLAS with additional optimizations like fused kernels and
-        integer tensor cores.
-      - Optimizes matrix multiplications and linear algebra operations used in
-        layers like dense, convolutional, and RNNs in TensorFlow.
-    * - `hipCUB <https://github.com/ROCm/hipCUB>`_
-      - :version-ref:`hipCUB rocm_version`
-      - Provides a C++ template library for parallel algorithms for reduction,
-        scan, sort and select.
-      - Supports operations like ``tf.reduce_sum``, ``tf.cumsum``, ``tf.sort``
-        and other tensor operations in TensorFlow, especially those involving
-        scanning, sorting, and filtering.
-    * - `hipFFT <https://github.com/ROCm/hipFFT>`_
-      - :version-ref:`hipFFT rocm_version`
-      - Accelerates Fast Fourier Transforms (FFT) for signal processing tasks.
-      - Used for operations like signal processing, image filtering, and
-        certain types of neural networks requiring FFT-based transformations.
-    * - `hipSOLVER <https://github.com/ROCm/hipSOLVER>`_
-      - :version-ref:`hipSOLVER rocm_version`
-      - Provides GPU-accelerated direct linear solvers for dense and sparse
-        systems.
-      - Optimizes linear algebra functions such as solving systems of linear
-        equations, often used in optimization and training tasks.
-    * - `hipSPARSE <https://github.com/ROCm/hipSPARSE>`_
-      - :version-ref:`hipSPARSE rocm_version`
-      - Optimizes sparse matrix operations for efficient computations on sparse
-        data.
-      - Accelerates sparse matrix operations in models with sparse weight
-        matrices or activations, commonly used in neural networks.
-    * - `MIOpen <https://github.com/ROCm/MIOpen>`_
-      - :version-ref:`MIOpen rocm_version`
-      - Provides optimized deep learning primitives such as convolutions,
-        pooling,
-        normalization, and activation functions.
-      - Speeds up convolutional neural networks (CNNs) and other layers. Used
-        in TensorFlow for layers like ``tf.nn.conv2d``, ``tf.nn.relu``, and
-        ``tf.nn.lstm_cell``.
-    * - `RCCL <https://github.com/ROCm/rccl>`_
-      - :version-ref:`RCCL rocm_version`
-      - Optimizes for multi-GPU communication for operations like AllReduce and
-        Broadcast.
-      - Distributed data parallel training (``tf.distribute.MirroredStrategy``).
-        Handles communication in multi-GPU setups.
-    * - `rocThrust <https://github.com/ROCm/rocThrust>`_
-      - :version-ref:`rocThrust rocm_version`
-      - Provides a C++ template library for parallel algorithms like sorting,
-        reduction, and scanning.
-      - Reduction operations like ``tf.reduce_sum``, ``tf.cumsum`` for computing
-        the cumulative sum of elements along a given axis or ``tf.unique`` to
-        finds unique elements in a tensor can use rocThrust.
-
-Supported and unsupported features
-===============================================================================
-
-The following section maps supported data types and GPU-accelerated TensorFlow
-features to their minimum supported ROCm and TensorFlow versions.
-
-Data types
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The data type of a tensor is specified using the ``dtype`` attribute or
-argument, and TensorFlow supports a wide range of data types for different use
-cases.
-
-The basic, single data types of `tf.dtypes <https://www.tensorflow.org/api_docs/python/tf/dtypes>`_
-are as follows:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Data type
-      - Description
-      - Since TensorFlow
-      - Since ROCm
-    * - ``bfloat16``
-      - 16-bit bfloat (brain floating point).
-      - 1.0.0
-      - 1.7
-    * - ``bool``
-      - Boolean.
-      - 1.0.0
-      - 1.7
-    * - ``complex128``
-      - 128-bit complex.
-      - 1.0.0
-      - 1.7
-    * - ``complex64``
-      - 64-bit complex.
-      - 1.0.0
-      - 1.7
-    * - ``double``
-      - 64-bit (double precision) floating-point.
-      - 1.0.0
-      - 1.7
-    * - ``float16``
-      - 16-bit (half precision) floating-point.
-      - 1.0.0
-      - 1.7
-    * - ``float32``
-      - 32-bit (single precision) floating-point.
-      - 1.0.0
-      - 1.7
-    * - ``float64``
-      - 64-bit (double precision) floating-point.
-      - 1.0.0
-      - 1.7
-    * - ``half``
-      - 16-bit (half precision) floating-point.
-      - 2.0.0
-      - 2.0
-    * - ``int16``
-      - Signed 16-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``int32``
-      - Signed 32-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``int64``
-      - Signed 64-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``int8``
-      - Signed 8-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``qint16``
-      - Signed quantized 16-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``qint32``
-      - Signed quantized 32-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``qint8``
-      - Signed quantized 8-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``quint16``
-      - Unsigned quantized 16-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``quint8``
-      - Unsigned quantized 8-bit integer.
-      - 1.0.0
-      - 1.7
-    * - ``resource``
-      - Handle to a mutable, dynamically allocated resource.
-      - 1.0.0
-      - 1.7
-    * - ``string``
-      - Variable-length string, represented as byte array.
-      - 1.0.0
-      - 1.7
-    * - ``uint16``
-      - Unsigned 16-bit (word) integer.
-      - 1.0.0
-      - 1.7
-    * - ``uint32``
-      - Unsigned 32-bit (dword) integer.
-      - 1.5.0
-      - 1.7
-    * - ``uint64``
-      - Unsigned 64-bit (qword) integer.
-      - 1.5.0
-      - 1.7
-    * - ``uint8``
-      - Unsigned 8-bit (byte) integer.
-      - 1.0.0
-      - 1.7
-    * - ``variant``
-      - Data of arbitrary type (known at runtime).
-      - 1.4.0
-      - 1.7
-
-Features
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This table provides an overview of key features in TensorFlow and their
-availability in ROCm.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Module
-      - Description
-      - Since TensorFlow
-      - Since ROCm
-    * - ``tf.linalg`` (Linear Algebra)
-      - Operations for matrix and tensor computations, such as
-        ``tf.linalg.matmul`` (matrix multiplication), ``tf.linalg.inv``
-        (matrix inversion) and ``tf.linalg.cholesky`` (Cholesky decomposition).
-        These leverage GPUs for high-performance linear algebra operations.
-      - 1.4
-      - 1.8.2
-    * - ``tf.nn`` (Neural Network Operations)
-      - GPU-accelerated building blocks for deep learning models, such as 2D
-        convolutions with ``tf.nn.conv2d``, max pooling operations with
-        ``tf.nn.max_pool``, activation functions like ``tf.nn.relu`` or softmax
-        for output layers with ``tf.nn.softmax``.
-      - 1.0
-      - 1.8.2
-    * - ``tf.image`` (Image Processing)
-      - GPU-accelerated functions for image preprocessing and augmentations,
-        such as resize images with ``tf.image.resize``, flip images horizontally
-        with ``tf.image.flip_left_right`` and adjust image brightness randomly
-        with ``tf.image.random_brightness``.
-      - 1.1
-      - 1.8.2
-    * - ``tf.keras`` (High-Level API)
-      - GPU acceleration for Keras layers and models, including dense layers
-        (``tf.keras.layers.Dense``), convolutional layers
-        (``tf.keras.layers.Conv2D``) and recurrent layers
-        (``tf.keras.layers.LSTM``).
-      - 1.4
-      - 1.8.2
-    * - ``tf.math`` (Mathematical Operations)
-      - GPU-accelerated mathematical operations, such as sum across dimensions
-        with ``tf.math.reduce_sum``, elementwise exponentiation with
-        ``tf.math.exp`` and sigmoid activation (``tf.math.sigmoid``).
-      - 1.5
-      - 1.8.2
-    * - ``tf.signal`` (Signal Processing)
-      - Functions for spectral analysis and signal transformations.
-      - 1.13
-      - 2.1
-    * - ``tf.data`` (Data Input Pipeline)
-      - GPU-accelerated data preprocessing for efficient input pipelines,
-        Prefetching with ``tf.data.experimental.AUTOTUNE``. GPU-enabled
-        transformations like map and batch.
-      - 1.4
-      - 1.8.2
-    * - ``tf.distribute`` (Distributed Training)
-      - Enabling to scale computations across multiple devices on a single
-        machine or across multiple machines.
-      - 1.13
-      - 2.1
-    * - ``tf.random`` (Random Number Generation)
-      - GPU-accelerated random number generation
-      - 1.12
-      - 1.9.2
-    * - ``tf.TensorArray`` (Dynamic Array Operations)
-      - Enables dynamic tensor manipulation on GPUs.
-      - 1.0
-      - 1.8.2
-    * - ``tf.sparse`` (Sparse Tensor Operations)
-      - GPU-accelerated sparse matrix manipulations.
-      - 1.9
-      - 1.9.0
-    * - ``tf.experimental.numpy``
-      - GPU-accelerated NumPy-like API for numerical computations.
-      - 2.4
-      - 4.1.1
-    * - ``tf.RaggedTensor``
-      - Handling of variable-length sequences and ragged tensors with GPU
-        support.
-      - 1.13
-      - 2.1
-    * - ``tf.function`` with XLA (Accelerated Linear Algebra)
-      - Enable GPU-accelerated functions in optimization.
-      - 1.14
-      - 2.4
-    * - ``tf.quantization``
-      - Quantized operations for inference, accelerated on GPUs.
-      - 1.12
-      - 1.9.2
-
-Distributed library features
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Enables developers to scale computations across multiple devices on a single machine or
-across multiple machines.
-
-.. list-table::
-   :header-rows: 1
-
-   * - Feature
-     - Description
-     - Since TensorFlow
-     - Since ROCm
-   * - ``MultiWorkerMirroredStrategy``
-     - Synchronous training across multiple workers using mirrored variables.
-     - 2.0
-     - 3.0
-   * - ``MirroredStrategy``
-     - Synchronous training across multiple GPUs on one machine.
-     - 1.5
-     - 2.5
-   * - ``TPUStrategy``
-     - Efficiently trains models on Google TPUs.
-     - 1.9
-     - ❌
-   * - ``ParameterServerStrategy``
-     - Asynchronous training using parameter servers for variable management.
-     - 2.1
-     - 4.0
-   * - ``CentralStorageStrategy``
-     - Keeps variables on a single device and performs computation on multiple
-       devices.
-     - 2.3
-     - 4.1
-   * - ``CollectiveAllReduceStrategy``
-     - Synchronous training across multiple devices and hosts.
-     - 1.14
-     - 3.5
-   * - Distribution Strategies API
-     - High-level API to simplify distributed training configuration and
-       execution.
-     - 1.10
-     - 3.0
-
-Unsupported TensorFlow features
-===============================================================================
-
-The following are GPU-accelerated TensorFlow features not currently supported by
-ROCm.
-
-.. list-table::
-    :header-rows: 1
-
-    * - Feature
-      - Description
-      - Since TensorFlow
-    * - Mixed Precision with TF32
-      - Mixed precision with TF32 is used for matrix multiplications,
-        convolutions, and other linear algebra operations, particularly in
-        deep learning workloads like CNNs and transformers.
-      - 2.4
-    * - ``tf.distribute.TPUStrategy``
-      - Efficiently trains models on Google TPUs.
-      - 1.9
-
-Use cases and recommendations
-===============================================================================
-
-* The `Training a Neural Collaborative Filtering (NCF) Recommender on an AMD
-  GPU <https://rocm.blogs.amd.com/artificial-intelligence/ncf/README.html>`_
-  blog post discusses training an NCF recommender system using TensorFlow. It
-  explains how NCF improves traditional collaborative filtering methods by
-  leveraging neural networks to model non-linear user-item interactions. The
-  post outlines the implementation using the recommenders library, focusing on
-  the use of implicit data (for example, user interactions like viewing or
-  purchasing) and how it addresses challenges like the lack of negative values.
-
-* The `Creating a PyTorch/TensorFlow code environment on AMD GPUs
-  <https://rocm.blogs.amd.com/software-tools-optimization/pytorch-tensorflow-env/README.html>`_
-  blog post provides instructions for creating a machine learning environment
-  for PyTorch and TensorFlow on AMD GPUs using ROCm. It covers steps like
-  installing the libraries, cloning code repositories, installing dependencies,
-  and troubleshooting potential issues with CUDA-based code. Additionally, it
-  explains how to HIPify code (port CUDA code to HIP) and manage Docker images
-  for a better experience on AMD GPUs. This guide aims to help data scientists
-  and ML practitioners adapt their code for AMD GPUs.
-
-For more use cases and recommendations, see the `ROCm Tensorflow blog posts <https://rocm.blogs.amd.com/blog/tag/tensorflow.html>`_.
--- a/docs/conceptual/ai-pytorch-inception.md
+++ b/docs/conceptual/ai-pytorch-inception.md
--- a/docs/conceptual/cmake-packages.rst
+++ b/docs/conceptual/cmake-packages.rst
@@ -1,407 +0,0 @@
-.. meta::
-   :description: Using CMake
-   :keywords: CMake, dependencies, HIP, C++, AMD, ROCm
-
-*********************************
-Using CMake
-*********************************
-
-Most components in ROCm support CMake. Projects depending on header-only or
-library components typically require CMake 3.5 or higher whereas those wanting
-to make use of the CMake HIP language support will require CMake 3.21 or higher.
-
-Finding dependencies
-====================
-
-.. note::
-
-  For a complete
-  reference on how to deal with dependencies in CMake, refer to the CMake docs
-  on `find_package
-  <https://cmake.org/cmake/help/latest/command/find_package.html>`_ and the
-  `Using Dependencies Guide
-  <https://cmake.org/cmake/help/latest/guide/using-dependencies/index.html>`_
-  to get an overview of CMake related facilities.
-
-In short, CMake supports finding dependencies in two ways:
-
-* In Module mode, it consults a file ``Find<PackageName>.cmake`` which tries to find the component
-  in typical install locations and layouts. CMake ships a few dozen such scripts, but users and projects
-  may ship them as well.
-
-* In Config mode, it locates a file named ``<packagename>-config.cmake`` or
-  ``<PackageName>Config.cmake`` which describes the installed component in all regards needed to
-  consume it.
-
-ROCm predominantly relies on Config mode, one notable exception being the Module
-driving the compilation of HIP programs on NVIDIA runtimes. As such, when
-dependencies are not found in standard system locations, one either has to
-instruct CMake to search for package config files in additional folders using
-the ``CMAKE_PREFIX_PATH`` variable (a semi-colon separated list of file system
-paths), or using ``<PackageName>_ROOT`` variable on a project-specific basis.
-
-There are nearly a dozen ways to set these variables. One may be more convenient
-over the other depending on your workflow. Conceptually the simplest is adding
-it to your CMake configuration command on the command line via
-``-D CMAKE_PREFIX_PATH=....`` . AMD packaged ROCm installs can typically be
-added to the config file search paths such as:
-
-*  Windows: ``-D CMAKE_PREFIX_PATH=${env:HIP_PATH}``
-
-*  Linux: ``-D CMAKE_PREFIX_PATH=/opt/rocm``
-
-ROCm provides the respective *config-file* packages, and this enables
-``find_package`` to be used directly. ROCm does not require any Find module as
-the *config-file* packages are shipped with the upstream projects, such as
-rocPRIM and other ROCm libraries.
-
-For a complete guide on where and how ROCm may be installed on a system, refer
-to the installation guides for
-`Linux <https://rocm.docs.amd.com/projects/install-on-linux/en/latest/tutorial/quick-start.html>`_
-and
-`Windows <https://rocm.docs.amd.com/projects/install-on-windows/en/latest/index.html>`_.
-
-Using HIP in CMake
-==================
-
-ROCm components providing a C/C++ interface support consumption via any
-C/C++ toolchain that CMake knows how to drive. ROCm also supports the CMake HIP
-language features, allowing users to program using the HIP single-source
-programming model. When a program (or translation-unit) uses the HIP API without
-compiling any GPU device code, HIP can be treated in CMake as a simple C/C++
-library.
-
-Using the HIP single-source programming model
---------------------------------------------
-
-Source code written in the HIP dialect of C++ typically uses the `.hip`
-extension. When the HIP CMake language is enabled, it will automatically
-associate such source files with the HIP toolchain being used.
-
-.. code-block:: cmake
-
-  cmake_minimum_required(VERSION 3.21) # HIP language support requires 3.21
-  cmake_policy(VERSION 3.21.3...3.27)
-  project(MyProj LANGUAGES HIP)
-  add_executable(MyApp Main.hip)
-
-Should you have existing CUDA code that is from the source compatible subset of
-HIP, you can tell CMake that despite their `.cu` extension, they're HIP sources.
-Do note that this mostly facilitates compiling kernel code-only source files,
-as host-side CUDA API won't compile in this fashion.
-
-.. code-block:: cmake
-
-  add_library(MyLib MyLib.cu)
-  set_source_files_properties(MyLib.cu PROPERTIES LANGUAGE HIP)
-
-CMake itself only hosts part of the HIP language support, such as defining
-HIP-specific properties, etc. while the other half ships with the HIP
-implementation, such as ROCm. CMake will search for a file
-`hip-lang-config.cmake` describing how the the properties defined by CMake
-translate to toolchain invocations. If one installs ROCm using non-standard
-methods or layouts and CMake can't locate this file or detect parts of the SDK,
-there's a catch-all, last resort variable consulted locating this file,
-``-D CMAKE_HIP_COMPILER_ROCM_ROOT:PATH=`` which should be set the root of the
-ROCm installation.
-
-.. note::
-    Imported targets defined by `hip-lang-config.cmake` are for internal use
-    only.
-
-If the user doesn't provide a semi-colon delimited list of device architectures
-via ``CMAKE_HIP_ARCHITECTURES``, CMake will select some sensible default. It is
-advised though that if a user knows what devices they wish to target, then set
-this variable explicitly.
-
-Consuming ROCm C/C++ libraries
------------------------------
-
-Libraries such as rocBLAS, rocFFT, MIOpen, etc. behave as C/C++ libraries.
-Illustrated in the example below is a C++ application using MIOpen from CMake.
-It calls ``find_package(miopen)``, which provides the ``MIOpen`` imported
-target. This can be linked with ``target_link_libraries``
-
-.. code-block:: cmake
-
-  cmake_minimum_required(VERSION 3.5) # find_package(miopen) requires 3.5
-  cmake_policy(VERSION 3.5...3.27)
-  project(MyProj LANGUAGES CXX)
-  find_package(miopen)
-  add_library(MyLib ...)
-  target_link_libraries(MyLib PUBLIC MIOpen)
-
-.. note::
-
-  Most libraries are designed as host-only API, so using a GPU device
-  compiler is not necessary for downstream projects unless they use GPU device
-  code.
-
-Consuming the HIP API in C++ code
---------------------------------
-
-Consuming the HIP API without compiling single-source GPU device code can be
-done using any C++ compiler. The ``find_package(hip)`` provides the
-``hip::host`` imported target to use HIP in this scenario.
-
-.. code-block:: cmake
-
-  cmake_minimum_required(VERSION 3.5) # find_package(hip) requires 3.5
-  cmake_policy(VERSION 3.5...3.27)
-  project(MyProj LANGUAGES CXX)
-  find_package(hip REQUIRED)
-  add_executable(MyApp ...)
-  target_link_libraries(MyApp PRIVATE hip::host)
-
-When mixing such ``CXX`` sources with ``HIP`` sources holding device-code, link
-only to `hip::host`. If HIP sources don't have `.hip` as their extension, use
-`set_source_files_properties(<hip_sources>... PROPERTIES LANGUAGE HIP)` on them.
-Linking to `hip::host` will set all the necessary flags for the ``CXX`` sources
-while ``HIP`` sources inherit all flags from the built-in language support.
-Having HIP sources in a target will turn the |LINK_LANG|_ into ``HIP``.
-
-.. |LINK_LANG| replace:: ``LINKER_LANGUAGE``
-.. _LINK_LANG: https://cmake.org/cmake/help/latest/prop_tgt/LINKER_LANGUAGE.html
-
-Compiling device code in C++ language mode
------------------------------------------
-
-.. attention::
-
-  The workflow detailed here is considered legacy and is shown for
-  understanding's sake. It pre-dates the existence of HIP language support in
-  CMake. If source code has HIP device code in it, it is a HIP source file
-  and should be compiled as such. Only resort to the method below if your
-  HIP-enabled CMake code path can't mandate CMake version 3.21.
-
-If code uses the HIP API and compiles GPU device code, it requires using a
-device compiler. The compiler for CMake can be set using either the
-``CMAKE_C_COMPILER`` and ``CMAKE_CXX_COMPILER`` variable or using the ``CC``
-and ``CXX`` environment variables. This can be set when configuring CMake or
-put into a CMake toolchain file. The device compiler must be set to a
-compiler that supports AMD GPU targets, which is usually Clang.
-
-The ``find_package(hip)`` provides the ``hip::device`` imported target to add
-all the flags necessary for device compilation.
-
-.. code-block:: cmake
-
-  cmake_minimum_required(VERSION 3.8) # cxx_std_11 requires 3.8
-  cmake_policy(VERSION 3.8...3.27)
-  project(MyProj LANGUAGES CXX)
-  find_package(hip REQUIRED)
-  add_library(MyLib ...)
-  target_link_libraries(MyLib PRIVATE hip::device)
-  target_compile_features(MyLib PRIVATE cxx_std_11)
-
-.. note::
-
-  Compiling for the GPU device requires at least C++11.
-
-This project can then be configured with the following CMake commands:
-
-*  Windows: ``cmake -D CMAKE_CXX_COMPILER:PATH=${env:HIP_PATH}\bin\clang++.exe``
-*  Linux: ``cmake -D CMAKE_CXX_COMPILER:PATH=/opt/rocm/bin/amdclang++``
-
-Which use the device compiler provided from the binary packages of
-`ROCm HIP SDK <https://www.amd.com/en/developer/resources/rocm-hub/hip-sdk.html>`_ and
-`repo.radeon.com <https://repo.radeon.com>`_ respectively.
-
-When using the ``CXX`` language support to compile HIP device code, selecting the
-target GPU architectures is done via setting the ``GPU_TARGETS`` variable.
-``CMAKE_HIP_ARCHITECTURES`` only exists when the HIP language is enabled. By
-default, this is set to some subset of the currently supported architectures of
-AMD ROCm. It can be set to the CMake option ``-D GPU_TARGETS="gfx1032;gfx1035"``.
-
-ROCm CMake packages
-------------------
-
-+-----------+----------+--------------------------------------------------------+
-| Component | Package  | Targets                                                |
-+===========+==========+========================================================+
-| HIP       | hip      | ``hip::host``, ``hip::device``                         |
-+-----------+----------+--------------------------------------------------------+
-| rocPRIM   | rocprim  | ``roc::rocprim``                                       |
-+-----------+----------+--------------------------------------------------------+
-| rocThrust | rocthrust| ``roc::rocthrust``                                     |
-+-----------+----------+--------------------------------------------------------+
-| hipCUB    | hipcub   | ``hip::hipcub``                                        |
-+-----------+----------+--------------------------------------------------------+
-| rocRAND   | rocrand  | ``roc::rocrand``                                       |
-+-----------+----------+--------------------------------------------------------+
-| rocBLAS   | rocblas  | ``roc::rocblas``                                       |
-+-----------+----------+--------------------------------------------------------+
-| rocSOLVER | rocsolver| ``roc::rocsolver``                                     |
-+-----------+----------+--------------------------------------------------------+
-| hipBLAS   | hipblas  | ``roc::hipblas``                                       |
-+-----------+----------+--------------------------------------------------------+
-| rocFFT    | rocfft   | ``roc::rocfft``                                        |
-+-----------+----------+--------------------------------------------------------+
-| hipFFT    | hipfft   | ``hip::hipfft``                                        |
-+-----------+----------+--------------------------------------------------------+
-| rocSPARSE | rocsparse| ``roc::rocsparse``                                     |
-+-----------+----------+--------------------------------------------------------+
-| hipSPARSE | hipsparse| ``roc::hipsparse``                                     |
-+-----------+----------+--------------------------------------------------------+
-| rocALUTION|rocalution| ``roc::rocalution``                                    |
-+-----------+----------+--------------------------------------------------------+
-| RCCL      | rccl     | ``rccl``                                               |
-+-----------+----------+--------------------------------------------------------+
-| MIOpen    | miopen   | ``MIOpen``                                             |
-+-----------+----------+--------------------------------------------------------+
-| MIGraphX  | migraphx | ``migraphx::migraphx``, ``migraphx::migraphx_c``,      |
-|           |          | ``migraphx::migraphx_cpu``, ``migraphx::migraphx_gpu``,|
-|           |          | ``migraphx::migraphx_onnx``, ``migraphx::migraphx_tf`` |
-+-----------+----------+--------------------------------------------------------+
-
-Using CMake presets
-===================
-
-CMake command lines depending on how specific users like to be when compiling
-code can grow to unwieldy lengths. This is the primary reason why projects tend
-to bake script snippets into their build definitions controlling compiler
-warning levels, changing CMake defaults (``CMAKE_BUILD_TYPE`` or
-``BUILD_SHARED_LIBS`` just to name a few) and all sorts anti-patterns, all in
-the name of convenience.
-
-Load on the command-line interface (CLI) starts immediately by selecting a
-toolchain, the set of utilities used to compile programs. To ease some of the
-toolchain related pains, CMake does consult the ``CC`` and ``CXX`` environmental
-variables when setting a default ``CMAKE_C[XX]_COMPILER`` respectively, but that
-is just the tip of the iceberg. There's a fair number of variables related to
-just the toolchain itself (typically supplied using
-`toolchain files <https://cmake.org/cmake/help/latest/manual/cmake-toolchains.7.html>`_
-), and then we still haven't talked about user preference or project-specific
-options.
-
-IDEs supporting CMake (Visual Studio, Visual Studio Code, CLion, etc.) all came
-up with their own way to register command-line fragments of different purpose in
-a setup-and-forget fashion for quick assembly using graphical front-ends. This is
-all nice, but configurations aren't portable, nor can they be reused in
-Continuous Integration (CI) pipelines. CMake has condensed existing practice
-into a portable JSON format that works in all IDEs and can be invoked from any
-command line. This is
-`CMake Presets <https://cmake.org/cmake/help/latest/manual/cmake-presets.7.html>`_.
-
-There are two types of preset files: one supplied by the project, called
-``CMakePresets.json`` which is meant to be committed to version control,
-typically used to drive CI; and one meant for the user to provide, called
-``CMakeUserPresets.json``, typically used to house user preference and adapting
-the build to the user's environment. These JSON files are allowed to include
-other JSON files and the user presets always implicitly includes the non-user
-variant.
-
-Using HIP with presets
----------------------
-
-Following is an example ``CMakeUserPresets.json`` file which actually compiles
-the `amd/rocm-examples <https://github.com/amd/rocm-examples>`_ suite of sample
-applications on a typical ROCm installation:
-
-.. code-block:: json
-
-  {
-    "version": 3,
-    "cmakeMinimumRequired": {
-      "major": 3,
-      "minor": 21,
-      "patch": 0
-    },
-    "configurePresets": [
-      {
-        "name": "layout",
-        "hidden": true,
-        "binaryDir": "${sourceDir}/build/${presetName}",
-        "installDir": "${sourceDir}/install/${presetName}"
-      },
-      {
-        "name": "generator-ninja-multi-config",
-        "hidden": true,
-        "generator": "Ninja Multi-Config"
-      },
-      {
-        "name": "toolchain-makefiles-c/c++-amdclang",
-        "hidden": true,
-        "cacheVariables": {
-          "CMAKE_C_COMPILER": "/opt/rocm/bin/amdclang",
-          "CMAKE_CXX_COMPILER": "/opt/rocm/bin/amdclang++",
-          "CMAKE_HIP_COMPILER": "/opt/rocm/bin/amdclang++"
-        }
-      },
-      {
-        "name": "clang-strict-iso-high-warn",
-        "hidden": true,
-        "cacheVariables": {
-          "CMAKE_C_FLAGS": "-Wall -Wextra -pedantic",
-          "CMAKE_CXX_FLAGS": "-Wall -Wextra -pedantic",
-          "CMAKE_HIP_FLAGS": "-Wall -Wextra -pedantic"
-        }
-      },
-      {
-        "name": "ninja-mc-rocm",
-        "displayName": "Ninja Multi-Config ROCm",
-        "inherits": [
-          "layout",
-          "generator-ninja-multi-config",
-          "toolchain-makefiles-c/c++-amdclang",
-          "clang-strict-iso-high-warn"
-        ]
-      }
-    ],
-    "buildPresets": [
-      {
-        "name": "ninja-mc-rocm-debug",
-        "displayName": "Debug",
-        "configuration": "Debug",
-        "configurePreset": "ninja-mc-rocm"
-      },
-      {
-        "name": "ninja-mc-rocm-release",
-        "displayName": "Release",
-        "configuration": "Release",
-        "configurePreset": "ninja-mc-rocm"
-      },
-      {
-        "name": "ninja-mc-rocm-debug-verbose",
-        "displayName": "Debug (verbose)",
-        "configuration": "Debug",
-        "configurePreset": "ninja-mc-rocm",
-        "verbose": true
-      },
-      {
-        "name": "ninja-mc-rocm-release-verbose",
-        "displayName": "Release (verbose)",
-        "configuration": "Release",
-        "configurePreset": "ninja-mc-rocm",
-        "verbose": true
-      }
-    ],
-    "testPresets": [
-      {
-        "name": "ninja-mc-rocm-debug",
-        "displayName": "Debug",
-        "configuration": "Debug",
-        "configurePreset": "ninja-mc-rocm",
-        "execution": {
-          "jobs": 0
-        }
-      },
-      {
-        "name": "ninja-mc-rocm-release",
-        "displayName": "Release",
-        "configuration": "Release",
-        "configurePreset": "ninja-mc-rocm",
-        "execution": {
-          "jobs": 0
-        }
-      }
-    ]
-  }
-
-.. note::
-
-  Getting presets to work reliably on Windows requires some CMake improvements
-  and/or support from compiler vendors. (Refer to
-  `Add support to the Visual Studio generators <https://gitlab.kitware.com/cmake/cmake/-/issues/24245>`_
-  and `Sourcing environment scripts <https://gitlab.kitware.com/cmake/cmake/-/issues/21619>`_
-  .)
--- a/docs/conceptual/compiler-topics.md
+++ b/docs/conceptual/compiler-topics.md
@@ -1,14 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="AMD ROCm documentation">
-  <meta name="keywords" content="documentation, guides, installation, compatibility, support,
-  reference, ROCm, AMD">
-</head>
-
-# Using compiler features
-
-The following topics describe using specific features of the compilation tools:
-
-* [ROCm compiler infrastructure](https://rocm.docs.amd.com/projects/llvm-project/en/latest/index.html)
-* [Using AddressSanitizer](https://rocm.docs.amd.com/projects/llvm-project/en/latest/conceptual/using-gpu-sanitizer.html)
-* [OpenMP support](https://rocm.docs.amd.com/projects/llvm-project/en/latest/conceptual/openmp.html)
--- a/docs/conceptual/file-reorg.md
+++ b/docs/conceptual/file-reorg.md
@@ -1,172 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="ROCm Linux Filesystem Hierarchy Standard reorganization">
-  <meta name="keywords" content="FHS, Linux Filesystem Hierarchy Standard, directory structure,
-  AMD, ROCm">
-</head>
-
-# ROCm Linux Filesystem Hierarchy Standard reorganization
-
-## Introduction
-
-The ROCm Software has adopted the Linux Filesystem Hierarchy Standard (FHS) [https://refspecs.linuxfoundation.org/FHS_3.0/fhs/index.html](https://refspecs.linuxfoundation.org/FHS_3.0/fhs/index.html) in order to to ensure ROCm is consistent with standard open source conventions. The following sections specify how current and future releases of ROCm adhere to FHS, how the previous ROCm file system is supported, and how improved versioning specifications are applied to ROCm.
-
-## Adopting the FHS
-
-In order to standardize ROCm directory structure and directory content layout ROCm has adopted the [FHS](https://refspecs.linuxfoundation.org/FHS_3.0/fhs/index.html), adhering to open source conventions for Linux-based distribution. FHS ensures internal consistency within the ROCm stack, as well as external consistency with other systems and distributions. The ROCm proposed file structure is outlined below:
-
-```none
-/opt/rocm-<ver>
-    | -- bin
-         | -- all public binaries
-    | -- lib
-         | -- lib<soname>.so->lib<soname>.so.major->lib<soname>.so.major.minor.patch
-              (public libaries to link with applications)
-         | -- <component>
-              | -- architecture dependent libraries and binaries used internally by components
-         | -- cmake
-              | -- <component>
-                   | --<component>-config.cmake
-    | -- libexec
-         | -- <component>
-              | -- non ISA/architecture independent executables used internally by components
-    | -- include
-         | -- <component>
-              | -- public header files
-    | -- share
-         | -- html
-              | -- <component>
-                   | -- html documentation
-         | -- info
-              | -- <component>
-                   | -- info files
-         | -- man
-              | -- <component>
-                   | -- man pages
-         | -- doc
-              | -- <component>
-                   | -- license files
-         | -- <component>
-              | -- samples
-              | -- architecture independent misc files
-```
-
-## Changes from earlier ROCm versions
-
-The following table provides a brief overview of the new ROCm FHS layout, compared to the layout of earlier ROCm versions. Note that /opt/ is used to denote the default rocm-installation-path and should be replaced in case of a non-standard installation location of the ROCm distribution.
-
-```none
- ______________________________________________________
-|  New ROCm Layout            |  Previous ROCm Layout  |
-|_____________________________|________________________|
-| /opt/rocm-<ver>             | /opt/rocm-<ver>        |
-|     | -- bin                |     | -- bin           |
-|     | -- lib                |     | -- lib           |
-|          | -- cmake         |     | -- include       |
-|     | -- libexec            |     | -- <component_1> |
-|     | -- include            |          | -- bin      |
-|          | -- <component_1> |          | -- cmake    |
-|     | -- share              |          | -- doc      |
-|          | -- html          |          | -- lib      |
-|          | -- info          |          | -- include  |
-|          | -- man           |          | -- samples  |
-|          | -- doc           |     | -- <component_n> |
-|          | -- <component_1> |          | -- bin      |
-|               | -- samples  |          | -- cmake    |
-|               | -- ..       |          | -- doc      |
-|          | -- <component_n> |          | -- lib      |
-|               | -- samples  |          | -- include  |
-|               | -- ..       |          | -- samples  |
-|______________________________________________________|
-```
-
-## ROCm FHS reorganization: backward compatibility
-
-The FHS file organization for ROCm was first introduced in the release of ROCm 5.2 . Backward compatibility was implemented to make sure users could still run their ROCm applications while transitioning to the new FHS. ROCm has moved header files and libraries to their new locations as indicated in the above structure, and included symbolic-links and wrapper header files in their old location for backward compatibility. The following sections detail ROCm backward compatibility implementation for wrapper header files, executable files, library files and CMake config files.
-
-### Wrapper header files
-
-Wrapper header files are placed in the old location (
-`/opt/rocm-<ver>/<component>/include`) with a warning message to include files
-from the new location (`/opt/rocm-<ver>/include`) as shown in the example below.
-
-```cpp
-#pragma message "This file is deprecated. Use file from include path /opt/rocm-ver/include/ and prefix with hip."
-#include <hip/hip_runtime.h>
-```
-
-* Starting at ROCm 5.2 release, the deprecation for backward compatibility wrapper header files is: `#pragma` message announcing `#warning`.
-* Starting from ROCm 6.0 (tentatively) backward compatibility for wrapper header files will be removed, and the `#pragma` message will be announcing `#error`.
-
-### Executable files
-
-Executable files are available in the `/opt/rocm-<ver>/bin` folder. For backward
-compatibility, the old library location (`/opt/rocm-<ver>/<component>/bin`) has a
-soft link to the library at the new location. Soft links will be removed in a
-future release, tentatively ROCm v6.0.
-
-```bash
-$ ls -l /opt/rocm/hip/bin/
-lrwxrwxrwx 1 root root   24 Jan 1 23:32 hipcc -> ../../bin/hipcc
-```
-
-### Library files
-
-Library files are available in the `/opt/rocm-<ver>/lib` folder. For backward
-compatibility, the old library location (`/opt/rocm-<ver>/<component>/lib`) has a
-soft link to the library at the new location. Soft links will be removed in a
-future release, tentatively ROCm v6.0.
-
-```shell
-$ ls -l /opt/rocm/hip/lib/
-drwxr-xr-x 4 root root 4096 Jan 1 10:45 cmake
-lrwxrwxrwx 1 root root   24 Jan 1 23:32 libamdhip64.so -> ../../lib/libamdhip64.so
-```
-
-### CMake config files
-
-All CMake configuration files are available in the
-`/opt/rocm-<ver>/lib/cmake/<component>` folder. For backward compatibility, the
-old CMake locations (`/opt/rocm-<ver>/<component>/lib/cmake`) consist of a soft
-link to the new CMake config. Soft links will be removed in a future release,
-tentatively ROCm v6.0.
-
-```shell
-$ ls -l /opt/rocm/hip/lib/cmake/hip/
-lrwxrwxrwx 1 root root 42 Jan 1 23:32 hip-config.cmake -> ../../../../lib/cmake/hip/hip-config.cmake
-```
-
-## Changes required in applications using ROCm
-
-Applications using ROCm are advised to use the new file paths. As the old files
-will be deprecated in a future release. Applications have to make sure to include
-correct header file and use correct search paths.
-
-1. `#include<header_file.h>` needs to be changed to
-   `#include <component/header_file.h>`
-
-   For example: `#include <hip.h>` needs to change
-   to `#include <hip/hip.h>`
-
-2. Any variable in CMake or Makefiles pointing to component folder needs to
-   changed.
-
-   For example: `VAR1=/opt/rocm/hip` needs to be changed to `VAR1=/opt/rocm`
-   `VAR2=/opt/rocm/hsa` needs to be changed to `VAR2=/opt/rocm`
-
-3. Any reference to `/opt/rocm/<component>/bin` or `/opt/rocm/<component>/lib`
-   needs to be changed to `/opt/rocm/bin` and `/opt/rocm/lib/`, respectively.
-
-## Changes in versioning specifications
-
-In order to better manage ROCm dependencies specification and allow smoother releases of ROCm while avoiding dependency conflicts, ROCm software shall adhere to the following scheme when numbering and incrementing ROCm files versions:
-
-rocm-\<ver\>, where \<ver\> = \<x.y.z\>
-
-x.y.z denote: MAJOR.MINOR.PATCH
-
-z: PATCH - increment z when implementing backward compatible bug fixes.
-
-y: MINOR - increment y when implementing minor changes that add functionality but are still backward compatible.
-
-x: MAJOR - increment x when implementing major changes that are not backward compatible.
--- a/docs/conceptual/gpu-arch.md
+++ b/docs/conceptual/gpu-arch.md
@@ -1,72 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="GPU architecture">
-  <meta name="keywords" content="GPU architecture, architecture support, MI200, MI250, RDNA,
-  MI100, AMD Instinct">
-</head>
-
-(gpu-arch-documentation)=
-
-# GPU architecture documentation
-
-:::::{grid} 1 1 2 2
-:gutter: 1
-
-:::{grid-item-card}
-**AMD Instinct MI300 series**
-
-Review hardware aspects of the AMD Instinct™ MI300 series of GPU accelerators and the CDNA™ 3
-architecture.
-
-* [AMD Instinct™ MI300 microarchitecture](./gpu-arch/mi300.md)
-* [AMD Instinct MI300/CDNA3 ISA](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf)
-* [White paper](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/white-papers/amd-cdna-3-white-paper.pdf)
-* [Performance counters](./gpu-arch/mi300-mi200-performance-counters.rst)
-:::
-
-:::{grid-item-card}
-**AMD Instinct MI200 series**
-
-Review hardware aspects of the AMD Instinct™ MI200 series of GPU accelerators and the CDNA™ 2
-architecture.
-
-* [AMD Instinct™ MI250 microarchitecture](./gpu-arch/mi250.md)
-* [AMD Instinct MI200/CDNA2 ISA](https://www.amd.com/system/files/TechDocs/instinct-mi200-cdna2-instruction-set-architecture.pdf)
-* [White paper](https://www.amd.com/content/dam/amd/en/documents/instinct-business-docs/white-papers/amd-cdna2-white-paper.pdf)
-* [Performance counters](./gpu-arch/mi300-mi200-performance-counters.rst)
-
-:::
-
-:::{grid-item-card}
-**AMD Instinct MI100**
-
-Review hardware aspects of the AMD Instinct™ MI100 series of GPU accelerators and the CDNA™ 1
-architecture.
-
-* [AMD Instinct™ MI100 microarchitecture](./gpu-arch/mi100.md)
-* [AMD Instinct MI100/CDNA1 ISA](https://www.amd.com/system/files/TechDocs/instinct-mi100-cdna1-shader-instruction-set-architecture%C2%A0.pdf)
-* [White paper](https://www.amd.com/content/dam/amd/en/documents/instinct-business-docs/white-papers/amd-cdna-white-paper.pdf)
-
-:::
-
-:::{grid-item-card}
-**RDNA**
-
-* [AMD RDNA4 ISA](https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf)
-* [AMD RDNA3 ISA](https://www.amd.com/system/files/TechDocs/rdna3-shader-instruction-set-architecture-feb-2023_0.pdf)
-* [AMD RDNA2 ISA](https://www.amd.com/system/files/TechDocs/rdna2-shader-instruction-set-architecture.pdf)
-* [AMD RDNA ISA](https://www.amd.com/system/files/TechDocs/rdna-shader-instruction-set-architecture.pdf)
-
-:::
-
-:::{grid-item-card}
-**Older architectures**
-
-* [AMD Instinct MI50/Vega 7nm ISA](https://www.amd.com/system/files/TechDocs/vega-7nm-shader-instruction-set-architecture.pdf)
-* [AMD Instinct MI25/Vega ISA](https://www.amd.com/system/files/TechDocs/vega-shader-instruction-set-architecture.pdf)
-* [AMD GCN3 ISA](https://www.amd.com/system/files/TechDocs/gcn3-instruction-set-architecture.pdf)
-* [AMD Vega Architecture White Paper](https://en.wikichip.org/w/images/a/a1/vega-whitepaper.pdf)
-
-:::
-
-:::::
--- a/docs/conceptual/gpu-arch/mi100.md
+++ b/docs/conceptual/gpu-arch/mi100.md
@@ -1,95 +0,0 @@
---
-myst:
-  html_meta:
-    "description lang=en": "Learn about the AMD Instinct MI100 series architecture."
-    "keywords": "Instinct, MI100, microarchitecture, AMD, ROCm"
---
-
-# AMD Instinct™ MI100 microarchitecture
-
-The following image shows the node-level architecture of a system that
-comprises two AMD EPYC™ processors and (up to) eight AMD Instinct™ accelerators.
-The two EPYC processors are connected to each other with the AMD Infinity™
-fabric which provides a high-bandwidth (up to 18 GT/sec) and coherent links such
-that each processor can access the available node memory as a single
-shared-memory domain in a non-uniform memory architecture (NUMA) fashion. In a
-2P, or dual-socket, configuration, three AMD Infinity™ fabric links are
-available to connect the processors plus one PCIe Gen 4 x16 link per processor
-can attach additional I/O devices such as the host adapters for the network
-fabric.
-
-![Structure of a single GCD in the AMD Instinct MI100 accelerator](../../data/conceptual/gpu-arch/image004.png "Node-level system architecture with two AMD EPYC™ processors and eight AMD Instinct™ accelerators.")
-
-In a typical node configuration, each processor can host up to four AMD
-Instinct™ accelerators that are attached using PCIe Gen 4 links at 16 GT/sec,
-which corresponds to a peak bidirectional link bandwidth of 32 GB/sec. Each hive
-of four accelerators can participate in a fully connected, coherent AMD
-Instinct™ fabric that connects the four accelerators using 23 GT/sec AMD
-Infinity fabric links that run at a higher frequency than the inter-processor
-links. This inter-GPU link can be established in certified server systems if the
-GPUs are mounted in neighboring PCIe slots by installing the AMD Infinity
-Fabric™ bridge for the AMD Instinct™ accelerators.
-
-## Microarchitecture
-
-The microarchitecture of the AMD Instinct accelerators is based on the AMD CDNA
-architecture, which targets compute applications such as high-performance
-computing (HPC) and AI & machine learning (ML) that run on everything from
-individual servers to the world's largest exascale supercomputers. The overall
-system architecture is designed for extreme scalability and compute performance.
-
-![Structure of the AMD Instinct accelerator (MI100 generation)](../../data/conceptual/gpu-arch/image005.png "Structure of the AMD Instinct accelerator (MI100 generation)")
-
-The above image shows the AMD Instinct accelerator with its PCIe Gen 4 x16
-link (16 GT/sec, at the bottom) that connects the GPU to (one of) the host
-processor(s). It also shows the three AMD Infinity Fabric ports that provide
-high-speed links (23 GT/sec, also at the bottom) to the other GPUs of the local
-hive.
-
-On the left and right of the floor plan, the High Bandwidth Memory (HBM)
-attaches via the GPU memory controller.  The MI100 generation of the AMD
-Instinct accelerator offers four stacks of HBM generation 2 (HBM2) for a total
-of 32GB with a 4,096bit-wide memory interface. The peak memory bandwidth of the
-attached HBM2 is 1.228 TB/sec at a memory clock frequency of 1.2 GHz.
-
-The execution units of the GPU are depicted in the above image as Compute
-Units (CU). There are a total 120 compute units that are physically organized
-into eight Shader Engines (SE) with fifteen compute units per shader engine.
-Each compute unit is further sub-divided into four SIMD units that process SIMD
-instructions of 16 data elements per instruction. This enables the CU to process
-64 data elements (a so-called 'wavefront') at a peak clock frequency of 1.5 GHz.
-Therefore, the theoretical maximum FP64 peak performance is 11.5 TFLOPS
-(`4 [SIMD units] x 16 [elements per instruction] x 120 [CU] x 1.5 [GHz]`).
-
-![Block diagram of an MI100 compute unit with detailed SIMD view of the AMD CDNA architecture](../../data/conceptual/gpu-arch/image006.png "An MI100 compute unit with detailed SIMD view of the AMD CDNA architecture")
-
-The preceding image shows the block diagram of a single CU of an AMD Instinct™
-MI100 accelerator and summarizes how instructions flow through the execution
-engines. The CU fetches the instructions via a 32KB instruction cache and moves
-them forward to execution via a dispatcher. The CU can handle up to ten
-wavefronts at a time and feed their instructions into the execution unit. The
-execution unit contains 256 vector general-purpose registers (VGPR) and 800
-scalar general-purpose registers (SGPR). The VGPR and SGPR are dynamically
-allocated to the executing wavefronts. A wavefront can access a maximum of 102
-scalar registers. Excess scalar-register usage will cause register spilling and
-thus may affect execution performance.
-
-A wavefront can occupy any number of VGPRs from 0 to 256, directly affecting
-occupancy; that is, the number of concurrently active wavefronts in the CU. For
-instance, with 119 VGPRs used, only two wavefronts can be active in the CU at
-the same time. With the instruction latency of four cycles per SIMD instruction,
-the occupancy should be as high as possible such that the compute unit can
-improve execution efficiency by scheduling instructions from multiple
-wavefronts.
-
-:::{table} Peak-performance capabilities of MI100 for different data types.
-:name: mi100-perf
-| Computation and Data Type | FLOPS/CLOCK/CU | Peak TFLOPS |
-| :------------------------ | :------------: | ----------: |
-| Vector FP64               | 64             | 11.5        |
-| Matrix FP32               | 256            | 46.1        |
-| Vector FP32               | 128            | 23.1        |
-| Matrix FP16               | 1024           | 184.6       |
-| Matrix BF16               | 512            | 92.3        |
-
-:::
--- a/docs/conceptual/gpu-arch/mi250.md
+++ b/docs/conceptual/gpu-arch/mi250.md
@@ -1,134 +0,0 @@
---
-myst:
-  html_meta:
-    "description lang=en": "Learn about the AMD Instinct MI250 series architecture."
-    "keywords": "Instinct, MI250, microarchitecture, AMD, ROCm"
---
-
-# AMD Instinct™ MI250 microarchitecture
-
-The microarchitecture of the AMD Instinct MI250 accelerators is based on the
-AMD CDNA 2 architecture that targets compute applications such as HPC,
-artificial intelligence (AI), and machine learning (ML) and that run on
-everything from individual servers to the world’s largest exascale
-supercomputers. The overall system architecture is designed for extreme
-scalability and compute performance.
-
-The following image shows the components of a single Graphics Compute Die (GCD) of the CDNA 2 architecture. On the top and the bottom are AMD Infinity Fabric™
-interfaces and their physical links that are used to connect the GPU die to the
-other system-level components of the node (see also Section 2.2). Both
-interfaces can drive four AMD Infinity Fabric links. One of the AMD Infinity
-Fabric links of the controller at the bottom can be configured as a PCIe link.
-Each of the AMD Infinity Fabric links between GPUs can run at up to 25 GT/sec,
-which correlates to a peak transfer bandwidth of 50 GB/sec for a 16-wide link (
-two bytes per transaction). Section 2.2 has more details on the number of AMD
-Infinity Fabric links and the resulting transfer rates between the system-level
-components.
-
-To the left and the right are memory controllers that attach the High Bandwidth
-Memory (HBM) modules to the GCD. AMD Instinct MI250 GPUs use HBM2e, which offers
-a peak memory bandwidth of 1.6 TB/sec per GCD.
-
-The execution units of the GPU are depicted in the following image as Compute
-Units (CU). The MI250 GCD has 104 active CUs. Each compute unit is further
-subdivided into four SIMD units that process SIMD instructions of 16 data
-elements per instruction (for the FP64 data type). This enables the CU to
-process 64 work items (a so-called “wavefront”) at a peak clock frequency of 1.7
-GHz. Therefore, the theoretical maximum FP64 peak performance per GCD is 22.6
-TFLOPS for vector instructions. This equates to 45.3 TFLOPS for vector instructions for both GCDs together. The MI250 compute units also provide specialized
-execution units (also called matrix cores), which are geared toward executing
-matrix operations like matrix-matrix multiplications. For FP64, the peak
-performance of these units amounts to 90.5 TFLOPS.
-
-![Structure of a single GCD in the AMD Instinct MI250 accelerator.](../../data/conceptual/gpu-arch/image001.png "Structure of a single GCD in the AMD Instinct MI250 accelerator.")
-
-```{list-table} Peak-performance capabilities of the MI250 OAM for different data types.
-:header-rows: 1
-:name: mi250-perf-table
-
-*
-  - Computation and Data Type
-  - FLOPS/CLOCK/CU
-  - Peak TFLOPS
-*
-  - Matrix FP64
-  - 256
-  - 90.5
-*
-  - Vector FP64
-  - 128
-  - 45.3
-*
-  - Matrix FP32
-  - 256
-  - 90.5
-*
-  - Packed FP32
-  - 256
-  - 90.5
-*
-  - Vector FP32
-  - 128
-  - 45.3
-*
-  - Matrix FP16
-  - 1024
-  - 362.1
-*
-  - Matrix BF16
-  - 1024
-  - 362.1
-*
-  - Matrix INT8
-  - 1024
-  - 362.1
-```
-
-The above table summarizes the aggregated peak performance of the AMD
-Instinct MI250 OCP Open Accelerator Modules (OAM, OCP is short for Open Compute
-Platform) and its two GCDs for different data types and execution units. The
-middle column lists the peak performance (number of data elements processed in a
-single instruction) of a single compute unit if a SIMD (or matrix) instruction
-is being retired in each clock cycle. The third column lists the theoretical
-peak performance of the OAM module. The theoretical aggregated peak memory
-bandwidth of the GPU is 3.2 TB/sec (1.6 TB/sec per GCD).
-
-![Dual-GCD architecture of the AMD Instinct MI250 accelerators](../../data/conceptual/gpu-arch/image002.png "Dual-GCD architecture of the AMD Instinct MI250 accelerators")
-
-The following image shows the block diagram of an OAM package that consists
-of two GCDs, each of which constitutes one GPU device in the system. The two
-GCDs in the package are connected via four AMD Infinity Fabric links running at
-a theoretical peak rate of 25 GT/sec, giving 200 GB/sec peak transfer bandwidth
-between the two GCDs of an OAM, or a bidirectional peak transfer bandwidth of
-400 GB/sec for the same.
-
-## Node-level architecture
-
-The following image shows the node-level architecture of a system that is
-based on the AMD Instinct MI250 accelerator. The MI250 OAMs attach to the host
-system via PCIe Gen 4 x16 links (yellow lines). Each GCD maintains its own PCIe
-x16 link to the host part of the system. Depending on the server platform, the
-GCD can attach to the AMD EPYC processor directly or via an optional PCIe switch
-. Note that some platforms may offer an x8 interface to the GCDs, which reduces
-the available host-to-GPU bandwidth.
-
-![Block diagram of AMD Instinct MI250 Accelerators with 3rd Generation AMD EPYC processor](../../data/conceptual/gpu-arch/image003.png "Block diagram of AMD Instinct MI250 Accelerators with 3rd Generation AMD EPYC processor")
-
-The preceding image shows the node-level architecture of a system with AMD
-EPYC processors in a dual-socket configuration and four AMD Instinct MI250
-accelerators. The MI250 OAMs attach to the host processors system via PCIe Gen 4
-x16 links (yellow lines). Depending on the system design, a PCIe switch may
-exist to make more PCIe lanes available for additional components like network
-interfaces and/or storage devices. Each GCD maintains its own PCIe x16 link to
-the host part of the system or to the PCIe switch. Please note, some platforms
-may offer an x8 interface to the GCDs, which will reduce the available
-host-to-GPU bandwidth.
-
-Between the OAMs and their respective GCDs, a peer-to-peer (P2P) network allows
-for direct data exchange between the GPU dies via AMD Infinity Fabric links (
-black, green, and red lines). Each of these 16-wide links connects to one of the
-two GPU dies in the MI250 OAM and operates at 25 GT/sec, which corresponds to a
-theoretical peak transfer rate of 50 GB/sec per link (or 100 GB/sec
-bidirectional peak transfer bandwidth). The GCD pairs 2 and 6 as well as GCDs 0
-and 4 connect via two XGMI links, which is indicated by the thicker red line in
-the preceding image.
--- a/docs/conceptual/gpu-arch/mi300-mi200-performance-counters.rst
+++ b/docs/conceptual/gpu-arch/mi300-mi200-performance-counters.rst
@@ -1,757 +0,0 @@
-.. meta::
-  :description: MI300 and MI200 series performance counters and metrics
-  :keywords: MI300, MI200, performance counters, command processor counters
-
-***************************************************************************************************
-MI300 and MI200 series performance counters and metrics
-***************************************************************************************************
-
-This document lists and describes the hardware performance counters and derived metrics available
-for the AMD Instinct™ MI300 and MI200 GPU. You can also access this information using the
-:doc:`ROCProfiler tool <rocprofiler:rocprofv1>`.
-
-MI300 and MI200 series performance counters
-===============================================================
-
-Series performance counters include the following categories:
-
-* :ref:`command-processor-counters`
-* :ref:`graphics-register-bus-manager-counters`
-* :ref:`spi-counters`
-* :ref:`compute-unit-counters`
-* :ref:`l1i-and-sl1d-cache-counters`
-* :ref:`vector-l1-cache-subsystem-counters`
-* :ref:`l2-cache-access-counters`
-
-The following sections provide additional details for each category.
-
-.. note::
-
-  Preliminary validation of all MI300 and MI200 series performance counters is in progress. Those with
-  an asterisk (*) require further evaluation.
-
-.. _command-processor-counters:
-
-Command processor counters
---------------------------------------------------------------------------------------------------------------
-
-Command processor counters are further classified into command processor-fetcher and command
-processor-compute.
-
-Command processor-fetcher counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``CPF_CMP_UTCL1_STALL_ON_TRANSLATION``", "Cycles", "Number of cycles one of the compute unified translation caches (L1) is stalled waiting on translation"
-  "``CPF_CPF_STAT_BUSY``", "Cycles", "Number of cycles command processor-fetcher is busy"
-  "``CPF_CPF_STAT_IDLE``", "Cycles", "Number of cycles command processor-fetcher is idle"
-  "``CPF_CPF_STAT_STALL``", "Cycles", "Number of cycles command processor-fetcher is stalled"
-  "``CPF_CPF_TCIU_BUSY``", "Cycles", "Number of cycles command processor-fetcher texture cache interface unit interface is busy"
-  "``CPF_CPF_TCIU_IDLE``", "Cycles", "Number of cycles command processor-fetcher texture cache interface unit interface is idle"
-  "``CPF_CPF_TCIU_STALL``", "Cycles", "Number of cycles command processor-fetcher texture cache interface unit interface is stalled waiting on free tags"
-
-The texture cache interface unit is the interface between the command processor and the memory
-system.
-
-Command processor-compute counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``CPC_ME1_BUSY_FOR_PACKET_DECODE``", "Cycles", "Number of cycles command processor-compute micro engine is busy decoding packets"
-  "``CPC_UTCL1_STALL_ON_TRANSLATION``", "Cycles", "Number of cycles one of the unified translation caches (L1) is stalled waiting on translation"
-  "``CPC_CPC_STAT_BUSY``", "Cycles", "Number of cycles command processor-compute is busy"
-  "``CPC_CPC_STAT_IDLE``", "Cycles", "Number of cycles command processor-compute is idle"
-  "``CPC_CPC_STAT_STALL``", "Cycles", "Number of cycles command processor-compute is stalled"
-  "``CPC_CPC_TCIU_BUSY``", "Cycles", "Number of cycles command processor-compute texture cache interface unit interface is busy"
-  "``CPC_CPC_TCIU_IDLE``", "Cycles", "Number of cycles command processor-compute texture cache interface unit interface is idle"
-  "``CPC_CPC_UTCL2IU_BUSY``", "Cycles", "Number of cycles command processor-compute unified translation cache (L2) interface is busy"
-  "``CPC_CPC_UTCL2IU_IDLE``", "Cycles", "Number of cycles command processor-compute unified translation cache (L2) interface is idle"
-  "``CPC_CPC_UTCL2IU_STALL``", "Cycles", "Number of cycles command processor-compute unified translation cache (L2) interface is stalled"
-  "``CPC_ME1_DC0_SPI_BUSY``", "Cycles", "Number of cycles command processor-compute micro engine processor is busy"
-
-The micro engine runs packet-processing firmware on the command processor-compute counter.
-
-.. _graphics-register-bus-manager-counters:
-
-Graphics register bus manager counters
---------------------------------------------------------------------------------------------------------------
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``GRBM_COUNT``", "Cycles","Number of free-running GPU cycles"
-  "``GRBM_GUI_ACTIVE``", "Cycles", "Number of GPU active cycles"
-  "``GRBM_CP_BUSY``", "Cycles", "Number of cycles any of the command processor blocks are busy"
-  "``GRBM_SPI_BUSY``", "Cycles", "Number of cycles any of the shader processor input is busy in the shader engines"
-  "``GRBM_TA_BUSY``", "Cycles", "Number of cycles any of the texture addressing unit is busy in the shader engines"
-  "``GRBM_TC_BUSY``", "Cycles", "Number of cycles any of the texture cache blocks are busy"
-  "``GRBM_CPC_BUSY``", "Cycles", "Number of cycles the command processor-compute is busy"
-  "``GRBM_CPF_BUSY``", "Cycles", "Number of cycles the command processor-fetcher is busy"
-  "``GRBM_UTCL2_BUSY``", "Cycles", "Number of cycles the unified translation cache (Level 2 [L2]) block is busy"
-  "``GRBM_EA_BUSY``", "Cycles", "Number of cycles the efficiency arbiter block is busy"
-
-Texture cache blocks include:
-
-* Texture cache arbiter
-* Texture cache per pipe, also known as vector Level 1 (L1) cache
-* Texture cache per channel, also known as known as L2 cache
-* Texture cache interface
-
-.. _spi-counters:
-
-Shader processor input counters
---------------------------------------------------------------------------------------------------------------
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SPI_CSN_BUSY``", "Cycles", "Number of cycles with outstanding waves"
-  "``SPI_CSN_WINDOW_VALID``", "Cycles", "Number of cycles enabled by ``perfcounter_start`` event"
-  "``SPI_CSN_NUM_THREADGROUPS``", "Workgroups", "Number of dispatched workgroups"
-  "``SPI_CSN_WAVE``", "Wavefronts", "Number of dispatched wavefronts"
-  "``SPI_RA_REQ_NO_ALLOC``", "Cycles", "Number of arbiter cycles with requests but no allocation"
-  "``SPI_RA_REQ_NO_ALLOC_CSN``", "Cycles", "Number of arbiter cycles with compute shader (n\ :sup:`th` pipe) requests but no compute shader (n\ :sup:`th` pipe) allocation"
-  "``SPI_RA_RES_STALL_CSN``", "Cycles", "Number of arbiter stall cycles due to shortage of compute shader (n\ :sup:`th` pipe) pipeline slots"
-  "``SPI_RA_TMP_STALL_CSN``", "Cycles", "Number of stall cycles due to shortage of temp space"
-  "``SPI_RA_WAVE_SIMD_FULL_CSN``", "SIMD-cycles", "Accumulated number of single instruction, multiple data (SIMD) per cycle affected by shortage of wave slots for compute shader (n\ :sup:`th` pipe) wave dispatch"
-  "``SPI_RA_VGPR_SIMD_FULL_CSN``", "SIMD-cycles", "Accumulated number of SIMDs per cycle affected by shortage of vector general-purpose register (VGPR) slots for compute shader (n\ :sup:`th` pipe) wave dispatch"
-  "``SPI_RA_SGPR_SIMD_FULL_CSN``", "SIMD-cycles", "Accumulated number of SIMDs per cycle affected by shortage of scalar general-purpose register (SGPR) slots for compute shader (n\ :sup:`th` pipe) wave dispatch"
-  "``SPI_RA_LDS_CU_FULL_CSN``", "CU", "Number of compute units affected by shortage of local data share (LDS) space for compute shader (n\ :sup:`th` pipe) wave dispatch"
-  "``SPI_RA_BAR_CU_FULL_CSN``", "CU", "Number of compute units with compute shader (n\ :sup:`th` pipe) waves waiting at a BARRIER"
-  "``SPI_RA_BULKY_CU_FULL_CSN``", "CU", "Number of compute units with compute shader (n\ :sup:`th` pipe) waves waiting for BULKY resource"
-  "``SPI_RA_TGLIM_CU_FULL_CSN``", "Cycles", "Number of compute shader (n\ :sup:`th` pipe) wave stall cycles due to restriction of ``tg_limit`` for thread group size"
-  "``SPI_RA_WVLIM_STALL_CSN``", "Cycles", "Number of cycles compute shader (n\ :sup:`th` pipe) is stalled due to ``WAVE_LIMIT``"
-  "``SPI_VWC_CSC_WR``", "Qcycles", "Number of quad-cycles taken to initialize VGPRs when launching waves"
-  "``SPI_SWC_CSC_WR``", "Qcycles", "Number of quad-cycles taken to initialize SGPRs when launching waves"
-
-.. _compute-unit-counters:
-
-Compute unit counters
---------------------------------------------------------------------------------------------------------------
-
-The compute unit counters are further classified into instruction mix, matrix fused multiply-add (FMA)
-operation counters, level counters, wavefront counters, wavefront cycle counters, and LDS counters.
-
-Instruction mix
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_INSTS``", "Instr", "Number of instructions issued"
-  "``SQ_INSTS_VALU``", "Instr", "Number of vector arithmetic logic unit (VALU) instructions including matrix FMA issued"
-  "``SQ_INSTS_VALU_ADD_F16``", "Instr", "Number of VALU half-precision floating-point (F16) ``ADD`` or ``SUB`` instructions issued"
-  "``SQ_INSTS_VALU_MUL_F16``", "Instr", "Number of VALU F16 Multiply instructions issued"
-  "``SQ_INSTS_VALU_FMA_F16``", "Instr", "Number of VALU F16 FMA or multiply-add instructions issued"
-  "``SQ_INSTS_VALU_TRANS_F16``", "Instr", "Number of VALU F16 Transcendental instructions issued"
-  "``SQ_INSTS_VALU_ADD_F32``", "Instr", "Number of VALU full-precision floating-point (F32) ``ADD`` or ``SUB`` instructions issued"
-  "``SQ_INSTS_VALU_MUL_F32``", "Instr", "Number of VALU F32 Multiply instructions issued"
-  "``SQ_INSTS_VALU_FMA_F32``", "Instr", "Number of VALU F32 FMAor multiply-add instructions issued"
-  "``SQ_INSTS_VALU_TRANS_F32``", "Instr", "Number of VALU F32 Transcendental instructions issued"
-  "``SQ_INSTS_VALU_ADD_F64``", "Instr", "Number of VALU F64 ``ADD`` or ``SUB`` instructions issued"
-  "``SQ_INSTS_VALU_MUL_F64``", "Instr", "Number of VALU F64 Multiply instructions issued"
-  "``SQ_INSTS_VALU_FMA_F64``", "Instr", "Number of VALU F64 FMA or multiply-add instructions issued"
-  "``SQ_INSTS_VALU_TRANS_F64``", "Instr", "Number of VALU F64 Transcendental instructions issued"
-  "``SQ_INSTS_VALU_INT32``", "Instr", "Number of VALU 32-bit integer instructions (signed or unsigned) issued"
-  "``SQ_INSTS_VALU_INT64``", "Instr", "Number of VALU 64-bit integer instructions (signed or unsigned) issued"
-  "``SQ_INSTS_VALU_CVT``", "Instr", "Number of VALU Conversion instructions issued"
-  "``SQ_INSTS_VALU_MFMA_I8``", "Instr", "Number of 8-bit Integer matrix FMA instructions issued"
-  "``SQ_INSTS_VALU_MFMA_F16``", "Instr", "Number of F16 matrix FMA instructions issued"
-  "``SQ_INSTS_VALU_MFMA_F32``", "Instr", "Number of F32 matrix FMA instructions issued"
-  "``SQ_INSTS_VALU_MFMA_F64``", "Instr", "Number of F64 matrix FMA instructions issued"
-  "``SQ_INSTS_MFMA``", "Instr", "Number of matrix FMA instructions issued"
-  "``SQ_INSTS_VMEM_WR``", "Instr", "Number of vector memory write instructions (including flat) issued"
-  "``SQ_INSTS_VMEM_RD``", "Instr", "Number of vector memory read instructions (including flat) issued"
-  "``SQ_INSTS_VMEM``", "Instr", "Number of vector memory instructions issued, including both flat and buffer instructions"
-  "``SQ_INSTS_SALU``", "Instr", "Number of scalar arithmetic logic unit (SALU) instructions issued"
-  "``SQ_INSTS_SMEM``", "Instr", "Number of scalar memory instructions issued"
-  "``SQ_INSTS_SMEM_NORM``", "Instr", "Number of scalar memory instructions normalized to match ``smem_level`` issued"
-  "``SQ_INSTS_FLAT``", "Instr", "Number of flat instructions issued"
-  "``SQ_INSTS_FLAT_LDS_ONLY``", "Instr", "**MI200 series only** Number of FLAT instructions that read/write only from/to LDS issued. Works only if ``EARLY_TA_DONE`` is enabled."
-  "``SQ_INSTS_LDS``", "Instr", "Number of LDS instructions issued **(MI200: includes flat; MI300: does not include flat)**"
-  "``SQ_INSTS_GDS``", "Instr", "Number of global data share instructions issued"
-  "``SQ_INSTS_EXP_GDS``", "Instr", "Number of EXP and global data share instructions excluding skipped export instructions issued"
-  "``SQ_INSTS_BRANCH``", "Instr", "Number of branch instructions issued"
-  "``SQ_INSTS_SENDMSG``", "Instr", "Number of ``SENDMSG`` instructions including ``s_endpgm`` issued"
-  "``SQ_INSTS_VSKIPPED``", "Instr", "Number of vector instructions skipped"
-
-Flat instructions allow read, write, and atomic access to a generic memory address pointer that can
-resolve to any of the following physical memories:
-
-* Global Memory
-* Scratch ("private")
-* LDS ("shared")
-* Invalid - ``MEM_VIOL`` TrapStatus
-
-Matrix fused multiply-add operation counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_INSTS_VALU_MFMA_MOPS_I8``", "IOP", "Number of 8-bit integer matrix FMA ops in the unit of 512"
-  "``SQ_INSTS_VALU_MFMA_MOPS_F16``", "FLOP", "Number of F16 floating matrix FMA ops in the unit of 512"
-  "``SQ_INSTS_VALU_MFMA_MOPS_BF16``", "FLOP", "Number of BF16 floating matrix FMA ops in the unit of 512"
-  "``SQ_INSTS_VALU_MFMA_MOPS_F32``", "FLOP", "Number of F32 floating matrix FMA ops in the unit of 512"
-  "``SQ_INSTS_VALU_MFMA_MOPS_F64``", "FLOP", "Number of F64 floating matrix FMA ops in the unit of 512"
-
-Level counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. note::
-
-  All level counters must be followed by ``SQ_ACCUM_PREV_HIRES`` counter to measure average latency.
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_ACCUM_PREV``", "Count", "Accumulated counter sample value where accumulation takes place once every four cycles"
-  "``SQ_ACCUM_PREV_HIRES``", "Count", "Accumulated counter sample value where accumulation takes place once every cycle"
-  "``SQ_LEVEL_WAVES``", "Waves", "Number of inflight waves"
-  "``SQ_INST_LEVEL_VMEM``", "Instr", "Number of inflight vector memory (including flat) instructions"
-  "``SQ_INST_LEVEL_SMEM``", "Instr", "Number of inflight scalar memory instructions"
-  "``SQ_INST_LEVEL_LDS``", "Instr", "Number of inflight LDS (including flat) instructions"
-  "``SQ_IFETCH_LEVEL``", "Instr", "Number of inflight instruction fetch requests from the cache"
-
-Use the following formulae to calculate latencies:
-
-* Vector memory latency = ``SQ_ACCUM_PREV_HIRES`` divided by ``SQ_INSTS_VMEM``
-* Wave latency = ``SQ_ACCUM_PREV_HIRES`` divided by ``SQ_WAVE``
-* LDS latency = ``SQ_ACCUM_PREV_HIRES`` divided by ``SQ_INSTS_LDS``
-* Scalar memory latency = ``SQ_ACCUM_PREV_HIRES`` divided by ``SQ_INSTS_SMEM_NORM``
-* Instruction fetch latency = ``SQ_ACCUM_PREV_HIRES`` divided by ``SQ_IFETCH``
-
-Wavefront counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_WAVES``", "Waves", "Number of wavefronts dispatched to sequencers, including both new and restored wavefronts"
-  "``SQ_WAVES_SAVED``", "Waves", "Number of context-saved waves"
-  "``SQ_WAVES_RESTORED``", "Waves", "Number of context-restored waves sent to sequencers"
-  "``SQ_WAVES_EQ_64``", "Waves", "Number of wavefronts with exactly 64 active threads sent to sequencers"
-  "``SQ_WAVES_LT_64``", "Waves", "Number of wavefronts with less than 64 active threads sent to sequencers"
-  "``SQ_WAVES_LT_48``", "Waves", "Number of wavefronts with less than 48 active threads sent to sequencers"
-  "``SQ_WAVES_LT_32``", "Waves", "Number of wavefronts with less than 32 active threads sent to sequencers"
-  "``SQ_WAVES_LT_16``", "Waves", "Number of wavefronts with less than 16 active threads sent to sequencers"
-
-Wavefront cycle counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_CYCLES``", "Cycles", "Clock cycles"
-  "``SQ_BUSY_CYCLES``", "Cycles", "Number of cycles while sequencers reports it to be busy"
-  "``SQ_BUSY_CU_CYCLES``", "Qcycles", "Number of quad-cycles each compute unit is busy"
-  "``SQ_VALU_MFMA_BUSY_CYCLES``", "Cycles", "Number of cycles the matrix FMA arithmetic logic unit (ALU) is busy"
-  "``SQ_WAVE_CYCLES``", "Qcycles", "Number of quad-cycles spent by waves in the compute units"
-  "``SQ_WAIT_ANY``", "Qcycles", "Number of quad-cycles spent waiting for anything"
-  "``SQ_WAIT_INST_ANY``", "Qcycles", "Number of quad-cycles spent waiting for any instruction to be issued"
-  "``SQ_ACTIVE_INST_ANY``", "Qcycles", "Number of quad-cycles spent by each wave to work on an instruction"
-  "``SQ_ACTIVE_INST_VMEM``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on a vector memory instruction"
-  "``SQ_ACTIVE_INST_LDS``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on an LDS instruction"
-  "``SQ_ACTIVE_INST_VALU``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on a VALU instruction"
-  "``SQ_ACTIVE_INST_SCA``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on a SALU or scalar memory instruction"
-  "``SQ_ACTIVE_INST_EXP_GDS``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on an ``EXPORT`` or ``GDS`` instruction"
-  "``SQ_ACTIVE_INST_MISC``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on a ``BRANCH`` or ``SENDMSG`` instruction"
-  "``SQ_ACTIVE_INST_FLAT``", "Qcycles", "Number of quad-cycles spent by the sequencer instruction arbiter to work on a flat instruction"
-  "``SQ_INST_CYCLES_VMEM_WR``", "Qcycles", "Number of quad-cycles spent to send addr and cmd data for vector memory write instructions"
-  "``SQ_INST_CYCLES_VMEM_RD``", "Qcycles", "Number of quad-cycles spent to send addr and cmd data for vector memory read instructions"
-  "``SQ_INST_CYCLES_SMEM``", "Qcycles", "Number of quad-cycles spent to execute scalar memory reads"
-  "``SQ_INST_CYCLES_SALU``", "Qcycles", "Number of quad-cycles spent to execute non-memory read scalar operations"
-  "``SQ_THREAD_CYCLES_VALU``", "Qcycles", "Number of quad-cycles spent to execute VALU operations on active threads"
-  "``SQ_WAIT_INST_LDS``", "Qcycles", "Number of quad-cycles spent waiting for LDS instruction to be issued"
-
-``SQ_THREAD_CYCLES_VALU`` is similar to ``INST_CYCLES_VALU``, but it's multiplied by the number of
-active threads.
-
-LDS counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_LDS_ATOMIC_RETURN``", "Cycles", "Number of atomic return cycles in LDS"
-  "``SQ_LDS_BANK_CONFLICT``", "Cycles", "Number of cycles LDS is stalled by bank conflicts"
-  "``SQ_LDS_ADDR_CONFLICT``", "Cycles", "Number of cycles LDS is stalled by address conflicts"
-  "``SQ_LDS_UNALIGNED_STALL``", "Cycles", "Number of cycles LDS is stalled processing flat unaligned load or store operations"
-  "``SQ_LDS_MEM_VIOLATIONS``", "Count", "Number of threads that have a memory violation in the LDS"
-  "``SQ_LDS_IDX_ACTIVE``", "Cycles", "Number of cycles LDS is used for indexed operations"
-
-Miscellaneous counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQ_IFETCH``", "Count", "Number of instruction fetch requests from L1i, in 32-byte width"
-  "``SQ_ITEMS``", "Threads", "Number of valid items per wave"
-
-.. _l1i-and-sl1d-cache-counters:
-
-L1 instruction cache (L1i) and scalar L1 data cache (L1d) counters
---------------------------------------------------------------------------------------------------------------
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition"
-
-  "``SQC_ICACHE_REQ``", "Req", "Number of L1 instruction (L1i) cache requests"
-  "``SQC_ICACHE_HITS``", "Count", "Number of L1i cache hits"
-  "``SQC_ICACHE_MISSES``", "Count", "Number of non-duplicate L1i cache misses including uncached requests"
-  "``SQC_ICACHE_MISSES_DUPLICATE``", "Count", "Number of duplicate L1i cache misses whose previous lookup miss on the same cache line is not fulfilled yet"
-  "``SQC_DCACHE_REQ``", "Req", "Number of scalar L1d requests"
-  "``SQC_DCACHE_INPUT_VALID_READYB``", "Cycles", "Number of cycles while sequencer input is valid but scalar L1d is not ready"
-  "``SQC_DCACHE_HITS``", "Count", "Number of scalar L1d hits"
-  "``SQC_DCACHE_MISSES``", "Count", "Number of non-duplicate scalar L1d misses including uncached requests"
-  "``SQC_DCACHE_MISSES_DUPLICATE``", "Count", "Number of duplicate scalar L1d misses"
-  "``SQC_DCACHE_REQ_READ_1``", "Req", "Number of constant cache read requests in a single 32-bit data word"
-  "``SQC_DCACHE_REQ_READ_2``", "Req", "Number of constant cache read requests in two 32-bit data words"
-  "``SQC_DCACHE_REQ_READ_4``", "Req", "Number of constant cache read requests in four 32-bit data words"
-  "``SQC_DCACHE_REQ_READ_8``", "Req", "Number of constant cache read requests in eight 32-bit data words"
-  "``SQC_DCACHE_REQ_READ_16``", "Req", "Number of constant cache read requests in 16 32-bit data words"
-  "``SQC_DCACHE_ATOMIC``", "Req", "Number of atomic requests"
-  "``SQC_TC_REQ``", "Req", "Number of texture cache requests that were issued by instruction and constant caches"
-  "``SQC_TC_INST_REQ``", "Req", "Number of instruction requests to the L2 cache"
-  "``SQC_TC_DATA_READ_REQ``", "Req", "Number of data Read requests to the L2 cache"
-  "``SQC_TC_DATA_WRITE_REQ``", "Req", "Number of data write requests to the L2 cache"
-  "``SQC_TC_DATA_ATOMIC_REQ``", "Req", "Number of data atomic requests to the L2 cache"
-  "``SQC_TC_STALL``", "Cycles", "Number of cycles while the valid requests to the L2 cache are stalled"
-
-.. _vector-l1-cache-subsystem-counters:
-
-Vector L1 cache subsystem counters
---------------------------------------------------------------------------------------------------------------
-
-The vector L1 cache subsystem counters are further classified into texture addressing unit, texture data
-unit, vector L1d or texture cache per pipe, and texture cache arbiter counters.
-
-Texture addressing unit counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-  "``TA_TA_BUSY[n]``", "Cycles", "Texture addressing unit busy cycles", "0-15"
-  "``TA_TOTAL_WAVEFRONTS[n]``", "Instr", "Number of wavefronts processed by texture addressing unit", "0-15"
-  "``TA_BUFFER_WAVEFRONTS[n]``", "Instr", "Number of buffer wavefronts processed by texture addressing unit", "0-15"
-  "``TA_BUFFER_READ_WAVEFRONTS[n]``", "Instr", "Number of buffer read wavefronts processed by texture addressing unit", "0-15"
-  "``TA_BUFFER_WRITE_WAVEFRONTS[n]``", "Instr", "Number of buffer write wavefronts processed by texture addressing unit", "0-15"
-  "``TA_BUFFER_ATOMIC_WAVEFRONTS[n]``", "Instr", "Number of buffer atomic wavefronts processed by texture addressing unit", "0-15"
-  "``TA_BUFFER_TOTAL_CYCLES[n]``", "Cycles", "Number of buffer cycles (including read and write) issued to texture cache", "0-15"
-  "``TA_BUFFER_COALESCED_READ_CYCLES[n]``", "Cycles", "Number of coalesced buffer read cycles issued to texture cache", "0-15"
-  "``TA_BUFFER_COALESCED_WRITE_CYCLES[n]``", "Cycles", "Number of coalesced buffer write cycles issued to texture cache", "0-15"
-  "``TA_ADDR_STALLED_BY_TC_CYCLES[n]``", "Cycles", "Number of cycles texture addressing unit address path is stalled by texture cache", "0-15"
-  "``TA_DATA_STALLED_BY_TC_CYCLES[n]``", "Cycles", "Number of cycles texture addressing unit data path is stalled by texture cache", "0-15"
-  "``TA_ADDR_STALLED_BY_TD_CYCLES[n]``", "Cycles", "Number of cycles texture addressing unit address path is stalled by texture data unit", "0-15"
-  "``TA_FLAT_WAVEFRONTS[n]``", "Instr", "Number of flat opcode wavefronts processed by texture addressing unit", "0-15"
-  "``TA_FLAT_READ_WAVEFRONTS[n]``", "Instr", "Number of flat opcode read wavefronts processed by texture addressing unit", "0-15"
-  "``TA_FLAT_WRITE_WAVEFRONTS[n]``", "Instr", "Number of flat opcode write wavefronts processed by texture addressing unit", "0-15"
-  "``TA_FLAT_ATOMIC_WAVEFRONTS[n]``", "Instr", "Number of flat opcode atomic wavefronts processed by texture addressing unit", "0-15"
-
-Texture data unit counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-  "``TD_TD_BUSY[n]``", "Cycle", "Texture data unit busy cycles while it is processing or waiting for data", "0-15"
-  "``TD_TC_STALL[n]``", "Cycle", "Number of cycles texture data unit is stalled waiting for texture cache data", "0-15"
-  "``TD_SPI_STALL[n]``", "Cycle", "Number of cycles texture data unit is stalled by shader processor input", "0-15"
-  "``TD_LOAD_WAVEFRONT[n]``", "Instr", "Number of wavefront instructions (read, write, atomic)", "0-15"
-  "``TD_STORE_WAVEFRONT[n]``", "Instr", "Number of write wavefront instructions", "0-15"
-  "``TD_ATOMIC_WAVEFRONT[n]``", "Instr", "Number of atomic wavefront instructions", "0-15"
-  "``TD_COALESCABLE_WAVEFRONT[n]``", "Instr", "Number of coalescable wavefronts according to texture addressing unit", "0-15"
-
-Texture cache per pipe counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-  "``TCP_GATE_EN1[n]``", "Cycles", "Number of cycles vector L1d interface clocks are turned on", "0-15"
-  "``TCP_GATE_EN2[n]``", "Cycles", "Number of cycles vector L1d core clocks are turned on", "0-15"
-  "``TCP_TD_TCP_STALL_CYCLES[n]``", "Cycles", "Number of cycles texture data unit stalls vector L1d", "0-15"
-  "``TCP_TCR_TCP_STALL_CYCLES[n]``", "Cycles", "Number of cycles texture cache router stalls vector L1d", "0-15"
-  "``TCP_READ_TAGCONFLICT_STALL_CYCLES[n]``", "Cycles", "Number of cycles tag RAM conflict stalls on a read", "0-15"
-  "``TCP_WRITE_TAGCONFLICT_STALL_CYCLES[n]``", "Cycles", "Number of cycles tag RAM conflict stalls on a write", "0-15"
-  "``TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES[n]``", "Cycles", "Number of cycles tag RAM conflict stalls on an atomic", "0-15"
-  "``TCP_PENDING_STALL_CYCLES[n]``", "Cycles", "Number of cycles vector L1d is stalled due to data pending from L2 Cache", "0-15"
-  "``TCP_TCP_TA_DATA_STALL_CYCLES``", "Cycles", "Number of cycles texture cache per pipe stalls texture addressing unit data interface", "NA"
-  "``TCP_TA_TCP_STATE_READ[n]``", "Req", "Number of state reads", "0-15"
-  "``TCP_VOLATILE[n]``", "Req", "Number of L1 volatile pixels or buffers from texture addressing unit", "0-15"
-  "``TCP_TOTAL_ACCESSES[n]``", "Req", "Number of vector L1d accesses. Equals ``TCP_PERF_SEL_TOTAL_READ`+`TCP_PERF_SEL_TOTAL_NONREAD``", "0-15"
-  "``TCP_TOTAL_READ[n]``", "Req", "Number of vector L1d read accesses", "0-15"
-  "``TCP_TOTAL_WRITE[n]``", "Req", "Number of vector L1d write accesses", "0-15"
-  "``TCP_TOTAL_ATOMIC_WITH_RET[n]``", "Req", "Number of vector L1d atomic requests with return", "0-15"
-  "``TCP_TOTAL_ATOMIC_WITHOUT_RET[n]``", "Req", "Number of vector L1d atomic without return", "0-15"
-  "``TCP_TOTAL_WRITEBACK_INVALIDATES[n]``", "Count", "Total number of vector L1d writebacks and invalidates", "0-15"
-  "``TCP_UTCL1_REQUEST[n]``", "Req", "Number of address translation requests to unified translation cache (L1)", "0-15"
-  "``TCP_UTCL1_TRANSLATION_HIT[n]``", "Req", "Number of unified translation cache (L1) translation hits", "0-15"
-  "``TCP_UTCL1_TRANSLATION_MISS[n]``", "Req", "Number of unified translation cache (L1) translation misses", "0-15"
-  "``TCP_UTCL1_PERMISSION_MISS[n]``", "Req", "Number of unified translation cache (L1) permission misses", "0-15"
-  "``TCP_TOTAL_CACHE_ACCESSES[n]``", "Req", "Number of vector L1d cache accesses including hits and misses", "0-15"
-  "``TCP_TCP_LATENCY[n]``", "Cycles", "**MI200 series only** Accumulated wave access latency to vL1D over all wavefronts", "0-15"
-  "``TCP_TCC_READ_REQ_LATENCY[n]``", "Cycles", "**MI200 series only** Total vL1D to L2 request latency over all wavefronts for reads and atomics with return", "0-15"
-  "``TCP_TCC_WRITE_REQ_LATENCY[n]``", "Cycles", "**MI200 series only** Total vL1D to L2 request latency over all wavefronts for writes and atomics without return", "0-15"
-  "``TCP_TCC_READ_REQ[n]``", "Req", "Number of read requests to L2 cache", "0-15"
-  "``TCP_TCC_WRITE_REQ[n]``", "Req", "Number of write requests to L2 cache", "0-15"
-  "``TCP_TCC_ATOMIC_WITH_RET_REQ[n]``", "Req", "Number of atomic requests to L2 cache with return", "0-15"
-  "``TCP_TCC_ATOMIC_WITHOUT_RET_REQ[n]``", "Req", "Number of atomic requests to L2 cache without return", "0-15"
-  "``TCP_TCC_NC_READ_REQ[n]``", "Req", "Number of non-coherently cached read requests to L2 cache", "0-15"
-  "``TCP_TCC_UC_READ_REQ[n]``", "Req", "Number of uncached read requests to L2 cache", "0-15"
-  "``TCP_TCC_CC_READ_REQ[n]``", "Req", "Number of coherently cached read requests to L2 cache", "0-15"
-  "``TCP_TCC_RW_READ_REQ[n]``", "Req", "Number of coherently cached with write read requests to L2 cache", "0-15"
-  "``TCP_TCC_NC_WRITE_REQ[n]``", "Req", "Number of non-coherently cached write requests to L2 cache", "0-15"
-  "``TCP_TCC_UC_WRITE_REQ[n]``", "Req", "Number of uncached write requests to L2 cache", "0-15"
-  "``TCP_TCC_CC_WRITE_REQ[n]``", "Req", "Number of coherently cached write requests to L2 cache", "0-15"
-  "``TCP_TCC_RW_WRITE_REQ[n]``", "Req", "Number of coherently cached with write write requests to L2 cache", "0-15"
-  "``TCP_TCC_NC_ATOMIC_REQ[n]``", "Req", "Number of non-coherently cached atomic requests to L2 cache", "0-15"
-  "``TCP_TCC_UC_ATOMIC_REQ[n]``", "Req", "Number of uncached atomic requests to L2 cache", "0-15"
-  "``TCP_TCC_CC_ATOMIC_REQ[n]``", "Req", "Number of coherently cached atomic requests to L2 cache", "0-15"
-  "``TCP_TCC_RW_ATOMIC_REQ[n]``", "Req", "Number of coherently cached with write atomic requests to L2 cache", "0-15"
-
-Note that:
-
-* ``TCP_TOTAL_READ[n]`` = ``TCP_PERF_SEL_TOTAL_HIT_LRU_READ`` + ``TCP_PERF_SEL_TOTAL_MISS_LRU_READ`` + ``TCP_PERF_SEL_TOTAL_MISS_EVICT_READ``
-* ``TCP_TOTAL_WRITE[n]`` = ``TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE``+ ``TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE``
-* ``TCP_TOTAL_WRITEBACK_INVALIDATES[n]`` = ``TCP_PERF_SEL_TOTAL_WBINVL1``+ ``TCP_PERF_SEL_TOTAL_WBINVL1_VOL``+ ``TCP_PERF_SEL_CP_TCP_INVALIDATE``+ ``TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL``
-
-Texture cache arbiter counters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. csv-table::
-  :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-  "``TCA_CYCLE[n]``", "Cycles", "Number of texture cache arbiter cycles", "0-31"
-  "``TCA_BUSY[n]``", "Cycles", "Number of cycles texture cache arbiter has a pending request", "0-31"
-
-.. _l2-cache-access-counters:
-
-L2 cache access counters
---------------------------------------------------------------------------------------------------------------
-
-L2 cache is also known as texture cache per channel.
-
-.. tab-set::
-
-    .. tab-item:: MI300 hardware counter
-
-      .. csv-table::
-        :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-        "``TCC_CYCLE[n]``", "Cycles", "Number of L2 cache free-running clocks", "0-31"
-        "``TCC_BUSY[n]``", "Cycles", "Number of L2 cache busy cycles", "0-31"
-        "``TCC_REQ[n]``", "Req", "Number of L2 cache requests of all types (measured at the tag block)", "0-31"
-        "``TCC_STREAMING_REQ[n]``", "Req", "Number of L2 cache streaming requests (measured at the tag block)", "0-31"
-        "``TCC_NC_REQ[n]``", "Req", "Number of non-coherently cached requests (measured at the tag block)", "0-31"
-        "``TCC_UC_REQ[n]``", "Req", "Number of uncached requests. This is measured at the tag block", "0-31"
-        "``TCC_CC_REQ[n]``", "Req", "Number of coherently cached requests. This is measured at the tag block", "0-31"
-        "``TCC_RW_REQ[n]``", "Req", "Number of coherently cached with write requests. This is measured at the tag block", "0-31"
-        "``TCC_PROBE[n]``", "Req", "Number of probe requests", "0-31"
-        "``TCC_PROBE_ALL[n]``", "Req", "Number of external probe requests with ``EA_TCC_preq_all == 1``", "0-31"
-        "``TCC_READ[n]``", "Req", "Number of L2 cache read requests (includes compressed reads but not metadata reads)", "0-31"
-        "``TCC_WRITE[n]``", "Req", "Number of L2 cache write requests", "0-31"
-        "``TCC_ATOMIC[n]``", "Req", "Number of L2 cache atomic requests of all types", "0-31"
-        "``TCC_HIT[n]``", "Req", "Number of L2 cache hits", "0-31"
-        "``TCC_MISS[n]``", "Req", "Number of L2 cache misses", "0-31"
-        "``TCC_WRITEBACK[n]``", "Req", "Number of lines written back to the main memory, including writebacks of dirty lines and uncached write or atomic requests", "0-31"
-        "``TCC_EA0_WRREQ[n]``", "Req", "Number of 32-byte and 64-byte transactions going over the ``TC_EA_wrreq`` interface (doesn't include probe commands)", "0-31"
-        "``TCC_EA0_WRREQ_64B[n]``", "Req", "Total number of 64-byte transactions (write or ``CMPSWAP``) going over the ``TC_EA_wrreq`` interface", "0-31"
-        "``TCC_EA0_WR_UNCACHED_32B[n]``", "Req", "Number of 32 or 64-byte write or atomic going over the ``TC_EA_wrreq`` interface due to uncached traffic", "0-31"
-        "``TCC_EA0_WRREQ_STALL[n]``", "Cycles", "Number of cycles a write request is stalled", "0-31"
-        "``TCC_EA0_WRREQ_IO_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of input-output (IO) credits", "0-31"
-        "``TCC_EA0_WRREQ_GMI_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of GMI credits", "0-31"
-        "``TCC_EA0_WRREQ_DRAM_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of DRAM credits", "0-31"
-        "``TCC_TOO_MANY_EA_WRREQS_STALL[n]``", "Cycles", "Number of cycles the L2 cache is unable to send an efficiency arbiter write request due to it reaching its maximum capacity of pending efficiency arbiter write requests", "0-31"
-        "``TCC_EA0_WRREQ_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter write requests in flight", "0-31"
-        "``TCC_EA0_ATOMIC[n]``", "Req", "Number of 32-byte or 64-byte atomic requests going over the ``TC_EA_wrreq`` interface", "0-31"
-        "``TCC_EA0_ATOMIC_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter atomic requests in flight", "0-31"
-        "``TCC_EA0_RDREQ[n]``", "Req", "Number of 32-byte or 64-byte read requests to efficiency arbiter", "0-31"
-        "``TCC_EA0_RDREQ_32B[n]``", "Req", "Number of 32-byte read requests to efficiency arbiter", "0-31"
-        "``TCC_EA0_RD_UNCACHED_32B[n]``", "Req", "Number of 32-byte efficiency arbiter reads due to uncached traffic. A 64-byte request is counted as 2", "0-31"
-        "``TCC_EA0_RDREQ_IO_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of IO credits", "0-31"
-        "``TCC_EA0_RDREQ_GMI_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of GMI credits", "0-31"
-        "``TCC_EA0_RDREQ_DRAM_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of DRAM credits", "0-31"
-        "``TCC_EA0_RDREQ_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter read requests in flight", "0-31"
-        "``TCC_EA0_RDREQ_DRAM[n]``", "Req", "Number of 32-byte or 64-byte efficiency arbiter read requests to High Bandwidth Memory (HBM)", "0-31"
-        "``TCC_EA0_WRREQ_DRAM[n]``", "Req", "Number of 32-byte or 64-byte efficiency arbiter write requests to HBM", "0-31"
-        "``TCC_TAG_STALL[n]``", "Cycles", "Number of cycles the normal request pipeline in the tag is stalled for any reason", "0-31"
-        "``TCC_NORMAL_WRITEBACK[n]``", "Req", "Number of writebacks due to requests that are not writeback requests", "0-31"
-        "``TCC_ALL_TC_OP_WB_WRITEBACK[n]``", "Req", "Number of writebacks due to all ``TC_OP`` writeback requests", "0-31"
-        "``TCC_NORMAL_EVICT[n]``", "Req", "Number of evictions due to requests that are not invalidate or probe requests", "0-31"
-        "``TCC_ALL_TC_OP_INV_EVICT[n]``", "Req", "Number of evictions due to all ``TC_OP`` invalidate requests", "0-31"
-
-    .. tab-item:: MI200 hardware counter
-
-      .. csv-table::
-        :header: "Hardware counter", "Unit", "Definition", "Value range for ``n``"
-
-        "``TCC_CYCLE[n]``", "Cycles", "Number of L2 cache free-running clocks", "0-31"
-        "``TCC_BUSY[n]``", "Cycles", "Number of L2 cache busy cycles", "0-31"
-        "``TCC_REQ[n]``", "Req", "Number of L2 cache requests of all types (measured at the tag block)", "0-31"
-        "``TCC_STREAMING_REQ[n]``", "Req", "Number of L2 cache streaming requests (measured at the tag block)", "0-31"
-        "``TCC_NC_REQ[n]``", "Req", "Number of non-coherently cached requests (measured at the tag block)", "0-31"
-        "``TCC_UC_REQ[n]``", "Req", "Number of uncached requests. This is measured at the tag block", "0-31"
-        "``TCC_CC_REQ[n]``", "Req", "Number of coherently cached requests. This is measured at the tag block", "0-31"
-        "``TCC_RW_REQ[n]``", "Req", "Number of coherently cached with write requests. This is measured at the tag block", "0-31"
-        "``TCC_PROBE[n]``", "Req", "Number of probe requests", "0-31"
-        "``TCC_PROBE_ALL[n]``", "Req", "Number of external probe requests with ``EA_TCC_preq_all == 1``", "0-31"
-        "``TCC_READ[n]``", "Req", "Number of L2 cache read requests (includes compressed reads but not metadata reads)", "0-31"
-        "``TCC_WRITE[n]``", "Req", "Number of L2 cache write requests", "0-31"
-        "``TCC_ATOMIC[n]``", "Req", "Number of L2 cache atomic requests of all types", "0-31"
-        "``TCC_HIT[n]``", "Req", "Number of L2 cache hits", "0-31"
-        "``TCC_MISS[n]``", "Req", "Number of L2 cache misses", "0-31"
-        "``TCC_WRITEBACK[n]``", "Req", "Number of lines written back to the main memory, including writebacks of dirty lines and uncached write or atomic requests", "0-31"
-        "``TCC_EA_WRREQ[n]``", "Req", "Number of 32-byte and 64-byte transactions going over the ``TC_EA_wrreq`` interface (doesn't include probe commands)", "0-31"
-        "``TCC_EA_WRREQ_64B[n]``", "Req", "Total number of 64-byte transactions (write or ``CMPSWAP``) going over the ``TC_EA_wrreq`` interface", "0-31"
-        "``TCC_EA_WR_UNCACHED_32B[n]``", "Req", "Number of 32 write or atomic going over the ``TC_EA_wrreq`` interface due to uncached traffic. A 64-byte request will be counted as 2", "0-31"
-        "``TCC_EA_WRREQ_STALL[n]``", "Cycles", "Number of cycles a write request is stalled", "0-31"
-        "``TCC_EA_WRREQ_IO_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of input-output (IO) credits", "0-31"
-        "``TCC_EA_WRREQ_GMI_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of GMI credits", "0-31"
-        "``TCC_EA_WRREQ_DRAM_CREDIT_STALL[n]``", "Cycles", "Number of cycles an efficiency arbiter write request is stalled due to the interface running out of DRAM credits", "0-31"
-        "``TCC_TOO_MANY_EA_WRREQS_STALL[n]``", "Cycles", "Number of cycles the L2 cache is unable to send an efficiency arbiter write request due to it reaching its maximum capacity of pending efficiency arbiter write requests", "0-31"
-        "``TCC_EA_WRREQ_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter write requests in flight", "0-31"
-        "``TCC_EA_ATOMIC[n]``", "Req", "Number of 32-byte or 64-byte atomic requests going over the ``TC_EA_wrreq`` interface", "0-31"
-        "``TCC_EA_ATOMIC_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter atomic requests in flight", "0-31"
-        "``TCC_EA_RDREQ[n]``", "Req", "Number of 32-byte or 64-byte read requests to efficiency arbiter", "0-31"
-        "``TCC_EA_RDREQ_32B[n]``", "Req", "Number of 32-byte read requests to efficiency arbiter", "0-31"
-        "``TCC_EA_RD_UNCACHED_32B[n]``", "Req", "Number of 32-byte efficiency arbiter reads due to uncached traffic. A 64-byte request is counted as 2", "0-31"
-        "``TCC_EA_RDREQ_IO_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of IO credits", "0-31"
-        "``TCC_EA_RDREQ_GMI_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of GMI credits", "0-31"
-        "``TCC_EA_RDREQ_DRAM_CREDIT_STALL[n]``", "Cycles", "Number of cycles there is a stall due to the read request interface running out of DRAM credits", "0-31"
-        "``TCC_EA_RDREQ_LEVEL[n]``", "Req", "The accumulated number of efficiency arbiter read requests in flight", "0-31"
-        "``TCC_EA_RDREQ_DRAM[n]``", "Req", "Number of 32-byte or 64-byte efficiency arbiter read requests to High Bandwidth Memory (HBM)", "0-31"
-        "``TCC_EA_WRREQ_DRAM[n]``", "Req", "Number of 32-byte or 64-byte efficiency arbiter write requests to HBM", "0-31"
-        "``TCC_TAG_STALL[n]``", "Cycles", "Number of cycles the normal request pipeline in the tag is stalled for any reason", "0-31"
-        "``TCC_NORMAL_WRITEBACK[n]``", "Req", "Number of writebacks due to requests that are not writeback requests", "0-31"
-        "``TCC_ALL_TC_OP_WB_WRITEBACK[n]``", "Req", "Number of writebacks due to all ``TC_OP`` writeback requests", "0-31"
-        "``TCC_NORMAL_EVICT[n]``", "Req", "Number of evictions due to requests that are not invalidate or probe requests", "0-31"
-        "``TCC_ALL_TC_OP_INV_EVICT[n]``", "Req", "Number of evictions due to all ``TC_OP`` invalidate requests", "0-31"
-
-Note the following:
-
-* ``TCC_REQ[n]`` may be more than the number of requests arriving at the texture cache per channel,
-  but it's a good indication of the total amount of work that needs to be performed.
-* For ``TCC_EA0_WRREQ[n]``, atomics may travel over the same interface and are generally classified as
-  write requests.
-* CC mtypes can produce uncached requests, and those are included in
-  ``TCC_EA0_WR_UNCACHED_32B[n]``
-* ``TCC_EA0_WRREQ_LEVEL[n]`` is primarily intended to measure average efficiency arbiter write latency.
-
-  * Average write latency = ``TCC_PERF_SEL_EA0_WRREQ_LEVEL`` divided by ``TCC_PERF_SEL_EA0_WRREQ``
-
-* ``TCC_EA0_ATOMIC_LEVEL[n]`` is primarily intended to measure average efficiency arbiter atomic
-  latency
-
-  * Average atomic latency = ``TCC_PERF_SEL_EA0_WRREQ_ATOMIC_LEVEL`` divided by ``TCC_PERF_SEL_EA0_WRREQ_ATOMIC``
-
-* ``TCC_EA0_RDREQ_LEVEL[n]`` is primarily intended to measure average efficiency arbiter read latency.
-
-  * Average read latency = ``TCC_PERF_SEL_EA0_RDREQ_LEVEL`` divided by ``TCC_PERF_SEL_EA0_RDREQ``
-
-* Stalls can occur regardless of the need for a read to be performed
-* Normally, stalls are measured exactly at one point in the pipeline however in the case of
-  ``TCC_TAG_STALL[n]``, probes can stall the pipeline at a variety of places. There is no single point that
-  can accurately measure the total stalls
-
-MI300 and MI200 series derived metrics list
-==============================================================
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``ALUStalledByLDS``", "Percentage of GPU time ALU units are stalled due to the LDS input queue being full or the output queue not being ready (value range: 0% (optimal) to 100%)"
-  "``FetchSize``", "Total kilobytes fetched from the video memory; measured with all extra fetches and any cache or memory effects taken into account"
-  "``FlatLDSInsts``", "Average number of flat instructions that read from or write to LDS, run per work item (affected by flow control)"
-  "``FlatVMemInsts``", "Average number of flat instructions that read from or write to the video memory, run per work item (affected by flow control). Includes flat instructions that read from or write to scratch"
-  "``GDSInsts``", "Average number of global data share read or write instructions run per work item (affected by flow control)"
-  "``GPUBusy``", "Percentage of time GPU is busy"
-  "``L2CacheHit``", "Percentage of fetch, write, atomic, and other instructions that hit the data in L2 cache (value range: 0% (no hit) to 100% (optimal))"
-  "``LDSBankConflict``", "Percentage of GPU time LDS is stalled by bank conflicts (value range: 0% (optimal) to 100%)"
-  "``LDSInsts``", "Average number of LDS read or write instructions run per work item (affected by flow control). Excludes flat instructions that read from or write to LDS."
-  "``MemUnitBusy``", "Percentage of GPU time the memory unit is active, which is measured with all extra fetches and writes and any cache or memory effects taken into account (value range: 0% to 100% (fetch-bound))"
-  "``MemUnitStalled``", "Percentage of GPU time the memory unit is stalled (value range: 0% (optimal) to 100%)"
-  "``MemWrites32B``", "Total number of effective 32B write transactions to the memory"
-  "``TCA_BUSY_sum``", "Total number of cycles texture cache arbiter has a pending request, over all texture cache arbiter instances"
-  "``TCA_CYCLE_sum``", "Total number of cycles over all texture cache arbiter instances"
-  "``SALUBusy``", "Percentage of GPU time scalar ALU instructions are processed (value range: 0% to 100% (optimal))"
-  "``SALUInsts``", "Average number of scalar ALU instructions run per work item (affected by flow control)"
-  "``SFetchInsts``", "Average number of scalar fetch instructions from the video memory run per work item (affected by flow control)"
-  "``VALUBusy``", "Percentage of GPU time vector ALU instructions are processed (value range: 0% to 100% (optimal))"
-  "``VALUInsts``", "Average number of vector ALU instructions run per work item (affected by flow control)"
-  "``VALUUtilization``", "Percentage of active vector ALU threads in a wave, where a lower number can mean either more thread divergence in a wave or that the work-group size is not a multiple of 64 (value range: 0%, 100% (optimal - no thread divergence))"
-  "``VFetchInsts``", "Average number of vector fetch instructions from the video memory run per work-item (affected by flow control); excludes flat instructions that fetch from video memory"
-  "``VWriteInsts``", "Average number of vector write instructions to the video memory run per work-item (affected by flow control); excludes flat instructions that write to video memory"
-  "``Wavefronts``", "Total wavefronts"
-  "``WRITE_REQ_32B``", "Total number of 32-byte effective memory writes"
-  "``WriteSize``", "Total kilobytes written to the video memory; measured with all extra fetches and any cache or memory effects taken into account"
-  "``WriteUnitStalled``", "Percentage of GPU time the write unit is stalled (value range: 0% (optimal) to 100%)"
-
-You can lower ``ALUStalledByLDS`` by reducing LDS bank conflicts or number of LDS accesses.
-You can lower ``MemUnitStalled`` by reducing the number or size of fetches and writes.
-``MemUnitBusy`` includes the stall time (``MemUnitStalled``).
-
-Hardware counters by and over all texture addressing unit instances
---------------------------------------------------------------------------------------------------------------
-
-The following table shows the hardware counters *by* all texture addressing unit instances.
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TA_BUFFER_WAVEFRONTS_sum``", "Total number of buffer wavefronts processed"
-  "``TA_BUFFER_READ_WAVEFRONTS_sum``", "Total number of buffer read wavefronts processed"
-  "``TA_BUFFER_WRITE_WAVEFRONTS_sum``", "Total number of buffer write wavefronts processed"
-  "``TA_BUFFER_ATOMIC_WAVEFRONTS_sum``", "Total number of buffer atomic wavefronts processed"
-  "``TA_BUFFER_TOTAL_CYCLES_sum``", "Total number of buffer cycles (including read and write) issued to texture cache"
-  "``TA_BUFFER_COALESCED_READ_CYCLES_sum``", "Total number of coalesced buffer read cycles issued to texture cache"
-  "``TA_BUFFER_COALESCED_WRITE_CYCLES_sum``", "Total number of coalesced buffer write cycles issued to texture cache"
-  "``TA_FLAT_READ_WAVEFRONTS_sum``", "Sum of flat opcode reads processed"
-  "``TA_FLAT_WRITE_WAVEFRONTS_sum``", "Sum of flat opcode writes processed"
-  "``TA_FLAT_WAVEFRONTS_sum``", "Total number of flat opcode wavefronts processed"
-  "``TA_FLAT_ATOMIC_WAVEFRONTS_sum``", "Total number of flat opcode atomic wavefronts processed"
-  "``TA_TOTAL_WAVEFRONTS_sum``", "Total number of wavefronts processed"
-
-The following table shows the hardware counters *over* all texture addressing unit instances.
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TA_ADDR_STALLED_BY_TC_CYCLES_sum``", "Total number of cycles texture addressing unit address path is stalled by texture cache"
-  "``TA_ADDR_STALLED_BY_TD_CYCLES_sum``", "Total number of cycles texture addressing unit address path is stalled by texture data unit"
-  "``TA_BUSY_avr``", "Average number of busy cycles"
-  "``TA_BUSY_max``", "Maximum number of texture addressing unit busy cycles"
-  "``TA_BUSY_min``", "Minimum number of texture addressing unit busy cycles"
-  "``TA_DATA_STALLED_BY_TC_CYCLES_sum``", "Total number of cycles texture addressing unit data path is stalled by texture cache"
-  "``TA_TA_BUSY_sum``", "Total number of texture addressing unit busy cycles"
-
-Hardware counters over all texture cache per channel instances
---------------------------------------------------------------------------------------------------------------
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TCC_ALL_TC_OP_WB_WRITEBACK_sum``", "Total number of writebacks due to all ``TC_OP`` writeback requests."
-  "``TCC_ALL_TC_OP_INV_EVICT_sum``", "Total number of evictions due to all ``TC_OP`` invalidate requests."
-  "``TCC_ATOMIC_sum``", "Total number of L2 cache atomic requests of all types."
-  "``TCC_BUSY_avr``", "Average number of L2 cache busy cycles."
-  "``TCC_BUSY_sum``", "Total number of L2 cache busy cycles."
-  "``TCC_CC_REQ_sum``", "Total number of coherently cached requests."
-  "``TCC_CYCLE_sum``", "Total number of L2 cache free running clocks."
-  "``TCC_EA0_WRREQ_sum``", "Total number of 32-byte and 64-byte transactions going over the ``TC_EA0_wrreq`` interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."
-  "``TCC_EA0_WRREQ_64B_sum``", "Total number of 64-byte transactions (write or `CMPSWAP`) going over the ``TC_EA0_wrreq`` interface."
-  "``TCC_EA0_WR_UNCACHED_32B_sum``", "Total Number of 32-byte write or atomic going over the ``TC_EA0_wrreq`` interface due to uncached traffic. Note that coherently cached mtypes can produce uncached requests, and those are included in this. A 64-byte request is counted as 2."
-  "``TCC_EA0_WRREQ_STALL_sum``", "Total Number of cycles a write request is stalled, over all instances."
-  "``TCC_EA0_WRREQ_IO_CREDIT_STALL_sum``", "Total number of cycles an efficiency arbiter write request is stalled due to the interface running out of IO credits, over all instances."
-  "``TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum``", "Total number of cycles an efficiency arbiter write request is stalled due to the interface running out of GMI credits, over all instances."
-  "``TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum``", "Total number of cycles an efficiency arbiter write request is stalled due to the interface running out of DRAM credits, over all instances."
-  "``TCC_EA0_WRREQ_LEVEL_sum``", "Total number of efficiency arbiter write requests in flight."
-  "``TCC_EA0_RDREQ_LEVEL_sum``", "Total number of efficiency arbiter read requests in flight."
-  "``TCC_EA0_ATOMIC_sum``", "Total Number of 32-byte or 64-byte atomic requests going over the ``TC_EA0_wrreq`` interface."
-  "``TCC_EA0_ATOMIC_LEVEL_sum``", "Total number of efficiency arbiter atomic requests in flight."
-  "``TCC_EA0_RDREQ_sum``", "Total number of 32-byte or 64-byte read requests to efficiency arbiter."
-  "``TCC_EA0_RDREQ_32B_sum``", "Total number of 32-byte read requests to efficiency arbiter."
-  "``TCC_EA0_RD_UNCACHED_32B_sum``", "Total number of 32-byte efficiency arbiter reads due to uncached traffic."
-  "``TCC_EA0_RDREQ_IO_CREDIT_STALL_sum``", "Total number of cycles there is a stall due to the read request interface running out of IO credits."
-  "``TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum``", "Total number of cycles there is a stall due to the read request interface running out of GMI credits."
-  "``TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum``", "Total number of cycles there is a stall due to the read request interface running out of DRAM credits."
-  "``TCC_EA0_RDREQ_DRAM_sum``", "Total number of 32-byte or 64-byte efficiency arbiter read requests to HBM."
-  "``TCC_EA0_WRREQ_DRAM_sum``", "Total number of 32-byte or 64-byte efficiency arbiter write requests to HBM."
-  "``TCC_HIT_sum``", "Total number of L2 cache hits."
-  "``TCC_MISS_sum``", "Total number of L2 cache misses."
-  "``TCC_NC_REQ_sum``", "Total number of non-coherently cached requests."
-  "``TCC_NORMAL_WRITEBACK_sum``", "Total number of writebacks due to requests that are not writeback requests."
-  "``TCC_NORMAL_EVICT_sum``", "Total number of evictions due to requests that are not invalidate or probe requests."
-  "``TCC_PROBE_sum``", "Total number of probe requests."
-  "``TCC_PROBE_ALL_sum``", "Total number of external probe requests with ``EA0_TCC_preq_all == 1``."
-  "``TCC_READ_sum``", "Total number of L2 cache read requests (including compressed reads but not metadata reads)."
-  "``TCC_REQ_sum``", "Total number of all types of L2 cache requests."
-  "``TCC_RW_REQ_sum``", "Total number of coherently cached with write requests."
-  "``TCC_STREAMING_REQ_sum``", "Total number of L2 cache streaming requests."
-  "``TCC_TAG_STALL_sum``", "Total number of cycles the normal request pipeline in the tag is stalled for any reason."
-  "``TCC_TOO_MANY_EA0_WRREQS_STALL_sum``", "Total number of cycles L2 cache is unable to send an efficiency arbiter write request due to it reaching its maximum capacity of pending efficiency arbiter write requests."
-  "``TCC_UC_REQ_sum``", "Total number of uncached requests."
-  "``TCC_WRITE_sum``", "Total number of L2 cache write requests."
-  "``TCC_WRITEBACK_sum``", "Total number of lines written back to the main memory including writebacks of dirty lines and uncached write or atomic requests."
-  "``TCC_WRREQ_STALL_max``", "Maximum number of cycles a write request is stalled."
-
-Hardware counters by, for, or over all texture cache per pipe instances
----------------------------------------------------------------------------------------------------------------
-
-The following table shows the hardware counters *by* all texture cache per pipe instances.
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TCP_TA_TCP_STATE_READ_sum``", "Total number of state reads by ATCPPI"
-  "``TCP_TOTAL_CACHE_ACCESSES_sum``", "Total number of vector L1d accesses (including hits and misses)"
-  "``TCP_UTCL1_PERMISSION_MISS_sum``", "Total number of unified translation cache (L1) permission misses"
-  "``TCP_UTCL1_REQUEST_sum``", "Total number of address translation requests to unified translation cache (L1)"
-  "``TCP_UTCL1_TRANSLATION_MISS_sum``", "Total number of unified translation cache (L1) translation misses"
-  "``TCP_UTCL1_TRANSLATION_HIT_sum``", "Total number of unified translation cache (L1) translation hits"
-
-The following table shows the hardware counters *for* all texture cache per pipe instances.
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TCP_TCC_READ_REQ_LATENCY_sum``", "Total vector L1d to L2 request latency over all wavefronts for reads and atomics with return"
-  "``TCP_TCC_WRITE_REQ_LATENCY_sum``", "Total vector L1d to L2 request latency over all wavefronts for writes and atomics without return"
-  "``TCP_TCP_LATENCY_sum``", "Total wave access latency to vector L1d over all wavefronts"
-
-The following table shows the hardware counters *over* all texture cache per pipe instances.
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum``", "Total number of cycles tag RAM conflict stalls on an atomic"
-  "``TCP_GATE_EN1_sum``", "Total number of cycles vector L1d interface clocks are turned on"
-  "``TCP_GATE_EN2_sum``", "Total number of cycles vector L1d core clocks are turned on"
-  "``TCP_PENDING_STALL_CYCLES_sum``", "Total number of cycles vector L1d cache is stalled due to data pending from L2 Cache"
-  "``TCP_READ_TAGCONFLICT_STALL_CYCLES_sum``", "Total number of cycles tag RAM conflict stalls on a read"
-  "``TCP_TCC_ATOMIC_WITH_RET_REQ_sum``", "Total number of atomic requests to L2 cache with return"
-  "``TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum``", "Total number of atomic requests to L2 cache without return"
-  "``TCP_TCC_CC_READ_REQ_sum``", "Total number of coherently cached read requests to L2 cache"
-  "``TCP_TCC_CC_WRITE_REQ_sum``", "Total number of coherently cached write requests to L2 cache"
-  "``TCP_TCC_CC_ATOMIC_REQ_sum``", "Total number of coherently cached atomic requests to L2 cache"
-  "``TCP_TCC_NC_READ_REQ_sum``", "Total number of non-coherently cached read requests to L2 cache"
-  "``TCP_TCC_NC_WRITE_REQ_sum``", "Total number of non-coherently cached write requests to L2 cache"
-  "``TCP_TCC_NC_ATOMIC_REQ_sum``", "Total number of non-coherently cached atomic requests to L2 cache"
-  "``TCP_TCC_READ_REQ_sum``", "Total number of read requests to L2 cache"
-  "``TCP_TCC_RW_READ_REQ_sum``", "Total number of coherently cached with write read requests to L2 cache"
-  "``TCP_TCC_RW_WRITE_REQ_sum``", "Total number of coherently cached with write write requests to L2 cache"
-  "``TCP_TCC_RW_ATOMIC_REQ_sum``", "Total number of coherently cached with write atomic requests to L2 cache"
-  "``TCP_TCC_UC_READ_REQ_sum``", "Total number of uncached read requests to L2 cache"
-  "``TCP_TCC_UC_WRITE_REQ_sum``", "Total number of uncached write requests to L2 cache"
-  "``TCP_TCC_UC_ATOMIC_REQ_sum``", "Total number of uncached atomic requests to L2 cache"
-  "``TCP_TCC_WRITE_REQ_sum``", "Total number of write requests to L2 cache"
-  "``TCP_TCR_TCP_STALL_CYCLES_sum``", "Total number of cycles texture cache router stalls vector L1d"
-  "``TCP_TD_TCP_STALL_CYCLES_sum``", "Total number of cycles texture data unit stalls vector L1d"
-  "``TCP_TOTAL_ACCESSES_sum``", "Total number of vector L1d accesses"
-  "``TCP_TOTAL_READ_sum``", "Total number of vector L1d read accesses"
-  "``TCP_TOTAL_WRITE_sum``", "Total number of vector L1d write accesses"
-  "``TCP_TOTAL_ATOMIC_WITH_RET_sum``", "Total number of vector L1d atomic requests with return"
-  "``TCP_TOTAL_ATOMIC_WITHOUT_RET_sum``", "Total number of vector L1d atomic requests without return"
-  "``TCP_TOTAL_WRITEBACK_INVALIDATES_sum``", "Total number of vector L1d writebacks and invalidates"
-  "``TCP_VOLATILE_sum``", "Total number of L1 volatile pixels or buffers from texture addressing unit"
-  "``TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum``", "Total number of cycles tag RAM conflict stalls on a write"
-
-Hardware counter over all texture data unit instances
--------------------------------------------------------
-
-.. csv-table::
-  :header: "Hardware counter", "Definition"
-
-  "``TD_ATOMIC_WAVEFRONT_sum``", "Total number of atomic wavefront instructions"
-  "``TD_COALESCABLE_WAVEFRONT_sum``", "Total number of coalescable wavefronts according to texture addressing unit"
-  "``TD_LOAD_WAVEFRONT_sum``", "Total number of wavefront instructions (read, write, atomic)"
-  "``TD_SPI_STALL_sum``", "Total number of cycles texture data unit is stalled by shader processor input"
-  "``TD_STORE_WAVEFRONT_sum``", "Total number of write wavefront instructions"
-  "``TD_TC_STALL_sum``", "Total number of cycles texture data unit is stalled waiting for texture cache data"
-  "``TD_TD_BUSY_sum``", "Total number of texture data unit busy cycles while it is processing or waiting for data"
--- a/docs/conceptual/gpu-arch/mi300.md
+++ b/docs/conceptual/gpu-arch/mi300.md
@@ -1,129 +0,0 @@
---
-myst:
-  html_meta:
-    "description lang=en": "Learn about the AMD Instinct MI300 series architecture."
-    "keywords": "Instinct, MI300X, MI300A, microarchitecture, AMD, ROCm"
---
-
-# AMD Instinct™ MI300 series microarchitecture
-
-The AMD Instinct MI300 series accelerators are based on the AMD CDNA 3
-architecture which was designed to deliver leadership performance for HPC, artificial intelligence (AI), and machine
-learning (ML) workloads. The AMD Instinct MI300 series accelerators are well-suited for extreme scalability and compute performance, running
-on everything from individual servers to the world’s largest exascale supercomputers.
-
-With the MI300 series, AMD is introducing the Accelerator Complex Die (XCD), which contains the
-GPU computational elements of the processor along with the lower levels of the cache hierarchy.
-
-The following image depicts the structure of a single XCD in the AMD Instinct MI300 accelerator series.
-
-```{figure} ../../data/shared/xcd-sys-arch.png
---
-name: mi300-xcd
-align: center
---
-XCD-level system architecture showing 40 Compute Units, each with 32 KB L1 cache, a Unified Compute System with 4 ACE Compute Accelerators, shared 4MB of L2 cache and an HWS Hardware Scheduler.
-```
-
-On the XCD, four Asynchronous Compute Engines (ACEs) send compute shader workgroups to the
-Compute Units (CUs). The XCD has 40 CUs: 38 active CUs at the aggregate level and 2 disabled CUs for
-yield management. The CUs all share a 4 MB L2 cache that serves to coalesce all memory traffic for the
-die. With less than half of the CUs of the AMD Instinct MI200 Series compute die, the AMD CDNA™ 3
-XCD die is a smaller building block. However, it uses more advanced packaging and the processor
-can include 6 or 8 XCDs for up to 304 CUs, roughly 40% more than MI250X.
-
-The MI300 Series integrate up to 8 vertically stacked XCDs, 8 stacks of
-High-Bandwidth Memory 3 (HBM3) and 4 I/O dies (containing system
-infrastructure) using the AMD Infinity Fabric™ technology as interconnect.
-
-The Matrix Cores inside the CDNA 3 CUs have significant improvements, emphasizing AI and machine
-learning, enhancing throughput of existing data types while adding support for new data types.
-CDNA 2 Matrix Cores support FP16 and BF16, while offering INT8 for inference. Compared to MI250X
-accelerators, CDNA 3 Matrix Cores triple the performance for FP16 and BF16, while providing a
-performance gain of 6.8 times for INT8. FP8 has a performance gain of 16 times compared to FP32,
-while TF32 has a gain of 4 times compared to FP32.
-
-```{list-table} Peak-performance capabilities of the MI300X for different data types.
-:header-rows: 1
-:name: mi300x-perf-table
-
-*
-  - Computation and Data Type
-  - FLOPS/CLOCK/CU
-  - Peak TFLOPS
-*
-  - Matrix FP64
-  - 256
-  - 163.4
-*
-  - Vector FP64
-  - 128
-  - 81.7
-*
-  - Matrix FP32
-  - 256
-  - 163.4
-*
-  - Vector FP32
-  - 256
-  - 163.4
-*
-  - Vector TF32
-  - 1024
-  - 653.7
-*
-  - Matrix FP16
-  - 2048
-  - 1307.4
-*
-  - Matrix BF16
-  - 2048
-  - 1307.4
-*
-  - Matrix FP8
-  - 4096
-  - 2614.9
-*
-  - Matrix INT8
-  - 4096
-  - 2614.9
-```
-
-The above table summarizes the aggregated peak performance of the AMD Instinct MI300X Open
-Compute Platform (OCP) Open Accelerator Modules (OAMs) for different data types and command
-processors. The middle column lists the peak performance (number of data elements processed in a
-single instruction) of a single compute unit if a SIMD (or matrix) instruction is submitted in each clock
-cycle. The third column lists the theoretical peak performance of the OAM. The theoretical aggregated
-peak memory bandwidth of the GPU is 5.3 TB per second.
-
-The following image shows the block diagram of the APU (left) and the OAM package (right) both
-connected via AMD Infinity Fabric™ network on-chip.
-
-```{figure} ../../data/conceptual/gpu-arch/image008.png
---
-name: mi300-arch
-alt:
-align: center
---
-MI300 series system architecture showing MI300A (left) with 6 XCDs and 3 CCDs, while the MI300X (right) has 8 XCDs.
-```
-
-## Node-level architecture
-
-```{figure} ../../data/shared/mi300-node-level-arch.png
---
-name: mi300-node
-
-align: center
---
-MI300 series node-level architecture showing 8 fully interconnected MI300X OAM modules connected to (optional) PCIEe switches via retimers and HGX connectors.
-```
-
-The image above shows the node-level architecture of a system with AMD EPYC processors in a
-dual-socket configuration and eight AMD Instinct MI300X accelerators. The MI300X OAMs attach to the
-host system via PCIe Gen 5 x16 links (yellow lines). The GPUs are using seven high-bandwidth,
-low-latency AMD Infinity Fabric™ links (red lines) to form a fully connected 8-GPU system.
-
-<!---
-We need performance data about the P2P communication here.
-->
--- a/docs/conceptual/gpu-isolation.md
+++ b/docs/conceptual/gpu-isolation.md
@@ -1,116 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="GPU isolation techniques">
-  <meta name="keywords" content="GPU isolation techniques, UUID, universally unique identifier,
-  environment variables, virtual machines, AMD, ROCm">
-</head>
-
-# GPU isolation techniques
-
-Restricting the access of applications to a subset of GPUs, aka isolating
-GPUs allows users to hide GPU resources from programs. The programs by default
-will only use the "exposed" GPUs ignoring other (hidden) GPUs in the system.
-
-There are multiple ways to achieve isolation of GPUs in the ROCm software stack,
-differing in which applications they apply to and the security they provide.
-This page serves as an overview of the techniques.
-
-## Environment variables
-
-The runtimes in the ROCm software stack read these environment variables to
-select the exposed or default device to present to applications using them.
-
-Environment variables shouldn't be used for isolating untrusted applications,
-as an application can reset them before initializing the runtime.
-
-### `ROCR_VISIBLE_DEVICES`
-
-A list of device indices or {abbr}`UUID (universally unique identifier)`s
-that will be exposed to applications.
-
-Runtime
-: ROCm Software Runtime. Applies to all applications using the user mode ROCm
-  software stack.
-
-```{code-block} shell
-:caption: Example to expose the 1. device and a device based on UUID.
-export ROCR_VISIBLE_DEVICES="0,GPU-DEADBEEFDEADBEEF"
-```
-
-### `GPU_DEVICE_ORDINAL`
-
-Devices indices exposed to OpenCL and HIP applications.
-
-Runtime
-: ROCm Compute Language Runtime (`ROCclr`). Applies to applications and runtimes
-  using the `ROCclr` abstraction layer including HIP and OpenCL applications.
-
-```{code-block} shell
-:caption: Example to expose the 1. and 3. device in the system.
-export GPU_DEVICE_ORDINAL="0,2"
-```
-
-(hip_visible_devices)=
-
-### `HIP_VISIBLE_DEVICES`
-
-Device indices exposed to HIP applications.
-
-Runtime: HIP runtime. Applies only to applications using HIP on the AMD platform.
-
-```{code-block} shell
-:caption: Example to expose the 1. and 3. devices in the system.
-export HIP_VISIBLE_DEVICES="0,2"
-```
-
-### `CUDA_VISIBLE_DEVICES`
-
-Provided for CUDA compatibility, has the same effect as `HIP_VISIBLE_DEVICES`
-on the AMD platform.
-
-Runtime
-: HIP or CUDA Runtime. Applies to HIP applications on the AMD or NVIDIA platform
-  and CUDA applications.
-
-### `OMP_DEFAULT_DEVICE`
-
-Default device used for OpenMP target offloading.
-
-Runtime
-: OpenMP Runtime. Applies only to applications using OpenMP offloading.
-
-```{code-block} shell
-:caption: Example on setting the default device to the third device.
-export OMP_DEFAULT_DEVICE="2"
-```
-
-## Docker
-
-Docker uses Linux kernel namespaces to provide isolated environments for
-applications. This isolation applies to most devices by default, including
-GPUs. To access them in containers explicit access must be granted, please see
-{ref}`docker-access-gpus-in-container` for details.
-Specifically refer to {ref}`docker-restrict-gpus` on exposing just a subset
-of all GPUs.
-
-Docker isolation is more secure than environment variables, and applies
-to all programs that use the `amdgpu` kernel module interfaces.
-Even programs that don't use the ROCm runtime, like graphics applications
-using OpenGL or Vulkan, can only access the GPUs exposed to the container.
-
-## GPU passthrough to virtual machines
-
-Virtual machines achieve the highest level of isolation, because even the kernel
-of the virtual machine is isolated from the host. Devices physically installed
-in the host system can be passed to the virtual machine using PCIe passthrough.
-This allows for using the GPU with a different operating systems like a Windows
-guest from a Linux host.
-
-Setting up PCIe passthrough is specific to the hypervisor used. ROCm officially
-supports [VMware ESXi](https://www.vmware.com/products/esxi-and-esx.html)
-for select GPUs.
-
-<!--
-TODO: This should link to a page about virtualization that explains
-      pass-through and SR-IOV and how-tos for maybe `libvirt` and `VMWare`
-->
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -5,16 +5,9 @@
 # https://www.sphinx-doc.org/en/master/usage/configuration.html

 import os
-import shutil
 import sys
 from pathlib import Path

-shutil.copy2("../RELEASE.md", "./about/release-notes.md")
-shutil.copy2("../CHANGELOG.md", "./release/changelog.md")
-
-os.system("mkdir -p ../_readthedocs/html/downloads")
-os.system("cp compatibility/compatibility-matrix-historical-6.0.csv ../_readthedocs/html/downloads/compatibility-matrix-historical-6.0.csv")
-
 latex_engine = "xelatex"
 latex_elements = {
    "fontpkg": r"""
@@ -44,6 +37,7 @@ all_article_info_author = ""
 article_pages = [
    {"file": "preview/index", "os": ["linux"],},
    {"file": "preview/release", "os": ["linux"],},
+    {"file": "preview/versions", "os": ["linux"],},
    {"file": "preview/install/index", "os": ["linux"],},
    {"file": "preview/install/instinct-driver", "os": ["linux"],},
    {"file": "preview/install/rocm", "os": ["linux"],},
@@ -55,64 +49,9 @@ article_pages = [
    {"file": "preview/benchmark-docker/inference", "os": ["linux"],},
    {"file": "preview/benchmark-docker/inference-vllm-llama-3.1-405b-fp4", "os": ["linux"],},
    {"file": "preview/benchmark-docker/inference-sglang-deepseek-r1-fp4", "os": ["linux"],},
-
-    # {"file": "about/release-notes", "os": ["linux"], "date": "2025-06-26"},
-    # {"file": "release/changelog", "os": ["linux"],},
-    # {"file": "compatibility/compatibility-matrix", "os": ["linux"]},
-    # {"file": "compatibility/ml-compatibility/pytorch-compatibility", "os": ["linux"]},
-    # {"file": "compatibility/ml-compatibility/tensorflow-compatibility", "os": ["linux"]},
-    # {"file": "compatibility/ml-compatibility/jax-compatibility", "os": ["linux"]},
-    # {"file": "how-to/deep-learning-rocm", "os": ["linux"]},
-    #
-    # {"file": "how-to/rocm-for-ai/index", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/install", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/system-health-check", "os": ["linux"]},
-    #
-    # {"file": "how-to/rocm-for-ai/training/index", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/train-a-model", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/prerequisite-system-validation", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/benchmark-docker/megatron-lm", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/benchmark-docker/pytorch-training", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/benchmark-docker/mpt-llm-foundry", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/training/scale-model-training", "os": ["linux"]},
-    #
-    # {"file": "how-to/rocm-for-ai/fine-tuning/index", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/fine-tuning/overview", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/fine-tuning/fine-tuning-and-inference", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/fine-tuning/single-gpu-fine-tuning-and-inference", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/fine-tuning/multi-gpu-fine-tuning-and-inference", "os": ["linux"]},
-    #
-    # {"file": "how-to/rocm-for-ai/inference/index", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/hugging-face-models", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/llm-inference-frameworks", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/benchmark-docker/vllm", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/benchmark-docker/previous-versions/vllm-0.8.5-20250513", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/benchmark-docker/pytorch-inference", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference/deploy-your-model", "os": ["linux"]},
-    #
-    # {"file": "how-to/rocm-for-ai/inference-optimization/index", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/model-quantization", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/model-acceleration-libraries", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/optimizing-with-composable-kernel", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/optimizing-triton-kernel", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/profiling-and-debugging", "os": ["linux"]},
-    # {"file": "how-to/rocm-for-ai/inference-optimization/workload", "os": ["linux"]},
-    #
-    # {"file": "how-to/system-optimization/index", "os": ["linux"]},
-    # {"file": "how-to/system-optimization/mi300x", "os": ["linux"]},
-    # {"file": "how-to/system-optimization/mi200", "os": ["linux"]},
-    # {"file": "how-to/system-optimization/mi100", "os": ["linux"]},
-    # {"file": "how-to/system-optimization/w6000-v620", "os": ["linux"]},
-    # {"file": "how-to/tuning-guides/mi300x/index", "os": ["linux"]},
-    # {"file": "how-to/tuning-guides/mi300x/system", "os": ["linux"]},
-    # {"file": "how-to/tuning-guides/mi300x/workload", "os": ["linux"]},
-    # {"file": "how-to/system-debugging", "os": ["linux"]},
-    # {"file": "how-to/gpu-enabled-mpi", "os": ["linux"]},
 ]

 external_toc_path = "./sphinx/_toc.yml"
-# Options to improve documentation build time for preview release documentation
-external_toc_exclude_missing = True # don't build files that aren't in the TOC
 external_projects_remote_repository = "" # don't fetch data to resolve intersphinx xrefs

 # Add the _extensions directory to Python's search path
@@ -120,13 +59,8 @@ sys.path.append(str(Path(__file__).parent / 'extension'))

 extensions = ["rocm_docs", "sphinx_reredirects", "sphinx_sitemap", "sphinxcontrib.datatemplates", "version-ref", "csv-to-list-table"]

-compatibility_matrix_file = str(Path(__file__).parent / 'compatibility/compatibility-matrix-historical-6.0.csv')
-
 external_projects_current_project = "rocm"

-# Uncomment if facing rate limit exceed issue with local build
-# external_projects_remote_repository = ""
-
 html_baseurl = os.environ.get("READTHEDOCS_CANONICAL_URL", "https://rocm-stg.amd.com/")
 html_context = {}
 if os.environ.get("READTHEDOCS", "") == "True":
@@ -135,16 +69,14 @@ if os.environ.get("READTHEDOCS", "") == "True":
 html_theme = "rocm_docs_theme"
 html_theme_options = {"flavor": "rocm-docs-home"}

-html_static_path = ["sphinx/static/css", "extension/how-to/rocm-for-ai/inference"]
-html_css_files = ["rocm_custom.css", "rocm_rn.css", "vllm-benchmark.css"]
-html_js_files = ["vllm-benchmark.js"]
+html_static_path = ["sphinx/static/css", "sphinx/static/js"]
+html_css_files = ["rocm_custom.css", "rocm_rn.css"]
+html_js_files = ["preview-version-list.js"]

 html_title = "ROCm 7.0 Alpha documentation"

 html_theme_options = {"link_main_doc": False}

-redirects = {"reference/openmp/openmp": "../../about/compatibility/openmp.html"}
-
 numfig = False

 html_context = {
--- a/docs/contribute/building.md
+++ b/docs/contribute/building.md
@@ -1,150 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="Building ROCm documentation">
-  <meta name="keywords" content="documentation, Visual Studio Code, GitHub, command line,
-  AMD, ROCm">
-</head>
-
-# Building documentation
-
-## GitHub
-
-If you open a pull request and scroll down to the summary panel,
-there is a commit status section. Next to the line
-`docs/readthedocs.com:advanced-micro-devices-demo`, there is a `Details` link.
-If you click this, it takes you to the Read the Docs build for your pull request.
-
-![GitHub PR commit status](../data/contribute/commit-status.png)
-
-If you don't see this line, click `Show all checks` to get an itemized view.
-
-## Command line
-
-You can build our documentation via the command line using Python.
-
-See the `build.tools.python` setting in the [Read the Docs configuration file](https://github.com/ROCm/ROCm/blob/develop/.readthedocs.yaml) for the Python version used by Read the Docs to build documentation.
-
-See the [Python requirements file](https://github.com/ROCm/ROCm/blob/develop/docs/sphinx/requirements.txt) for Python packages needed to build the documentation.
-
-Use the Python Virtual Environment (`venv`) and run the following commands from the project root:
-
-```sh
-python3 -mvenv .venv
-
-.venv/bin/python     -m pip install -r docs/sphinx/requirements.txt
-.venv/bin/python     -m sphinx -T -E -b html -d _build/doctrees -D language=en docs _build/html
-```
-
-Navigate to `_build/html/index.html` and open this file in a web browser.
-
-## Visual Studio Code
-
-With the help of a few extensions, you can create a productive environment to author and test
-documentation locally using Visual Studio (VS) Code. Follow these steps to configure VS Code:
-
-1. Install the required extensions:
-
-   * Python: `(ms-python.python)`
-   * Live Server: `(ritwickdey.LiveServer)`
-
-2. Add the following entries to `.vscode/settings.json`.
-
-    ```json
-      {
-        "liveServer.settings.root": "/.vscode/build/html",
-        "liveServer.settings.wait": 1000,
-        "python.terminal.activateEnvInCurrentTerminal": true
-      }
-    ```
-
-    * `liveServer.settings.root`: Sets the root of the output website for live previews. Must be changed
-      alongside the `tasks.json` command.
-    * `liveServer.settings.wait`: Tells the live server to wait with the update in order to give Sphinx time to
-      regenerate the site contents and not refresh before the build is complete.
-    * `python.terminal.activateEnvInCurrentTerminal`: Activates the automatic virtual environment, so you
-      can build the site from the integrated terminal.
-
-3. Add the following tasks to `.vscode/tasks.json`.
-
-    ```json
-      {
-        "version": "2.0.0",
-        "tasks": [
-          {
-            "label": "Build Docs",
-            "type": "process",
-            "windows": {
-              "command": "${workspaceFolder}/.venv/Scripts/python.exe"
-            },
-            "command": "${workspaceFolder}/.venv/bin/python3",
-            "args": [
-              "-m",
-              "sphinx",
-              "-j",
-              "auto",
-              "-T",
-              "-b",
-              "html",
-              "-d",
-              "${workspaceFolder}/.vscode/build/doctrees",
-              "-D",
-              "language=en",
-              "${workspaceFolder}/docs",
-              "${workspaceFolder}/.vscode/build/html"
-            ],
-            "problemMatcher": [
-              {
-                "owner": "sphinx",
-                "fileLocation": "absolute",
-                "pattern": {
-                  "regexp": "^(?:.*\\.{3}\\s+)?(\\/[^:]*|[a-zA-Z]:\\\\[^:]*):(\\d+):\\s+(WARNING|ERROR):\\s+(.*)$",
-                  "file": 1,
-                  "line": 2,
-                  "severity": 3,
-                  "message": 4
-                }
-              },
-              {
-              "owner": "sphinx",
-                "fileLocation": "absolute",
-                "pattern": {
-                  "regexp": "^(?:.*\\.{3}\\s+)?(\\/[^:]*|[a-zA-Z]:\\\\[^:]*):{1,2}\\s+(WARNING|ERROR):\\s+(.*)$",
-                  "file": 1,
-                  "severity": 2,
-                  "message": 3
-                }
-              }
-            ],
-            "group": {
-              "kind": "build",
-              "isDefault": true
-            }
-          }
-        ]
-      }
-    ```
-
-    > Implementation detail: two problem matchers were needed to be defined,
-    > because VS Code doesn't tolerate some problem information being potentially
-    > absent. While a single regex could match all types of errors, if a capture
-    > group remains empty (the line number doesn't show up in all warning/error
-    > messages) but the `pattern` references said empty capture group, VS Code
-    > discards the message completely.
-
-4. Configure the Python virtual environment (`venv`).
-
-    From the Command Palette, run `Python: Create Environment`. Select `venv` environment and
-    `docs/sphinx/requirements.txt`.
-
-5. Build the docs.
-
-    Launch the default build task using one of the following options:
-
-    * A hotkey (the default is `Ctrl+Shift+B`)
-    * Issuing the `Tasks: Run Build Task` from the Command Palette
-
-6. Open the live preview.
-
-    Navigate to the site output within VS Code: right-click on `.vscode/build/html/index.html` and
-    select `Open with Live Server`. The contents should update on every rebuild without having to
-    refresh the browser.
--- a/docs/contribute/contributing.md
+++ b/docs/contribute/contributing.md
@@ -1,77 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="Contributing to ROCm">
-  <meta name="keywords" content="ROCm, contributing, contribute, maintainer, contributor">
-</head>
-
-# Contributing to the ROCm documentation
-
-The ROCm documentation, like all of ROCm, is open source and available on GitHub. You can contribute to the ROCm documentation by forking the appropriate repository, making your changes, and opening a pull request.
-
-To provide feedback on the ROCm documentation, including submitting an issue or suggesting a feature, see [Providing feedback about the ROCm documentation](./feedback.md).
-
-## The ROCm repositories
-
-The repositories for ROCm and all ROCm components are available on GitHub.
-
-| Module | Documentation location |
-| --- | --- |
-| ROCm framework | [https://github.com/ROCm/ROCm/tree/develop/docs](https://github.com/ROCm/ROCm/tree/develop/docs) |
-| ROCm installation for Linux | [https://github.com/ROCm/rocm-install-on-linux/tree/develop/docs](https://github.com/ROCm/rocm-install-on-linux/tree/develop/docs) |
-| ROCm HIP SDK installation for Windows |  [https://github.com/ROCm/rocm-install-on-windows/tree/develop/docs](https://github.com/ROCm/rocm-install-on-windows/tree/develop/docs) |
-
-Individual components have their own repositories with their own documentation in their own `docs` folders.
-
-The sub-folders within the `docs` folders across ROCm are typically structured as follows:
-
-| Sub-folder name | Documentation type |
-|-------|----------|
-| `install` | Installation instructions, build instructions, and prerequisites |
-| `conceptual` | Important concepts |
-| `how-to` | How to implement specific use cases |
-| `tutorials` | Tutorials |
-| `reference` | API references and other reference resources |
-
-## Editing and adding to the documentation
-
-ROCm documentation follows the [Google developer documentation style guide](https://developers.google.com/style/highlights).
-
-Most topics in the ROCm documentation are written in [reStructuredText (rst)](https://www.sphinx-doc.org/en/master/usage/restructuredtext/index.html), with some topics written in Markdown. Only use reStructuredText when adding new topics. Only use Markdown if the topic you are editing is already in Markdown.
-
-To edit or add to the documentation:
-
-1. Fork the repository you want to add to or edit.
-2. Clone your fork locally.
-3. Create a new local branch cut from the `develop` branch of the repository.
-4. Make your changes to the documentation.
-
-5. Optionally, build the documentation locally before creating a pull request by running the following commands from within the `docs` folder:
-
-    ```bash
-     pip3 install -r sphinx/requirements.txt  # You only need to run this command once
-     python3 -m sphinx -T -E -b html -d _build/doctrees -D language=en . _build/html
-     ```
-
-    The output files will be located in the `docs/_build` folder. Open `docs/_build/html/index.html` to view the documentation.
-
-    For more information on ROCm build tools, see [Documentation toolchain](toolchain.md).
-6. Push your changes. A GitHub link will be returned in the output of the `git push` command. Open this link in a browser to create the pull request.
-
-    The documentation is built as part of the checks on pull request, along with spell checking and linting. Scroll to the bottom of your pull request to view all the checks.
-
-    Verify that the linting and spell checking have passed, and that the documentation was built successfully. New words or acronyms can be added to the [wordlist file](https://github.com/ROCm/rocm-docs-core/blob/develop/.wordlist.txt). The wordlist is subject to approval by the ROCm documentation team.
-
-    The Read The Docs build of your pull request can be accessed by clicking on the Details link next to the Read The Docs build check. Verify that your changes are in the build and look as expected.
-
-    ![The GitHub checks are collapsed by default and can be accessed by clicking on "Show All Checks".](../data/contribute/GitHubCheck-Highlight.png)
-  
-    ![The Read The Docs Build is accessed from the Details link in the Read The Docs check.](../data/contribute/GitHub-ReadThe-Docs-Highlight.png)
-
-    Your pull request will be reviewed by a member of the ROCm documentation team.
-
-See the [GitHub documentation](https://docs.github.com/en) for information on how to fork and clone a repository, and how to create and push a local branch.
-
-```{important}
-By creating a pull request (PR), you agree to allow your contribution to be licensed under the terms of the
-LICENSE.txt file in the corresponding repository. Different repositories can use different licenses.
-```
--- a/docs/contribute/feedback.md
+++ b/docs/contribute/feedback.md
@@ -1,27 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="Providing feedback for ROCm documentation">
-  <meta name="keywords" content="documentation, pull request, GitHub, AMD, ROCm">
-</head>
-
-# Providing feedback about the ROCm documentation
-
-Feedback about the ROCm documentation is welcome. You can provide feedback about the ROCm documentation either through GitHub Discussions or GitHub Issues.
-
-## Participating in discussions through GitHub Discussions
-
-You can ask questions, view announcements, suggest new features, and communicate with other members of the community through [GitHub Discussions](https://github.com/ROCm/ROCm/discussions).
-
-## Submitting issues through GitHub Issues
-
-You can submit issues through [GitHub Issues](https://github.com/ROCm/ROCm/issues).
-
-When creating a new issue, follow the following guidelines:
-
-1. Always do a search to see if the same issue already exists. If the issue already exists, upvote it, and comment or post to provide any additional details you might have.
-2. If you find an issue that is similar to your issue, log your issue, then add a comment that includes a link to the similar issue, as well as its issue number.
-3. Always provide as much information as possible. This helps reduce the time required to reproduce the issue.
-
-After creating your issue, make sure to check it regularly for any requests for additional information.
-
-For information about contributing content to the ROCm documentation, see [Contributing to the ROCm documentation](./contributing.md).
--- a/docs/contribute/toolchain.md
+++ b/docs/contribute/toolchain.md
@@ -1,46 +0,0 @@
-<head>
-  <meta charset="UTF-8">
-  <meta name="description" content="ROCm documentation toolchain">
-  <meta name="keywords" content="documentation, toolchain, Sphinx, Doxygen, MyST, AMD, ROCm">
-</head>
-
-# ROCm documentation toolchain
-
-The ROCm documentation relies on several open source toolchains and sites.
-
-## rocm-docs-core
-
-[rocm-docs-core](https://github.com/ROCm/rocm-docs-core) is an AMD-maintained
-project that applies customizations for the ROCm documentation. This project is the tool most ROCm repositories use as part of their documentation build pipeline. It is available as a [pip package on PyPI](https://pypi.org/project/rocm-docs-core/).
-
-See the user and developer guides for rocm-docs-core at
-{doc}`rocm-docs-core documentation<rocm-docs-core:index>`.
-
-## Sphinx
-
-[Sphinx](https://www.sphinx-doc.org/en/master/) is a documentation generator originally used for Python. It is now widely used in the open source community.
-
-### Sphinx External ToC
-
-[Sphinx External ToC](https://sphinx-external-toc.readthedocs.io/en/latest/intro.html) is a Sphinx extension used for ROCm documentation navigation. This tool generates a navigation menu on the left
-based on a YAML file (`_toc.yml.in`) that contains the table of contents.
-
-### Sphinx-book-theme
-
-[Sphinx-book-theme](https://sphinx-book-theme.readthedocs.io/en/latest/) is a Sphinx theme that defines the base appearance for ROCm documentation. ROCm documentation applies some customization, such as a custom header and footer, on top of the Sphinx Book Theme.
-
-### Sphinx Design
-
-[Sphinx design](https://sphinx-design.readthedocs.io/en/latest/index.html) is a Sphinx extension that adds design functionality. ROCm documentation uses Sphinx Design for grids, cards, and synchronized tabs.
-
-## Doxygen
-
-[Doxygen](https://www.doxygen.nl/) is a documentation generator that extracts information from in-code comments. It is used for API documentation.
-
-## Breathe
-
-[Breathe](https://www.breathe-doc.org/) is a Sphinx plugin for integrating Doxygen content.
-
-## Read the Docs
-
-[Read the Docs](https://docs.readthedocs.io/en/stable/) is the service that builds and hosts the HTML version of the ROCm documentation.
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--- a/docs/data/how-to/llm-fine-tuning-optimization/vllm-single-gpu-log.png
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--- a/docs/data/how-to/llm-fine-tuning-optimization/weight-update.png
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--- a/docs/data/how-to/rocm-for-ai/2-node-training-master.png
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--- a/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.7.3_20250325-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.7.3_20250325-benchmark-models.yaml
@@ -1,159 +0,0 @@
-vllm_benchmark:
-  unified_docker:
-    latest:
-      pull_tag: rocm/vllm:rocm6.3.1_instinct_vllm0.7.3_20250325
-      docker_hub_url: https://hub.docker.com/layers/rocm/vllm/rocm6.3.1_instinct_vllm0.7.3_20250325/images/sha256-25245924f61750b19be6dcd8e787e46088a496c1fe17ee9b9e397f3d84d35640
-      rocm_version: 6.3.1
-      vllm_version: 0.7.3
-      pytorch_version: 2.7.0 (dev nightly)
-      hipblaslt_version: 0.13
-  model_groups:
-    - group: Llama
-      tag: llama
-      models:
-      - model: Llama 3.1 8B
-        mad_tag: pyt_vllm_llama-3.1-8b
-        model_repo: meta-llama/Llama-3.1-8B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-8B
-        precision: float16
-      - model: Llama 3.1 70B
-        mad_tag: pyt_vllm_llama-3.1-70b
-        model_repo: meta-llama/Llama-3.1-70B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-        precision: float16
-      - model: Llama 3.1 405B
-        mad_tag: pyt_vllm_llama-3.1-405b
-        model_repo: meta-llama/Llama-3.1-405B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-405B-Instruct
-        precision: float16
-      - model: Llama 3.2 11B Vision
-        mad_tag: pyt_vllm_llama-3.2-11b-vision-instruct
-        model_repo: meta-llama/Llama-3.2-11B-Vision-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.2-11B-Vision-Instruct
-        precision: float16
-      - model: Llama 2 7B
-        mad_tag: pyt_vllm_llama-2-7b
-        model_repo: meta-llama/Llama-2-7b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-7b-chat-hf
-        precision: float16
-      - model: Llama 2 70B
-        mad_tag: pyt_vllm_llama-2-70b
-        model_repo: meta-llama/Llama-2-70b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-70b-chat-hf
-        precision: float16
-      - model: Llama 3.1 8B FP8
-        mad_tag: pyt_vllm_llama-3.1-8b_fp8
-        model_repo: amd/Llama-3.1-8B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-8B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 70B FP8
-        mad_tag: pyt_vllm_llama-3.1-70b_fp8
-        model_repo: amd/Llama-3.1-70B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-70B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 405B FP8
-        mad_tag: pyt_vllm_llama-3.1-405b_fp8
-        model_repo: amd/Llama-3.1-405B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-405B-Instruct-FP8-KV
-        precision: float8
-    - group: Mistral
-      tag: mistral
-      models:
-      - model: Mixtral MoE 8x7B
-        mad_tag: pyt_vllm_mixtral-8x7b
-        model_repo: mistralai/Mixtral-8x7B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x7B-Instruct-v0.1
-        precision: float16
-      - model: Mixtral MoE 8x22B
-        mad_tag: pyt_vllm_mixtral-8x22b
-        model_repo: mistralai/Mixtral-8x22B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x22B-Instruct-v0.1
-        precision: float16
-      - model: Mistral 7B
-        mad_tag: pyt_vllm_mistral-7b
-        model_repo: mistralai/Mistral-7B-Instruct-v0.3
-        url: https://huggingface.co/mistralai/Mistral-7B-Instruct-v0.3
-        precision: float16
-      - model: Mixtral MoE 8x7B FP8
-        mad_tag: pyt_vllm_mixtral-8x7b_fp8
-        model_repo: amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mixtral MoE 8x22B FP8
-        mad_tag: pyt_vllm_mixtral-8x22b_fp8
-        model_repo: amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mistral 7B FP8
-        mad_tag: pyt_vllm_mistral-7b_fp8
-        model_repo: amd/Mistral-7B-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mistral-7B-v0.1-FP8-KV
-        precision: float8
-    - group: Qwen
-      tag: qwen
-      models:
-      - model: Qwen2 7B
-        mad_tag: pyt_vllm_qwen2-7b
-        model_repo: Qwen/Qwen2-7B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-7B-Instruct
-        precision: float16
-      - model: Qwen2 72B
-        mad_tag: pyt_vllm_qwen2-72b
-        model_repo: Qwen/Qwen2-72B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-72B-Instruct
-        precision: float16
-    - group: JAIS
-      tag: jais
-      models:
-      - model: JAIS 13B
-        mad_tag: pyt_vllm_jais-13b
-        model_repo: core42/jais-13b-chat
-        url: https://huggingface.co/core42/jais-13b-chat
-        precision: float16
-      - model: JAIS 30B
-        mad_tag: pyt_vllm_jais-30b
-        model_repo: core42/jais-30b-chat-v3
-        url: https://huggingface.co/core42/jais-30b-chat-v3
-        precision: float16
-    - group: DBRX
-      tag: dbrx
-      models:
-      - model: DBRX Instruct
-        mad_tag: pyt_vllm_dbrx-instruct
-        model_repo: databricks/dbrx-instruct
-        url: https://huggingface.co/databricks/dbrx-instruct
-        precision: float16
-      - model: DBRX Instruct FP8
-        mad_tag: pyt_vllm_dbrx_fp8
-        model_repo: amd/dbrx-instruct-FP8-KV
-        url: https://huggingface.co/amd/dbrx-instruct-FP8-KV
-        precision: float8
-    - group: Gemma
-      tag: gemma
-      models:
-      - model: Gemma 2 27B
-        mad_tag: pyt_vllm_gemma-2-27b
-        model_repo: google/gemma-2-27b
-        url: https://huggingface.co/google/gemma-2-27b
-        precision: float16
-    - group: Cohere
-      tag: cohere
-      models:
-      - model: C4AI Command R+ 08-2024
-        mad_tag: pyt_vllm_c4ai-command-r-plus-08-2024
-        model_repo: CohereForAI/c4ai-command-r-plus-08-2024
-        url: https://huggingface.co/CohereForAI/c4ai-command-r-plus-08-2024
-        precision: float16
-      - model: C4AI Command R+ 08-2024 FP8
-        mad_tag: pyt_vllm_command-r-plus_fp8
-        model_repo: amd/c4ai-command-r-plus-FP8-KV
-        url: https://huggingface.co/amd/c4ai-command-r-plus-FP8-KV
-        precision: float8
-    - group: DeepSeek
-      tag: deepseek
-      models:
-      - model: DeepSeek MoE 16B
-        mad_tag: pyt_vllm_deepseek-moe-16b-chat
-        model_repo: deepseek-ai/deepseek-moe-16b-chat
-        url: https://huggingface.co/deepseek-ai/deepseek-moe-16b-chat
-        precision: float16
--- a/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.3_20250415-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.3_20250415-benchmark-models.yaml
@@ -1,152 +0,0 @@
-vllm_benchmark:
-  unified_docker:
-    latest:
-      pull_tag: rocm/vllm:rocm6.3.1_instinct_vllm0.8.3_20250415
-      docker_hub_url: https://hub.docker.com/layers/rocm/vllm/rocm6.3.1_instinct_vllm0.8.3_20250415/images/sha256-ad9062dea3483d59dedb17c67f7c49f30eebd6eb37c3fac0a171fb19696cc845
-      rocm_version: 6.3.1
-      vllm_version: 0.8.3
-      pytorch_version: 2.7.0 (dev nightly)
-      hipblaslt_version: 0.13
-  model_groups:
-    - group: Llama
-      tag: llama
-      models:
-      - model: Llama 3.1 8B
-        mad_tag: pyt_vllm_llama-3.1-8b
-        model_repo: meta-llama/Llama-3.1-8B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-8B
-        precision: float16
-      - model: Llama 3.1 70B
-        mad_tag: pyt_vllm_llama-3.1-70b
-        model_repo: meta-llama/Llama-3.1-70B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-        precision: float16
-      - model: Llama 3.1 405B
-        mad_tag: pyt_vllm_llama-3.1-405b
-        model_repo: meta-llama/Llama-3.1-405B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-405B-Instruct
-        precision: float16
-      - model: Llama 3.2 11B Vision
-        mad_tag: pyt_vllm_llama-3.2-11b-vision-instruct
-        model_repo: meta-llama/Llama-3.2-11B-Vision-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.2-11B-Vision-Instruct
-        precision: float16
-      - model: Llama 2 7B
-        mad_tag: pyt_vllm_llama-2-7b
-        model_repo: meta-llama/Llama-2-7b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-7b-chat-hf
-        precision: float16
-      - model: Llama 2 70B
-        mad_tag: pyt_vllm_llama-2-70b
-        model_repo: meta-llama/Llama-2-70b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-70b-chat-hf
-        precision: float16
-      - model: Llama 3.1 8B FP8
-        mad_tag: pyt_vllm_llama-3.1-8b_fp8
-        model_repo: amd/Llama-3.1-8B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-8B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 70B FP8
-        mad_tag: pyt_vllm_llama-3.1-70b_fp8
-        model_repo: amd/Llama-3.1-70B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-70B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 405B FP8
-        mad_tag: pyt_vllm_llama-3.1-405b_fp8
-        model_repo: amd/Llama-3.1-405B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-405B-Instruct-FP8-KV
-        precision: float8
-    - group: Mistral
-      tag: mistral
-      models:
-      - model: Mixtral MoE 8x7B
-        mad_tag: pyt_vllm_mixtral-8x7b
-        model_repo: mistralai/Mixtral-8x7B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x7B-Instruct-v0.1
-        precision: float16
-      - model: Mixtral MoE 8x22B
-        mad_tag: pyt_vllm_mixtral-8x22b
-        model_repo: mistralai/Mixtral-8x22B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x22B-Instruct-v0.1
-        precision: float16
-      - model: Mistral 7B
-        mad_tag: pyt_vllm_mistral-7b
-        model_repo: mistralai/Mistral-7B-Instruct-v0.3
-        url: https://huggingface.co/mistralai/Mistral-7B-Instruct-v0.3
-        precision: float16
-      - model: Mixtral MoE 8x7B FP8
-        mad_tag: pyt_vllm_mixtral-8x7b_fp8
-        model_repo: amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mixtral MoE 8x22B FP8
-        mad_tag: pyt_vllm_mixtral-8x22b_fp8
-        model_repo: amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mistral 7B FP8
-        mad_tag: pyt_vllm_mistral-7b_fp8
-        model_repo: amd/Mistral-7B-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mistral-7B-v0.1-FP8-KV
-        precision: float8
-    - group: Qwen
-      tag: qwen
-      models:
-      - model: Qwen2 7B
-        mad_tag: pyt_vllm_qwen2-7b
-        model_repo: Qwen/Qwen2-7B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-7B-Instruct
-        precision: float16
-      - model: Qwen2 72B
-        mad_tag: pyt_vllm_qwen2-72b
-        model_repo: Qwen/Qwen2-72B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-72B-Instruct
-        precision: float16
-      - model: QwQ-32B
-        mad_tag: pyt_vllm_qwq-32b
-        model_repo: Qwen/QwQ-32B
-        url: https://huggingface.co/Qwen/QwQ-32B
-        precision: float16
-        tunableop: true
-    - group: DBRX
-      tag: dbrx
-      models:
-      - model: DBRX Instruct
-        mad_tag: pyt_vllm_dbrx-instruct
-        model_repo: databricks/dbrx-instruct
-        url: https://huggingface.co/databricks/dbrx-instruct
-        precision: float16
-      - model: DBRX Instruct FP8
-        mad_tag: pyt_vllm_dbrx_fp8
-        model_repo: amd/dbrx-instruct-FP8-KV
-        url: https://huggingface.co/amd/dbrx-instruct-FP8-KV
-        precision: float8
-    - group: Gemma
-      tag: gemma
-      models:
-      - model: Gemma 2 27B
-        mad_tag: pyt_vllm_gemma-2-27b
-        model_repo: google/gemma-2-27b
-        url: https://huggingface.co/google/gemma-2-27b
-        precision: float16
-    - group: Cohere
-      tag: cohere
-      models:
-      - model: C4AI Command R+ 08-2024
-        mad_tag: pyt_vllm_c4ai-command-r-plus-08-2024
-        model_repo: CohereForAI/c4ai-command-r-plus-08-2024
-        url: https://huggingface.co/CohereForAI/c4ai-command-r-plus-08-2024
-        precision: float16
-      - model: C4AI Command R+ 08-2024 FP8
-        mad_tag: pyt_vllm_command-r-plus_fp8
-        model_repo: amd/c4ai-command-r-plus-FP8-KV
-        url: https://huggingface.co/amd/c4ai-command-r-plus-FP8-KV
-        precision: float8
-    - group: DeepSeek
-      tag: deepseek
-      models:
-      - model: DeepSeek MoE 16B
-        mad_tag: pyt_vllm_deepseek-moe-16b-chat
-        model_repo: deepseek-ai/deepseek-moe-16b-chat
-        url: https://huggingface.co/deepseek-ai/deepseek-moe-16b-chat
-        precision: float16
--- a/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.5_20250513-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.5_20250513-benchmark-models.yaml
@@ -1,152 +0,0 @@
-vllm_benchmark:
-  unified_docker:
-    latest:
-      pull_tag: rocm/vllm:rocm6.3.1_vllm0.8.5_20250513
-      docker_hub_url: https://hub.docker.com/layers/rocm/vllm/rocm6.3.1_vllm_0.8.5_20250513/images/sha256-5c8b4436dd0464119d9df2b44c745fadf81512f18ffb2f4b5dc235c71ebe26b4
-      rocm_version: 6.3.1
-      vllm_version: 0.8.5
-      pytorch_version: 2.7.0+gitf717b2a
-      hipblaslt_version: 0.15
-  model_groups:
-    - group: Meta Llama
-      tag: llama
-      models:
-      - model: Llama 3.1 8B
-        mad_tag: pyt_vllm_llama-3.1-8b
-        model_repo: meta-llama/Llama-3.1-8B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-8B
-        precision: float16
-      - model: Llama 3.1 70B
-        mad_tag: pyt_vllm_llama-3.1-70b
-        model_repo: meta-llama/Llama-3.1-70B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-        precision: float16
-      - model: Llama 3.1 405B
-        mad_tag: pyt_vllm_llama-3.1-405b
-        model_repo: meta-llama/Llama-3.1-405B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-405B-Instruct
-        precision: float16
-      - model: Llama 3.2 11B Vision
-        mad_tag: pyt_vllm_llama-3.2-11b-vision-instruct
-        model_repo: meta-llama/Llama-3.2-11B-Vision-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.2-11B-Vision-Instruct
-        precision: float16
-      - model: Llama 2 7B
-        mad_tag: pyt_vllm_llama-2-7b
-        model_repo: meta-llama/Llama-2-7b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-7b-chat-hf
-        precision: float16
-      - model: Llama 2 70B
-        mad_tag: pyt_vllm_llama-2-70b
-        model_repo: meta-llama/Llama-2-70b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-70b-chat-hf
-        precision: float16
-      - model: Llama 3.1 8B FP8
-        mad_tag: pyt_vllm_llama-3.1-8b_fp8
-        model_repo: amd/Llama-3.1-8B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-8B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 70B FP8
-        mad_tag: pyt_vllm_llama-3.1-70b_fp8
-        model_repo: amd/Llama-3.1-70B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-70B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 405B FP8
-        mad_tag: pyt_vllm_llama-3.1-405b_fp8
-        model_repo: amd/Llama-3.1-405B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-405B-Instruct-FP8-KV
-        precision: float8
-    - group: Mistral AI
-      tag: mistral
-      models:
-      - model: Mixtral MoE 8x7B
-        mad_tag: pyt_vllm_mixtral-8x7b
-        model_repo: mistralai/Mixtral-8x7B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x7B-Instruct-v0.1
-        precision: float16
-      - model: Mixtral MoE 8x22B
-        mad_tag: pyt_vllm_mixtral-8x22b
-        model_repo: mistralai/Mixtral-8x22B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x22B-Instruct-v0.1
-        precision: float16
-      - model: Mistral 7B
-        mad_tag: pyt_vllm_mistral-7b
-        model_repo: mistralai/Mistral-7B-Instruct-v0.3
-        url: https://huggingface.co/mistralai/Mistral-7B-Instruct-v0.3
-        precision: float16
-      - model: Mixtral MoE 8x7B FP8
-        mad_tag: pyt_vllm_mixtral-8x7b_fp8
-        model_repo: amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mixtral MoE 8x22B FP8
-        mad_tag: pyt_vllm_mixtral-8x22b_fp8
-        model_repo: amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mistral 7B FP8
-        mad_tag: pyt_vllm_mistral-7b_fp8
-        model_repo: amd/Mistral-7B-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mistral-7B-v0.1-FP8-KV
-        precision: float8
-    - group: Qwen
-      tag: qwen
-      models:
-      - model: Qwen2 7B
-        mad_tag: pyt_vllm_qwen2-7b
-        model_repo: Qwen/Qwen2-7B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-7B-Instruct
-        precision: float16
-      - model: Qwen2 72B
-        mad_tag: pyt_vllm_qwen2-72b
-        model_repo: Qwen/Qwen2-72B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-72B-Instruct
-        precision: float16
-      - model: QwQ-32B
-        mad_tag: pyt_vllm_qwq-32b
-        model_repo: Qwen/QwQ-32B
-        url: https://huggingface.co/Qwen/QwQ-32B
-        precision: float16
-        tunableop: true
-    - group: Databricks DBRX
-      tag: dbrx
-      models:
-      - model: DBRX Instruct
-        mad_tag: pyt_vllm_dbrx-instruct
-        model_repo: databricks/dbrx-instruct
-        url: https://huggingface.co/databricks/dbrx-instruct
-        precision: float16
-      - model: DBRX Instruct FP8
-        mad_tag: pyt_vllm_dbrx_fp8
-        model_repo: amd/dbrx-instruct-FP8-KV
-        url: https://huggingface.co/amd/dbrx-instruct-FP8-KV
-        precision: float8
-    - group: Google Gemma
-      tag: gemma
-      models:
-      - model: Gemma 2 27B
-        mad_tag: pyt_vllm_gemma-2-27b
-        model_repo: google/gemma-2-27b
-        url: https://huggingface.co/google/gemma-2-27b
-        precision: float16
-    - group: Cohere
-      tag: cohere
-      models:
-      - model: C4AI Command R+ 08-2024
-        mad_tag: pyt_vllm_c4ai-command-r-plus-08-2024
-        model_repo: CohereForAI/c4ai-command-r-plus-08-2024
-        url: https://huggingface.co/CohereForAI/c4ai-command-r-plus-08-2024
-        precision: float16
-      - model: C4AI Command R+ 08-2024 FP8
-        mad_tag: pyt_vllm_command-r-plus_fp8
-        model_repo: amd/c4ai-command-r-plus-FP8-KV
-        url: https://huggingface.co/amd/c4ai-command-r-plus-FP8-KV
-        precision: float8
-    - group: DeepSeek
-      tag: deepseek
-      models:
-      - model: DeepSeek MoE 16B
-        mad_tag: pyt_vllm_deepseek-moe-16b-chat
-        model_repo: deepseek-ai/deepseek-moe-16b-chat
-        url: https://huggingface.co/deepseek-ai/deepseek-moe-16b-chat
-        precision: float16
--- a/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.5_20250521-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/previous-versions/vllm_0.8.5_20250521-benchmark-models.yaml
@@ -1,167 +0,0 @@
-vllm_benchmark:
-  unified_docker:
-    latest:
-      pull_tag: rocm/vllm:rocm6.3.1_vllm0.8.5_20250521
-      docker_hub_url: https://hub.docker.com/layers/rocm/vllm/rocm6.3.1_vllm_0.8.5_20250521/images/sha256-38410c51af7208897cd8b737c9bdfc126e9bc8952d4aa6b88c85482f03092a11
-      rocm_version: 6.3.1
-      vllm_version: 0.8.5 (0.8.6.dev315+g91a560098.rocm631)
-      pytorch_version: 2.7.0+gitf717b2a
-      hipblaslt_version: 0.15
-  model_groups:
-    - group: Meta Llama
-      tag: llama
-      models:
-        - model: Llama 3.1 8B
-          mad_tag: pyt_vllm_llama-3.1-8b
-          model_repo: meta-llama/Llama-3.1-8B-Instruct
-          url: https://huggingface.co/meta-llama/Llama-3.1-8B
-          precision: float16
-        - model: Llama 3.1 70B
-          mad_tag: pyt_vllm_llama-3.1-70b
-          model_repo: meta-llama/Llama-3.1-70B-Instruct
-          url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-          precision: float16
-        - model: Llama 3.1 405B
-          mad_tag: pyt_vllm_llama-3.1-405b
-          model_repo: meta-llama/Llama-3.1-405B-Instruct
-          url: https://huggingface.co/meta-llama/Llama-3.1-405B-Instruct
-          precision: float16
-        - model: Llama 3.2 11B Vision
-          mad_tag: pyt_vllm_llama-3.2-11b-vision-instruct
-          model_repo: meta-llama/Llama-3.2-11B-Vision-Instruct
-          url: https://huggingface.co/meta-llama/Llama-3.2-11B-Vision-Instruct
-          precision: float16
-        - model: Llama 2 7B
-          mad_tag: pyt_vllm_llama-2-7b
-          model_repo: meta-llama/Llama-2-7b-chat-hf
-          url: https://huggingface.co/meta-llama/Llama-2-7b-chat-hf
-          precision: float16
-        - model: Llama 2 70B
-          mad_tag: pyt_vllm_llama-2-70b
-          model_repo: meta-llama/Llama-2-70b-chat-hf
-          url: https://huggingface.co/meta-llama/Llama-2-70b-chat-hf
-          precision: float16
-        - model: Llama 3.1 8B FP8
-          mad_tag: pyt_vllm_llama-3.1-8b_fp8
-          model_repo: amd/Llama-3.1-8B-Instruct-FP8-KV
-          url: https://huggingface.co/amd/Llama-3.1-8B-Instruct-FP8-KV
-          precision: float8
-        - model: Llama 3.1 70B FP8
-          mad_tag: pyt_vllm_llama-3.1-70b_fp8
-          model_repo: amd/Llama-3.1-70B-Instruct-FP8-KV
-          url: https://huggingface.co/amd/Llama-3.1-70B-Instruct-FP8-KV
-          precision: float8
-        - model: Llama 3.1 405B FP8
-          mad_tag: pyt_vllm_llama-3.1-405b_fp8
-          model_repo: amd/Llama-3.1-405B-Instruct-FP8-KV
-          url: https://huggingface.co/amd/Llama-3.1-405B-Instruct-FP8-KV
-          precision: float8
-    - group: Mistral AI
-      tag: mistral
-      models:
-        - model: Mixtral MoE 8x7B
-          mad_tag: pyt_vllm_mixtral-8x7b
-          model_repo: mistralai/Mixtral-8x7B-Instruct-v0.1
-          url: https://huggingface.co/mistralai/Mixtral-8x7B-Instruct-v0.1
-          precision: float16
-        - model: Mixtral MoE 8x22B
-          mad_tag: pyt_vllm_mixtral-8x22b
-          model_repo: mistralai/Mixtral-8x22B-Instruct-v0.1
-          url: https://huggingface.co/mistralai/Mixtral-8x22B-Instruct-v0.1
-          precision: float16
-        - model: Mistral 7B
-          mad_tag: pyt_vllm_mistral-7b
-          model_repo: mistralai/Mistral-7B-Instruct-v0.3
-          url: https://huggingface.co/mistralai/Mistral-7B-Instruct-v0.3
-          precision: float16
-        - model: Mixtral MoE 8x7B FP8
-          mad_tag: pyt_vllm_mixtral-8x7b_fp8
-          model_repo: amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-          url: https://huggingface.co/amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-          precision: float8
-        - model: Mixtral MoE 8x22B FP8
-          mad_tag: pyt_vllm_mixtral-8x22b_fp8
-          model_repo: amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-          url: https://huggingface.co/amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-          precision: float8
-        - model: Mistral 7B FP8
-          mad_tag: pyt_vllm_mistral-7b_fp8
-          model_repo: amd/Mistral-7B-v0.1-FP8-KV
-          url: https://huggingface.co/amd/Mistral-7B-v0.1-FP8-KV
-          precision: float8
-    - group: Qwen
-      tag: qwen
-      models:
-        - model: Qwen2 7B
-          mad_tag: pyt_vllm_qwen2-7b
-          model_repo: Qwen/Qwen2-7B-Instruct
-          url: https://huggingface.co/Qwen/Qwen2-7B-Instruct
-          precision: float16
-        - model: Qwen2 72B
-          mad_tag: pyt_vllm_qwen2-72b
-          model_repo: Qwen/Qwen2-72B-Instruct
-          url: https://huggingface.co/Qwen/Qwen2-72B-Instruct
-          precision: float16
-        - model: QwQ-32B
-          mad_tag: pyt_vllm_qwq-32b
-          model_repo: Qwen/QwQ-32B
-          url: https://huggingface.co/Qwen/QwQ-32B
-          precision: float16
-          tunableop: true
-    - group: Databricks DBRX
-      tag: dbrx
-      models:
-        - model: DBRX Instruct
-          mad_tag: pyt_vllm_dbrx-instruct
-          model_repo: databricks/dbrx-instruct
-          url: https://huggingface.co/databricks/dbrx-instruct
-          precision: float16
-        - model: DBRX Instruct FP8
-          mad_tag: pyt_vllm_dbrx_fp8
-          model_repo: amd/dbrx-instruct-FP8-KV
-          url: https://huggingface.co/amd/dbrx-instruct-FP8-KV
-          precision: float8
-    - group: Google Gemma
-      tag: gemma
-      models:
-        - model: Gemma 2 27B
-          mad_tag: pyt_vllm_gemma-2-27b
-          model_repo: google/gemma-2-27b
-          url: https://huggingface.co/google/gemma-2-27b
-          precision: float16
-    - group: Cohere
-      tag: cohere
-      models:
-        - model: C4AI Command R+ 08-2024
-          mad_tag: pyt_vllm_c4ai-command-r-plus-08-2024
-          model_repo: CohereForAI/c4ai-command-r-plus-08-2024
-          url: https://huggingface.co/CohereForAI/c4ai-command-r-plus-08-2024
-          precision: float16
-        - model: C4AI Command R+ 08-2024 FP8
-          mad_tag: pyt_vllm_command-r-plus_fp8
-          model_repo: amd/c4ai-command-r-plus-FP8-KV
-          url: https://huggingface.co/amd/c4ai-command-r-plus-FP8-KV
-          precision: float8
-    - group: DeepSeek
-      tag: deepseek
-      models:
-        - model: DeepSeek MoE 16B
-          mad_tag: pyt_vllm_deepseek-moe-16b-chat
-          model_repo: deepseek-ai/deepseek-moe-16b-chat
-          url: https://huggingface.co/deepseek-ai/deepseek-moe-16b-chat
-          precision: float16
-    - group: Microsoft Phi
-      tag: phi
-      models:
-        - model: Phi-4
-          mad_tag: pyt_vllm_phi-4
-          model_repo: microsoft/phi-4
-          url: https://huggingface.co/microsoft/phi-4
-    - group: TII Falcon
-      tag: falcon
-      models:
-        - model: Falcon 180B
-          mad_tag: pyt_vllm_falcon-180b
-          model_repo: tiiuae/falcon-180B
-          url: https://huggingface.co/tiiuae/falcon-180B
-          precision: float16
--- a/docs/data/how-to/rocm-for-ai/inference/pytorch-inference-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/pytorch-inference-benchmark-models.yaml
@@ -1,33 +0,0 @@
-pytorch_inference_benchmark:
-  unified_docker:
-    latest: &rocm-pytorch-docker-latest
-      pull_tag: rocm/pytorch:latest
-      docker_hub_url:
-      rocm_version:
-      pytorch_version:
-      hipblaslt_version:
-  model_groups:
-    - group: CLIP
-      tag: clip
-      models:
-      - model: CLIP
-        mad_tag: pyt_clip_inference
-        model_repo: laion/CLIP-ViT-B-32-laion2B-s34B-b79K
-        url: https://huggingface.co/laion/CLIP-ViT-B-32-laion2B-s34B-b79K
-        precision: float16
-    - group: Chai-1
-      tag: chai
-      models:
-      - model: Chai-1
-        mad_tag: pyt_chai1_inference
-        model_repo: meta-llama/Llama-3.1-8B-Instruct
-        url: https://huggingface.co/chaidiscovery/chai-1
-        precision: float16
-    - group: Mochi Video
-      tag: mochi
-      models:
-      - model: Mochi 1
-        mad_tag: pyt_mochi_video_inference
-        model_repo: genmo/mochi-1-preview
-        url: https://huggingface.co/genmo/mochi-1-preview
-        precision: float16
--- a/docs/data/how-to/rocm-for-ai/inference/vllm-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/inference/vllm-benchmark-models.yaml
@@ -1,162 +0,0 @@
-vllm_benchmark:
-  unified_docker:
-    latest:
-      pull_tag: rocm/vllm:rocm6.4.1_vllm_0.9.0.1_20250605
-      docker_hub_url: https://hub.docker.com/layers/rocm/vllm/rocm6.4.1_vllm_0.9.0.1_20250605/images/sha256-f48beeb3d72663a93c77211eb45273d564451447c097e060befa713d565fa36c
-      rocm_version: 6.4.1
-      vllm_version: 0.9.0.1 (0.9.0.2.dev108+g71faa1880.rocm641)
-      pytorch_version: 2.7.0+gitf717b2a
-      hipblaslt_version: 0.15
-  model_groups:
-    - group: Meta Llama
-      tag: llama
-      models:
-      - model: Llama 3.1 8B
-        mad_tag: pyt_vllm_llama-3.1-8b
-        model_repo: meta-llama/Llama-3.1-8B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-8B
-        precision: float16
-      - model: Llama 3.1 70B
-        mad_tag: pyt_vllm_llama-3.1-70b
-        model_repo: meta-llama/Llama-3.1-70B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-        precision: float16
-      - model: Llama 3.1 405B
-        mad_tag: pyt_vllm_llama-3.1-405b
-        model_repo: meta-llama/Llama-3.1-405B-Instruct
-        url: https://huggingface.co/meta-llama/Llama-3.1-405B-Instruct
-        precision: float16
-      - model: Llama 2 7B
-        mad_tag: pyt_vllm_llama-2-7b
-        model_repo: meta-llama/Llama-2-7b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-7b-chat-hf
-        precision: float16
-      - model: Llama 2 70B
-        mad_tag: pyt_vllm_llama-2-70b
-        model_repo: meta-llama/Llama-2-70b-chat-hf
-        url: https://huggingface.co/meta-llama/Llama-2-70b-chat-hf
-        precision: float16
-      - model: Llama 3.1 8B FP8
-        mad_tag: pyt_vllm_llama-3.1-8b_fp8
-        model_repo: amd/Llama-3.1-8B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-8B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 70B FP8
-        mad_tag: pyt_vllm_llama-3.1-70b_fp8
-        model_repo: amd/Llama-3.1-70B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-70B-Instruct-FP8-KV
-        precision: float8
-      - model: Llama 3.1 405B FP8
-        mad_tag: pyt_vllm_llama-3.1-405b_fp8
-        model_repo: amd/Llama-3.1-405B-Instruct-FP8-KV
-        url: https://huggingface.co/amd/Llama-3.1-405B-Instruct-FP8-KV
-        precision: float8
-    - group: Mistral AI
-      tag: mistral
-      models:
-      - model: Mixtral MoE 8x7B
-        mad_tag: pyt_vllm_mixtral-8x7b
-        model_repo: mistralai/Mixtral-8x7B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x7B-Instruct-v0.1
-        precision: float16
-      - model: Mixtral MoE 8x22B
-        mad_tag: pyt_vllm_mixtral-8x22b
-        model_repo: mistralai/Mixtral-8x22B-Instruct-v0.1
-        url: https://huggingface.co/mistralai/Mixtral-8x22B-Instruct-v0.1
-        precision: float16
-      - model: Mistral 7B
-        mad_tag: pyt_vllm_mistral-7b
-        model_repo: mistralai/Mistral-7B-Instruct-v0.3
-        url: https://huggingface.co/mistralai/Mistral-7B-Instruct-v0.3
-        precision: float16
-      - model: Mixtral MoE 8x7B FP8
-        mad_tag: pyt_vllm_mixtral-8x7b_fp8
-        model_repo: amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x7B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mixtral MoE 8x22B FP8
-        mad_tag: pyt_vllm_mixtral-8x22b_fp8
-        model_repo: amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mixtral-8x22B-Instruct-v0.1-FP8-KV
-        precision: float8
-      - model: Mistral 7B FP8
-        mad_tag: pyt_vllm_mistral-7b_fp8
-        model_repo: amd/Mistral-7B-v0.1-FP8-KV
-        url: https://huggingface.co/amd/Mistral-7B-v0.1-FP8-KV
-        precision: float8
-    - group: Qwen
-      tag: qwen
-      models:
-      - model: Qwen2 7B
-        mad_tag: pyt_vllm_qwen2-7b
-        model_repo: Qwen/Qwen2-7B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-7B-Instruct
-        precision: float16
-      - model: Qwen2 72B
-        mad_tag: pyt_vllm_qwen2-72b
-        model_repo: Qwen/Qwen2-72B-Instruct
-        url: https://huggingface.co/Qwen/Qwen2-72B-Instruct
-        precision: float16
-      - model: QwQ-32B
-        mad_tag: pyt_vllm_qwq-32b
-        model_repo: Qwen/QwQ-32B
-        url: https://huggingface.co/Qwen/QwQ-32B
-        precision: float16
-        tunableop: true
-    - group: Databricks DBRX
-      tag: dbrx
-      models:
-      - model: DBRX Instruct
-        mad_tag: pyt_vllm_dbrx-instruct
-        model_repo: databricks/dbrx-instruct
-        url: https://huggingface.co/databricks/dbrx-instruct
-        precision: float16
-      - model: DBRX Instruct FP8
-        mad_tag: pyt_vllm_dbrx_fp8
-        model_repo: amd/dbrx-instruct-FP8-KV
-        url: https://huggingface.co/amd/dbrx-instruct-FP8-KV
-        precision: float8
-    - group: Google Gemma
-      tag: gemma
-      models:
-      - model: Gemma 2 27B
-        mad_tag: pyt_vllm_gemma-2-27b
-        model_repo: google/gemma-2-27b
-        url: https://huggingface.co/google/gemma-2-27b
-        precision: float16
-    - group: Cohere
-      tag: cohere
-      models:
-      - model: C4AI Command R+ 08-2024
-        mad_tag: pyt_vllm_c4ai-command-r-plus-08-2024
-        model_repo: CohereForAI/c4ai-command-r-plus-08-2024
-        url: https://huggingface.co/CohereForAI/c4ai-command-r-plus-08-2024
-        precision: float16
-      - model: C4AI Command R+ 08-2024 FP8
-        mad_tag: pyt_vllm_command-r-plus_fp8
-        model_repo: amd/c4ai-command-r-plus-FP8-KV
-        url: https://huggingface.co/amd/c4ai-command-r-plus-FP8-KV
-        precision: float8
-    - group: DeepSeek
-      tag: deepseek
-      models:
-      - model: DeepSeek MoE 16B
-        mad_tag: pyt_vllm_deepseek-moe-16b-chat
-        model_repo: deepseek-ai/deepseek-moe-16b-chat
-        url: https://huggingface.co/deepseek-ai/deepseek-moe-16b-chat
-        precision: float16
-    - group: Microsoft Phi
-      tag: phi
-      models:
-      - model: Phi-4
-        mad_tag: pyt_vllm_phi-4
-        model_repo: microsoft/phi-4
-        url: https://huggingface.co/microsoft/phi-4
-    - group: TII Falcon
-      tag: falcon
-      models:
-      - model: Falcon 180B
-        mad_tag: pyt_vllm_falcon-180b
-        model_repo: tiiuae/falcon-180B
-        url: https://huggingface.co/tiiuae/falcon-180B
-        precision: float16
--- a/docs/data/how-to/rocm-for-ai/llama2-7b-training-log-sample.png
+++ b/docs/data/how-to/rocm-for-ai/llama2-7b-training-log-sample.png
--- a/docs/data/how-to/rocm-for-ai/prep-training-datasets-my-gpt2-text-document.png
+++ b/docs/data/how-to/rocm-for-ai/prep-training-datasets-my-gpt2-text-document.png
--- a/docs/data/how-to/rocm-for-ai/rccl-tests-1-mpi-process-per-gpu.png
+++ b/docs/data/how-to/rocm-for-ai/rccl-tests-1-mpi-process-per-gpu.png
--- a/docs/data/how-to/rocm-for-ai/rccl-tests-4-mi300x-gpu-nodes.png
+++ b/docs/data/how-to/rocm-for-ai/rccl-tests-4-mi300x-gpu-nodes.png
--- a/docs/data/how-to/rocm-for-ai/rccl-tests-8-gpu.png
+++ b/docs/data/how-to/rocm-for-ai/rccl-tests-8-gpu.png
--- a/docs/data/how-to/rocm-for-ai/training/megatron-lm-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/training/megatron-lm-benchmark-models.yaml
@@ -1,29 +0,0 @@
-megatron-lm_benchmark:
-  model_groups:
-    - group: Meta Llama
-      tag: llama
-      models:
-      - model: Llama 3.3 70B
-        mad_tag: pyt_megatron_lm_train_llama-3.3-70b
-      - model: Llama 3.1 8B
-        mad_tag: pyt_megatron_lm_train_llama-3.1-8b
-      - model: Llama 3.1 70B
-        mad_tag: pyt_megatron_lm_train_llama-3.1-70b
-      - model: Llama 2 7B
-        mad_tag: pyt_megatron_lm_train_llama-2-7b
-      - model: Llama 2 70B
-        mad_tag: pyt_megatron_lm_train_llama-2-70b
-    - group: DeepSeek
-      tag: deepseek
-      models:
-      - model: DeepSeek-V3
-        mad_tag: pyt_megatron_lm_train_deepseek-v3-proxy
-      - model: DeepSeek-V2-Lite
-        mad_tag: pyt_megatron_lm_train_deepseek-v2-lite-16b
-    - group: Mistral AI
-      tag: mistral
-      models:
-      - model: Mixtral 8x7B
-        mad_tag: pyt_megatron_lm_train_mixtral-8x7b
-      - model: Mixtral 8x22B
-        mad_tag: pyt_megatron_lm_train_mixtral-8x22b-proxy
--- a/docs/data/how-to/rocm-for-ai/training/pytorch-training-benchmark-models.yaml
+++ b/docs/data/how-to/rocm-for-ai/training/pytorch-training-benchmark-models.yaml
@@ -1,120 +0,0 @@
-unified_docker:
-  latest:
-    pull_tag: rocm/pytorch-training:v25.6
-    docker_hub_url: https://hub.docker.com/r/rocm/pytorch-training/tags
-    rocm_version: 6.4.1
-    pytorch_version: 2.8.0a0+git7d205b2
-    python_version: 3.10.17
-    transformer_engine_version: 1.14.0+2f85f5f2
-    flash_attention_version: 3.0.0.post1
-    hipblaslt_version: 0.15.0-8c6919d
-    triton_version: 3.3.0
-model_groups:
-  - group: Pre-training
-    tag: pre-training
-    models:
-    - model: Llama 3.1 8B
-      mad_tag: pyt_train_llama-3.1-8b
-      model_repo: Llama-3.1-8B
-      url: https://huggingface.co/meta-llama/Llama-3.1-8B
-      precision: BF16
-      training_modes: [pretrain]
-    - model: Llama 3.1 70B
-      mad_tag: pyt_train_llama-3.1-70b
-      model_repo: Llama-3.1-70B
-      url: https://huggingface.co/meta-llama/Llama-3.1-70B-Instruct
-      precision: BF16
-      training_modes: [pretrain]
-    - model: FLUX.1-dev
-      mad_tag: pyt_train_flux
-      model_repo: Flux
-      url: https://huggingface.co/black-forest-labs/FLUX.1-dev
-      precision: BF16
-      training_modes: [pretrain]
-  - group: Fine-tuning
-    tag: fine-tuning
-    models:
-    - model: Llama 4 Scout 17B-16E
-      mad_tag: pyt_train_llama-4-scout-17b-16e
-      model_repo: Llama-4-17B_16E
-      url: https://huggingface.co/meta-llama/Llama-4-Scout-17B-16E
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 3.3 70B
-      mad_tag: pyt_train_llama-3.3-70b
-      model_repo: Llama-3.3-70B
-      url: https://huggingface.co/meta-llama/Llama-3.3-70B-Instruct
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora, finetune_qlora]
-    - model: Llama 3.2 1B
-      mad_tag: pyt_train_llama-3.2-1b
-      model_repo: Llama-3.2-1B
-      url: https://huggingface.co/meta-llama/Llama-3.2-1B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 3.2 3B
-      mad_tag: pyt_train_llama-3.2-3b
-      model_repo: Llama-3.2-3B
-      url: https://huggingface.co/meta-llama/Llama-3.2-3B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 3.2 Vision 11B
-      mad_tag: pyt_train_llama-3.2-vision-11b
-      model_repo: Llama-3.2-Vision-11B
-      url: https://huggingface.co/meta-llama/Llama-3.2-11B-Vision
-      precision: BF16
-      training_modes: [finetune_fw]
-    - model: Llama 3.2 Vision 90B
-      mad_tag: pyt_train_llama-3.2-vision-90b
-      model_repo: Llama-3.2-Vision-90B
-      url: https://huggingface.co/meta-llama/Llama-3.2-90B-Vision
-      precision: BF16
-      training_modes: [finetune_fw]
-    - model: Llama 3.1 8B
-      mad_tag: pyt_train_llama-3.1-8b
-      model_repo: Llama-3.1-8B
-      url: https://huggingface.co/meta-llama/Llama-3.1-8B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 3.1 70B
-      mad_tag: pyt_train_llama-3.1-70b
-      model_repo: Llama-3.1-70B
-      url: https://huggingface.co/meta-llama/Llama-3.1-70B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora, finetune_qlora]
-    - model: Llama 3.1 405B
-      mad_tag: pyt_train_llama-3.1-405b
-      model_repo: Llama-3.1-405B
-      url: https://huggingface.co/meta-llama/Llama-3.1-405B
-      precision: BF16
-      training_modes: [finetune_qlora, HF_finetune_lora]
-    - model: Llama 3 8B
-      mad_tag: pyt_train_llama-3-8b
-      model_repo: Llama-3-8B
-      url: https://huggingface.co/meta-llama/Meta-Llama-3-8B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 3 70B
-      mad_tag: pyt_train_llama-3-70b
-      model_repo: Llama-3-70B
-      url: https://huggingface.co/meta-llama/Meta-Llama-3-70B
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 2 7B
-      mad_tag: pyt_train_llama-2-7b
-      model_repo: Llama-2-7B
-      url: https://github.com/meta-llama/llama-models/tree/main/models/llama2
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora, finetune_qlora]
-    - model: Llama 2 13B
-      mad_tag: pyt_train_llama-2-13b
-      model_repo: Llama-2-13B
-      url: https://github.com/meta-llama/llama-models/tree/main/models/llama2
-      precision: BF16
-      training_modes: [finetune_fw, finetune_lora]
-    - model: Llama 2 70B
-      mad_tag: pyt_train_llama-2-70b
-      model_repo: Llama-2-70B
-      url: https://github.com/meta-llama/llama-models/tree/main/models/llama2
-      precision: BF16
-      training_modes: [finetune_lora, finetune_qlora, HF_finetune_lora]
--- a/docs/data/how-to/rocm-for-hpc/hpc-stack-2024_6_20.png
+++ b/docs/data/how-to/rocm-for-hpc/hpc-stack-2024_6_20.png
--- a/docs/data/how-to/tuning-guides/hipblaslt_auto_tuning_output_files.png
+++ b/docs/data/how-to/tuning-guides/hipblaslt_auto_tuning_output_files.png
--- a/docs/data/how-to/tuning-guides/hipblaslt_yaml_template.png
+++ b/docs/data/how-to/tuning-guides/hipblaslt_yaml_template.png
--- a/docs/data/how-to/tuning-guides/mi300a-rocm-bandwidth-test-output.png
+++ b/docs/data/how-to/tuning-guides/mi300a-rocm-bandwidth-test-output.png
--- a/docs/data/how-to/tuning-guides/mi300a-rocm-peak-bandwidth-output.png
+++ b/docs/data/how-to/tuning-guides/mi300a-rocm-peak-bandwidth-output.png
--- a/docs/data/how-to/tuning-guides/mi300a-rocm-smi-output.png
+++ b/docs/data/how-to/tuning-guides/mi300a-rocm-smi-output.png
--- a/docs/data/how-to/tuning-guides/mi300a-rocm-smi-showhw-output.png
+++ b/docs/data/how-to/tuning-guides/mi300a-rocm-smi-showhw-output.png
--- a/docs/data/how-to/tuning-guides/mi300a-rocm-smi-showtopo-output.png
+++ b/docs/data/how-to/tuning-guides/mi300a-rocm-smi-showtopo-output.png
--- a/docs/data/how-to/tuning-guides/perfetto-trace.svg
+++ b/docs/data/how-to/tuning-guides/perfetto-trace.svg
--- a/docs/data/how-to/tuning-guides/profiling-perfetto-ui.png
+++ b/docs/data/how-to/tuning-guides/profiling-perfetto-ui.png
--- a/docs/data/how-to/tuning-guides/rbt-bidirectional-bandwidth.png
+++ b/docs/data/how-to/tuning-guides/rbt-bidirectional-bandwidth.png
--- a/docs/data/how-to/tuning-guides/rbt-inter-device-access.png
+++ b/docs/data/how-to/tuning-guides/rbt-inter-device-access.png
--- a/docs/data/how-to/tuning-guides/rbt-inter-device-numa-distance.png
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--- a/docs/data/how-to/tuning-guides/rbt-unidirectional-bandwidth.png
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--- a/docs/data/how-to/tuning-guides/rocm-smi-showhw.png
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Author	SHA1	Message	Date
Peter Park	c9f487fd07	[docs/7.0-alpha] Add pointers to latest documentation (#5384 ) * add beta to version history * Update preview versions list * add pointers to latest docs	2025-09-18 12:21:22 -04:00
Peter Park	d504e8fe48	[docs/7.0-alpha] Update preview versions list (#5171 )	2025-08-08 10:11:30 -04:00
Peter Park	77479d3a6f	add beta to version history	2025-07-24 17:42:51 -04:00
Peter Park	5f9ad0a8f6	[docs/7.0-alpha] Add vLLM inference benchmark doc + some fixes (#5093 ) * Add vLLM doc + minor fixes * fix typo in docker pull tag "X" -> "x" * add docker hub links	2025-07-23 14:53:05 -04:00
Peter Park	ec32659e4c	fix sglang typo (#5036 )	2025-07-11 18:46:50 -04:00
Peter Park	6f12c1c0df	update wordlist and index	2025-07-11 18:35:26 -04:00
Peter Park	8d33b3add1	add sglang inference docker page	2025-07-11 18:35:26 -04:00
Peter Park	9ea7a4a430	Add Alpha 2 to versions list (#5032 )	2025-07-10 16:53:59 -04:00
Peter Park	f10305cd30	Fix repo.radeon.com link in alpha release notes (#5024 ) * fix repo.radeon.com link in alpha release notes * add "6.4.1"	2025-07-09 20:09:08 -04:00
Peter Park	6e8db283f0	Remove unused files and minor fixes in 7.0 alpha doc (#5023 ) * add preview versions list * fix typo * clarify hip compatibility note * megatron bf16 cmd opts * fix versions list url * add missing backslack	2025-07-09 17:38:27 -04:00
Peter Park	f445c554ec	Merge pull request #4999 from peterjunpark/docs/7.0-alpha Add docs for Alpha training Dockers	2025-07-02 21:18:44 -04:00
Peter Park	2c60d2f776	remove extra xref in training.rst	2025-07-02 19:32:35 -04:00
Peter Park	f62339a857	update .wordlist.txt	2025-07-02 19:30:44 -04:00
Peter Park	dc5cac0fbf	add alpha training docker docs	2025-07-02 19:28:26 -04:00