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tmp assigned rd0 instead of LR

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srichmo1
2023-09-05 10:03:20 -04:00
committed by ghidorahrex
parent be7458a436
commit 24b2275c0b
1 changed files with 1 additions and 1 deletions
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Ghidra/Processors/Atmel/data/languages/avr32a_instruction_flow.sinc
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@@ -154,7 +154,7 @@ RJMPdisp: disp is disp4_8 & sdisp0_2
# 0101 1101 0001 dddd
:ICALL rd0 is op4_12=0x5d1 & rd0 {
tmp:4 = LR;
tmp:4 = rd0;
LR = inst_next;
call [tmp];
}