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https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-01-09 05:58:00 -05:00
GP-6007: Added additional floating point config instructions
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ghidorahrex
@@ -6,6 +6,7 @@ define space ram type=ram_space size=4 wordsize=1 default;
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define space register type=register_space size=4;
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define space csreg type=ram_space size=2 wordsize=4;
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@define CSR_REG_START "0x0000"
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define register offset=0 size=4
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@@ -21,7 +22,9 @@ define register offset=0x100 size=4
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[d0.hi d0.lo d1.hi d1.lo];
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define register offset=0x200 size=4
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[ itb lb lc le ifc_lp];
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[ itb lb lc le ifc_lp
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fpcsr fpcfg
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];
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define register offset=0x1000 size=4
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[ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7
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@@ -37,109 +40,9 @@ define register offset=0x1000 size=8
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fd24 fd25 fd26 fd27 fd28 fd29 fd30 fd31
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];
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#define SRIDX(major, minor, ext) \
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# (((major) << 7) | ((minor) << 3) | (ext))
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define csreg offset=$(CSR_REG_START) size=4
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define csreg offset=0x0a9 size=4
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[
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cpu_ver core_id _ _ _ _ _ _ # SRIDX(0,0,n)
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icm_cfg _ _ _ _ _ _ _ # SRIDX(0,1,n)
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dcm_cfg _ _ _ _ _ _ _
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mmu_cfg _ _ _ _ _ _ _
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msc_cfg msc_cfg2 _ _ _ _ _ _
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fucop_exist _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(0,7,n)
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(0,15,n)
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psw ipsw p_ipsw _ _ _ _ _ # SRIDX(1,0,n)
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_ ivb int_ctrl int_gpr_push_dis _ _ _ _
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_ eva p_eva _ _ _ _ _
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_ itype p_itype _ _ _ _ _
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_ merr _ _ _ _ _ _
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_ ipc p_ipc oipc _ _ _ _
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_ _ p_p0 _ _ _ _ _
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_ _ p_p1 _ _ _ _ _ # SRIDX(1,7,n)
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int_mask int_mask2 int_mask3 _ _ _ _ _
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int_pend int_pend2 int_pend3 _ int_trigger int_trigger2 _ _
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sp_usr sp_priv sp_usr1 sp_priv1 sp_usr2 sp_priv2 sp_usr3 sp_priv3
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int_pri int_pri2 int_pri3 int_pri4 _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(1,15,n)
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mmu_ctl bg_region _ _ _ _ _ _ # SRIDX(2,0,n)
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l1_pptb _ _ _ _ _ _ _
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tlb_vpn _ _ _ _ _ _ _
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tlb_data _ _ _ _ _ _ _
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tlb_misc _ _ _ _ _ _ _
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vlpt_idx _ _ _ _ _ _ _
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ilmb _ _ _ _ _ _ _
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dlmb _ _ _ _ _ _ _ # SRIDX(2,7,n)
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cache_ctl _ _ _ _ _ _ _
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hsmp_saddr hsmp_eaddr _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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sdz_ctl misc_ctl ecc_misc _ _ _ _ _ # SRIDX(2,15,n)
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bpc0 bpc1 bpc2 bpc3 bpc4 bpc5 bpc6 bpc7 # SRIDX(3,0,n)
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bpa0 bpa1 bpa2 bpa3 bpa4 bpa5 bpa6 bpa7
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bpam0 bpam1 bpam2 bpam3 bpam4 bpam5 bpam6 bpam7
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bpv0 bpv1 bpv2 bpv3 bpv4 bpv5 bpv6 bpv7
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bpcid0 bpcid1 bpcid2 bpcid3 bpcid4 bpcid5 bpcid6 bpcid7
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edm_cfg _ _ _ _ _ _ _
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edmsw _ _ _ _ _ _ _
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edm_ctl _ _ _ _ _ _ _ # SRIDX(3,7,n)
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edm_dtr _ _ _ _ _ _ _
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bpmtc _ _ _ _ _ _ _
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dimbr _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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tecr0 tecr1 _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(3,15,n)
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pfmc0 pfmc1 pfmc2 _ _ _ _ _ # SRIDX(4,0,n)
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pfm_ctl _ _ _ _ _ _ _
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pft_ctl _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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prusr_acc_ctl _ _ _ _ _ _ _
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fucpr _ _ _ _ _ _ _
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hsp_ctl sp_bound sp_bound_priv sp_base sp_base_priv _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(4,7,n)
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(4,15,n)
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dma_cfg _ _ _ _ _ _ _ # SRIDX(5,0,n)
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dma_gcsw _ _ _ _ _ _ _
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dma_chnsel _ _ _ _ _ _ _
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dma_act _ _ _ _ _ _ _
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dma_setup _ _ _ _ _ _ _
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dma_isaddr _ _ _ _ _ _ _
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dma_esaddr _ _ _ _ _ _ _
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dma_tcnt dma_rcnt _ _ _ _ _ _ # SRIDX(5,7,n)
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dma_status dma_hstatus _ _ _ _ _ _
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dma_2dset dma_2dsctl _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _
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_ _ _ _ _ _ _ _ # SRIDX(5,15,n)
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secur0 _ _ _ _ _ _ _ # SRIDX(6,0,n)
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secur1 secur2 secur3 _ _ _ _ _
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ipc
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];
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define register offset=0x300 size=8 contextreg;
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@@ -396,25 +299,25 @@ UsrName: ifc_lp is Group=0 & Usr=29 & ifc_lp { export ifc_lp; }
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#UsrName: pc is Group=0 & Usr=31 & pc { export pc; } # handled separately
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# Group 1
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UsrName: dma_cfg is Group=1 & Usr=0 & dma_cfg { export dma_cfg; }
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UsrName: dma_gcsw is Group=1 & Usr=1 & dma_gcsw { export dma_gcsw; }
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UsrName: dma_chnsel is Group=1 & Usr=2 & dma_chnsel { export dma_chnsel; }
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UsrName: dma_act is Group=1 & Usr=3 & dma_act { export dma_act; }
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UsrName: dma_setup is Group=1 & Usr=4 & dma_setup { export dma_setup; }
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UsrName: dma_isaddr is Group=1 & Usr=5 & dma_isaddr { export dma_isaddr; }
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UsrName: dma_esaddr is Group=1 & Usr=6 & dma_esaddr { export dma_esaddr; }
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UsrName: dma_tcnt is Group=1 & Usr=7 & dma_tcnt { export dma_tcnt; }
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UsrName: dma_status is Group=1 & Usr=8 & dma_status { export dma_status; }
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UsrName: dma_2dset is Group=1 & Usr=9 & dma_2dset { export dma_2dset; }
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UsrName: dma_rcnt is Group=1 & Usr=23 & dma_rcnt { export dma_rcnt; }
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UsrName: dma_hstatus is Group=1 & Usr=24 & dma_hstatus { export dma_hstatus; }
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UsrName: dma_2dsctl is Group=1 & Usr=25 & dma_2dsctl { export dma_2dsctl; }
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UsrName: "dma_cfg" is Group=1 & Usr=0 { tmp:2 = 0x280; export *[csreg]:4 tmp; }
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UsrName: "dma_gcsw" is Group=1 & Usr=1 { tmp:2 = 0x288; export *[csreg]:4 tmp; }
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UsrName: "dma_chnsel" is Group=1 & Usr=2 { tmp:2 = 0x290; export *[csreg]:4 tmp; }
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UsrName: "dma_act" is Group=1 & Usr=3 { tmp:2 = 0x298; export *[csreg]:4 tmp; }
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UsrName: "dma_setup" is Group=1 & Usr=4 { tmp:2 = 0x2a0; export *[csreg]:4 tmp; }
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UsrName: "dma_isaddr" is Group=1 & Usr=5 { tmp:2 = 0x2a8; export *[csreg]:4 tmp; }
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UsrName: "dma_esaddr" is Group=1 & Usr=6 { tmp:2 = 0x2b0; export *[csreg]:4 tmp; }
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UsrName: "dma_tcnt" is Group=1 & Usr=7 { tmp:2 = 0x2b8; export *[csreg]:4 tmp; }
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UsrName: "dma_status" is Group=1 & Usr=8 { tmp:2 = 0x2c0; export *[csreg]:4 tmp; }
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UsrName: "dma_2dset" is Group=1 & Usr=9 { tmp:2 = 0x2c8; export *[csreg]:4 tmp; }
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UsrName: "dma_rcnt" is Group=1 & Usr=23 { tmp:2 = 0x2b9; export *[csreg]:4 tmp; }
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UsrName: "dma_hstatus" is Group=1 & Usr=24 { tmp:2 = 0x2c1; export *[csreg]:4 tmp; }
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UsrName: "dma_2dsctl" is Group=1 & Usr=25 { tmp:2 = 0x2c9; export *[csreg]:4 tmp; }
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# Group 2
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UsrName: pfmc0 is Group=2 & Usr=0 & pfmc0 { export pfmc0; }
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UsrName: pfmc1 is Group=2 & Usr=1 & pfmc1 { export pfmc1; }
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UsrName: pfmc2 is Group=2 & Usr=2 & pfmc2 { export pfmc2; }
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UsrName: pfm_ctl is Group=2 & Usr=4 & pfm_ctl { export pfm_ctl; }
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UsrName: "pfmc0" is Group=2 & Usr=0 { tmp:2 = 0x200; export *[csreg]:4 tmp; }
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UsrName: "pfmc1" is Group=2 & Usr=1 { tmp:2 = 0x201; export *[csreg]:4 tmp; }
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UsrName: "pfmc2" is Group=2 & Usr=2 { tmp:2 = 0x202; export *[csreg]:4 tmp; }
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UsrName: "pfm_ctl" is Group=2 & Usr=4 { tmp:2 = 0x208; export *[csreg]:4 tmp; }
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:mfusr Rt, UsrName is $(I32) & $(ALU_2) & Rt & UsrName & $(ALU2Z) & Sub6=0b100000 { UsrName = Rt; }
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@@ -1609,14 +1512,14 @@ define pcodeop fmfdr;
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}
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# FPU_MTCP
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define pcodeop ftmsr;
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:ftmsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x9 {
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Fsa = ftmsr(Rt);
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define pcodeop fmtsr;
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:fmtsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x9 {
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Fsa = fmtsr(Rt);
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}
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define pcodeop ftmdr;
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:ftmdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x9 {
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Fda = ftmdr(Rt);
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define pcodeop fmtdr;
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:fmtdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x9 {
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Fda = fmtdr(Rt);
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}
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# FPU_FLS
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@@ -1708,3 +1611,15 @@ OffImm12s: (offs) is Imm12s [ offs = Imm12s << 2; ] { export *[const]:4 offs; }
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Ra = Ra + OffImm12s;
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}
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:fmfcfg Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x0 & cop4=0x1 {
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Rt = fpcfg;
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}
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:fmfcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x1 & cop4=0x1 {
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Rt = fpcsr;
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}
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:fmtcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & Fsa & f2op=0x1 & cop4=0x9 {
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fpcsr = Rt;
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}
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