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[NDS32] Add support for the NDS32 Processor

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This commit is contained in:
Timothée COCAULT
2020-04-16 18:58:10 +02:00
committed by ghidorahrex
parent 9499199f83
commit fa7c3b1fec
20 changed files with 2375 additions and 0 deletions
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0
Ghidra/Processors/NDS32/Module.manifest Normal file
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15
Ghidra/Processors/NDS32/build.gradle Normal file
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apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
apply plugin: 'eclipse'
eclipse.project.name = 'Processors NDS32'
dependencies {
compile project(':Base')
// Temporary dependency so that pcodeTests can use the Decompiler switch recovery
compile project(':Decompiler')
}

50
Ghidra/Processors/NDS32/data/buildLanguage.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
+ Compile sleigh languages within this module.
+ Sleigh compiler options are read from the sleighArgs.txt file.
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
-->
<project name="privateBuildDeveloper" default="sleighCompile">
<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
<import file="../.antProperties.xml" optional="false" />
<target name="sleighCompile">
<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>
<path id="sleigh.class.path">
<fileset dir="${framework.path}/SoftwareModeling/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Generic/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Utility/lib">
<include name="*.jar"/>
</fileset>
</path>
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
<fail unless="sleigh.compile.exists" />
<java classname="${sleigh.compile.class}"
classpathref="sleigh.class.path"
fork="true"
failonerror="true">
<jvmarg value="-Xmx2048M"/>
<arg value="-i"/>
<arg value="sleighArgs.txt"/>
<arg value="-a"/>
<arg value="./languages"/>
</java>
</target>
</project>

576
Ghidra/Processors/NDS32/data/languages/lsmw.sinc Normal file
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macro Lmwbi(reg) {
reg = *mult_addr;
mult_addr = mult_addr + 4;
}
macro Lmwbd(reg) {
reg = *mult_addr;
mult_addr = mult_addr - 4;
}
macro Lmwai(reg) {
mult_addr = mult_addr + 4;
reg = *mult_addr;
}
macro Lmwad(reg) {
mult_addr = mult_addr - 4;
reg = *mult_addr;
}
macro Smwbi(reg) {
*mult_addr = reg;
mult_addr = mult_addr + 4;
}
macro Smwbd(reg) {
*mult_addr = reg;
mult_addr = mult_addr - 4;
}
macro Smwai(reg) {
mult_addr = mult_addr + 4;
*mult_addr = reg;
}
macro Smwad(reg) {
mult_addr = mult_addr - 4;
*mult_addr = reg;
}
Lmwbi.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwbi(a0); }
Lmwbi.a0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwbi(a1); }
Lmwbi.a1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwbi(a2); }
Lmwbi.a2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwbi(a3); }
Lmwbi.a3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwbi(a4); }
Lmwbi.a4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwbi(a5); }
Lmwbi.a5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwbi(s0); }
Lmwbi.s0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwbi(s1); }
Lmwbi.s1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwbi(s2); }
Lmwbi.s2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwbi(s3); }
Lmwbi.s3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwbi(s4); }
Lmwbi.s4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwbi(s5); }
Lmwbi.s5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwbi(s6); }
Lmwbi.s6: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwbi(s7); }
Lmwbi.s7: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwbi(s8); }
Lmwbi.s8: is LsmwRb_ & LsmwRe_ { }
Lmwbi.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwbi(ta); }
Lmwbi.ta: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwbi(t0); }
Lmwbi.t0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwbi(t1); }
Lmwbi.t1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwbi(t2); }
Lmwbi.t2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwbi(t3); }
Lmwbi.t3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwbi(t4); }
Lmwbi.t4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwbi(t5); }
Lmwbi.t5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwbi(t6); }
Lmwbi.t6: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwbi(t7); }
Lmwbi.t7: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwbi(t8); }
Lmwbi.t8: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwbi(t9); }
Lmwbi.t9: is LsmwRb_ & LsmwRe_ { }
Lmwbi.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwbi(p0); }
Lmwbi.p0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwbi(p1); }
Lmwbi.p1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.fp: fp is Enable4_fp=1 & fp { Lmwbi(fp); }
Lmwbi.fp: is Enable4_fp=0 { }
Lmwbi.gp: gp is Enable4_gp=1 & gp { Lmwbi(gp); }
Lmwbi.gp: is Enable4_gp=0 { }
Lmwbi.lp: lp is Enable4_lp=1 & lp { Lmwbi(lp); }
Lmwbi.lp: is Enable4_lp=0 { }
Lmwbi.sp: sp is Enable4_sp=1 & sp { Lmwbi(sp); }
Lmwbi.sp: is Enable4_sp=0 { }
Lmwbd.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwbd(a0); }
Lmwbd.a0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwbd(a1); }
Lmwbd.a1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwbd(a2); }
Lmwbd.a2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwbd(a3); }
Lmwbd.a3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwbd(a4); }
Lmwbd.a4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwbd(a5); }
Lmwbd.a5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwbd(s0); }
Lmwbd.s0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwbd(s1); }
Lmwbd.s1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwbd(s2); }
Lmwbd.s2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwbd(s3); }
Lmwbd.s3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwbd(s4); }
Lmwbd.s4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwbd(s5); }
Lmwbd.s5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwbd(s6); }
Lmwbd.s6: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwbd(s7); }
Lmwbd.s7: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwbd(s8); }
Lmwbd.s8: is LsmwRb_ & LsmwRe_ { }
Lmwbd.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwbd(ta); }
Lmwbd.ta: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwbd(t0); }
Lmwbd.t0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwbd(t1); }
Lmwbd.t1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwbd(t2); }
Lmwbd.t2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwbd(t3); }
Lmwbd.t3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwbd(t4); }
Lmwbd.t4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwbd(t5); }
Lmwbd.t5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwbd(t6); }
Lmwbd.t6: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwbd(t7); }
Lmwbd.t7: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwbd(t8); }
Lmwbd.t8: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwbd(t9); }
Lmwbd.t9: is LsmwRb_ & LsmwRe_ { }
Lmwbd.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwbd(p0); }
Lmwbd.p0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwbd(p1); }
Lmwbd.p1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.fp: fp is Enable4_fp=1 & fp { Lmwbd(fp); }
Lmwbd.fp: is Enable4_fp=0 { }
Lmwbd.gp: gp is Enable4_gp=1 & gp { Lmwbd(gp); }
Lmwbd.gp: is Enable4_gp=0 { }
Lmwbd.lp: lp is Enable4_lp=1 & lp { Lmwbd(lp); }
Lmwbd.lp: is Enable4_lp=0 { }
Lmwbd.sp: sp is Enable4_sp=1 & sp { Lmwbd(sp); }
Lmwbd.sp: is Enable4_sp=0 { }
Lmwai.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwai(a0); }
Lmwai.a0: is LsmwRb_ & LsmwRe_ { }
Lmwai.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwai(a1); }
Lmwai.a1: is LsmwRb_ & LsmwRe_ { }
Lmwai.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwai(a2); }
Lmwai.a2: is LsmwRb_ & LsmwRe_ { }
Lmwai.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwai(a3); }
Lmwai.a3: is LsmwRb_ & LsmwRe_ { }
Lmwai.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwai(a4); }
Lmwai.a4: is LsmwRb_ & LsmwRe_ { }
Lmwai.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwai(a5); }
Lmwai.a5: is LsmwRb_ & LsmwRe_ { }
Lmwai.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwai(s0); }
Lmwai.s0: is LsmwRb_ & LsmwRe_ { }
Lmwai.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwai(s1); }
Lmwai.s1: is LsmwRb_ & LsmwRe_ { }
Lmwai.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwai(s2); }
Lmwai.s2: is LsmwRb_ & LsmwRe_ { }
Lmwai.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwai(s3); }
Lmwai.s3: is LsmwRb_ & LsmwRe_ { }
Lmwai.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwai(s4); }
Lmwai.s4: is LsmwRb_ & LsmwRe_ { }
Lmwai.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwai(s5); }
Lmwai.s5: is LsmwRb_ & LsmwRe_ { }
Lmwai.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwai(s6); }
Lmwai.s6: is LsmwRb_ & LsmwRe_ { }
Lmwai.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwai(s7); }
Lmwai.s7: is LsmwRb_ & LsmwRe_ { }
Lmwai.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwai(s8); }
Lmwai.s8: is LsmwRb_ & LsmwRe_ { }
Lmwai.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwai(ta); }
Lmwai.ta: is LsmwRb_ & LsmwRe_ { }
Lmwai.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwai(t0); }
Lmwai.t0: is LsmwRb_ & LsmwRe_ { }
Lmwai.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwai(t1); }
Lmwai.t1: is LsmwRb_ & LsmwRe_ { }
Lmwai.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwai(t2); }
Lmwai.t2: is LsmwRb_ & LsmwRe_ { }
Lmwai.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwai(t3); }
Lmwai.t3: is LsmwRb_ & LsmwRe_ { }
Lmwai.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwai(t4); }
Lmwai.t4: is LsmwRb_ & LsmwRe_ { }
Lmwai.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwai(t5); }
Lmwai.t5: is LsmwRb_ & LsmwRe_ { }
Lmwai.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwai(t6); }
Lmwai.t6: is LsmwRb_ & LsmwRe_ { }
Lmwai.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwai(t7); }
Lmwai.t7: is LsmwRb_ & LsmwRe_ { }
Lmwai.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwai(t8); }
Lmwai.t8: is LsmwRb_ & LsmwRe_ { }
Lmwai.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwai(t9); }
Lmwai.t9: is LsmwRb_ & LsmwRe_ { }
Lmwai.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwai(p0); }
Lmwai.p0: is LsmwRb_ & LsmwRe_ { }
Lmwai.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwai(p1); }
Lmwai.p1: is LsmwRb_ & LsmwRe_ { }
Lmwai.fp: fp is Enable4_fp=1 & fp { Lmwai(fp); }
Lmwai.fp: is Enable4_fp=0 { }
Lmwai.gp: gp is Enable4_gp=1 & gp { Lmwai(gp); }
Lmwai.gp: is Enable4_gp=0 { }
Lmwai.lp: lp is Enable4_lp=1 & lp { Lmwai(lp); }
Lmwai.lp: is Enable4_lp=0 { }
Lmwai.sp: sp is Enable4_sp=1 & sp { Lmwai(sp); }
Lmwai.sp: is Enable4_sp=0 { }
Lmwad.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwad(a0); }
Lmwad.a0: is LsmwRb_ & LsmwRe_ { }
Lmwad.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwad(a1); }
Lmwad.a1: is LsmwRb_ & LsmwRe_ { }
Lmwad.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwad(a2); }
Lmwad.a2: is LsmwRb_ & LsmwRe_ { }
Lmwad.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwad(a3); }
Lmwad.a3: is LsmwRb_ & LsmwRe_ { }
Lmwad.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwad(a4); }
Lmwad.a4: is LsmwRb_ & LsmwRe_ { }
Lmwad.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwad(a5); }
Lmwad.a5: is LsmwRb_ & LsmwRe_ { }
Lmwad.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwad(s0); }
Lmwad.s0: is LsmwRb_ & LsmwRe_ { }
Lmwad.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwad(s1); }
Lmwad.s1: is LsmwRb_ & LsmwRe_ { }
Lmwad.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwad(s2); }
Lmwad.s2: is LsmwRb_ & LsmwRe_ { }
Lmwad.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwad(s3); }
Lmwad.s3: is LsmwRb_ & LsmwRe_ { }
Lmwad.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwad(s4); }
Lmwad.s4: is LsmwRb_ & LsmwRe_ { }
Lmwad.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwad(s5); }
Lmwad.s5: is LsmwRb_ & LsmwRe_ { }
Lmwad.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwad(s6); }
Lmwad.s6: is LsmwRb_ & LsmwRe_ { }
Lmwad.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwad(s7); }
Lmwad.s7: is LsmwRb_ & LsmwRe_ { }
Lmwad.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwad(s8); }
Lmwad.s8: is LsmwRb_ & LsmwRe_ { }
Lmwad.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwad(ta); }
Lmwad.ta: is LsmwRb_ & LsmwRe_ { }
Lmwad.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwad(t0); }
Lmwad.t0: is LsmwRb_ & LsmwRe_ { }
Lmwad.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwad(t1); }
Lmwad.t1: is LsmwRb_ & LsmwRe_ { }
Lmwad.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwad(t2); }
Lmwad.t2: is LsmwRb_ & LsmwRe_ { }
Lmwad.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwad(t3); }
Lmwad.t3: is LsmwRb_ & LsmwRe_ { }
Lmwad.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwad(t4); }
Lmwad.t4: is LsmwRb_ & LsmwRe_ { }
Lmwad.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwad(t5); }
Lmwad.t5: is LsmwRb_ & LsmwRe_ { }
Lmwad.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwad(t6); }
Lmwad.t6: is LsmwRb_ & LsmwRe_ { }
Lmwad.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwad(t7); }
Lmwad.t7: is LsmwRb_ & LsmwRe_ { }
Lmwad.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwad(t8); }
Lmwad.t8: is LsmwRb_ & LsmwRe_ { }
Lmwad.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwad(t9); }
Lmwad.t9: is LsmwRb_ & LsmwRe_ { }
Lmwad.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwad(p0); }
Lmwad.p0: is LsmwRb_ & LsmwRe_ { }
Lmwad.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwad(p1); }
Lmwad.p1: is LsmwRb_ & LsmwRe_ { }
Lmwad.fp: fp is Enable4_fp=1 & fp { Lmwad(fp); }
Lmwad.fp: is Enable4_fp=0 { }
Lmwad.gp: gp is Enable4_gp=1 & gp { Lmwad(gp); }
Lmwad.gp: is Enable4_gp=0 { }
Lmwad.lp: lp is Enable4_lp=1 & lp { Lmwad(lp); }
Lmwad.lp: is Enable4_lp=0 { }
Lmwad.sp: sp is Enable4_sp=1 & sp { Lmwad(sp); }
Lmwad.sp: is Enable4_sp=0 { }
Smwbi.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwbi(a0); }
Smwbi.a0: is LsmwRb_ & LsmwRe_ { }
Smwbi.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwbi(a1); }
Smwbi.a1: is LsmwRb_ & LsmwRe_ { }
Smwbi.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwbi(a2); }
Smwbi.a2: is LsmwRb_ & LsmwRe_ { }
Smwbi.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwbi(a3); }
Smwbi.a3: is LsmwRb_ & LsmwRe_ { }
Smwbi.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwbi(a4); }
Smwbi.a4: is LsmwRb_ & LsmwRe_ { }
Smwbi.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwbi(a5); }
Smwbi.a5: is LsmwRb_ & LsmwRe_ { }
Smwbi.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwbi(s0); }
Smwbi.s0: is LsmwRb_ & LsmwRe_ { }
Smwbi.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwbi(s1); }
Smwbi.s1: is LsmwRb_ & LsmwRe_ { }
Smwbi.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwbi(s2); }
Smwbi.s2: is LsmwRb_ & LsmwRe_ { }
Smwbi.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwbi(s3); }
Smwbi.s3: is LsmwRb_ & LsmwRe_ { }
Smwbi.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwbi(s4); }
Smwbi.s4: is LsmwRb_ & LsmwRe_ { }
Smwbi.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwbi(s5); }
Smwbi.s5: is LsmwRb_ & LsmwRe_ { }
Smwbi.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwbi(s6); }
Smwbi.s6: is LsmwRb_ & LsmwRe_ { }
Smwbi.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwbi(s7); }
Smwbi.s7: is LsmwRb_ & LsmwRe_ { }
Smwbi.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwbi(s8); }
Smwbi.s8: is LsmwRb_ & LsmwRe_ { }
Smwbi.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwbi(ta); }
Smwbi.ta: is LsmwRb_ & LsmwRe_ { }
Smwbi.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwbi(t0); }
Smwbi.t0: is LsmwRb_ & LsmwRe_ { }
Smwbi.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwbi(t1); }
Smwbi.t1: is LsmwRb_ & LsmwRe_ { }
Smwbi.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwbi(t2); }
Smwbi.t2: is LsmwRb_ & LsmwRe_ { }
Smwbi.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwbi(t3); }
Smwbi.t3: is LsmwRb_ & LsmwRe_ { }
Smwbi.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwbi(t4); }
Smwbi.t4: is LsmwRb_ & LsmwRe_ { }
Smwbi.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwbi(t5); }
Smwbi.t5: is LsmwRb_ & LsmwRe_ { }
Smwbi.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwbi(t6); }
Smwbi.t6: is LsmwRb_ & LsmwRe_ { }
Smwbi.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwbi(t7); }
Smwbi.t7: is LsmwRb_ & LsmwRe_ { }
Smwbi.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwbi(t8); }
Smwbi.t8: is LsmwRb_ & LsmwRe_ { }
Smwbi.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwbi(t9); }
Smwbi.t9: is LsmwRb_ & LsmwRe_ { }
Smwbi.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwbi(p0); }
Smwbi.p0: is LsmwRb_ & LsmwRe_ { }
Smwbi.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwbi(p1); }
Smwbi.p1: is LsmwRb_ & LsmwRe_ { }
Smwbi.fp: fp is Enable4_fp=1 & fp { Smwbi(fp); }
Smwbi.fp: is Enable4_fp=0 { }
Smwbi.gp: gp is Enable4_gp=1 & gp { Smwbi(gp); }
Smwbi.gp: is Enable4_gp=0 { }
Smwbi.lp: lp is Enable4_lp=1 & lp { Smwbi(lp); }
Smwbi.lp: is Enable4_lp=0 { }
Smwbi.sp: sp is Enable4_sp=1 & sp { Smwbi(sp); }
Smwbi.sp: is Enable4_sp=0 { }
Smwbd.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwbd(a0); }
Smwbd.a0: is LsmwRb_ & LsmwRe_ { }
Smwbd.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwbd(a1); }
Smwbd.a1: is LsmwRb_ & LsmwRe_ { }
Smwbd.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwbd(a2); }
Smwbd.a2: is LsmwRb_ & LsmwRe_ { }
Smwbd.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwbd(a3); }
Smwbd.a3: is LsmwRb_ & LsmwRe_ { }
Smwbd.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwbd(a4); }
Smwbd.a4: is LsmwRb_ & LsmwRe_ { }
Smwbd.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwbd(a5); }
Smwbd.a5: is LsmwRb_ & LsmwRe_ { }
Smwbd.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwbd(s0); }
Smwbd.s0: is LsmwRb_ & LsmwRe_ { }
Smwbd.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwbd(s1); }
Smwbd.s1: is LsmwRb_ & LsmwRe_ { }
Smwbd.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwbd(s2); }
Smwbd.s2: is LsmwRb_ & LsmwRe_ { }
Smwbd.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwbd(s3); }
Smwbd.s3: is LsmwRb_ & LsmwRe_ { }
Smwbd.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwbd(s4); }
Smwbd.s4: is LsmwRb_ & LsmwRe_ { }
Smwbd.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwbd(s5); }
Smwbd.s5: is LsmwRb_ & LsmwRe_ { }
Smwbd.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwbd(s6); }
Smwbd.s6: is LsmwRb_ & LsmwRe_ { }
Smwbd.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwbd(s7); }
Smwbd.s7: is LsmwRb_ & LsmwRe_ { }
Smwbd.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwbd(s8); }
Smwbd.s8: is LsmwRb_ & LsmwRe_ { }
Smwbd.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwbd(ta); }
Smwbd.ta: is LsmwRb_ & LsmwRe_ { }
Smwbd.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwbd(t0); }
Smwbd.t0: is LsmwRb_ & LsmwRe_ { }
Smwbd.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwbd(t1); }
Smwbd.t1: is LsmwRb_ & LsmwRe_ { }
Smwbd.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwbd(t2); }
Smwbd.t2: is LsmwRb_ & LsmwRe_ { }
Smwbd.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwbd(t3); }
Smwbd.t3: is LsmwRb_ & LsmwRe_ { }
Smwbd.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwbd(t4); }
Smwbd.t4: is LsmwRb_ & LsmwRe_ { }
Smwbd.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwbd(t5); }
Smwbd.t5: is LsmwRb_ & LsmwRe_ { }
Smwbd.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwbd(t6); }
Smwbd.t6: is LsmwRb_ & LsmwRe_ { }
Smwbd.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwbd(t7); }
Smwbd.t7: is LsmwRb_ & LsmwRe_ { }
Smwbd.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwbd(t8); }
Smwbd.t8: is LsmwRb_ & LsmwRe_ { }
Smwbd.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwbd(t9); }
Smwbd.t9: is LsmwRb_ & LsmwRe_ { }
Smwbd.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwbd(p0); }
Smwbd.p0: is LsmwRb_ & LsmwRe_ { }
Smwbd.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwbd(p1); }
Smwbd.p1: is LsmwRb_ & LsmwRe_ { }
Smwbd.fp: fp is Enable4_fp=1 & fp { Smwbd(fp); }
Smwbd.fp: is Enable4_fp=0 { }
Smwbd.gp: gp is Enable4_gp=1 & gp { Smwbd(gp); }
Smwbd.gp: is Enable4_gp=0 { }
Smwbd.lp: lp is Enable4_lp=1 & lp { Smwbd(lp); }
Smwbd.lp: is Enable4_lp=0 { }
Smwbd.sp: sp is Enable4_sp=1 & sp { Smwbd(sp); }
Smwbd.sp: is Enable4_sp=0 { }
Smwai.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwai(a0); }
Smwai.a0: is LsmwRb_ & LsmwRe_ { }
Smwai.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwai(a1); }
Smwai.a1: is LsmwRb_ & LsmwRe_ { }
Smwai.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwai(a2); }
Smwai.a2: is LsmwRb_ & LsmwRe_ { }
Smwai.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwai(a3); }
Smwai.a3: is LsmwRb_ & LsmwRe_ { }
Smwai.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwai(a4); }
Smwai.a4: is LsmwRb_ & LsmwRe_ { }
Smwai.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwai(a5); }
Smwai.a5: is LsmwRb_ & LsmwRe_ { }
Smwai.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwai(s0); }
Smwai.s0: is LsmwRb_ & LsmwRe_ { }
Smwai.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwai(s1); }
Smwai.s1: is LsmwRb_ & LsmwRe_ { }
Smwai.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwai(s2); }
Smwai.s2: is LsmwRb_ & LsmwRe_ { }
Smwai.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwai(s3); }
Smwai.s3: is LsmwRb_ & LsmwRe_ { }
Smwai.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwai(s4); }
Smwai.s4: is LsmwRb_ & LsmwRe_ { }
Smwai.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwai(s5); }
Smwai.s5: is LsmwRb_ & LsmwRe_ { }
Smwai.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwai(s6); }
Smwai.s6: is LsmwRb_ & LsmwRe_ { }
Smwai.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwai(s7); }
Smwai.s7: is LsmwRb_ & LsmwRe_ { }
Smwai.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwai(s8); }
Smwai.s8: is LsmwRb_ & LsmwRe_ { }
Smwai.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwai(ta); }
Smwai.ta: is LsmwRb_ & LsmwRe_ { }
Smwai.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwai(t0); }
Smwai.t0: is LsmwRb_ & LsmwRe_ { }
Smwai.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwai(t1); }
Smwai.t1: is LsmwRb_ & LsmwRe_ { }
Smwai.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwai(t2); }
Smwai.t2: is LsmwRb_ & LsmwRe_ { }
Smwai.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwai(t3); }
Smwai.t3: is LsmwRb_ & LsmwRe_ { }
Smwai.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwai(t4); }
Smwai.t4: is LsmwRb_ & LsmwRe_ { }
Smwai.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwai(t5); }
Smwai.t5: is LsmwRb_ & LsmwRe_ { }
Smwai.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwai(t6); }
Smwai.t6: is LsmwRb_ & LsmwRe_ { }
Smwai.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwai(t7); }
Smwai.t7: is LsmwRb_ & LsmwRe_ { }
Smwai.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwai(t8); }
Smwai.t8: is LsmwRb_ & LsmwRe_ { }
Smwai.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwai(t9); }
Smwai.t9: is LsmwRb_ & LsmwRe_ { }
Smwai.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwai(p0); }
Smwai.p0: is LsmwRb_ & LsmwRe_ { }
Smwai.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwai(p1); }
Smwai.p1: is LsmwRb_ & LsmwRe_ { }
Smwai.fp: fp is Enable4_fp=1 & fp { Smwai(fp); }
Smwai.fp: is Enable4_fp=0 { }
Smwai.gp: gp is Enable4_gp=1 & gp { Smwai(gp); }
Smwai.gp: is Enable4_gp=0 { }
Smwai.lp: lp is Enable4_lp=1 & lp { Smwai(lp); }
Smwai.lp: is Enable4_lp=0 { }
Smwai.sp: sp is Enable4_sp=1 & sp { Smwai(sp); }
Smwai.sp: is Enable4_sp=0 { }
Smwad.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwad(a0); }
Smwad.a0: is LsmwRb_ & LsmwRe_ { }
Smwad.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwad(a1); }
Smwad.a1: is LsmwRb_ & LsmwRe_ { }
Smwad.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwad(a2); }
Smwad.a2: is LsmwRb_ & LsmwRe_ { }
Smwad.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwad(a3); }
Smwad.a3: is LsmwRb_ & LsmwRe_ { }
Smwad.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwad(a4); }
Smwad.a4: is LsmwRb_ & LsmwRe_ { }
Smwad.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwad(a5); }
Smwad.a5: is LsmwRb_ & LsmwRe_ { }
Smwad.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwad(s0); }
Smwad.s0: is LsmwRb_ & LsmwRe_ { }
Smwad.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwad(s1); }
Smwad.s1: is LsmwRb_ & LsmwRe_ { }
Smwad.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwad(s2); }
Smwad.s2: is LsmwRb_ & LsmwRe_ { }
Smwad.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwad(s3); }
Smwad.s3: is LsmwRb_ & LsmwRe_ { }
Smwad.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwad(s4); }
Smwad.s4: is LsmwRb_ & LsmwRe_ { }
Smwad.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwad(s5); }
Smwad.s5: is LsmwRb_ & LsmwRe_ { }
Smwad.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwad(s6); }
Smwad.s6: is LsmwRb_ & LsmwRe_ { }
Smwad.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwad(s7); }
Smwad.s7: is LsmwRb_ & LsmwRe_ { }
Smwad.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwad(s8); }
Smwad.s8: is LsmwRb_ & LsmwRe_ { }
Smwad.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwad(ta); }
Smwad.ta: is LsmwRb_ & LsmwRe_ { }
Smwad.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwad(t0); }
Smwad.t0: is LsmwRb_ & LsmwRe_ { }
Smwad.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwad(t1); }
Smwad.t1: is LsmwRb_ & LsmwRe_ { }
Smwad.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwad(t2); }
Smwad.t2: is LsmwRb_ & LsmwRe_ { }
Smwad.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwad(t3); }
Smwad.t3: is LsmwRb_ & LsmwRe_ { }
Smwad.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwad(t4); }
Smwad.t4: is LsmwRb_ & LsmwRe_ { }
Smwad.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwad(t5); }
Smwad.t5: is LsmwRb_ & LsmwRe_ { }
Smwad.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwad(t6); }
Smwad.t6: is LsmwRb_ & LsmwRe_ { }
Smwad.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwad(t7); }
Smwad.t7: is LsmwRb_ & LsmwRe_ { }
Smwad.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwad(t8); }
Smwad.t8: is LsmwRb_ & LsmwRe_ { }
Smwad.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwad(t9); }
Smwad.t9: is LsmwRb_ & LsmwRe_ { }
Smwad.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwad(p0); }
Smwad.p0: is LsmwRb_ & LsmwRe_ { }
Smwad.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwad(p1); }
Smwad.p1: is LsmwRb_ & LsmwRe_ { }
Smwad.fp: fp is Enable4_fp=1 & fp { Smwad(fp); }
Smwad.fp: is Enable4_fp=0 { }
Smwad.gp: gp is Enable4_gp=1 & gp { Smwad(gp); }
Smwad.gp: is Enable4_gp=0 { }
Smwad.lp: lp is Enable4_lp=1 & lp { Smwad(lp); }
Smwad.lp: is Enable4_lp=0 { }
Smwad.sp: sp is Enable4_sp=1 & sp { Smwad(sp); }
Smwad.sp: is Enable4_sp=0 { }
Lmw.regs: is LsmwBa=0 & LsmwId=0 & Lmwbi.sp & Lmwbi.lp & Lmwbi.gp & Lmwbi.fp & Lmwbi.p1 & Lmwbi.p0 & Lmwbi.t9 & Lmwbi.t8 & Lmwbi.t7 & Lmwbi.t6 & Lmwbi.t5 & Lmwbi.t4 & Lmwbi.t3 & Lmwbi.t2 & Lmwbi.t1 & Lmwbi.t0 & Lmwbi.ta & Lmwbi.s8 & Lmwbi.s7 & Lmwbi.s6 & Lmwbi.s5 & Lmwbi.s4 & Lmwbi.s3 & Lmwbi.s2 & Lmwbi.s1 & Lmwbi.s0 & Lmwbi.a5 & Lmwbi.a4 & Lmwbi.a3 & Lmwbi.a2 & Lmwbi.a1 & Lmwbi.a0 { }
Lmw.regs: is LsmwBa=0 & LsmwId=1 & Lmwbd.a0 & Lmwbd.a1 & Lmwbd.a2 & Lmwbd.a3 & Lmwbd.a4 & Lmwbd.a5 & Lmwbd.s0 & Lmwbd.s1 & Lmwbd.s2 & Lmwbd.s3 & Lmwbd.s4 & Lmwbd.s5 & Lmwbd.s6 & Lmwbd.s7 & Lmwbd.s8 & Lmwbd.ta & Lmwbd.t0 & Lmwbd.t1 & Lmwbd.t2 & Lmwbd.t3 & Lmwbd.t4 & Lmwbd.t5 & Lmwbd.t6 & Lmwbd.t7 & Lmwbd.t8 & Lmwbd.t9 & Lmwbd.p0 & Lmwbd.p1 & Lmwbd.fp & Lmwbd.gp & Lmwbd.lp & Lmwbd.sp { }
Lmw.regs: is LsmwBa=1 & LsmwId=0 & Lmwai.sp & Lmwai.lp & Lmwai.gp & Lmwai.fp & Lmwai.p1 & Lmwai.p0 & Lmwai.t9 & Lmwai.t8 & Lmwai.t7 & Lmwai.t6 & Lmwai.t5 & Lmwai.t4 & Lmwai.t3 & Lmwai.t2 & Lmwai.t1 & Lmwai.t0 & Lmwai.ta & Lmwai.s8 & Lmwai.s7 & Lmwai.s6 & Lmwai.s5 & Lmwai.s4 & Lmwai.s3 & Lmwai.s2 & Lmwai.s1 & Lmwai.s0 & Lmwai.a5 & Lmwai.a4 & Lmwai.a3 & Lmwai.a2 & Lmwai.a1 & Lmwai.a0 { }
Lmw.regs: is LsmwBa=1 & LsmwId=1 & Lmwad.a0 & Lmwad.a1 & Lmwad.a2 & Lmwad.a3 & Lmwad.a4 & Lmwad.a5 & Lmwad.s0 & Lmwad.s1 & Lmwad.s2 & Lmwad.s3 & Lmwad.s4 & Lmwad.s5 & Lmwad.s6 & Lmwad.s7 & Lmwad.s8 & Lmwad.ta & Lmwad.t0 & Lmwad.t1 & Lmwad.t2 & Lmwad.t3 & Lmwad.t4 & Lmwad.t5 & Lmwad.t6 & Lmwad.t7 & Lmwad.t8 & Lmwad.t9 & Lmwad.p0 & Lmwad.p1 & Lmwad.fp & Lmwad.gp & Lmwad.lp & Lmwad.sp { }
Smw.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
Smw.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
Smw.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
Smw.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }
Lmwa.regs: is LsmwBa=0 & LsmwId=0 & Lmwbi.sp & Lmwbi.lp & Lmwbi.gp & Lmwbi.fp & Lmwbi.p1 & Lmwbi.p0 & Lmwbi.t9 & Lmwbi.t8 & Lmwbi.t7 & Lmwbi.t6 & Lmwbi.t5 & Lmwbi.t4 & Lmwbi.t3 & Lmwbi.t2 & Lmwbi.t1 & Lmwbi.t0 & Lmwbi.ta & Lmwbi.s8 & Lmwbi.s7 & Lmwbi.s6 & Lmwbi.s5 & Lmwbi.s4 & Lmwbi.s3 & Lmwbi.s2 & Lmwbi.s1 & Lmwbi.s0 & Lmwbi.a5 & Lmwbi.a4 & Lmwbi.a3 & Lmwbi.a2 & Lmwbi.a1 & Lmwbi.a0 { }
Lmwa.regs: is LsmwBa=0 & LsmwId=1 & Lmwbd.a0 & Lmwbd.a1 & Lmwbd.a2 & Lmwbd.a3 & Lmwbd.a4 & Lmwbd.a5 & Lmwbd.s0 & Lmwbd.s1 & Lmwbd.s2 & Lmwbd.s3 & Lmwbd.s4 & Lmwbd.s5 & Lmwbd.s6 & Lmwbd.s7 & Lmwbd.s8 & Lmwbd.ta & Lmwbd.t0 & Lmwbd.t1 & Lmwbd.t2 & Lmwbd.t3 & Lmwbd.t4 & Lmwbd.t5 & Lmwbd.t6 & Lmwbd.t7 & Lmwbd.t8 & Lmwbd.t9 & Lmwbd.p0 & Lmwbd.p1 & Lmwbd.fp & Lmwbd.gp & Lmwbd.lp & Lmwbd.sp { }
Lmwa.regs: is LsmwBa=1 & LsmwId=0 & Lmwai.sp & Lmwai.lp & Lmwai.gp & Lmwai.fp & Lmwai.p1 & Lmwai.p0 & Lmwai.t9 & Lmwai.t8 & Lmwai.t7 & Lmwai.t6 & Lmwai.t5 & Lmwai.t4 & Lmwai.t3 & Lmwai.t2 & Lmwai.t1 & Lmwai.t0 & Lmwai.ta & Lmwai.s8 & Lmwai.s7 & Lmwai.s6 & Lmwai.s5 & Lmwai.s4 & Lmwai.s3 & Lmwai.s2 & Lmwai.s1 & Lmwai.s0 & Lmwai.a5 & Lmwai.a4 & Lmwai.a3 & Lmwai.a2 & Lmwai.a1 & Lmwai.a0 { }
Lmwa.regs: is LsmwBa=1 & LsmwId=1 & Lmwad.a0 & Lmwad.a1 & Lmwad.a2 & Lmwad.a3 & Lmwad.a4 & Lmwad.a5 & Lmwad.s0 & Lmwad.s1 & Lmwad.s2 & Lmwad.s3 & Lmwad.s4 & Lmwad.s5 & Lmwad.s6 & Lmwad.s7 & Lmwad.s8 & Lmwad.ta & Lmwad.t0 & Lmwad.t1 & Lmwad.t2 & Lmwad.t3 & Lmwad.t4 & Lmwad.t5 & Lmwad.t6 & Lmwad.t7 & Lmwad.t8 & Lmwad.t9 & Lmwad.p0 & Lmwad.p1 & Lmwad.fp & Lmwad.gp & Lmwad.lp & Lmwad.sp { }
Smwa.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
Smwa.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
Smwa.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
Smwa.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }

105
Ghidra/Processors/NDS32/data/languages/nds32.cspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<returnaddress>
<register name="lp"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="24" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="a1" piece2="a0"/>
</pentry>
</output>
<unaffected>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="p0"/>
<register name="p1"/>
<register name="fp"/>
<register name="gp"/>
<register name="lp"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="a0"/>
<register name="a1"/>
<register name="a2"/>
<register name="a3"/>
<register name="a4"/>
<register name="a5"/>
<register name="ta"/>
<register name="t0"/>
<register name="t1"/>
<register name="t2"/>
<register name="t3"/>
<register name="t4"/>
<register name="t5"/>
<register name="t6"/>
<register name="t7"/>
<register name="t8"/>
<register name="t9"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>

14
Ghidra/Processors/NDS32/data/languages/nds32.dwarf Normal file
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<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="a0" auto_count="6"/> <!-- a0..a5 -->
<register_mapping dwarf="6" ghidra="s0" auto_count="9"/> <!-- s0..s8 -->
<register_mapping dwarf="15" ghidra="ta"/>
<register_mapping dwarf="16" ghidra="t0" auto_count="10"/> <!-- t0..t9 -->
<register_mapping dwarf="26" ghidra="p0" auto_count="2"/> <!-- p0..p1 -->
<register_mapping dwarf="28" ghidra="fp"/>
<register_mapping dwarf="29" ghidra="gp"/>
<register_mapping dwarf="30" ghidra="lp"/>
<register_mapping dwarf="31" ghidra="sp" stackpointer="true"/>
</register_mappings>
<call_frame_cfa value="0"/>
</dwarf>

31
Ghidra/Processors/NDS32/data/languages/nds32.ldefs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="NDS32"
endian="big"
instructionEndian="big"
size="32"
variant="default"
version="1.0"
slafile="nds32be.sla"
processorspec="nds32.pspec"
id="NDS32:BE:32:default">
<description>NDS32 default processor 32-bit big-endian</description>
<compiler name="default" spec="nds32.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="nds32.dwarf"/>
</language>
<language processor="NDS32"
endian="little"
instructionEndian="big"
size="32"
variant="default"
version="1.0"
slafile="nds32le.sla"
processorspec="nds32.pspec"
id="NDS32:LE:32:default">
<description>NDS32 default processor 32-bit little-endian</description>
<compiler name="default" spec="nds32.cspec" id="default"/>
<external_name tool="DWARF.register.mapping.file" name="nds32.dwarf"/>
</language>
</language_definitions>

5
Ghidra/Processors/NDS32/data/languages/nds32.opinion Normal file
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<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="167" processor="NDS32" size="32" />
</constraint>
</opinions>

6
Ghidra/Processors/NDS32/data/languages/nds32.pspec Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="pc"/>
</processor_spec>

1081
Ghidra/Processors/NDS32/data/languages/nds32.sinc Normal file
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7
Ghidra/Processors/NDS32/data/languages/nds32be.slaspec Normal file
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@define BASELINE_V2 "yes"
@define BASELINE_V3 "yes"
@define PERFORMANCE_V1 "yes"
@define PERFORMANCE_V2 "yes"
@define ENDIAN "big"
@include "nds32.sinc"

7
Ghidra/Processors/NDS32/data/languages/nds32le.slaspec Normal file
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@define BASELINE_V2 "yes"
@define BASELINE_V3 "yes"
@define PERFORMANCE_V1 "yes"
@define PERFORMANCE_V2 "yes"
@define ENDIAN "little"
@include "nds32.sinc"

13
Ghidra/Processors/NDS32/data/patterns/nds32_patterns.xml Normal file
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<patternlist>
<patternpairs totalbits="32" postbits="16">
<prepatterns>
<data>0xd5 ........</data>
<data>0x48 ........ ........ ........</data>
<data>0x92 0x00</data>
</prepatterns>
<postpatterns>
<data>0011101. ....1111 1......0 .0111100</data>
<funcstart/>
</postpatterns>
</patternpairs>
</patternlist>

5
Ghidra/Processors/NDS32/data/patterns/patternconstraints.xml Normal file
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<patternconstraints>
<language id="NDS32:*:*:*">
<patternfile>nds32_patterns.xml</patternfile>
</language>
</patternconstraints>

6
Ghidra/Processors/NDS32/data/sleighArgs.txt Normal file
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# Add sleigh compiler options to this file (one per line) which will
# be used when compiling each language within this module.
# All options should start with a '-' character.
#
# IMPORTANT: The -a option should NOT be specified
#

187
Ghidra/Processors/NDS32/src/main/java/ghidra/app/plugin/core/analysis/NDS32Analyzer.java Normal file
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package ghidra.app.plugin.core.analysis;
import java.math.BigInteger;
import ghidra.app.util.importer.MessageLog;
import ghidra.framework.options.Options;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressSet;
import ghidra.program.model.address.AddressSetView;
import ghidra.program.model.lang.Processor;
import ghidra.program.model.lang.Register;
import ghidra.program.model.lang.RegisterValue;
import ghidra.program.model.listing.ContextChangeException;
import ghidra.program.model.listing.Function;
import ghidra.program.model.listing.Instruction;
import ghidra.program.model.listing.Program;
import ghidra.program.model.listing.ProgramContext;
import ghidra.program.model.symbol.FlowType;
import ghidra.program.model.symbol.Symbol;
import ghidra.program.model.symbol.SymbolUtilities;
import ghidra.program.util.ContextEvaluator;
import ghidra.program.util.SymbolicPropogator;
import ghidra.program.util.VarnodeContext;
import ghidra.util.Msg;
import ghidra.util.exception.AssertException;
import ghidra.util.exception.CancelledException;
import ghidra.util.task.TaskMonitor;
public class NDS32Analyzer extends ConstantPropagationAnalyzer {
private final static String PROCESSOR_NAME = "NDS32";
private static final String SWITCH_OPTION_NAME = "Switch Table Recovery";
private static final String SWITCH_OPTION_DESCRIPTION = "Turn on to recover switch tables (not implemented yet !)";
private static final boolean SWITCH_OPTION_DEFAULT_VALUE = false;
private static final String RECOVER_GP_OPTION_NAME = "Recover global GP register writes";
private static final String RECOVER_GP_OPTION_DESCRIPTION = "Reads the global GP value from the symbol _SDA_BASE_";
private static final boolean RECOVER_GP_OPTION_DEFAULT_VALUE = true;
private boolean recoverSwitchTables = SWITCH_OPTION_DEFAULT_VALUE;
private boolean recoverGp = RECOVER_GP_OPTION_DEFAULT_VALUE;
private Address gpAssumptionValue = null;
private Register gp;
public NDS32Analyzer() {
super(PROCESSOR_NAME);
}
@Override
public boolean canAnalyze(Program program) {
boolean canAnalyze = program.getLanguage().getProcessor().equals(
Processor.findOrPossiblyCreateProcessor(PROCESSOR_NAME));
if (!canAnalyze) {
return false;
}
gp = program.getRegister("gp");
return true;
}
@Override
public void optionsChanged(Options options, Program program) {
super.optionsChanged(options, program);
options.registerOption(SWITCH_OPTION_NAME, recoverSwitchTables, null,
SWITCH_OPTION_DESCRIPTION);
recoverSwitchTables = options.getBoolean(SWITCH_OPTION_NAME, recoverSwitchTables);
options.registerOption(RECOVER_GP_OPTION_NAME, recoverGp, null,
RECOVER_GP_OPTION_DESCRIPTION);
recoverGp = options.getBoolean(RECOVER_GP_OPTION_NAME, recoverGp);
}
@Override
public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log)
throws CancelledException {
gpAssumptionValue = null;
checkForGlobalGP(program, set, monitor);
return super.added(program, set, monitor, log);
}
/**
* Check for a global GP register symbol or discovered symbol
* @param set
*/
private void checkForGlobalGP(Program program, AddressSetView set, TaskMonitor monitor) {
if (!recoverGp) {
return;
}
Symbol symbol = SymbolUtilities.getLabelOrFunctionSymbol(program, "_SDA_BASE_",
err -> Msg.error(this, err));
if (symbol != null) {
gpAssumptionValue = symbol.getAddress();
return;
}
// TODO : if the symbol doesn't exist, check manually... somewhere else
return;
}
@Override
public AddressSetView flowConstants(final Program program, Address flowStart,
AddressSetView flowSet, final SymbolicPropogator symEval, final TaskMonitor monitor)
throws CancelledException {
// get the function body
final Function func = program.getFunctionManager().getFunctionContaining(flowStart);
final AddressSet coveredSet = new AddressSet();
Address currentGPAssumptionValue = gpAssumptionValue;
// TODO : copypaste more code from MipsAddressAnalyzer to see if gp is written and act accordingly
if (func != null) {
flowStart = func.getEntryPoint();
if (currentGPAssumptionValue != null) {
ProgramContext programContext = program.getProgramContext();
RegisterValue gpVal = programContext.getRegisterValue(gp, flowStart);
if (gpVal == null || !gpVal.hasValue()) {
gpVal = new RegisterValue(gp,
BigInteger.valueOf(currentGPAssumptionValue.getOffset()));
try {
program.getProgramContext().setRegisterValue(func.getEntryPoint(),
func.getEntryPoint(), gpVal);
}
catch (ContextChangeException e) {
throw new AssertException("unexpected", e); // only happens for context register
}
}
}
}
ContextEvaluator eval = new ConstantPropagationContextEvaluator(trustWriteMemOption) {
@Override
public boolean evaluateDestination(VarnodeContext context, Instruction instruction) {
FlowType flowtype = instruction.getFlowType();
if (!flowtype.isJump()) {
return false;
}
if (recoverSwitchTables) {
String mnemonic = instruction.getMnemonicString();
if (mnemonic.equals("jr")) {
fixJumpTable(program, instruction, monitor);
}
}
return false;
}
};
AddressSet resultSet = symEval.flowConstants(flowStart, null, eval, true, monitor);
// Add in any addresses we should assume got covered
// These addresses are put on because we had to stop analysis due to an unknown register value
resultSet.add(coveredSet);
return resultSet;
}
/**
* @param program
* @param startInstr
* @param monitor
*/
private void fixJumpTable(Program program, Instruction startInstr, TaskMonitor monitor) {
/* TODO: implement switch recovery ?
* We are looking for tables like this :
*
* slti45 a0,0x4 <- table size
* beqzs8 LAB_005159ea <- default jump
* sethi ta, 0x515
* ori ta, ta, 0x9a0
* lw a0, [ta + (a0 << 0x2)] <- ref to table
* jr a0 <- table jump
*/
}
}

74
Ghidra/Processors/NDS32/src/main/java/ghidra/app/util/bin/format/elf/relocation/NDS32_ElfRelocationConstants.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
public class NDS32_ElfRelocationConstants {
public static final int R_NDS32_NONE = 0;
public static final int R_NDS32_16_RELA = 19;
public static final int R_NDS32_32_RELA = 20;
public static final int R_NDS32_9_PCREL_RELA = 22;
public static final int R_NDS32_15_PCREL_RELA = 23;
public static final int R_NDS32_17_PCREL_RELA = 24;
public static final int R_NDS32_25_PCREL_RELA = 25;
public static final int R_NDS32_HI20_RELA = 26;
public static final int R_NDS32_LO12S3_RELA = 27;
public static final int R_NDS32_LO12S2_RELA = 28;
public static final int R_NDS32_LO12S1_RELA = 29;
public static final int R_NDS32_LO12S0_RELA = 30;
public static final int R_NDS32_SDA15S3_RELA = 31;
public static final int R_NDS32_SDA15S2_RELA = 32;
public static final int R_NDS32_SDA15S1_RELA = 33;
public static final int R_NDS32_SDA15S0_RELA = 34;
public static final int R_NDS32_GOT20 = 37;
public static final int R_NDS32_25_PLTREL = 38;
public static final int R_NDS32_COPY = 39;
public static final int R_NDS32_GLOB_DAT = 40;
public static final int R_NDS32_JMP_SLOT = 41;
public static final int R_NDS32_RELATIVE = 42;
public static final int R_NDS32_GOTOFF = 43;
public static final int R_NDS32_GOTPC20 = 44;
public static final int R_NDS32_GOT_HI20 = 45;
public static final int R_NDS32_GOT_LO12 = 46;
public static final int R_NDS32_GOTPC_HI20 = 47;
public static final int R_NDS32_GOTPC_LO12 = 48;
public static final int R_NDS32_GOTOFF_HI20 = 49;
public static final int R_NDS32_GOTOFF_LO12 = 50;
public static final int R_NDS32_INSN16 = 51;
public static final int R_NDS32_LABEL = 52;
public static final int R_NDS32_LONGCALL1 = 53;
public static final int R_NDS32_LONGCALL2 = 54;
public static final int R_NDS32_LONGCALL3 = 55;
public static final int R_NDS32_LONGJUMP1 = 56;
public static final int R_NDS32_LONGJUMP2 = 57;
public static final int R_NDS32_LONGJUMP3 = 58;
public static final int R_NDS32_LOADSTORE = 59;
public static final int R_NDS32_9_FIXED_RELA = 60;
public static final int R_NDS32_15_FIXED_RELA = 61;
public static final int R_NDS32_17_FIXED_RELA = 62;
public static final int R_NDS32_25_FIXED_RELA = 63;
public static final int R_NDS32_PLTREL_HI20 = 64;
public static final int R_NDS32_PLTREL_LO12 = 65;
public static final int R_NDS32_PLT_GOTREL_HI20 = 66;
public static final int R_NDS32_PLT_GOTREL_LO12 = 67;
public static final int R_NDS32_LO12S0_ORI_RELA = 72;
public static final int R_NDS32_DWARF2_OP1_RELA = 77;
public static final int R_NDS32_DWARF2_OP2_RELA = 78;
public static final int R_NDS32_DWARF2_LEB_RELA = 79;
public static final int R_NDS32_WORD_9_PCREL_RELA = 94;
public static final int R_NDS32_LONGCALL4 = 107;
public static final int R_NDS32_RELA_NOP_MIX = 192;
public static final int R_NDS32_RELA_NOP_MAX = 255;
}

111
Ghidra/Processors/NDS32/src/main/java/ghidra/app/util/bin/format/elf/relocation/NDS32_ElfRelocationHandler.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
import java.util.Map;
import ghidra.app.util.bin.format.elf.ElfConstants;
import ghidra.app.util.bin.format.elf.ElfHeader;
import ghidra.app.util.bin.format.elf.ElfLoadHelper;
import ghidra.app.util.bin.format.elf.ElfRelocation;
import ghidra.app.util.bin.format.elf.ElfRelocationTable;
import ghidra.app.util.bin.format.elf.ElfSymbol;
import ghidra.app.util.importer.MessageLog;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressOutOfBoundsException;
import ghidra.program.model.listing.Program;
import ghidra.program.model.mem.Memory;
import ghidra.program.model.mem.MemoryAccessException;
import ghidra.util.exception.NotFoundException;
public class NDS32_ElfRelocationHandler extends ElfRelocationHandler {
@Override
public boolean canRelocate(ElfHeader elf) {
return elf.e_machine() == ElfConstants.EM_NDS32;
}
@Override
public NDS32_ElfRelocationContext createRelocationContext(ElfLoadHelper loadHelper,
ElfRelocationTable relocationTable, Map<ElfSymbol, Address> symbolMap) {
return new NDS32_ElfRelocationContext(this, loadHelper, relocationTable, symbolMap);
}
@Override
public void relocate(ElfRelocationContext elfRelocationContext, ElfRelocation relocation, Address relocationAddress)
throws MemoryAccessException, NotFoundException {
ElfHeader elf = elfRelocationContext.getElfHeader();
if (elf.e_machine() != ElfConstants.EM_NDS32) {
return;
}
if (!elf.is32Bit()) {
return;
}
NDS32_ElfRelocationContext nds32RelocationContext =
(NDS32_ElfRelocationContext) elfRelocationContext;
int type = relocation.getType();
int symbolIndex = relocation.getSymbolIndex();
doRelocate(nds32RelocationContext, type, symbolIndex, relocation, relocationAddress);
}
private void doRelocate(NDS32_ElfRelocationContext nds32RelocationContext, int relocType,
int symbolIndex, ElfRelocation relocation, Address relocationAddress)
throws MemoryAccessException, NotFoundException, AddressOutOfBoundsException {
Program program = nds32RelocationContext.getProgram();
Memory memory = program.getMemory();
MessageLog log = nds32RelocationContext.getLog();
ElfSymbol elfSymbol = nds32RelocationContext.getSymbol(symbolIndex);
long symbolValue = nds32RelocationContext.getSymbolValue(elfSymbol);
String symbolName = elfSymbol.getNameAsString();
// Read instruction as big endian
int oldValue = memory.getInt(relocationAddress, true);
long addend = 0;
if(relocation.hasAddend()) {
addend = relocation.getAddend();
}
int value = 0;
int newValue = 0;
switch(relocType) {
case NDS32_ElfRelocationConstants.R_NDS32_HI20_RELA:
value = (int)(symbolValue + addend);
newValue = (oldValue & 0xfff00000) | (value >> 12);
memory.setInt(relocationAddress, newValue, true);
break;
case NDS32_ElfRelocationConstants.R_NDS32_LO12S0_RELA:
value = (int)(symbolValue + addend);
newValue = (oldValue & 0xfffff000) | (value & 0xfff);
memory.setInt(relocationAddress, newValue, true);
break;
default:
markAsUnhandled(program, relocationAddress, relocType, symbolIndex, symbolName, log);
}
}
private static class NDS32_ElfRelocationContext extends ElfRelocationContext {
protected NDS32_ElfRelocationContext(ElfRelocationHandler handler, ElfLoadHelper loadHelper,
ElfRelocationTable relocationTable, Map<ElfSymbol, Address> symbolMap) {
super(handler, loadHelper, relocationTable, symbolMap);
}
}
}

41
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_LE_O0_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class NDS32_LE_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "NDS32:LE:32:default";
private static final String COMPILER_SPEC_ID = "default";
private static final String[] REG_DUMP_SET = new String[] {};
public NDS32_LE_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "NDS32LE_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(NDS32_LE_O0_EmulatorTest.class);
}
}

41
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_LE_O3_EmulatorTest.java Normal file
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/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class NDS32_LE_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "NDS32:LE:32:default";
private static final String COMPILER_SPEC_ID = "default";
private static final String[] REG_DUMP_SET = new String[] {};
public NDS32_LE_O3_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "NDS32LE_GCC_O3";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(NDS32_LE_O3_EmulatorTest.class);
}
}