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Implementing mulhsu.
Not the most pretty solution, but works.
This commit is contained in:
Lucas Clemente Vella
@@ -67,12 +67,12 @@ impl Architecture for RiscvArchitecture {
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fn instruction_ends_control_flow(instr: &str) -> bool {
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match instr {
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"li" | "lui" | "la" | "mv" | "add" | "addi" | "sub" | "neg" | "mul" | "mulhu"
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| "divu" | "remu" | "xor" | "xori" | "and" | "andi" | "or" | "ori" | "not" | "slli"
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| "sll" | "srli" | "srl" | "srai" | "seqz" | "snez" | "slt" | "slti" | "sltu"
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| "sltiu" | "sgtz" | "beq" | "beqz" | "bgeu" | "bltu" | "blt" | "bge" | "bltz"
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| "blez" | "bgtz" | "bgez" | "bne" | "bnez" | "jal" | "jalr" | "call" | "ecall"
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| "ebreak" | "lw" | "lb" | "lbu" | "lh" | "lhu" | "sw" | "sh" | "sb" | "nop"
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| "fence" | "fence.i" | "amoadd.w" | "amoadd.w.aq" | "amoadd.w.rl"
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| "mulhsu" | "divu" | "remu" | "xor" | "xori" | "and" | "andi" | "or" | "ori"
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| "not" | "slli" | "sll" | "srli" | "srl" | "srai" | "seqz" | "snez" | "slt"
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| "slti" | "sltu" | "sltiu" | "sgtz" | "beq" | "beqz" | "bgeu" | "bltu" | "blt"
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| "bge" | "bltz" | "blez" | "bgtz" | "bgez" | "bne" | "bnez" | "jal" | "jalr"
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| "call" | "ecall" | "ebreak" | "lw" | "lb" | "lbu" | "lh" | "lhu" | "sw" | "sh"
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| "sb" | "nop" | "fence" | "fence.i" | "amoadd.w" | "amoadd.w.aq" | "amoadd.w.rl"
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| "amoadd.w.aqrl" | "lr.w" | "lr.w.aq" | "lr.w.rl" | "lr.w.aqrl" | "sc.w"
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| "sc.w.aq" | "sc.w.rl" | "sc.w.aqrl" => false,
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"j" | "jr" | "tail" | "ret" | "unimp" => true,
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@@ -904,6 +904,27 @@ fn process_instruction(instr: &str, args: &[Argument]) -> Vec<String> {
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let (rd, r1, r2) = rrr(args);
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only_if_no_write_to_zero(format!("tmp1, {rd} <== mul({r1}, {r2});"), rd)
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}
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"mulhsu" => {
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let (rd, r1, r2) = rrr(args);
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only_if_no_write_to_zero_vec(
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vec![
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format!("tmp1 <== to_signed({r1});"),
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// tmp2 is 1 if tmp1 is non-negative
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"tmp2 <== is_positive(tmp1 + 1);".into(),
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// If negative, convert to positive
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"skip_if_zero 0, tmp2;".into(),
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"tmp1 <=X= 0 - tmp1;".into(),
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format!("tmp1, {rd} <== mul(tmp1, {r2});"),
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// If was negative before, convert back to negative
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"skip_if_zero (1-tmp2), 2;".into(),
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"tmp1 <== is_equal_zero(tmp1);".into(),
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// If the lower bits are zero, return the two's complement,
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// otherwise return one's complement.
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format!("{rd} <== wrap_signed(-{rd} - 1 + tmp1);"),
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],
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rd,
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)
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}
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"divu" => {
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let (rd, r1, r2) = rrr(args);
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only_if_no_write_to_zero(format!("{rd}, tmp1 <== divremu({r1}, {r2});"), rd)
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151
riscv/tests/instruction_tests/generated/mulhsu.S
Normal file
151
riscv/tests/instruction_tests/generated/mulhsu.S
Normal file
@@ -0,0 +1,151 @@
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# 0 "sources/mulhsu.S"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "/usr/include/stdc-predef.h" 1 3 4
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# 0 "<command-line>" 2
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# 1 "sources/mulhsu.S"
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# See LICENSE for license details.
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#*****************************************************************************
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# mulhsu.S
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#-----------------------------------------------------------------------------
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# Test mulhsu instruction.
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# 1 "sources/riscv_test.h" 1
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# 11 "sources/mulhsu.S" 2
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# 1 "sources/test_macros.h" 1
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#-----------------------------------------------------------------------
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# Helper macros
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#-----------------------------------------------------------------------
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# 20 "sources/test_macros.h"
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# We use a macro hack to simpify code generation for various numbers
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# of bubble cycles.
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# 36 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# RV64UI MACROS
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Tests for instructions with immediate operand
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#-----------------------------------------------------------------------
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# 92 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Tests for vector config instructions
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#-----------------------------------------------------------------------
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# 120 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Tests for an instruction with register operands
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#-----------------------------------------------------------------------
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# 148 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Tests for an instruction with register-register operands
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#-----------------------------------------------------------------------
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# 242 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Test memory instructions
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#-----------------------------------------------------------------------
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# 319 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Test branch instructions
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#-----------------------------------------------------------------------
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# 404 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Test jump instructions
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#-----------------------------------------------------------------------
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# 433 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# RV64UF MACROS
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Tests floating-point instructions
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#-----------------------------------------------------------------------
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# 569 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Pass and fail code (assumes test num is in x28)
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#-----------------------------------------------------------------------
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# 581 "sources/test_macros.h"
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#-----------------------------------------------------------------------
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# Test data section
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#-----------------------------------------------------------------------
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# 12 "sources/mulhsu.S" 2
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.globl __runtime_start; __runtime_start:
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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test_2: li x10, 2; ebreak; li x1, 0x00000000; li x2, 0x00000000; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 2; bne x3, x29, fail;;
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test_3: li x10, 3; ebreak; li x1, 0x00000001; li x2, 0x00000001; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 3; bne x3, x29, fail;;
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test_4: li x10, 4; ebreak; li x1, 0x00000003; li x2, 0x00000007; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 4; bne x3, x29, fail;;
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test_5: li x10, 5; ebreak; li x1, 0x00000000; li x2, 0xffff8000; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 5; bne x3, x29, fail;;
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test_6: li x10, 6; ebreak; li x1, 0x80000000; li x2, 0x00000000; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 6; bne x3, x29, fail;;
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test_7: li x10, 7; ebreak; li x1, 0x80000000; li x2, 0xffff8000; mulhsu x3, x1, x2;; li x29, 0x80004000; li x28, 7; bne x3, x29, fail;;
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test_30: li x10, 30; ebreak; li x1, 0xaaaaaaab; li x2, 0x0002fe7d; mulhsu x3, x1, x2;; li x29, 0xffff0081; li x28, 30; bne x3, x29, fail;;
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test_31: li x10, 31; ebreak; li x1, 0x0002fe7d; li x2, 0xaaaaaaab; mulhsu x3, x1, x2;; li x29, 0x0001fefe; li x28, 31; bne x3, x29, fail;;
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test_32: li x10, 32; ebreak; li x1, 0xff000000; li x2, 0xff000000; mulhsu x3, x1, x2;; li x29, 0xff010000; li x28, 32; bne x3, x29, fail;;
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test_33: li x10, 33; ebreak; li x1, 0xffffffff; li x2, 0xffffffff; mulhsu x3, x1, x2;; li x29, 0xffffffff; li x28, 33; bne x3, x29, fail;;
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test_34: li x10, 34; ebreak; li x1, 0xffffffff; li x2, 0x00000001; mulhsu x3, x1, x2;; li x29, 0xffffffff; li x28, 34; bne x3, x29, fail;;
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test_35: li x10, 35; ebreak; li x1, 0x00000001; li x2, 0xffffffff; mulhsu x3, x1, x2;; li x29, 0x00000000; li x28, 35; bne x3, x29, fail;;
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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test_8: li x10, 8; ebreak; li x1, 13<<20; li x2, 11<<20; mulhsu x1, x1, x2;; li x29, 36608; li x28, 8; bne x1, x29, fail;;
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test_9: li x10, 9; ebreak; li x1, 14<<20; li x2, 11<<20; mulhsu x2, x1, x2;; li x29, 39424; li x28, 9; bne x2, x29, fail;;
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test_10: li x10, 10; ebreak; li x1, 13<<20; mulhsu x1, x1, x1;; li x29, 43264; li x28, 10; bne x1, x29, fail;;
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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test_11: li x10, 11; ebreak; li x4, 0; test_11_l1: li x1, 13<<20; li x2, 11<<20; mulhsu x3, x1, x2; addi x6, x3, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, test_11_l1; li x29, 36608; li x28, 11; bne x6, x29, fail;;
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test_12: li x10, 12; ebreak; li x4, 0; test_12_l1: li x1, 14<<20; li x2, 11<<20; mulhsu x3, x1, x2; nop; addi x6, x3, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, test_12_l1; li x29, 39424; li x28, 12; bne x6, x29, fail;;
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test_13: li x10, 13; ebreak; li x4, 0; test_13_l1: li x1, 15<<20; li x2, 11<<20; mulhsu x3, x1, x2; nop; nop; addi x6, x3, 0; addi x4, x4, 1; li x5, 2; bne x4, x5, test_13_l1; li x29, 42240; li x28, 13; bne x6, x29, fail;;
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test_14: li x10, 14; ebreak; li x4, 0; test_14_l1: li x1, 13<<20; li x2, 11<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_14_l1; li x29, 36608; li x28, 14; bne x3, x29, fail;;
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test_15: li x10, 15; ebreak; li x4, 0; test_15_l1: li x1, 14<<20; li x2, 11<<20; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_15_l1; li x29, 39424; li x28, 15; bne x3, x29, fail;;
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test_16: li x10, 16; ebreak; li x4, 0; test_16_l1: li x1, 15<<20; li x2, 11<<20; nop; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_16_l1; li x29, 42240; li x28, 16; bne x3, x29, fail;;
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test_17: li x10, 17; ebreak; li x4, 0; test_17_l1: li x1, 13<<20; nop; li x2, 11<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_17_l1; li x29, 36608; li x28, 17; bne x3, x29, fail;;
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test_18: li x10, 18; ebreak; li x4, 0; test_18_l1: li x1, 14<<20; nop; li x2, 11<<20; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_18_l1; li x29, 39424; li x28, 18; bne x3, x29, fail;;
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test_19: li x10, 19; ebreak; li x4, 0; test_19_l1: li x1, 15<<20; nop; nop; li x2, 11<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_19_l1; li x29, 42240; li x28, 19; bne x3, x29, fail;;
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test_20: li x10, 20; ebreak; li x4, 0; test_20_l1: li x2, 11<<20; li x1, 13<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_20_l1; li x29, 36608; li x28, 20; bne x3, x29, fail;;
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test_21: li x10, 21; ebreak; li x4, 0; test_21_l1: li x2, 11<<20; li x1, 14<<20; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_21_l1; li x29, 39424; li x28, 21; bne x3, x29, fail;;
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test_22: li x10, 22; ebreak; li x4, 0; test_22_l1: li x2, 11<<20; li x1, 15<<20; nop; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_22_l1; li x29, 42240; li x28, 22; bne x3, x29, fail;;
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test_23: li x10, 23; ebreak; li x4, 0; test_23_l1: li x2, 11<<20; nop; li x1, 13<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_23_l1; li x29, 36608; li x28, 23; bne x3, x29, fail;;
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test_24: li x10, 24; ebreak; li x4, 0; test_24_l1: li x2, 11<<20; nop; li x1, 14<<20; nop; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_24_l1; li x29, 39424; li x28, 24; bne x3, x29, fail;;
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test_25: li x10, 25; ebreak; li x4, 0; test_25_l1: li x2, 11<<20; nop; nop; li x1, 15<<20; mulhsu x3, x1, x2; addi x4, x4, 1; li x5, 2; bne x4, x5, test_25_l1; li x29, 42240; li x28, 25; bne x3, x29, fail;;
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test_26: li x10, 26; ebreak; li x1, 31<<26; mulhsu x2, x0, x1;; li x29, 0; li x28, 26; bne x2, x29, fail;;
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test_27: li x10, 27; ebreak; li x1, 32<<26; mulhsu x2, x1, x0;; li x29, 0; li x28, 27; bne x2, x29, fail;;
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test_28: li x10, 28; ebreak; mulhsu x1, x0, x0;; li x29, 0; li x28, 28; bne x1, x29, fail;;
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test_29: li x10, 29; ebreak; li x1, 33<<20; li x2, 34<<20; mulhsu x0, x1, x2;; li x29, 0; li x28, 29; bne x0, x29, fail;;
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bne x0, x28, pass; fail: unimp;; pass: ___pass: j ___pass;
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.data
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.balign 4;
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83
riscv/tests/instruction_tests/sources/mulhsu.S
Normal file
83
riscv/tests/instruction_tests/sources/mulhsu.S
Normal file
@@ -0,0 +1,83 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# mulhsu.S
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#-----------------------------------------------------------------------------
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#
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# Test mulhsu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
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TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
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TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
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TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
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TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
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TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
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TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
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TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
||||
Reference in New Issue
Block a user