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https://github.com/zama-ai/tfhe-rs.git
synced 2026-01-08 22:28:01 -05:00
chore: fix typos
This commit is contained in:
@@ -31,7 +31,7 @@ impl KreyviumByteInput<FheUint8> for &FheUint8 {}
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/// representation of bits (u8 or FheUint8). To be able to compute FHE operations, it also owns
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/// an Option for a ServerKey.
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/// Since the original Kreyvium registers' sizes are not a multiple of 8, these registers (which
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/// store byte-like objects) have a size that is the eigth of the closest multiple of 8 above the
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/// store byte-like objects) have a size that is the eighth of the closest multiple of 8 above the
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/// originals' sizes.
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pub struct KreyviumStreamByte<T> {
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a_byte: StaticByteDeque<12, T>,
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@@ -31,7 +31,7 @@ impl TriviumByteInput<FheUint8> for &FheUint8 {}
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/// representation of bits (u8 or FheUint8). To be able to compute FHE operations, it also owns
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/// an Option for a ServerKey.
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/// Since the original Trivium registers' sizes are not a multiple of 8, these registers (which
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/// store byte-like objects) have a size that is the eigth of the closest multiple of 8 above the
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/// store byte-like objects) have a size that is the eighth of the closest multiple of 8 above the
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/// originals' sizes.
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pub struct TriviumStreamByte<T> {
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a_byte: StaticByteDeque<12, T>,
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@@ -141,7 +141,7 @@ use tfhe::integer::gen_keys_radix;
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use tfhe::shortint::parameters::PARAM_MESSAGE_2_CARRY_2;
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fn main() {
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// We create keys for radix represention to create 16 bits integers
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// We create keys for radix representation to create 16 bits integers
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// using 8 blocks of 2 bits
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let (cks, sks) = gen_keys_radix(PARAM_MESSAGE_2_CARRY_2, 8);
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@@ -809,7 +809,7 @@ where
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// Shifts and rotations are special cases where the right hand side
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// is for now, required to be a unsigned integer type.
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// And its contrains are a bit relaxed: rhs does not needs to have the same
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// And its constraints are a bit relaxed: rhs does not needs to have the same
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// amount a bits.
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macro_rules! generic_integer_impl_shift_rotate (
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($rust_trait_name:ident($rust_trait_method:ident) => $key_method:ident) => {
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@@ -57,7 +57,7 @@ impl AsRef<crate::integer::ServerKey> for ServerKey {
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// serde has a `rc` feature to allow deriving on Arc and Rc types
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// but activating it in our lib would mean also activate it for all the dependency stack,
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// so tfhe-rs users would have this feature enabled on our behalf and we don't want that
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// so whe implement the serialization / deseriazation ourselves.
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// so we implement the serialization / deseriazation ourselves.
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//
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// In the case of our ServerKey, this is fine, we expect programs to only
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// serialize and deserialize the same server key only once.
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@@ -177,7 +177,7 @@ pub trait IntegerRadixCiphertext: IntegerCiphertext + Sync + Send + From<Vec<Cip
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self.blocks().iter().all(|block| block.carry_is_empty())
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}
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/// Returns wether the ciphertext _seems_ like it holds/encrypts
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/// Returns whether the ciphertext _seems_ like it holds/encrypts
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/// a boolean (0 or 1) value.
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///
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/// Since it uses degree to do so, it will not
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@@ -717,7 +717,7 @@ where {
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// from the ciphertext that can represent the scalar value
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//
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// - The other part is to compare the ciphertext blocks not considered for the sign
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// computation with zero, and create a signle sign block from that.
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// computation with zero, and create a single sign block from that.
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//
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// The smaller the scalar value is comparaed to the ciphertext num bits encrypted,
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// the more the comparisons with zeros we have to do,
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@@ -434,8 +434,8 @@ where {
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.key
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.apply_lookup_table(last_block, &padding_block_creator_lut);
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let new_lew = num_blocks + ct.blocks.len();
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ct.blocks.resize(new_lew, padding_block);
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let new_len = num_blocks + ct.blocks.len();
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ct.blocks.resize(new_len, padding_block);
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}
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/// Extends the most significant blocks using the sign bit.
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@@ -689,7 +689,7 @@ impl ServerKey {
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T: SignedReciprocable,
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<<T as SignedReciprocable>::Unsigned as Reciprocable>::DoublePrecision: Send,
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{
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assert_ne!(divisor, T::ZERO, "Cannot devide by zero");
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assert_ne!(divisor, T::ZERO, "Cannot divide by zero");
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let numerator_bits = self.key.message_modulus.0.ilog2() * numerator.blocks.len() as u32;
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@@ -164,7 +164,7 @@ impl ServerKey {
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// if there is only 1 bit in the msg part, it means shift_within block is 0
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// thus only rotations is required.
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// We still need to padd with the value of the sign bit.
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// We still need to pad with the value of the sign bit.
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// And here since a block only has 1 bit of message
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// we can optimize things by not doing the pbs to extract this sign bit
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let sign_bit = ct.blocks()[num_blocks - rotations - 1].clone();
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@@ -176,7 +176,7 @@ impl ServerKey {
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let message_modulus = self.key.message_modulus.0 as u64;
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// In the artithemtic shift case we have to padd with the value of the sign bit.
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// In the artithemtic shift case we have to pad with the value of the sign bit.
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//
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// This creates the need for a different shifting lut than in the logical shift case
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// and also we need another PBS to create the padding block.
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@@ -199,7 +199,7 @@ impl ServerKey {
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});
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let last_block = &ct.blocks()[num_blocks - rotations - 1];
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let padd_block_creator_lut = self.key.generate_lookup_table(|x| {
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let pad_block_creator_lut = self.key.generate_lookup_table(|x| {
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let x = x % message_modulus;
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let x_sign_bit = x >> (num_bits_in_block - 1) & 1;
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// padding is a message full of 1 if sign bit is one
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@@ -211,7 +211,7 @@ impl ServerKey {
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|| self.key.apply_lookup_table(last_block, &last_block_lut),
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|| {
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self.key
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.apply_lookup_table(last_block, &padd_block_creator_lut)
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.apply_lookup_table(last_block, &pad_block_creator_lut)
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},
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)
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};
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@@ -175,10 +175,10 @@ fn rotate_left_helper(value: i64, n: u32, actual_bit_size: u32) -> i64 {
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// If the sign bit after rotation is one,
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// then all bits above it needs to be one
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let new_sign_bit = (tmp >> (actual_bit_size - 1)) & 1;
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let mut padd = -new_sign_bit;
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padd <<= actual_bit_size; // only bits above actual_bit_size should be set
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let mut pad = -new_sign_bit;
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pad <<= actual_bit_size; // only bits above actual_bit_size should be set
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padd | tmp
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pad | tmp
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}
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/// helper function to do a rotate right when the type used to store
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@@ -213,10 +213,10 @@ fn rotate_right_helper(value: i64, n: u32, actual_bit_size: u32) -> i64 {
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// If the sign bit after rotation is one,
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// then all bits above it needs to be one
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let new_sign_bit = (tmp >> (actual_bit_size - 1)) & 1;
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let mut padd = -new_sign_bit;
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padd <<= actual_bit_size; // only bits above actual_bit_size should be set
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let mut pad = -new_sign_bit;
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pad <<= actual_bit_size; // only bits above actual_bit_size should be set
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padd | tmp
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pad | tmp
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}
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/// Returns an array filled with random values such that:
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@@ -1833,7 +1833,7 @@ fn integer_signed_unchecked_scalar_div_rem(param: impl Into<PBSParameters>) {
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assert_eq!(r, signed_rem_under_modulus(clear_0, d, modulus));
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}
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// 3 / -3 taks the second branch in the if else if series
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// 3 / -3 takes the second branch in the if else if series
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for d in [3, -3] {
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{
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let neg_clear_0 = rng.gen_range(-modulus..=0);
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@@ -221,7 +221,7 @@ mod test_integer {
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safe_serialize(&ct_list, &mut buffer, 1 << 40).unwrap();
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for paremeter_set in [
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for parameter_set in [
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(
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PARAM_MESSAGE_3_CARRY_3_KS_PBS.into(),
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ListSizeConstraint::exact_size(3),
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@@ -248,12 +248,12 @@ mod test_integer {
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assert!(safe_deserialize_conformant::<CompactFheUint8List>(
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buffer.as_slice(),
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1 << 20,
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paremeter_set,
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parameter_set,
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)
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.is_err());
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}
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for paremeter_set in [
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for parameter_set in [
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(
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PARAM_MESSAGE_2_CARRY_2_KS_PBS.into(),
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ListSizeConstraint::exact_size(3),
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@@ -273,7 +273,7 @@ mod test_integer {
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]
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.iter()
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{
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assert!(ct_list.is_conformant(paremeter_set));
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assert!(ct_list.is_conformant(parameter_set));
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}
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let ct2 = safe_deserialize_conformant::<CompactFheUint8List>(
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