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feat(hpu): Soft Reset Support and fix some runtime registers

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This commit is contained in:
Helder Campos
2025-06-30 17:04:19 +01:00
committed by Pierre Gardrat
parent 3b48ef301e
commit a83c92f28f
3 changed files with 38 additions and 2 deletions
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12
backends/tfhe-hpu-backend/config_store/v80/hpu_regif_core_cfg_3in3.toml
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@@ -49,3 +49,15 @@ offset= 0x10
read_access="Read"
write_access="Write"
duplicate=["_pc0_lsb", "_pc0_msb", "_pc1_lsb", "_pc1_msb", "_pc2_lsb", "_pc2_msb", "_pc3_lsb", "_pc3_msb", "_pc4_lsb", "_pc4_msb", "_pc5_lsb", "_pc5_msb", "_pc6_lsb", "_pc6_msb", "_pc7_lsb", "_pc7_msb", "_pc8_lsb", "_pc8_msb", "_pc9_lsb", "_pc9_msb", "_pc10_lsb", "_pc10_msb", "_pc11_lsb", "_pc11_msb", "_pc12_lsb", "_pc12_msb", "_pc13_lsb", "_pc13_msb", "_pc14_lsb", "_pc14_msb", "_pc15_lsb", "_pc15_msb"]
[section.hpu_reset]
description="Used to control the HPU soft reset"
offset= 0x100
[section.hpu_reset.register.trigger]
description="A soft reset for the whole HPU reconfigurable logic"
owner="Kernel"
read_access="Read"
write_access="WriteNotify"
field.request = { size_b=1, offset_b=0 , default={Cst=0}, description="request"}
field.done = { size_b=1, offset_b=31 , default={Cst=0}, description="done"}

4
backends/tfhe-hpu-backend/src/interface/rtl/runtime.rs
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@@ -354,7 +354,7 @@ impl InfoPePbs {
}
pub fn update_load_bsk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
(1..16).for_each(|i| {
(0..16).for_each(|i| {
let reg_name = format!("runtime_3in3::pep_load_bsk_rcp_dur_pc{i}");
let reg = regmap
.register()
@@ -364,7 +364,7 @@ impl InfoPePbs {
});
}
pub fn update_load_ksk_rcp_dur(&mut self, ffi_hw: &mut ffi::HpuHw, regmap: &FlatRegmap) {
(1..16).for_each(|i| {
(0..16).for_each(|i| {
let reg_name = format!("runtime_1in3::pep_load_ksk_rcp_dur_pc{i}");
let reg = regmap
.register()

24
backends/tfhe-hpu-backend/src/utils/hputil.rs
View File

@@ -79,6 +79,9 @@ pub enum Command {
#[arg(short, long, default_value_t = String::from("trace.json"))]
file: String,
},
#[clap(about = "Resets all HPU processing logic")]
SoftReset {},
}
#[derive(Clone, Debug, ValueEnum)]
@@ -286,5 +289,26 @@ fn main() {
serde_json::to_writer_pretty(file.make_writer(), &parsed)
.expect("Could not write trace dump");
}
Command::SoftReset {} => {
let soft_reset = regmap
.register()
.get("hpu_reset::trigger")
.expect("The current HPU does not support soft reset.");
let soft_reset_addr = *soft_reset.offset() as u64;
for reset in [true, false].into_iter() {
hpu_hw.write_reg(soft_reset_addr, reset as u32);
loop {
let done = {
let val = hpu_hw.read_reg(soft_reset_addr);
let fields = soft_reset.as_field(val);
*fields.get("done").expect("Unknown field") != 0
};
if done == reset {
break;
}
}
}
}
}
}