mirror of
https://github.com/tinygrad/tinygrad.git
synced 2026-01-09 15:08:02 -05:00
am: rdna 4 support (#9621)
* hm * fix * return this * fine * g * ruff * fix
This commit is contained in:
nimlgen
@@ -294,6 +294,7 @@ generate_vfio() {
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generate_am() {
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clang2py -k cdefstum \
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extra/amdpci/headers/v11_structs.h \
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extra/amdpci/headers/v12_structs.h \
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extra/amdpci/headers/amdgpu_vm.h \
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extra/amdpci/headers/discovery.h \
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extra/amdpci/headers/amdgpu_ucode.h \
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@@ -346,6 +347,13 @@ generate_am() {
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-o $BASE/am/mp_13_0_0.py
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fixup $BASE/am/mp_13_0_0.py
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14_0_3 reuses 14_0_2
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clang2py -k cdefstum \
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extra/amdpci/headers/mp_14_0_2_offset.h \
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extra/amdpci/headers/mp_14_0_2_sh_mask.h \
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-o $BASE/am/mp_14_0_3.py
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fixup $BASE/am/mp_14_0_3.py
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clang2py -k cdefstum \
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extra/amdpci/headers/mp_11_0_offset.h \
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extra/amdpci/headers/mp_11_0_sh_mask.h \
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@@ -416,6 +424,12 @@ generate_am() {
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-o $BASE/am/nbio_2_3_0.py
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fixup $BASE/am/nbio_2_3_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/mmhub_4_1_0_offset.h \
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extra/amdpci/headers/mmhub_4_1_0_sh_mask.h \
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-o $BASE/am/mmhub_4_1_0.py
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fixup $BASE/am/mmhub_4_1_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/nbio_4_3_0_offset.h \
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extra/amdpci/headers/nbio_4_3_0_sh_mask.h \
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@@ -440,6 +454,12 @@ generate_am() {
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-o $BASE/am/osssys_6_0_0.py
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fixup $BASE/am/osssys_6_0_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/osssys_7_0_0_offset.h \
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extra/amdpci/headers/osssys_7_0_0_sh_mask.h \
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-o $BASE/am/osssys_7_0_0.py
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fixup $BASE/am/osssys_7_0_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/smu_v13_0_0_ppsmc.h \
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extra/amdpci/headers/smu13_driver_if_v13_0_0.h \
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@@ -447,11 +467,27 @@ generate_am() {
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-o $BASE/am/smu_v13_0_0.py
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fixup $BASE/am/smu_v13_0_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/smu_v14_0_0_pmfw.h \
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extra/amdpci/headers/smu_v14_0_2_ppsmc.h \
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extra/amdpci/headers/smu14_driver_if_v14_0_0.h \
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extra/amdpci/headers/smu14_driver_if_v14_0.h \
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extra/amdpci/headers/amdgpu_smu.h \
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--clang-args="-include stdint.h" \
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-o $BASE/am/smu_v14_0_3.py
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fixup $BASE/am/smu_v14_0_3.py
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clang2py -k cdefstum \
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extra/amdpci/headers/hdp_6_0_0_offset.h \
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extra/amdpci/headers/hdp_6_0_0_sh_mask.h \
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-o $BASE/am/hdp_6_0_0.py
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fixup $BASE/am/hdp_6_0_0.py
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clang2py -k cdefstum \
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extra/amdpci/headers/hdp_7_0_0_offset.h \
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extra/amdpci/headers/hdp_7_0_0_sh_mask.h \
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-o $BASE/am/hdp_7_0_0.py
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fixup $BASE/am/hdp_7_0_0.py
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}
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generate_sqtt() {
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@@ -21,395 +21,426 @@
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*
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*/
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#ifndef _DISCOVERY_H_
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#define _DISCOVERY_H_
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#define uint32_t unsigned int
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#define uint8_t unsigned char
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#define uint16_t unsigned short
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#define uint64_t unsigned long long
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#define u32 unsigned int
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#define u8 unsigned char
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#define u16 unsigned short
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#define u64 unsigned long long
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#define bool unsigned char
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#define PSP_HEADER_SIZE 256
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#define BINARY_SIGNATURE 0x28211407
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#define DISCOVERY_TABLE_SIGNATURE 0x53445049
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#define GC_TABLE_ID 0x4347
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#define HARVEST_TABLE_SIGNATURE 0x56524148
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#define VCN_INFO_TABLE_ID 0x004E4356
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#define MALL_INFO_TABLE_ID 0x4C4C414D
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#define NPS_INFO_TABLE_ID 0x0053504E
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typedef enum {
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IP_DISCOVERY = 0,
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GC,
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HARVEST_INFO,
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VCN_INFO,
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MALL_INFO,
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NPS_INFO,
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TOTAL_TABLES = 6
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} table;
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#pragma pack(1)
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typedef struct table_info
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{
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uint16_t offset; /* Byte offset */
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uint16_t checksum; /* Byte sum of the table */
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uint16_t size; /* Table size */
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uint16_t padding;
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} table_info;
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typedef struct binary_header
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{
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/* psp structure should go at the top of this structure */
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uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
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uint16_t version_major;
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uint16_t version_minor;
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uint16_t binary_checksum; /* Byte sum of the binary after this field */
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uint16_t binary_size; /* Binary Size*/
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table_info table_list[TOTAL_TABLES];
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} binary_header;
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typedef struct die_info
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{
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uint16_t die_id;
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uint16_t die_offset; /* Points to the corresponding die_header structure */
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} die_info;
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typedef struct ip_discovery_header
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{
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uint32_t signature; /* Table Signature */
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uint16_t version; /* Table Version */
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uint16_t size; /* Table Size */
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uint32_t id; /* Table ID */
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uint16_t num_dies; /* Number of Dies */
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die_info die_info[16]; /* list die information for up to 16 dies */
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union {
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uint16_t padding[1]; /* version <= 3 */
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struct { /* version == 4 */
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uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */
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uint8_t reserved : 7;
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uint8_t reserved2;
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};
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};
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} ip_discovery_header;
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typedef struct ip
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{
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uint16_t hw_id; /* Hardware ID */
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uint8_t number_instance; /* instance of the IP */
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uint8_t num_base_address; /* Number of Base Addresses */
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uint8_t major; /* HCID Major */
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uint8_t minor; /* HCID Minor */
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uint8_t revision; /* HCID Revision */
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#if defined(__BIG_ENDIAN)
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uint8_t reserved : 4; /* Placeholder field */
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uint8_t harvest : 4; /* Harvest */
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#else
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uint8_t harvest : 4; /* Harvest */
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uint8_t reserved : 4; /* Placeholder field */
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#endif
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uint32_t base_address[1]; /* variable number of Addresses */
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} ip;
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typedef struct ip_v3
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{
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uint16_t hw_id; /* Hardware ID */
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uint8_t instance_number; /* Instance number for the IP */
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uint8_t num_base_address; /* Number of base addresses*/
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uint8_t major; /* Hardware ID.major version */
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uint8_t minor; /* Hardware ID.minor version */
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uint8_t revision; /* Hardware ID.revision version */
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#if defined(__BIG_ENDIAN)
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uint8_t variant : 4; /* HW variant */
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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#else
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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uint8_t variant : 4; /* HW variant */
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#endif
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uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/
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} ip_v3;
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typedef struct ip_v4 {
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uint16_t hw_id; /* Hardware ID */
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uint8_t instance_number; /* Instance number for the IP */
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uint8_t num_base_address; /* Number of base addresses*/
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uint8_t major; /* Hardware ID.major version */
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uint8_t minor; /* Hardware ID.minor version */
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uint8_t revision; /* Hardware ID.revision version */
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#if defined(LITTLEENDIAN_CPU)
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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uint8_t variant : 4; /* HW variant */
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#elif defined(BIGENDIAN_CPU)
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uint8_t variant : 4; /* HW variant */
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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#endif
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uint64_t base_address_64[1];
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} ip_v4;
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typedef struct die_header
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{
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uint16_t die_id;
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uint16_t num_ips;
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} die_header;
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typedef struct ip_structure
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{
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ip_discovery_header* header;
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struct die
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{
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die_header *die_header;
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union
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{
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ip *ip_list;
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ip_v3 *ip_v3_list;
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ip_v4 *ip_v4_list;
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}; /* IP list. Variable size*/
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} die;
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} ip_structure;
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struct gpu_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size; /* size of the entire header+data in bytes */
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};
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struct gc_info_v1_0 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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};
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struct gc_info_v1_1 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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};
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struct gc_info_v1_2 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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uint32_t gc_num_tcp_per_wpg;
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uint32_t gc_tcp_l1_size;
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uint32_t gc_num_sqc_per_wgp;
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uint32_t gc_l1_instruction_cache_size_per_sqc;
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uint32_t gc_l1_data_cache_size_per_sqc;
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uint32_t gc_gl1c_per_sa;
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uint32_t gc_gl1c_size_per_instance;
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uint32_t gc_gl2c_per_gpu;
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};
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struct gc_info_v2_0 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
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uint32_t gc_num_sh_per_se;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_tccs;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_packer_per_sc;
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};
|
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|
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struct gc_info_v2_1 {
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struct gpu_info_header header;
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|
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
|
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uint32_t gc_num_sh_per_se;
|
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uint32_t gc_num_rb_per_se;
|
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uint32_t gc_num_tccs;
|
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uint32_t gc_num_gprs;
|
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uint32_t gc_num_max_gs_thds;
|
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uint32_t gc_gs_table_depth;
|
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uint32_t gc_gsprim_buff_depth;
|
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uint32_t gc_parameter_cache_depth;
|
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uint32_t gc_double_offchip_lds_buffer;
|
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uint32_t gc_wave_size;
|
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uint32_t gc_max_waves_per_simd;
|
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uint32_t gc_max_scratch_slots_per_cu;
|
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uint32_t gc_lds_size;
|
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uint32_t gc_num_sc_per_se;
|
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uint32_t gc_num_packer_per_sc;
|
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/* new for v2_1 */
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uint32_t gc_num_tcp_per_sh;
|
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uint32_t gc_tcp_size_per_cu;
|
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uint32_t gc_num_sdp_interface;
|
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uint32_t gc_num_cu_per_sqc;
|
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uint32_t gc_instruction_cache_size_per_sqc;
|
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uint32_t gc_scalar_data_cache_size_per_sqc;
|
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uint32_t gc_tcc_size;
|
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};
|
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|
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typedef struct harvest_info_header {
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uint32_t signature; /* Table Signature */
|
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uint32_t version; /* Table Version */
|
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} harvest_info_header;
|
||||
|
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typedef struct harvest_info {
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uint16_t hw_id; /* Hardware ID */
|
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uint8_t number_instance; /* Instance of the IP */
|
||||
uint8_t reserved; /* Reserved for alignment */
|
||||
} harvest_info;
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||||
|
||||
typedef struct harvest_table {
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harvest_info_header header;
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harvest_info list[32];
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||||
} harvest_table;
|
||||
|
||||
struct mall_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct mall_info_v1_0 {
|
||||
struct mall_info_header header;
|
||||
uint32_t mall_size_per_m;
|
||||
uint32_t m_s_present;
|
||||
uint32_t m_half_use;
|
||||
uint32_t m_mall_config;
|
||||
uint32_t reserved[5];
|
||||
};
|
||||
|
||||
struct mall_info_v2_0 {
|
||||
struct mall_info_header header;
|
||||
uint32_t mall_size_per_umc;
|
||||
uint32_t reserved[8];
|
||||
};
|
||||
|
||||
#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
|
||||
|
||||
struct vcn_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct vcn_instance_info_v1_0
|
||||
{
|
||||
uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
|
||||
union _fuse_data {
|
||||
struct {
|
||||
uint32_t av1_disabled : 1;
|
||||
uint32_t vp9_disabled : 1;
|
||||
uint32_t hevc_disabled : 1;
|
||||
uint32_t h264_disabled : 1;
|
||||
uint32_t reserved : 28;
|
||||
} bits;
|
||||
uint32_t all_bits;
|
||||
} fuse_data;
|
||||
uint32_t reserved[2];
|
||||
};
|
||||
|
||||
struct vcn_info_v1_0 {
|
||||
struct vcn_info_header header;
|
||||
uint32_t num_of_instances; /* number of entries used in instance_info below*/
|
||||
struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
|
||||
uint32_t reserved[4];
|
||||
};
|
||||
|
||||
#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12
|
||||
|
||||
struct nps_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */
|
||||
};
|
||||
|
||||
struct nps_instance_info_v1_0 {
|
||||
uint64_t base_address;
|
||||
uint64_t limit_address;
|
||||
};
|
||||
|
||||
struct nps_info_v1_0 {
|
||||
struct nps_info_header header;
|
||||
uint32_t nps_type;
|
||||
uint32_t count;
|
||||
struct nps_instance_info_v1_0
|
||||
instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES];
|
||||
};
|
||||
|
||||
enum amd_hw_ip_block_type {
|
||||
#ifndef _DISCOVERY_H_
|
||||
#define _DISCOVERY_H_
|
||||
|
||||
#define PSP_HEADER_SIZE 256
|
||||
#define BINARY_SIGNATURE 0x28211407
|
||||
#define DISCOVERY_TABLE_SIGNATURE 0x53445049
|
||||
#define GC_TABLE_ID 0x4347
|
||||
#define HARVEST_TABLE_SIGNATURE 0x56524148
|
||||
#define VCN_INFO_TABLE_ID 0x004E4356
|
||||
#define MALL_INFO_TABLE_ID 0x4C4C414D
|
||||
#define NPS_INFO_TABLE_ID 0x0053504E
|
||||
|
||||
typedef enum {
|
||||
IP_DISCOVERY = 0,
|
||||
GC,
|
||||
HARVEST_INFO,
|
||||
VCN_INFO,
|
||||
MALL_INFO,
|
||||
NPS_INFO,
|
||||
TOTAL_TABLES = 6
|
||||
} table;
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct table_info
|
||||
{
|
||||
uint16_t offset; /* Byte offset */
|
||||
uint16_t checksum; /* Byte sum of the table */
|
||||
uint16_t size; /* Table size */
|
||||
uint16_t padding;
|
||||
} table_info;
|
||||
|
||||
typedef struct binary_header
|
||||
{
|
||||
/* psp structure should go at the top of this structure */
|
||||
uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
|
||||
uint16_t version_major;
|
||||
uint16_t version_minor;
|
||||
uint16_t binary_checksum; /* Byte sum of the binary after this field */
|
||||
uint16_t binary_size; /* Binary Size*/
|
||||
table_info table_list[TOTAL_TABLES];
|
||||
} binary_header;
|
||||
|
||||
typedef struct die_info
|
||||
{
|
||||
uint16_t die_id;
|
||||
uint16_t die_offset; /* Points to the corresponding die_header structure */
|
||||
} die_info;
|
||||
|
||||
|
||||
typedef struct ip_discovery_header
|
||||
{
|
||||
uint32_t signature; /* Table Signature */
|
||||
uint16_t version; /* Table Version */
|
||||
uint16_t size; /* Table Size */
|
||||
uint32_t id; /* Table ID */
|
||||
uint16_t num_dies; /* Number of Dies */
|
||||
die_info die_info[16]; /* list die information for up to 16 dies */
|
||||
union {
|
||||
uint16_t padding[1]; /* version <= 3 */
|
||||
struct { /* version == 4 */
|
||||
uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */
|
||||
uint8_t reserved : 7;
|
||||
uint8_t reserved2;
|
||||
};
|
||||
};
|
||||
} ip_discovery_header;
|
||||
|
||||
typedef struct ip
|
||||
{
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t number_instance; /* instance of the IP */
|
||||
uint8_t num_base_address; /* Number of Base Addresses */
|
||||
uint8_t major; /* HCID Major */
|
||||
uint8_t minor; /* HCID Minor */
|
||||
uint8_t revision; /* HCID Revision */
|
||||
#if defined(__BIG_ENDIAN)
|
||||
uint8_t reserved : 4; /* Placeholder field */
|
||||
uint8_t harvest : 4; /* Harvest */
|
||||
#else
|
||||
uint8_t harvest : 4; /* Harvest */
|
||||
uint8_t reserved : 4; /* Placeholder field */
|
||||
#endif
|
||||
uint32_t base_address[]; /* variable number of Addresses */
|
||||
} ip;
|
||||
|
||||
typedef struct ip_v3
|
||||
{
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t instance_number; /* Instance number for the IP */
|
||||
uint8_t num_base_address; /* Number of base addresses*/
|
||||
uint8_t major; /* Hardware ID.major version */
|
||||
uint8_t minor; /* Hardware ID.minor version */
|
||||
uint8_t revision; /* Hardware ID.revision version */
|
||||
#if defined(__BIG_ENDIAN)
|
||||
uint8_t variant : 4; /* HW variant */
|
||||
uint8_t sub_revision : 4; /* HCID Sub-Revision */
|
||||
#else
|
||||
uint8_t sub_revision : 4; /* HCID Sub-Revision */
|
||||
uint8_t variant : 4; /* HW variant */
|
||||
#endif
|
||||
uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/
|
||||
} ip_v3;
|
||||
|
||||
typedef struct ip_v4 {
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t instance_number; /* Instance number for the IP */
|
||||
uint8_t num_base_address; /* Number of base addresses*/
|
||||
uint8_t major; /* Hardware ID.major version */
|
||||
uint8_t minor; /* Hardware ID.minor version */
|
||||
uint8_t revision; /* Hardware ID.revision version */
|
||||
#if defined(LITTLEENDIAN_CPU)
|
||||
uint8_t sub_revision : 4; /* HCID Sub-Revision */
|
||||
uint8_t variant : 4; /* HW variant */
|
||||
#elif defined(BIGENDIAN_CPU)
|
||||
uint8_t variant : 4; /* HW variant */
|
||||
uint8_t sub_revision : 4; /* HCID Sub-Revision */
|
||||
#endif
|
||||
} ip_v4;
|
||||
|
||||
typedef struct die_header
|
||||
{
|
||||
uint16_t die_id;
|
||||
uint16_t num_ips;
|
||||
} die_header;
|
||||
|
||||
typedef struct ip_structure
|
||||
{
|
||||
ip_discovery_header* header;
|
||||
struct die
|
||||
{
|
||||
die_header *die_header;
|
||||
union
|
||||
{
|
||||
ip *ip_list;
|
||||
ip_v3 *ip_v3_list;
|
||||
ip_v4 *ip_v4_list;
|
||||
}; /* IP list. Variable size*/
|
||||
} die;
|
||||
} ip_structure;
|
||||
|
||||
struct gpu_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct gc_info_v1_0 {
|
||||
struct gpu_info_header header;
|
||||
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_wgp0_per_sa;
|
||||
uint32_t gc_num_wgp1_per_sa;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_gl2c;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_sa_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
uint32_t gc_num_gl2a;
|
||||
};
|
||||
|
||||
struct gc_info_v1_1 {
|
||||
struct gpu_info_header header;
|
||||
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_wgp0_per_sa;
|
||||
uint32_t gc_num_wgp1_per_sa;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_gl2c;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_sa_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
uint32_t gc_num_gl2a;
|
||||
uint32_t gc_num_tcp_per_sa;
|
||||
uint32_t gc_num_sdp_interface;
|
||||
uint32_t gc_num_tcps;
|
||||
};
|
||||
|
||||
struct gc_info_v1_2 {
|
||||
struct gpu_info_header header;
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_wgp0_per_sa;
|
||||
uint32_t gc_num_wgp1_per_sa;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_gl2c;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_sa_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
uint32_t gc_num_gl2a;
|
||||
uint32_t gc_num_tcp_per_sa;
|
||||
uint32_t gc_num_sdp_interface;
|
||||
uint32_t gc_num_tcps;
|
||||
uint32_t gc_num_tcp_per_wpg;
|
||||
uint32_t gc_tcp_l1_size;
|
||||
uint32_t gc_num_sqc_per_wgp;
|
||||
uint32_t gc_l1_instruction_cache_size_per_sqc;
|
||||
uint32_t gc_l1_data_cache_size_per_sqc;
|
||||
uint32_t gc_gl1c_per_sa;
|
||||
uint32_t gc_gl1c_size_per_instance;
|
||||
uint32_t gc_gl2c_per_gpu;
|
||||
};
|
||||
|
||||
struct gc_info_v1_3 {
|
||||
struct gpu_info_header header;
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_wgp0_per_sa;
|
||||
uint32_t gc_num_wgp1_per_sa;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_gl2c;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_sa_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
uint32_t gc_num_gl2a;
|
||||
uint32_t gc_num_tcp_per_sa;
|
||||
uint32_t gc_num_sdp_interface;
|
||||
uint32_t gc_num_tcps;
|
||||
uint32_t gc_num_tcp_per_wpg;
|
||||
uint32_t gc_tcp_l1_size;
|
||||
uint32_t gc_num_sqc_per_wgp;
|
||||
uint32_t gc_l1_instruction_cache_size_per_sqc;
|
||||
uint32_t gc_l1_data_cache_size_per_sqc;
|
||||
uint32_t gc_gl1c_per_sa;
|
||||
uint32_t gc_gl1c_size_per_instance;
|
||||
uint32_t gc_gl2c_per_gpu;
|
||||
uint32_t gc_tcp_size_per_cu;
|
||||
uint32_t gc_tcp_cache_line_size;
|
||||
uint32_t gc_instruction_cache_size_per_sqc;
|
||||
uint32_t gc_instruction_cache_line_size;
|
||||
uint32_t gc_scalar_data_cache_size_per_sqc;
|
||||
uint32_t gc_scalar_data_cache_line_size;
|
||||
uint32_t gc_tcc_size;
|
||||
uint32_t gc_tcc_cache_line_size;
|
||||
};
|
||||
|
||||
struct gc_info_v2_0 {
|
||||
struct gpu_info_header header;
|
||||
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_cu_per_sh;
|
||||
uint32_t gc_num_sh_per_se;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_tccs;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
};
|
||||
|
||||
struct gc_info_v2_1 {
|
||||
struct gpu_info_header header;
|
||||
|
||||
uint32_t gc_num_se;
|
||||
uint32_t gc_num_cu_per_sh;
|
||||
uint32_t gc_num_sh_per_se;
|
||||
uint32_t gc_num_rb_per_se;
|
||||
uint32_t gc_num_tccs;
|
||||
uint32_t gc_num_gprs;
|
||||
uint32_t gc_num_max_gs_thds;
|
||||
uint32_t gc_gs_table_depth;
|
||||
uint32_t gc_gsprim_buff_depth;
|
||||
uint32_t gc_parameter_cache_depth;
|
||||
uint32_t gc_double_offchip_lds_buffer;
|
||||
uint32_t gc_wave_size;
|
||||
uint32_t gc_max_waves_per_simd;
|
||||
uint32_t gc_max_scratch_slots_per_cu;
|
||||
uint32_t gc_lds_size;
|
||||
uint32_t gc_num_sc_per_se;
|
||||
uint32_t gc_num_packer_per_sc;
|
||||
/* new for v2_1 */
|
||||
uint32_t gc_num_tcp_per_sh;
|
||||
uint32_t gc_tcp_size_per_cu;
|
||||
uint32_t gc_num_sdp_interface;
|
||||
uint32_t gc_num_cu_per_sqc;
|
||||
uint32_t gc_instruction_cache_size_per_sqc;
|
||||
uint32_t gc_scalar_data_cache_size_per_sqc;
|
||||
uint32_t gc_tcc_size;
|
||||
};
|
||||
|
||||
typedef struct harvest_info_header {
|
||||
uint32_t signature; /* Table Signature */
|
||||
uint32_t version; /* Table Version */
|
||||
} harvest_info_header;
|
||||
|
||||
typedef struct harvest_info {
|
||||
uint16_t hw_id; /* Hardware ID */
|
||||
uint8_t number_instance; /* Instance of the IP */
|
||||
uint8_t reserved; /* Reserved for alignment */
|
||||
} harvest_info;
|
||||
|
||||
typedef struct harvest_table {
|
||||
harvest_info_header header;
|
||||
harvest_info list[32];
|
||||
} harvest_table;
|
||||
|
||||
struct mall_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct mall_info_v1_0 {
|
||||
struct mall_info_header header;
|
||||
uint32_t mall_size_per_m;
|
||||
uint32_t m_s_present;
|
||||
uint32_t m_half_use;
|
||||
uint32_t m_mall_config;
|
||||
uint32_t reserved[5];
|
||||
};
|
||||
|
||||
struct mall_info_v2_0 {
|
||||
struct mall_info_header header;
|
||||
uint32_t mall_size_per_umc;
|
||||
uint32_t reserved[8];
|
||||
};
|
||||
|
||||
#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
|
||||
|
||||
struct vcn_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes */
|
||||
};
|
||||
|
||||
struct vcn_instance_info_v1_0
|
||||
{
|
||||
uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
|
||||
union _fuse_data {
|
||||
struct {
|
||||
uint32_t av1_disabled : 1;
|
||||
uint32_t vp9_disabled : 1;
|
||||
uint32_t hevc_disabled : 1;
|
||||
uint32_t h264_disabled : 1;
|
||||
uint32_t reserved : 28;
|
||||
} bits;
|
||||
uint32_t all_bits;
|
||||
} fuse_data;
|
||||
uint32_t reserved[2];
|
||||
};
|
||||
|
||||
struct vcn_info_v1_0 {
|
||||
struct vcn_info_header header;
|
||||
uint32_t num_of_instances; /* number of entries used in instance_info below*/
|
||||
struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
|
||||
uint32_t reserved[4];
|
||||
};
|
||||
|
||||
#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12
|
||||
|
||||
struct nps_info_header {
|
||||
uint32_t table_id; /* table ID */
|
||||
uint16_t version_major; /* table version */
|
||||
uint16_t version_minor; /* table version */
|
||||
uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */
|
||||
};
|
||||
|
||||
struct nps_instance_info_v1_0 {
|
||||
uint64_t base_address;
|
||||
uint64_t limit_address;
|
||||
};
|
||||
|
||||
struct nps_info_v1_0 {
|
||||
struct nps_info_header header;
|
||||
uint32_t nps_type;
|
||||
uint32_t count;
|
||||
struct nps_instance_info_v1_0
|
||||
instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES];
|
||||
};
|
||||
|
||||
enum amd_hw_ip_block_type {
|
||||
GC_HWIP = 1,
|
||||
HDP_HWIP,
|
||||
SDMA0_HWIP,
|
||||
@@ -565,3 +596,5 @@ static int hw_id_map[MAX_HWIP] = {
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
219
extra/amdpci/headers/hdp_7_0_0_offset.h
Normal file
219
extra/amdpci/headers/hdp_7_0_0_offset.h
Normal file
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _hdp_7_0_0_OFFSET_HEADER
|
||||
#define _hdp_7_0_0_OFFSET_HEADER
|
||||
|
||||
|
||||
|
||||
// addressBlock: hdp_hdpdec
|
||||
// base address: 0x3c80
|
||||
#define regHDP_MMHUB_TLVL 0x0008
|
||||
#define regHDP_MMHUB_TLVL_BASE_IDX 0
|
||||
#define regHDP_MMHUB_UNITID 0x0009
|
||||
#define regHDP_MMHUB_UNITID_BASE_IDX 0
|
||||
#define regHDP_NONSURFACE_BASE 0x0040
|
||||
#define regHDP_NONSURFACE_BASE_BASE_IDX 0
|
||||
#define regHDP_NONSURFACE_INFO 0x0041
|
||||
#define regHDP_NONSURFACE_INFO_BASE_IDX 0
|
||||
#define regHDP_NONSURFACE_BASE_HI 0x0042
|
||||
#define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0
|
||||
#define regHDP_SURFACE_WRITE_FLAGS 0x00c4
|
||||
#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
|
||||
#define regHDP_SURFACE_READ_FLAGS 0x00c5
|
||||
#define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0
|
||||
#define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6
|
||||
#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0
|
||||
#define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7
|
||||
#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0
|
||||
#define regHDP_NONSURF_FLAGS 0x00c8
|
||||
#define regHDP_NONSURF_FLAGS_BASE_IDX 0
|
||||
#define regHDP_NONSURF_FLAGS_CLR 0x00c9
|
||||
#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
|
||||
#define regHDP_SW_SEMAPHORE 0x00cd
|
||||
#define regHDP_SW_SEMAPHORE_BASE_IDX 0
|
||||
#define regHDP_DEBUG0 0x00ce
|
||||
#define regHDP_DEBUG0_BASE_IDX 0
|
||||
#define regHDP_LAST_SURFACE_HIT 0x00d0
|
||||
#define regHDP_LAST_SURFACE_HIT_BASE_IDX 0
|
||||
#define regHDP_OUTSTANDING_REQ 0x00d1
|
||||
#define regHDP_OUTSTANDING_REQ_BASE_IDX 0
|
||||
#define regHDP_HOST_PATH_CNTL 0x00d2
|
||||
#define regHDP_HOST_PATH_CNTL_BASE_IDX 0
|
||||
#define regHDP_MISC_CNTL 0x00d3
|
||||
#define regHDP_MISC_CNTL_BASE_IDX 0
|
||||
#define regHDP_MEM_POWER_CTRL 0x00d4
|
||||
#define regHDP_MEM_POWER_CTRL_BASE_IDX 0
|
||||
#define regHDP_CLK_CNTL 0x00d5
|
||||
#define regHDP_CLK_CNTL_BASE_IDX 0
|
||||
#define regHDP_MMHUB_CNTL 0x00d6
|
||||
#define regHDP_MMHUB_CNTL_BASE_IDX 0
|
||||
#define regHDP_XDP_BUSY_STS 0x00d7
|
||||
#define regHDP_XDP_BUSY_STS_BASE_IDX 0
|
||||
#define regHDP_XDP_MMHUB_ERROR 0x00d8
|
||||
#define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0
|
||||
#define regHDP_XDP_MMHUB_ERROR_CLR 0x00da
|
||||
#define regHDP_XDP_MMHUB_ERROR_CLR_BASE_IDX 0
|
||||
#define regHDP_VERSION 0x00db
|
||||
#define regHDP_VERSION_BASE_IDX 0
|
||||
#define regHDP_MEMIO_CNTL 0x00f6
|
||||
#define regHDP_MEMIO_CNTL_BASE_IDX 0
|
||||
#define regHDP_MEMIO_ADDR 0x00f7
|
||||
#define regHDP_MEMIO_ADDR_BASE_IDX 0
|
||||
#define regHDP_MEMIO_STATUS 0x00f8
|
||||
#define regHDP_MEMIO_STATUS_BASE_IDX 0
|
||||
#define regHDP_MEMIO_WR_DATA 0x00f9
|
||||
#define regHDP_MEMIO_WR_DATA_BASE_IDX 0
|
||||
#define regHDP_MEMIO_RD_DATA 0x00fa
|
||||
#define regHDP_MEMIO_RD_DATA_BASE_IDX 0
|
||||
#define regHDP_XDP_DIRECT2HDP_FIRST 0x0100
|
||||
#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_FLUSH 0x0101
|
||||
#define regHDP_XDP_D2H_FLUSH_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_BAR_UPDATE 0x0102
|
||||
#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_3 0x0103
|
||||
#define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_4 0x0104
|
||||
#define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_5 0x0105
|
||||
#define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_6 0x0106
|
||||
#define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_7 0x0107
|
||||
#define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_8 0x0108
|
||||
#define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_9 0x0109
|
||||
#define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_10 0x010a
|
||||
#define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_11 0x010b
|
||||
#define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_12 0x010c
|
||||
#define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_13 0x010d
|
||||
#define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_14 0x010e
|
||||
#define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_15 0x010f
|
||||
#define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_16 0x0110
|
||||
#define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_17 0x0111
|
||||
#define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_18 0x0112
|
||||
#define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_19 0x0113
|
||||
#define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_20 0x0114
|
||||
#define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_21 0x0115
|
||||
#define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_22 0x0116
|
||||
#define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_23 0x0117
|
||||
#define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_24 0x0118
|
||||
#define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_25 0x0119
|
||||
#define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_26 0x011a
|
||||
#define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_27 0x011b
|
||||
#define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_28 0x011c
|
||||
#define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_29 0x011d
|
||||
#define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_30 0x011e
|
||||
#define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_31 0x011f
|
||||
#define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_32 0x0120
|
||||
#define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_33 0x0121
|
||||
#define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0
|
||||
#define regHDP_XDP_D2H_RSVD_34 0x0122
|
||||
#define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0
|
||||
#define regHDP_XDP_DIRECT2HDP_LAST 0x0123
|
||||
#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR_CFG 0x0124
|
||||
#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_OFFSET 0x0125
|
||||
#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR0 0x0126
|
||||
#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR1 0x0127
|
||||
#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR2 0x0128
|
||||
#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR3 0x0129
|
||||
#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR4 0x012a
|
||||
#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR5 0x012b
|
||||
#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_MBX_ADDR6 0x012c
|
||||
#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
|
||||
#define regHDP_XDP_HDP_MBX_MC_CFG 0x012d
|
||||
#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
|
||||
#define regHDP_XDP_HDP_MC_CFG 0x012e
|
||||
#define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0
|
||||
#define regHDP_XDP_HST_CFG 0x012f
|
||||
#define regHDP_XDP_HST_CFG_BASE_IDX 0
|
||||
#define regHDP_XDP_HDP_IPH_CFG 0x0131
|
||||
#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR0 0x0134
|
||||
#define regHDP_XDP_P2P_BAR0_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR1 0x0135
|
||||
#define regHDP_XDP_P2P_BAR1_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR2 0x0136
|
||||
#define regHDP_XDP_P2P_BAR2_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR3 0x0137
|
||||
#define regHDP_XDP_P2P_BAR3_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR4 0x0138
|
||||
#define regHDP_XDP_P2P_BAR4_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR5 0x0139
|
||||
#define regHDP_XDP_P2P_BAR5_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR6 0x013a
|
||||
#define regHDP_XDP_P2P_BAR6_BASE_IDX 0
|
||||
#define regHDP_XDP_P2P_BAR7 0x013b
|
||||
#define regHDP_XDP_P2P_BAR7_BASE_IDX 0
|
||||
#define regHDP_XDP_FLUSH_ARMED_STS 0x013c
|
||||
#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
|
||||
#define regHDP_XDP_FLUSH_CNTR0_STS 0x013d
|
||||
#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
|
||||
#define regHDP_XDP_STICKY 0x013f
|
||||
#define regHDP_XDP_STICKY_BASE_IDX 0
|
||||
#define regHDP_XDP_CHKN 0x0140
|
||||
#define regHDP_XDP_CHKN_BASE_IDX 0
|
||||
#define regHDP_XDP_BARS_ADDR_39_36 0x0144
|
||||
#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
|
||||
#define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
|
||||
#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
|
||||
#define regHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
|
||||
#define regHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
|
||||
#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2 0x0149
|
||||
#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
|
||||
|
||||
#endif
|
||||
735
extra/amdpci/headers/hdp_7_0_0_sh_mask.h
Normal file
735
extra/amdpci/headers/hdp_7_0_0_sh_mask.h
Normal file
@@ -0,0 +1,735 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _hdp_7_0_0_SH_MASK_HEADER
|
||||
#define _hdp_7_0_0_SH_MASK_HEADER
|
||||
|
||||
|
||||
// addressBlock: hdp_hdpdec
|
||||
//HDP_MMHUB_TLVL
|
||||
#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
|
||||
#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
|
||||
#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
|
||||
#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
|
||||
#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
|
||||
#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x0000000FL
|
||||
#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x000000F0L
|
||||
#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000F00L
|
||||
#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x0000F000L
|
||||
#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x000F0000L
|
||||
//HDP_MMHUB_UNITID
|
||||
#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
|
||||
#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
|
||||
#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
|
||||
#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
|
||||
#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
|
||||
#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
|
||||
//HDP_NONSURFACE_BASE
|
||||
#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
|
||||
#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
|
||||
//HDP_NONSURFACE_INFO
|
||||
#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
|
||||
#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
|
||||
#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
|
||||
#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
|
||||
//HDP_NONSURFACE_BASE_HI
|
||||
#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
|
||||
#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
|
||||
//HDP_SURFACE_WRITE_FLAGS
|
||||
#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0
|
||||
#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1
|
||||
#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L
|
||||
#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L
|
||||
//HDP_SURFACE_READ_FLAGS
|
||||
#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0
|
||||
#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1
|
||||
#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L
|
||||
#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L
|
||||
//HDP_SURFACE_WRITE_FLAGS_CLR
|
||||
#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0
|
||||
#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1
|
||||
#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L
|
||||
#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L
|
||||
//HDP_SURFACE_READ_FLAGS_CLR
|
||||
#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0
|
||||
#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1
|
||||
#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L
|
||||
#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L
|
||||
//HDP_NONSURF_FLAGS
|
||||
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
|
||||
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
|
||||
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
|
||||
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
|
||||
//HDP_NONSURF_FLAGS_CLR
|
||||
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
|
||||
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
|
||||
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
|
||||
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
|
||||
//HDP_SW_SEMAPHORE
|
||||
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
|
||||
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
|
||||
//HDP_DEBUG0
|
||||
#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
|
||||
#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL
|
||||
//HDP_LAST_SURFACE_HIT
|
||||
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
|
||||
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
|
||||
//HDP_OUTSTANDING_REQ
|
||||
#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
|
||||
#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
|
||||
#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
|
||||
#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
|
||||
//HDP_HOST_PATH_CNTL
|
||||
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
|
||||
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
|
||||
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
|
||||
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
|
||||
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
|
||||
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
|
||||
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
|
||||
//HDP_MISC_CNTL
|
||||
#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
|
||||
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
|
||||
#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8
|
||||
#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT 0x9
|
||||
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
|
||||
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
|
||||
#define HDP_MISC_CNTL__NACK_ENABLE__SHIFT 0x13
|
||||
#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14
|
||||
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
|
||||
#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16
|
||||
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
|
||||
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
|
||||
#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
|
||||
#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
|
||||
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
|
||||
#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L
|
||||
#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK 0x00000200L
|
||||
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
|
||||
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L
|
||||
#define HDP_MISC_CNTL__NACK_ENABLE_MASK 0x00080000L
|
||||
#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK 0x00100000L
|
||||
#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
|
||||
#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L
|
||||
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
|
||||
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
|
||||
#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
|
||||
//HDP_MEM_POWER_CTRL
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT 0x0
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT 0x1
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT 0x2
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT 0x3
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT 0x4
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK 0x00000001L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK 0x00000002L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK 0x00000004L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK 0x00000008L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
|
||||
#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L
|
||||
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L
|
||||
//HDP_CLK_CNTL
|
||||
#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
|
||||
#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
|
||||
#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b
|
||||
#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
|
||||
#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
|
||||
#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
|
||||
#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
|
||||
#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
|
||||
#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
|
||||
#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L
|
||||
#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
|
||||
#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
|
||||
#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
|
||||
#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
|
||||
//HDP_MMHUB_CNTL
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE__SHIFT 0x5
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE__SHIFT 0x6
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE_MASK 0x00000020L
|
||||
#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE_MASK 0x00000040L
|
||||
//HDP_XDP_BUSY_STS
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT 0x0
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT 0x1
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT 0x2
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT 0x3
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT 0x4
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT 0x5
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT 0x6
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT 0x7
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT 0x8
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT 0x9
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT 0xa
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT 0xb
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT 0xc
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT 0xd
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT 0xf
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT 0x10
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT 0x11
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT 0x12
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT 0x13
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT 0x14
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT 0x15
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT 0x16
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT 0x17
|
||||
#define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT 0x18
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK 0x00000001L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK 0x00000002L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK 0x00000004L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK 0x00000008L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK 0x00000010L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK 0x00000020L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK 0x00000040L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK 0x00000080L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK 0x00000100L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK 0x00000200L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK 0x00000400L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK 0x00000800L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK 0x00001000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK 0x00002000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK 0x00004000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK 0x00008000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK 0x00010000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK 0x00020000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK 0x00040000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK 0x00080000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK 0x00100000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK 0x00200000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK 0x00400000L
|
||||
#define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK 0x00800000L
|
||||
#define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK 0x01000000L
|
||||
//HDP_XDP_MMHUB_ERROR
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
|
||||
#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
|
||||
#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
|
||||
//HDP_XDP_MMHUB_ERROR_CLR
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR__SHIFT 0x1
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR__SHIFT 0x2
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR__SHIFT 0x3
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR__SHIFT 0x4
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR__SHIFT 0x5
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR__SHIFT 0x6
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR__SHIFT 0x7
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR__SHIFT 0x9
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR__SHIFT 0xa
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR__SHIFT 0xb
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR__SHIFT 0xc
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR__SHIFT 0xd
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR__SHIFT 0xe
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR__SHIFT 0xf
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR__SHIFT 0x10
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR__SHIFT 0x11
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR__SHIFT 0x12
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR__SHIFT 0x13
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR__SHIFT 0x15
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR__SHIFT 0x16
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR__SHIFT 0x17
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR_MASK 0x00000002L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR_MASK 0x00000004L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR_MASK 0x00000008L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR_MASK 0x00000010L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR_MASK 0x00000020L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR_MASK 0x00000040L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR_MASK 0x00000080L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR_MASK 0x00000200L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR_MASK 0x00000400L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR_MASK 0x00000800L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR_MASK 0x00001000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR_MASK 0x00002000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR_MASK 0x00004000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR_MASK 0x00008000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR_MASK 0x00010000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR_MASK 0x00020000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR_MASK 0x00040000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR_MASK 0x00080000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR_MASK 0x00200000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR_MASK 0x00400000L
|
||||
#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR_MASK 0x00800000L
|
||||
//HDP_VERSION
|
||||
#define HDP_VERSION__MINVER__SHIFT 0x0
|
||||
#define HDP_VERSION__MAJVER__SHIFT 0x8
|
||||
#define HDP_VERSION__REV__SHIFT 0x10
|
||||
#define HDP_VERSION__MINVER_MASK 0x000000FFL
|
||||
#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
|
||||
#define HDP_VERSION__REV_MASK 0x00FF0000L
|
||||
//HDP_MEMIO_CNTL
|
||||
#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
|
||||
#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
|
||||
#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
|
||||
#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
|
||||
#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
|
||||
#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
|
||||
#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
|
||||
#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
|
||||
#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
|
||||
#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
|
||||
#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
|
||||
#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
|
||||
#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
|
||||
//HDP_MEMIO_ADDR
|
||||
#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
|
||||
#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
|
||||
//HDP_MEMIO_STATUS
|
||||
#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
|
||||
#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
|
||||
#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
|
||||
#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
|
||||
#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
|
||||
#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
|
||||
#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
|
||||
#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
|
||||
//HDP_MEMIO_WR_DATA
|
||||
#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
|
||||
#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
|
||||
//HDP_MEMIO_RD_DATA
|
||||
#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
|
||||
#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_DIRECT2HDP_FIRST
|
||||
#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_FLUSH
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
|
||||
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
|
||||
//HDP_XDP_D2H_BAR_UPDATE
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
|
||||
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
|
||||
//HDP_XDP_D2H_RSVD_3
|
||||
#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_4
|
||||
#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_5
|
||||
#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_6
|
||||
#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_7
|
||||
#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_8
|
||||
#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_9
|
||||
#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_10
|
||||
#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_11
|
||||
#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_12
|
||||
#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_13
|
||||
#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_14
|
||||
#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_15
|
||||
#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_16
|
||||
#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_17
|
||||
#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_18
|
||||
#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_19
|
||||
#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_20
|
||||
#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_21
|
||||
#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_22
|
||||
#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_23
|
||||
#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_24
|
||||
#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_25
|
||||
#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_26
|
||||
#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_27
|
||||
#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_28
|
||||
#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_29
|
||||
#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_30
|
||||
#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_31
|
||||
#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_32
|
||||
#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_33
|
||||
#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_D2H_RSVD_34
|
||||
#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_DIRECT2HDP_LAST
|
||||
#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
|
||||
#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_P2P_BAR_CFG
|
||||
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
|
||||
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
|
||||
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
|
||||
//HDP_XDP_P2P_MBX_OFFSET
|
||||
#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
|
||||
//HDP_XDP_P2P_MBX_ADDR0
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR1
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR2
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR3
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR4
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR5
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_P2P_MBX_ADDR6
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
|
||||
//HDP_XDP_HDP_MBX_MC_CFG
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
|
||||
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
|
||||
//HDP_XDP_HDP_MC_CFG
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE__SHIFT 0x0
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE__SHIFT 0x1
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE__SHIFT 0x2
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE_MASK 0x00000001L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE_MASK 0x00000002L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE_MASK 0x00000004L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
|
||||
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
|
||||
//HDP_XDP_HST_CFG
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
|
||||
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
|
||||
//HDP_XDP_HDP_IPH_CFG
|
||||
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
|
||||
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
|
||||
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
|
||||
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
|
||||
//HDP_XDP_P2P_BAR0
|
||||
#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR1
|
||||
#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR2
|
||||
#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR3
|
||||
#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR4
|
||||
#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR5
|
||||
#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR6
|
||||
#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_P2P_BAR7
|
||||
#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
|
||||
#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
|
||||
#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
|
||||
#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
|
||||
#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
|
||||
//HDP_XDP_FLUSH_ARMED_STS
|
||||
#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
|
||||
#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
|
||||
//HDP_XDP_FLUSH_CNTR0_STS
|
||||
#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
|
||||
#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
|
||||
//HDP_XDP_STICKY
|
||||
#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
|
||||
#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
|
||||
#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
|
||||
#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
|
||||
//HDP_XDP_CHKN
|
||||
#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
|
||||
#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
|
||||
#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
|
||||
#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
|
||||
#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
|
||||
#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
|
||||
#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
|
||||
#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
|
||||
//HDP_XDP_BARS_ADDR_39_36
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
|
||||
#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
|
||||
//HDP_XDP_MC_VM_FB_LOCATION_BASE
|
||||
#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
|
||||
#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
|
||||
//HDP_XDP_GPU_IOV_VIOLATION_LOG
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x01F00000L
|
||||
//HDP_XDP_GPU_IOV_VIOLATION_LOG2
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
|
||||
#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
|
||||
|
||||
#endif
|
||||
1341
extra/amdpci/headers/mmhub_4_1_0_offset.h
Normal file
1341
extra/amdpci/headers/mmhub_4_1_0_offset.h
Normal file
File diff suppressed because it is too large
Load Diff
6943
extra/amdpci/headers/mmhub_4_1_0_sh_mask.h
Normal file
6943
extra/amdpci/headers/mmhub_4_1_0_sh_mask.h
Normal file
File diff suppressed because it is too large
Load Diff
359
extra/amdpci/headers/mp_14_0_0_offset.h
Normal file
359
extra/amdpci/headers/mp_14_0_0_offset.h
Normal file
@@ -0,0 +1,359 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
*/
|
||||
#ifndef _mp_14_0_0_OFFSET_HEADER
|
||||
#define _mp_14_0_0_OFFSET_HEADER
|
||||
|
||||
// addressBlock: mp_SmuMp1_SmnDec
|
||||
// base address: 0x0
|
||||
#define regMP1_SMN_C2PMSG_0 0x0240
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||||
#define regMP1_SMN_C2PMSG_0_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_1 0x0241
|
||||
#define regMP1_SMN_C2PMSG_1_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_2 0x0242
|
||||
#define regMP1_SMN_C2PMSG_2_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_3 0x0243
|
||||
#define regMP1_SMN_C2PMSG_3_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_4 0x0244
|
||||
#define regMP1_SMN_C2PMSG_4_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_5 0x0245
|
||||
#define regMP1_SMN_C2PMSG_5_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_6 0x0246
|
||||
#define regMP1_SMN_C2PMSG_6_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_7 0x0247
|
||||
#define regMP1_SMN_C2PMSG_7_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_8 0x0248
|
||||
#define regMP1_SMN_C2PMSG_8_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_9 0x0249
|
||||
#define regMP1_SMN_C2PMSG_9_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_10 0x024a
|
||||
#define regMP1_SMN_C2PMSG_10_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_11 0x024b
|
||||
#define regMP1_SMN_C2PMSG_11_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_12 0x024c
|
||||
#define regMP1_SMN_C2PMSG_12_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_13 0x024d
|
||||
#define regMP1_SMN_C2PMSG_13_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_14 0x024e
|
||||
#define regMP1_SMN_C2PMSG_14_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_15 0x024f
|
||||
#define regMP1_SMN_C2PMSG_15_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_16 0x0250
|
||||
#define regMP1_SMN_C2PMSG_16_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_17 0x0251
|
||||
#define regMP1_SMN_C2PMSG_17_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_18 0x0252
|
||||
#define regMP1_SMN_C2PMSG_18_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_19 0x0253
|
||||
#define regMP1_SMN_C2PMSG_19_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_20 0x0254
|
||||
#define regMP1_SMN_C2PMSG_20_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_21 0x0255
|
||||
#define regMP1_SMN_C2PMSG_21_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_22 0x0256
|
||||
#define regMP1_SMN_C2PMSG_22_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_23 0x0257
|
||||
#define regMP1_SMN_C2PMSG_23_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_24 0x0258
|
||||
#define regMP1_SMN_C2PMSG_24_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_25 0x0259
|
||||
#define regMP1_SMN_C2PMSG_25_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_26 0x025a
|
||||
#define regMP1_SMN_C2PMSG_26_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_27 0x025b
|
||||
#define regMP1_SMN_C2PMSG_27_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_28 0x025c
|
||||
#define regMP1_SMN_C2PMSG_28_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_29 0x025d
|
||||
#define regMP1_SMN_C2PMSG_29_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_30 0x025e
|
||||
#define regMP1_SMN_C2PMSG_30_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_31 0x025f
|
||||
#define regMP1_SMN_C2PMSG_31_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_32 0x0260
|
||||
#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_33 0x0261
|
||||
#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_34 0x0262
|
||||
#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_35 0x0263
|
||||
#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_36 0x0264
|
||||
#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_37 0x0265
|
||||
#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_38 0x0266
|
||||
#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_39 0x0267
|
||||
#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_40 0x0268
|
||||
#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_41 0x0269
|
||||
#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_42 0x026a
|
||||
#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_43 0x026b
|
||||
#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_44 0x026c
|
||||
#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_45 0x026d
|
||||
#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_46 0x026e
|
||||
#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_47 0x026f
|
||||
#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_48 0x0270
|
||||
#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_49 0x0271
|
||||
#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_50 0x0272
|
||||
#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_51 0x0273
|
||||
#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_52 0x0274
|
||||
#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_53 0x0275
|
||||
#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_54 0x0276
|
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#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_55 0x0277
|
||||
#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_56 0x0278
|
||||
#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_57 0x0279
|
||||
#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_58 0x027a
|
||||
#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_59 0x027b
|
||||
#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_60 0x027c
|
||||
#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_61 0x027d
|
||||
#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_62 0x027e
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||||
#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_63 0x027f
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||||
#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_64 0x0280
|
||||
#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_65 0x0281
|
||||
#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_66 0x0282
|
||||
#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_67 0x0283
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||||
#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_68 0x0284
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||||
#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_69 0x0285
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||||
#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_70 0x0286
|
||||
#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_71 0x0287
|
||||
#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_72 0x0288
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||||
#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_73 0x0289
|
||||
#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_74 0x028a
|
||||
#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_75 0x028b
|
||||
#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_76 0x028c
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||||
#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
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||||
#define regMP1_SMN_C2PMSG_77 0x028d
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||||
#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_78 0x028e
|
||||
#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_79 0x028f
|
||||
#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_80 0x0290
|
||||
#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_81 0x0291
|
||||
#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_82 0x0292
|
||||
#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_83 0x0293
|
||||
#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_84 0x0294
|
||||
#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_85 0x0295
|
||||
#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_86 0x0296
|
||||
#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_87 0x0297
|
||||
#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_88 0x0298
|
||||
#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_89 0x0299
|
||||
#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_90 0x029a
|
||||
#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_91 0x029b
|
||||
#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_92 0x029c
|
||||
#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_93 0x029d
|
||||
#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_94 0x029e
|
||||
#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_95 0x029f
|
||||
#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_96 0x02a0
|
||||
#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_97 0x02a1
|
||||
#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_98 0x02a2
|
||||
#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_99 0x02a3
|
||||
#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_100 0x02a4
|
||||
#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_101 0x02a5
|
||||
#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_102 0x02a6
|
||||
#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_103 0x02a7
|
||||
#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_104 0x02a8
|
||||
#define regMP1_SMN_C2PMSG_104_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_105 0x02a9
|
||||
#define regMP1_SMN_C2PMSG_105_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_106 0x02aa
|
||||
#define regMP1_SMN_C2PMSG_106_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_107 0x02ab
|
||||
#define regMP1_SMN_C2PMSG_107_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_108 0x02ac
|
||||
#define regMP1_SMN_C2PMSG_108_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_109 0x02ad
|
||||
#define regMP1_SMN_C2PMSG_109_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_110 0x02ae
|
||||
#define regMP1_SMN_C2PMSG_110_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_111 0x02af
|
||||
#define regMP1_SMN_C2PMSG_111_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_112 0x02b0
|
||||
#define regMP1_SMN_C2PMSG_112_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_113 0x02b1
|
||||
#define regMP1_SMN_C2PMSG_113_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_114 0x02b2
|
||||
#define regMP1_SMN_C2PMSG_114_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_115 0x02b3
|
||||
#define regMP1_SMN_C2PMSG_115_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_116 0x02b4
|
||||
#define regMP1_SMN_C2PMSG_116_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_117 0x02b5
|
||||
#define regMP1_SMN_C2PMSG_117_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_118 0x02b6
|
||||
#define regMP1_SMN_C2PMSG_118_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_119 0x02b7
|
||||
#define regMP1_SMN_C2PMSG_119_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_120 0x02b8
|
||||
#define regMP1_SMN_C2PMSG_120_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_121 0x02b9
|
||||
#define regMP1_SMN_C2PMSG_121_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_122 0x02ba
|
||||
#define regMP1_SMN_C2PMSG_122_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_123 0x02bb
|
||||
#define regMP1_SMN_C2PMSG_123_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_124 0x02bc
|
||||
#define regMP1_SMN_C2PMSG_124_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_125 0x02bd
|
||||
#define regMP1_SMN_C2PMSG_125_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_126 0x02be
|
||||
#define regMP1_SMN_C2PMSG_126_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_127 0x02bf
|
||||
#define regMP1_SMN_C2PMSG_127_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_CREDIT 0x0340
|
||||
#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_SW_INT 0x0341
|
||||
#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL 0x0342
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
|
||||
#define regMP1_SMN_FPS_CNT 0x0343
|
||||
#define regMP1_SMN_FPS_CNT_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH0 0x03c0
|
||||
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH1 0x03c1
|
||||
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH2 0x03c2
|
||||
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH3 0x03c3
|
||||
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH4 0x03c4
|
||||
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH5 0x03c5
|
||||
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH6 0x03c6
|
||||
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH7 0x03c7
|
||||
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH8 0x03c8
|
||||
#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH9 0x03c9
|
||||
#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH10 0x03ca
|
||||
#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH11 0x03cb
|
||||
#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH12 0x03cc
|
||||
#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH13 0x03cd
|
||||
#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH14 0x03ce
|
||||
#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH15 0x03cf
|
||||
#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH16 0x03d0
|
||||
#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH17 0x03d1
|
||||
#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH18 0x03d2
|
||||
#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH19 0x03d3
|
||||
#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH20 0x03d4
|
||||
#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH21 0x03d5
|
||||
#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH22 0x03d6
|
||||
#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH23 0x03d7
|
||||
#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH24 0x03d8
|
||||
#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH25 0x03d9
|
||||
#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH26 0x03da
|
||||
#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH27 0x03db
|
||||
#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH28 0x03dc
|
||||
#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH29 0x03dd
|
||||
#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH30 0x03de
|
||||
#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH31 0x03df
|
||||
#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0
|
||||
|
||||
|
||||
#endif
|
||||
534
extra/amdpci/headers/mp_14_0_0_sh_mask.h
Normal file
534
extra/amdpci/headers/mp_14_0_0_sh_mask.h
Normal file
@@ -0,0 +1,534 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _mp_14_0_0_SH_MASK_HEADER
|
||||
#define _mp_14_0_0_SH_MASK_HEADER
|
||||
|
||||
// addressBlock: mp_SmuMp1Pub_CruDec
|
||||
//MP1_CRU1_MP1_FIRMWARE_FLAGS
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1_SmnDec
|
||||
//MP1_SMN_C2PMSG_0
|
||||
#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_1
|
||||
#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_2
|
||||
#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_3
|
||||
#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_4
|
||||
#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_5
|
||||
#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_6
|
||||
#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_7
|
||||
#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_8
|
||||
#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_9
|
||||
#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_10
|
||||
#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_11
|
||||
#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_12
|
||||
#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_13
|
||||
#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_14
|
||||
#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_15
|
||||
#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_16
|
||||
#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_17
|
||||
#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_18
|
||||
#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_19
|
||||
#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_20
|
||||
#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_21
|
||||
#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_22
|
||||
#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_23
|
||||
#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_24
|
||||
#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_25
|
||||
#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_26
|
||||
#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_27
|
||||
#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_28
|
||||
#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_29
|
||||
#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_30
|
||||
#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_31
|
||||
#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_32
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_33
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_34
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_35
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_36
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_37
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_38
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_39
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_40
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_41
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_42
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_43
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_44
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_45
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_46
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_47
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_48
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_49
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_50
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_51
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_52
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_53
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_54
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_55
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_56
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_57
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_58
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_59
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_60
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_61
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_62
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_63
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_64
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_65
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_66
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_67
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_68
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_69
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_70
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_71
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_72
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_73
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_74
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_75
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_76
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_77
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_78
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_79
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_80
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_81
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_82
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_83
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_84
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_85
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_86
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_87
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_88
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_89
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_90
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_91
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_92
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_93
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_94
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_95
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_96
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_97
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_98
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_99
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_100
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_101
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_102
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_103
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_104
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_105
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_106
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_107
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_108
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_109
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_110
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_111
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_112
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_113
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_114
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_115
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_116
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_117
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_118
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_119
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_120
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_121
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_122
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_123
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_124
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_125
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_126
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_127
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_IH_CREDIT
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
|
||||
//MP1_SMN_IH_SW_INT
|
||||
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
|
||||
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
|
||||
//MP1_SMN_IH_SW_INT_CTRL
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
|
||||
//MP1_SMN_FPS_CNT
|
||||
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
|
||||
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH1
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH2
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH3
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH4
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH5
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH6
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH7
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH8
|
||||
#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH9
|
||||
#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH10
|
||||
#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH11
|
||||
#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH12
|
||||
#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH13
|
||||
#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH14
|
||||
#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH15
|
||||
#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH16
|
||||
#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH17
|
||||
#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH18
|
||||
#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH19
|
||||
#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH20
|
||||
#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH21
|
||||
#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH22
|
||||
#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH23
|
||||
#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH24
|
||||
#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH25
|
||||
#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH26
|
||||
#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH27
|
||||
#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH28
|
||||
#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH29
|
||||
#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH30
|
||||
#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH31
|
||||
#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
|
||||
|
||||
#endif
|
||||
468
extra/amdpci/headers/mp_14_0_2_offset.h
Normal file
468
extra/amdpci/headers/mp_14_0_2_offset.h
Normal file
@@ -0,0 +1,468 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _mp_14_0_2_OFFSET_HEADER
|
||||
#define _mp_14_0_2_OFFSET_HEADER
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1_SmnDec
|
||||
// base address: 0x0
|
||||
#define regMP1_SMN_C2PMSG_0 0x0040
|
||||
#define regMP1_SMN_C2PMSG_0_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_1 0x0041
|
||||
#define regMP1_SMN_C2PMSG_1_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_2 0x0042
|
||||
#define regMP1_SMN_C2PMSG_2_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_3 0x0043
|
||||
#define regMP1_SMN_C2PMSG_3_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_4 0x0044
|
||||
#define regMP1_SMN_C2PMSG_4_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_5 0x0045
|
||||
#define regMP1_SMN_C2PMSG_5_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_6 0x0046
|
||||
#define regMP1_SMN_C2PMSG_6_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_7 0x0047
|
||||
#define regMP1_SMN_C2PMSG_7_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_8 0x0048
|
||||
#define regMP1_SMN_C2PMSG_8_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_9 0x0049
|
||||
#define regMP1_SMN_C2PMSG_9_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_10 0x004a
|
||||
#define regMP1_SMN_C2PMSG_10_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_11 0x004b
|
||||
#define regMP1_SMN_C2PMSG_11_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_12 0x004c
|
||||
#define regMP1_SMN_C2PMSG_12_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_13 0x004d
|
||||
#define regMP1_SMN_C2PMSG_13_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_14 0x004e
|
||||
#define regMP1_SMN_C2PMSG_14_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_15 0x004f
|
||||
#define regMP1_SMN_C2PMSG_15_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_16 0x0050
|
||||
#define regMP1_SMN_C2PMSG_16_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_17 0x0051
|
||||
#define regMP1_SMN_C2PMSG_17_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_18 0x0052
|
||||
#define regMP1_SMN_C2PMSG_18_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_19 0x0053
|
||||
#define regMP1_SMN_C2PMSG_19_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_20 0x0054
|
||||
#define regMP1_SMN_C2PMSG_20_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_21 0x0055
|
||||
#define regMP1_SMN_C2PMSG_21_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_22 0x0056
|
||||
#define regMP1_SMN_C2PMSG_22_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_23 0x0057
|
||||
#define regMP1_SMN_C2PMSG_23_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_24 0x0058
|
||||
#define regMP1_SMN_C2PMSG_24_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_25 0x0059
|
||||
#define regMP1_SMN_C2PMSG_25_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_26 0x005a
|
||||
#define regMP1_SMN_C2PMSG_26_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_27 0x005b
|
||||
#define regMP1_SMN_C2PMSG_27_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_28 0x005c
|
||||
#define regMP1_SMN_C2PMSG_28_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_29 0x005d
|
||||
#define regMP1_SMN_C2PMSG_29_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_30 0x005e
|
||||
#define regMP1_SMN_C2PMSG_30_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_31 0x005f
|
||||
#define regMP1_SMN_C2PMSG_31_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_32 0x0060
|
||||
#define regMP1_SMN_C2PMSG_32_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_33 0x0061
|
||||
#define regMP1_SMN_C2PMSG_33_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_34 0x0062
|
||||
#define regMP1_SMN_C2PMSG_34_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_35 0x0063
|
||||
#define regMP1_SMN_C2PMSG_35_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_36 0x0064
|
||||
#define regMP1_SMN_C2PMSG_36_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_37 0x0065
|
||||
#define regMP1_SMN_C2PMSG_37_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_38 0x0066
|
||||
#define regMP1_SMN_C2PMSG_38_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_39 0x0067
|
||||
#define regMP1_SMN_C2PMSG_39_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_40 0x0068
|
||||
#define regMP1_SMN_C2PMSG_40_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_41 0x0069
|
||||
#define regMP1_SMN_C2PMSG_41_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_42 0x006a
|
||||
#define regMP1_SMN_C2PMSG_42_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_43 0x006b
|
||||
#define regMP1_SMN_C2PMSG_43_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_44 0x006c
|
||||
#define regMP1_SMN_C2PMSG_44_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_45 0x006d
|
||||
#define regMP1_SMN_C2PMSG_45_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_46 0x006e
|
||||
#define regMP1_SMN_C2PMSG_46_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_47 0x006f
|
||||
#define regMP1_SMN_C2PMSG_47_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_48 0x0070
|
||||
#define regMP1_SMN_C2PMSG_48_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_49 0x0071
|
||||
#define regMP1_SMN_C2PMSG_49_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_50 0x0072
|
||||
#define regMP1_SMN_C2PMSG_50_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_51 0x0073
|
||||
#define regMP1_SMN_C2PMSG_51_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_52 0x0074
|
||||
#define regMP1_SMN_C2PMSG_52_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_53 0x0075
|
||||
#define regMP1_SMN_C2PMSG_53_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_54 0x0076
|
||||
#define regMP1_SMN_C2PMSG_54_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_55 0x0077
|
||||
#define regMP1_SMN_C2PMSG_55_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_56 0x0078
|
||||
#define regMP1_SMN_C2PMSG_56_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_57 0x0079
|
||||
#define regMP1_SMN_C2PMSG_57_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_58 0x007a
|
||||
#define regMP1_SMN_C2PMSG_58_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_59 0x007b
|
||||
#define regMP1_SMN_C2PMSG_59_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_60 0x007c
|
||||
#define regMP1_SMN_C2PMSG_60_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_61 0x007d
|
||||
#define regMP1_SMN_C2PMSG_61_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_62 0x007e
|
||||
#define regMP1_SMN_C2PMSG_62_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_63 0x007f
|
||||
#define regMP1_SMN_C2PMSG_63_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_64 0x0080
|
||||
#define regMP1_SMN_C2PMSG_64_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_65 0x0081
|
||||
#define regMP1_SMN_C2PMSG_65_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_66 0x0082
|
||||
#define regMP1_SMN_C2PMSG_66_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_67 0x0083
|
||||
#define regMP1_SMN_C2PMSG_67_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_68 0x0084
|
||||
#define regMP1_SMN_C2PMSG_68_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_69 0x0085
|
||||
#define regMP1_SMN_C2PMSG_69_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_70 0x0086
|
||||
#define regMP1_SMN_C2PMSG_70_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_71 0x0087
|
||||
#define regMP1_SMN_C2PMSG_71_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_72 0x0088
|
||||
#define regMP1_SMN_C2PMSG_72_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_73 0x0089
|
||||
#define regMP1_SMN_C2PMSG_73_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_74 0x008a
|
||||
#define regMP1_SMN_C2PMSG_74_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_75 0x008b
|
||||
#define regMP1_SMN_C2PMSG_75_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_76 0x008c
|
||||
#define regMP1_SMN_C2PMSG_76_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_77 0x008d
|
||||
#define regMP1_SMN_C2PMSG_77_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_78 0x008e
|
||||
#define regMP1_SMN_C2PMSG_78_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_79 0x008f
|
||||
#define regMP1_SMN_C2PMSG_79_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_80 0x0090
|
||||
#define regMP1_SMN_C2PMSG_80_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_81 0x0091
|
||||
#define regMP1_SMN_C2PMSG_81_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_82 0x0092
|
||||
#define regMP1_SMN_C2PMSG_82_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_83 0x0093
|
||||
#define regMP1_SMN_C2PMSG_83_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_84 0x0094
|
||||
#define regMP1_SMN_C2PMSG_84_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_85 0x0095
|
||||
#define regMP1_SMN_C2PMSG_85_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_86 0x0096
|
||||
#define regMP1_SMN_C2PMSG_86_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_87 0x0097
|
||||
#define regMP1_SMN_C2PMSG_87_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_88 0x0098
|
||||
#define regMP1_SMN_C2PMSG_88_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_89 0x0099
|
||||
#define regMP1_SMN_C2PMSG_89_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_90 0x009a
|
||||
#define regMP1_SMN_C2PMSG_90_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_91 0x009b
|
||||
#define regMP1_SMN_C2PMSG_91_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_92 0x009c
|
||||
#define regMP1_SMN_C2PMSG_92_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_93 0x009d
|
||||
#define regMP1_SMN_C2PMSG_93_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_94 0x009e
|
||||
#define regMP1_SMN_C2PMSG_94_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_95 0x009f
|
||||
#define regMP1_SMN_C2PMSG_95_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_96 0x00a0
|
||||
#define regMP1_SMN_C2PMSG_96_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_97 0x00a1
|
||||
#define regMP1_SMN_C2PMSG_97_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_98 0x00a2
|
||||
#define regMP1_SMN_C2PMSG_98_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_99 0x00a3
|
||||
#define regMP1_SMN_C2PMSG_99_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_100 0x00a4
|
||||
#define regMP1_SMN_C2PMSG_100_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_101 0x00a5
|
||||
#define regMP1_SMN_C2PMSG_101_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_102 0x00a6
|
||||
#define regMP1_SMN_C2PMSG_102_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_103 0x00a7
|
||||
#define regMP1_SMN_C2PMSG_103_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_104 0x00a8
|
||||
#define regMP1_SMN_C2PMSG_104_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_105 0x00a9
|
||||
#define regMP1_SMN_C2PMSG_105_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_106 0x00aa
|
||||
#define regMP1_SMN_C2PMSG_106_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_107 0x00ab
|
||||
#define regMP1_SMN_C2PMSG_107_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_108 0x00ac
|
||||
#define regMP1_SMN_C2PMSG_108_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_109 0x00ad
|
||||
#define regMP1_SMN_C2PMSG_109_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_110 0x00ae
|
||||
#define regMP1_SMN_C2PMSG_110_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_111 0x00af
|
||||
#define regMP1_SMN_C2PMSG_111_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_112 0x00b0
|
||||
#define regMP1_SMN_C2PMSG_112_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_113 0x00b1
|
||||
#define regMP1_SMN_C2PMSG_113_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_114 0x00b2
|
||||
#define regMP1_SMN_C2PMSG_114_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_115 0x00b3
|
||||
#define regMP1_SMN_C2PMSG_115_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_116 0x00b4
|
||||
#define regMP1_SMN_C2PMSG_116_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_117 0x00b5
|
||||
#define regMP1_SMN_C2PMSG_117_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_118 0x00b6
|
||||
#define regMP1_SMN_C2PMSG_118_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_119 0x00b7
|
||||
#define regMP1_SMN_C2PMSG_119_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_120 0x00b8
|
||||
#define regMP1_SMN_C2PMSG_120_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_121 0x00b9
|
||||
#define regMP1_SMN_C2PMSG_121_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_122 0x00ba
|
||||
#define regMP1_SMN_C2PMSG_122_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_123 0x00bb
|
||||
#define regMP1_SMN_C2PMSG_123_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_124 0x00bc
|
||||
#define regMP1_SMN_C2PMSG_124_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_125 0x00bd
|
||||
#define regMP1_SMN_C2PMSG_125_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_126 0x00be
|
||||
#define regMP1_SMN_C2PMSG_126_BASE_IDX 1
|
||||
#define regMP1_SMN_C2PMSG_127 0x00bf
|
||||
#define regMP1_SMN_C2PMSG_127_BASE_IDX 1
|
||||
#define regMP1_SMN_IH_CREDIT 0x0140
|
||||
#define regMP1_SMN_IH_CREDIT_BASE_IDX 1
|
||||
#define regMP1_SMN_IH_SW_INT 0x0141
|
||||
#define regMP1_SMN_IH_SW_INT_BASE_IDX 1
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL 0x0142
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 1
|
||||
#define regMP1_SMN_FPS_CNT 0x0143
|
||||
#define regMP1_SMN_FPS_CNT_BASE_IDX 1
|
||||
#define regMP1_SMN_PUB_CTRL 0x0144
|
||||
#define regMP1_SMN_PUB_CTRL_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH0 0x01c0
|
||||
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH1 0x01c1
|
||||
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH2 0x01c2
|
||||
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH3 0x01c3
|
||||
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH4 0x01c4
|
||||
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH5 0x01c5
|
||||
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH6 0x01c6
|
||||
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH7 0x01c7
|
||||
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH8 0x01c8
|
||||
#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH9 0x01c9
|
||||
#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH10 0x01ca
|
||||
#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH11 0x01cb
|
||||
#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH12 0x01cc
|
||||
#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH13 0x01cd
|
||||
#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH14 0x01ce
|
||||
#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH15 0x01cf
|
||||
#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH16 0x01d0
|
||||
#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH17 0x01d1
|
||||
#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH18 0x01d2
|
||||
#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH19 0x01d3
|
||||
#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH20 0x01d4
|
||||
#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH21 0x01d5
|
||||
#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH22 0x01d6
|
||||
#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH23 0x01d7
|
||||
#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH24 0x01d8
|
||||
#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH25 0x01d9
|
||||
#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH26 0x01da
|
||||
#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH27 0x01db
|
||||
#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH28 0x01dc
|
||||
#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH29 0x01dd
|
||||
#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH30 0x01de
|
||||
#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 1
|
||||
#define regMP1_SMN_EXT_SCRATCH31 0x01df
|
||||
#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 1
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMpASP_SmnDec
|
||||
// base address: 0x0
|
||||
#define regMPASP_SMN_C2PMSG_32 0x0060
|
||||
#define regMPASP_SMN_C2PMSG_32_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_33 0x0061
|
||||
#define regMPASP_SMN_C2PMSG_33_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_34 0x0062
|
||||
#define regMPASP_SMN_C2PMSG_34_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_35 0x0063
|
||||
#define regMPASP_SMN_C2PMSG_35_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_36 0x0064
|
||||
#define regMPASP_SMN_C2PMSG_36_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_37 0x0065
|
||||
#define regMPASP_SMN_C2PMSG_37_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_38 0x0066
|
||||
#define regMPASP_SMN_C2PMSG_38_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_39 0x0067
|
||||
#define regMPASP_SMN_C2PMSG_39_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_60 0x007c
|
||||
#define regMPASP_SMN_C2PMSG_60_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_61 0x007d
|
||||
#define regMPASP_SMN_C2PMSG_61_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_62 0x007e
|
||||
#define regMPASP_SMN_C2PMSG_62_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_63 0x007f
|
||||
#define regMPASP_SMN_C2PMSG_63_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_64 0x0080
|
||||
#define regMPASP_SMN_C2PMSG_64_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_65 0x0081
|
||||
#define regMPASP_SMN_C2PMSG_65_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_66 0x0082
|
||||
#define regMPASP_SMN_C2PMSG_66_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_67 0x0083
|
||||
#define regMPASP_SMN_C2PMSG_67_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_68 0x0084
|
||||
#define regMPASP_SMN_C2PMSG_68_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_69 0x0085
|
||||
#define regMPASP_SMN_C2PMSG_69_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_70 0x0086
|
||||
#define regMPASP_SMN_C2PMSG_70_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_71 0x0087
|
||||
#define regMPASP_SMN_C2PMSG_71_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_72 0x0088
|
||||
#define regMPASP_SMN_C2PMSG_72_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_73 0x0089
|
||||
#define regMPASP_SMN_C2PMSG_73_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_74 0x008a
|
||||
#define regMPASP_SMN_C2PMSG_74_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_75 0x008b
|
||||
#define regMPASP_SMN_C2PMSG_75_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_76 0x008c
|
||||
#define regMPASP_SMN_C2PMSG_76_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_77 0x008d
|
||||
#define regMPASP_SMN_C2PMSG_77_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_78 0x008e
|
||||
#define regMPASP_SMN_C2PMSG_78_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_79 0x008f
|
||||
#define regMPASP_SMN_C2PMSG_79_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_80 0x0090
|
||||
#define regMPASP_SMN_C2PMSG_80_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_81 0x0091
|
||||
#define regMPASP_SMN_C2PMSG_81_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_82 0x0092
|
||||
#define regMPASP_SMN_C2PMSG_82_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_83 0x0093
|
||||
#define regMPASP_SMN_C2PMSG_83_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_84 0x0094
|
||||
#define regMPASP_SMN_C2PMSG_84_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_85 0x0095
|
||||
#define regMPASP_SMN_C2PMSG_85_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_86 0x0096
|
||||
#define regMPASP_SMN_C2PMSG_86_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_87 0x0097
|
||||
#define regMPASP_SMN_C2PMSG_87_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_88 0x0098
|
||||
#define regMPASP_SMN_C2PMSG_88_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_89 0x0099
|
||||
#define regMPASP_SMN_C2PMSG_89_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_100 0x00a4
|
||||
#define regMPASP_SMN_C2PMSG_100_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_101 0x00a5
|
||||
#define regMPASP_SMN_C2PMSG_101_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_102 0x00a6
|
||||
#define regMPASP_SMN_C2PMSG_102_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_103 0x00a7
|
||||
#define regMPASP_SMN_C2PMSG_103_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_109 0x00ad
|
||||
#define regMPASP_SMN_C2PMSG_109_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_115 0x00b3
|
||||
#define regMPASP_SMN_C2PMSG_115_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_116 0x00b4
|
||||
#define regMPASP_SMN_C2PMSG_116_BASE_IDX 0
|
||||
#define regMPASP_SMN_C2PMSG_119_BASE_IDX 0
|
||||
#define regMPASP_SMN_IH_CREDIT 0x0140
|
||||
#define regMPASP_SMN_IH_CREDIT_BASE_IDX 0
|
||||
#define regMPASP_SMN_IH_SW_INT 0x0141
|
||||
#define regMPASP_SMN_IH_SW_INT_BASE_IDX 0
|
||||
#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
|
||||
#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
|
||||
|
||||
|
||||
// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec
|
||||
// base address: 0x3b00000
|
||||
#define regMP1_CRU1_MP1_FIRMWARE_FLAGS 0x4009
|
||||
#define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX 7
|
||||
|
||||
|
||||
#endif
|
||||
692
extra/amdpci/headers/mp_14_0_2_sh_mask.h
Normal file
692
extra/amdpci/headers/mp_14_0_2_sh_mask.h
Normal file
@@ -0,0 +1,692 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _mp_14_0_2_SH_MASK_HEADER
|
||||
#define _mp_14_0_2_SH_MASK_HEADER
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1_SmnDec
|
||||
//MP1_SMN_C2PMSG_0
|
||||
#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_1
|
||||
#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_2
|
||||
#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_3
|
||||
#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_4
|
||||
#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_5
|
||||
#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_6
|
||||
#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_7
|
||||
#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_8
|
||||
#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_9
|
||||
#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_10
|
||||
#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_11
|
||||
#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_12
|
||||
#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_13
|
||||
#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_14
|
||||
#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_15
|
||||
#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_16
|
||||
#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_17
|
||||
#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_18
|
||||
#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_19
|
||||
#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_20
|
||||
#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_21
|
||||
#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_22
|
||||
#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_23
|
||||
#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_24
|
||||
#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_25
|
||||
#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_26
|
||||
#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_27
|
||||
#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_28
|
||||
#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_29
|
||||
#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_30
|
||||
#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_31
|
||||
#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_32
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_33
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_34
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_35
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_36
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_37
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_38
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_39
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_40
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_41
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_42
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_43
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_44
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_45
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_46
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_47
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_48
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_49
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_50
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_51
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_52
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_53
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_54
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_55
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_56
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_57
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_58
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_59
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_60
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_61
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_62
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_63
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_64
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_65
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_66
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_67
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_68
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_69
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_70
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_71
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_72
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_73
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_74
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_75
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_76
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_77
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_78
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_79
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_80
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_81
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_82
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_83
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_84
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_85
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_86
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_87
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_88
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_89
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_90
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_91
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_92
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_93
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_94
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_95
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_96
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_97
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_98
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_99
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_100
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_101
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_102
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_103
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_104
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_105
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_106
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_107
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_108
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_109
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_110
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_111
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_112
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_113
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_114
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_115
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_116
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_117
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_118
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_119
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_120
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_121
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_122
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_123
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_124
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_125
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_126
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_127
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_IH_CREDIT
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
|
||||
//MP1_SMN_IH_SW_INT
|
||||
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
|
||||
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
|
||||
//MP1_SMN_IH_SW_INT_CTRL
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
|
||||
//MP1_SMN_FPS_CNT
|
||||
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
|
||||
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_PUB_CTRL
|
||||
#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0
|
||||
#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L
|
||||
//MP1_SMN_EXT_SCRATCH0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH1
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH2
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH3
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH4
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH5
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH6
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH7
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH8
|
||||
#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH9
|
||||
#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH10
|
||||
#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH11
|
||||
#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH12
|
||||
#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH13
|
||||
#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH14
|
||||
#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH15
|
||||
#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH16
|
||||
#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH17
|
||||
#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH18
|
||||
#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH19
|
||||
#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH20
|
||||
#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH21
|
||||
#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH22
|
||||
#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH23
|
||||
#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH24
|
||||
#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH25
|
||||
#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH26
|
||||
#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH27
|
||||
#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH28
|
||||
#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH29
|
||||
#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH30
|
||||
#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH31
|
||||
#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMpASP_SmnDec
|
||||
//MPASP_SMN_C2PMSG_32
|
||||
#define MPASP_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_33
|
||||
#define MPASP_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_34
|
||||
#define MPASP_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_35
|
||||
#define MPASP_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_36
|
||||
#define MPASP_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_37
|
||||
#define MPASP_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_38
|
||||
#define MPASP_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_39
|
||||
#define MPASP_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_60
|
||||
#define MPASP_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_61
|
||||
#define MPASP_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_62
|
||||
#define MPASP_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_63
|
||||
#define MPASP_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_64
|
||||
#define MPASP_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_65
|
||||
#define MPASP_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_66
|
||||
#define MPASP_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_67
|
||||
#define MPASP_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_68
|
||||
#define MPASP_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_69
|
||||
#define MPASP_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_70
|
||||
#define MPASP_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_71
|
||||
#define MPASP_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_72
|
||||
#define MPASP_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_73
|
||||
#define MPASP_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_74
|
||||
#define MPASP_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_75
|
||||
#define MPASP_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_76
|
||||
#define MPASP_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_77
|
||||
#define MPASP_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_78
|
||||
#define MPASP_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_79
|
||||
#define MPASP_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_80
|
||||
#define MPASP_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_81
|
||||
#define MPASP_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_82
|
||||
#define MPASP_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_83
|
||||
#define MPASP_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_84
|
||||
#define MPASP_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_85
|
||||
#define MPASP_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_86
|
||||
#define MPASP_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_87
|
||||
#define MPASP_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_88
|
||||
#define MPASP_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_89
|
||||
#define MPASP_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_100
|
||||
#define MPASP_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_101
|
||||
#define MPASP_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_102
|
||||
#define MPASP_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_103
|
||||
#define MPASP_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_109
|
||||
#define MPASP_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_115
|
||||
#define MPASP_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_C2PMSG_116
|
||||
#define MPASP_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
|
||||
#define MPASP_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MPASP_SMN_IH_CREDIT
|
||||
#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
|
||||
#define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
|
||||
#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
|
||||
#define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
|
||||
//MPASP_SMN_IH_SW_INT
|
||||
#define MPASP_SMN_IH_SW_INT__ID__SHIFT 0x0
|
||||
#define MPASP_SMN_IH_SW_INT__VALID__SHIFT 0x8
|
||||
#define MPASP_SMN_IH_SW_INT__ID_MASK 0x000000FFL
|
||||
#define MPASP_SMN_IH_SW_INT__VALID_MASK 0x00000100L
|
||||
//MPASP_SMN_IH_SW_INT_CTRL
|
||||
#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
|
||||
#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
|
||||
#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
|
||||
#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
|
||||
|
||||
|
||||
// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec
|
||||
//MP1_CRU1_MP1_FIRMWARE_FLAGS
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
|
||||
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
|
||||
|
||||
|
||||
#endif
|
||||
279
extra/amdpci/headers/osssys_7_0_0_offset.h
Normal file
279
extra/amdpci/headers/osssys_7_0_0_offset.h
Normal file
@@ -0,0 +1,279 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef _osssys_7_0_0_OFFSET_HEADER
|
||||
#define _osssys_7_0_0_OFFSET_HEADER
|
||||
|
||||
|
||||
|
||||
// addressBlock: osssys_osssysdec
|
||||
// base address: 0x4280
|
||||
#define regIH_VMID_0_LUT 0x0000
|
||||
#define regIH_VMID_0_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_1_LUT 0x0001
|
||||
#define regIH_VMID_1_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_2_LUT 0x0002
|
||||
#define regIH_VMID_2_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_3_LUT 0x0003
|
||||
#define regIH_VMID_3_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_4_LUT 0x0004
|
||||
#define regIH_VMID_4_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_5_LUT 0x0005
|
||||
#define regIH_VMID_5_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_6_LUT 0x0006
|
||||
#define regIH_VMID_6_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_7_LUT 0x0007
|
||||
#define regIH_VMID_7_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_8_LUT 0x0008
|
||||
#define regIH_VMID_8_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_9_LUT 0x0009
|
||||
#define regIH_VMID_9_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_10_LUT 0x000a
|
||||
#define regIH_VMID_10_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_11_LUT 0x000b
|
||||
#define regIH_VMID_11_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_12_LUT 0x000c
|
||||
#define regIH_VMID_12_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_13_LUT 0x000d
|
||||
#define regIH_VMID_13_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_14_LUT 0x000e
|
||||
#define regIH_VMID_14_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_15_LUT 0x000f
|
||||
#define regIH_VMID_15_LUT_BASE_IDX 0
|
||||
#define regIH_VMID_0_LUT_MM 0x0010
|
||||
#define regIH_VMID_0_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_1_LUT_MM 0x0011
|
||||
#define regIH_VMID_1_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_2_LUT_MM 0x0012
|
||||
#define regIH_VMID_2_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_3_LUT_MM 0x0013
|
||||
#define regIH_VMID_3_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_4_LUT_MM 0x0014
|
||||
#define regIH_VMID_4_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_5_LUT_MM 0x0015
|
||||
#define regIH_VMID_5_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_6_LUT_MM 0x0016
|
||||
#define regIH_VMID_6_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_7_LUT_MM 0x0017
|
||||
#define regIH_VMID_7_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_8_LUT_MM 0x0018
|
||||
#define regIH_VMID_8_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_9_LUT_MM 0x0019
|
||||
#define regIH_VMID_9_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_10_LUT_MM 0x001a
|
||||
#define regIH_VMID_10_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_11_LUT_MM 0x001b
|
||||
#define regIH_VMID_11_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_12_LUT_MM 0x001c
|
||||
#define regIH_VMID_12_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_13_LUT_MM 0x001d
|
||||
#define regIH_VMID_13_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_14_LUT_MM 0x001e
|
||||
#define regIH_VMID_14_LUT_MM_BASE_IDX 0
|
||||
#define regIH_VMID_15_LUT_MM 0x001f
|
||||
#define regIH_VMID_15_LUT_MM_BASE_IDX 0
|
||||
#define regIH_COOKIE_0 0x0020
|
||||
#define regIH_COOKIE_0_BASE_IDX 0
|
||||
#define regIH_COOKIE_1 0x0021
|
||||
#define regIH_COOKIE_1_BASE_IDX 0
|
||||
#define regIH_COOKIE_2 0x0022
|
||||
#define regIH_COOKIE_2_BASE_IDX 0
|
||||
#define regIH_COOKIE_3 0x0023
|
||||
#define regIH_COOKIE_3_BASE_IDX 0
|
||||
#define regIH_COOKIE_4 0x0024
|
||||
#define regIH_COOKIE_4_BASE_IDX 0
|
||||
#define regIH_COOKIE_5 0x0025
|
||||
#define regIH_COOKIE_5_BASE_IDX 0
|
||||
#define regIH_COOKIE_6 0x0026
|
||||
#define regIH_COOKIE_6_BASE_IDX 0
|
||||
#define regIH_COOKIE_7 0x0027
|
||||
#define regIH_COOKIE_7_BASE_IDX 0
|
||||
#define regIH_REGISTER_LAST_PART0 0x003f
|
||||
#define regIH_REGISTER_LAST_PART0_BASE_IDX 0
|
||||
#define regIH_RB_CNTL 0x0080
|
||||
#define regIH_RB_CNTL_BASE_IDX 0
|
||||
#define regIH_RB_RPTR 0x0081
|
||||
#define regIH_RB_RPTR_BASE_IDX 0
|
||||
#define regIH_RB_WPTR 0x0082
|
||||
#define regIH_RB_WPTR_BASE_IDX 0
|
||||
#define regIH_RB_BASE 0x0083
|
||||
#define regIH_RB_BASE_BASE_IDX 0
|
||||
#define regIH_RB_BASE_HI 0x0084
|
||||
#define regIH_RB_BASE_HI_BASE_IDX 0
|
||||
#define regIH_RB_WPTR_ADDR_HI 0x0085
|
||||
#define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0
|
||||
#define regIH_RB_WPTR_ADDR_LO 0x0086
|
||||
#define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0
|
||||
#define regIH_DOORBELL_RPTR 0x0087
|
||||
#define regIH_DOORBELL_RPTR_BASE_IDX 0
|
||||
#define regIH_DOORBELL_RETRY_CAM 0x0088
|
||||
#define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0
|
||||
#define regIH_RB_CNTL_RING1 0x008c
|
||||
#define regIH_RB_CNTL_RING1_BASE_IDX 0
|
||||
#define regIH_RB_RPTR_RING1 0x008d
|
||||
#define regIH_RB_RPTR_RING1_BASE_IDX 0
|
||||
#define regIH_RB_WPTR_RING1 0x008e
|
||||
#define regIH_RB_WPTR_RING1_BASE_IDX 0
|
||||
#define regIH_RB_BASE_RING1 0x008f
|
||||
#define regIH_RB_BASE_RING1_BASE_IDX 0
|
||||
#define regIH_RB_BASE_HI_RING1 0x0090
|
||||
#define regIH_RB_BASE_HI_RING1_BASE_IDX 0
|
||||
#define regIH_DOORBELL_RPTR_RING1 0x0093
|
||||
#define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0
|
||||
#define regIH_RETRY_CAM_ACK 0x00a4
|
||||
#define regIH_RETRY_CAM_ACK_BASE_IDX 0
|
||||
#define regIH_VERSION 0x00a5
|
||||
#define regIH_VERSION_BASE_IDX 0
|
||||
#define regIH_CNTL 0x00a8
|
||||
#define regIH_CNTL_BASE_IDX 0
|
||||
#define regIH_CLK_CTRL 0x00a9
|
||||
#define regIH_CLK_CTRL_BASE_IDX 0
|
||||
#define regIH_STORM_CLIENT_LIST_CNTL 0x00aa
|
||||
#define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
|
||||
#define regIH_LIMIT_INT_RATE_CNTL 0x00ab
|
||||
#define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
|
||||
#define regIH_RETRY_INT_CAM_CNTL 0x00ac
|
||||
#define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0
|
||||
#define regIH_MEM_POWER_CTRL 0x00ad
|
||||
#define regIH_MEM_POWER_CTRL_BASE_IDX 0
|
||||
#define regIH_MEM_POWER_CTRL2 0x00ae
|
||||
#define regIH_MEM_POWER_CTRL2_BASE_IDX 0
|
||||
#define regIH_CNTL2 0x00c1
|
||||
#define regIH_CNTL2_BASE_IDX 0
|
||||
#define regIH_STATUS 0x00c2
|
||||
#define regIH_STATUS_BASE_IDX 0
|
||||
#define regIH_PERFMON_CNTL 0x00c3
|
||||
#define regIH_PERFMON_CNTL_BASE_IDX 0
|
||||
#define regIH_PERFCOUNTER0_RESULT 0x00c4
|
||||
#define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0
|
||||
#define regIH_PERFCOUNTER1_RESULT 0x00c5
|
||||
#define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
|
||||
#define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca
|
||||
#define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_DATA_CONTROL 0x00cb
|
||||
#define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
|
||||
#define regIH_DSM_MATCH_FCN_ID 0x00cc
|
||||
#define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0
|
||||
#define regIH_VF_RB_STATUS 0x00ce
|
||||
#define regIH_VF_RB_STATUS_BASE_IDX 0
|
||||
#define regIH_VF_RB_STATUS2 0x00cf
|
||||
#define regIH_VF_RB_STATUS2_BASE_IDX 0
|
||||
#define regIH_VF_RB1_STATUS 0x00d0
|
||||
#define regIH_VF_RB1_STATUS_BASE_IDX 0
|
||||
#define regIH_VF_RB1_STATUS2 0x00d1
|
||||
#define regIH_VF_RB1_STATUS2_BASE_IDX 0
|
||||
#define regIH_RB_STATUS 0x00d4
|
||||
#define regIH_RB_STATUS_BASE_IDX 0
|
||||
#define regIH_INT_FLOOD_CNTL 0x00d5
|
||||
#define regIH_INT_FLOOD_CNTL_BASE_IDX 0
|
||||
#define regIH_RB0_INT_FLOOD_STATUS 0x00d6
|
||||
#define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
|
||||
#define regIH_RB1_INT_FLOOD_STATUS 0x00d7
|
||||
#define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
|
||||
#define regIH_INT_FLOOD_STATUS 0x00d9
|
||||
#define regIH_INT_FLOOD_STATUS_BASE_IDX 0
|
||||
#define regIH_INT_FLAGS 0x00dc
|
||||
#define regIH_INT_FLAGS_BASE_IDX 0
|
||||
#define regIH_SCRATCH 0x00e0
|
||||
#define regIH_SCRATCH_BASE_IDX 0
|
||||
#define regIH_CLIENT_CREDIT_ERROR 0x00e1
|
||||
#define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
|
||||
#define regIH_GPU_IOV_VIOLATION_LOG 0x00e2
|
||||
#define regIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
|
||||
#define regIH_GPU_IOV_VIOLATION_LOG2 0x00e3
|
||||
#define regIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
|
||||
#define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4
|
||||
#define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
|
||||
#define regIH_CREDIT_STATUS 0x00e5
|
||||
#define regIH_CREDIT_STATUS_BASE_IDX 0
|
||||
#define regIH_MMHUB_ERROR 0x00e6
|
||||
#define regIH_MMHUB_ERROR_BASE_IDX 0
|
||||
#define regIH_VF_RB_STATUS3 0x00ea
|
||||
#define regIH_VF_RB_STATUS3_BASE_IDX 0
|
||||
#define regIH_VF_RB_STATUS4 0x00eb
|
||||
#define regIH_VF_RB_STATUS4_BASE_IDX 0
|
||||
#define regIH_VF_RB1_STATUS3 0x00ec
|
||||
#define regIH_VF_RB1_STATUS3_BASE_IDX 0
|
||||
#define regIH_MSI_STORM_CTRL 0x00f1
|
||||
#define regIH_MSI_STORM_CTRL_BASE_IDX 0
|
||||
#define regIH_MSI_STORM_CLIENT_INDEX 0x00f2
|
||||
#define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0
|
||||
#define regIH_MSI_STORM_CLIENT_DATA 0x00f3
|
||||
#define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0
|
||||
#define regIH_LAST_INT_INFO0 0x00f9
|
||||
#define regIH_LAST_INT_INFO0_BASE_IDX 0
|
||||
#define regIH_LAST_INT_INFO1 0x00fa
|
||||
#define regIH_LAST_INT_INFO1_BASE_IDX 0
|
||||
#define regIH_LAST_INT_INFO2 0x00fb
|
||||
#define regIH_LAST_INT_INFO2_BASE_IDX 0
|
||||
#define regIH_REGISTER_LAST_PART2 0x00ff
|
||||
#define regIH_REGISTER_LAST_PART2_BASE_IDX 0
|
||||
#define regSEM_MAILBOX 0x010a
|
||||
#define regSEM_MAILBOX_BASE_IDX 0
|
||||
#define regSEM_MAILBOX_CLEAR 0x010b
|
||||
#define regSEM_MAILBOX_CLEAR_BASE_IDX 0
|
||||
#define regSEM_REGISTER_LAST_PART2 0x017f
|
||||
#define regSEM_REGISTER_LAST_PART2_BASE_IDX 0
|
||||
#define regIH_ACTIVE_FCN_ID 0x0180
|
||||
#define regIH_ACTIVE_FCN_ID_BASE_IDX 0
|
||||
#define regIH_VIRT_RESET_REQ 0x0181
|
||||
#define regIH_VIRT_RESET_REQ_BASE_IDX 0
|
||||
#define regIH_CLIENT_CFG 0x0182
|
||||
#define regIH_CLIENT_CFG_BASE_IDX 0
|
||||
#define regIH_RING1_CLIENT_CFG_INDEX 0x0183
|
||||
#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX 0
|
||||
#define regIH_RING1_CLIENT_CFG_DATA 0x0184
|
||||
#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX 0
|
||||
#define regIH_CLIENT_CFG_INDEX 0x0185
|
||||
#define regIH_CLIENT_CFG_INDEX_BASE_IDX 0
|
||||
#define regIH_CLIENT_CFG_DATA 0x0186
|
||||
#define regIH_CLIENT_CFG_DATA_BASE_IDX 0
|
||||
#define regIH_CLIENT_CFG_DATA2 0x0187
|
||||
#define regIH_CLIENT_CFG_DATA2_BASE_IDX 0
|
||||
#define regIH_CID_REMAP_INDEX 0x0188
|
||||
#define regIH_CID_REMAP_INDEX_BASE_IDX 0
|
||||
#define regIH_CID_REMAP_DATA 0x0189
|
||||
#define regIH_CID_REMAP_DATA_BASE_IDX 0
|
||||
#define regIH_CHICKEN 0x018a
|
||||
#define regIH_CHICKEN_BASE_IDX 0
|
||||
#define regIH_INT_DROP_CNTL 0x018c
|
||||
#define regIH_INT_DROP_CNTL_BASE_IDX 0
|
||||
#define regIH_INT_DROP_MATCH_VALUE0 0x018d
|
||||
#define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0
|
||||
#define regIH_INT_DROP_MATCH_VALUE1 0x018e
|
||||
#define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0
|
||||
#define regIH_INT_DROP_MATCH_MASK0 0x018f
|
||||
#define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0
|
||||
#define regIH_INT_DROP_MATCH_MASK1 0x0190
|
||||
#define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0
|
||||
#define regIH_MMHUB_CNTL 0x01a7
|
||||
#define regIH_MMHUB_CNTL_BASE_IDX 0
|
||||
#define regIH_REGISTER_LAST_PART1 0x01a8
|
||||
#define regIH_REGISTER_LAST_PART1_BASE_IDX 0
|
||||
|
||||
#endif
|
||||
1029
extra/amdpci/headers/osssys_7_0_0_sh_mask.h
Normal file
1029
extra/amdpci/headers/osssys_7_0_0_sh_mask.h
Normal file
File diff suppressed because it is too large
Load Diff
1889
extra/amdpci/headers/smu14_driver_if_v14_0.h
Normal file
1889
extra/amdpci/headers/smu14_driver_if_v14_0.h
Normal file
File diff suppressed because it is too large
Load Diff
262
extra/amdpci/headers/smu14_driver_if_v14_0_0.h
Normal file
262
extra/amdpci/headers/smu14_driver_if_v14_0_0.h
Normal file
@@ -0,0 +1,262 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SMU14_DRIVER_IF_V14_0_0_H
|
||||
#define SMU14_DRIVER_IF_V14_0_0_H
|
||||
|
||||
typedef struct {
|
||||
int32_t value;
|
||||
uint32_t numFractionalBits;
|
||||
} FloatInIntFormat_t;
|
||||
|
||||
typedef enum {
|
||||
DSPCLK_DCFCLK = 0,
|
||||
DSPCLK_DISPCLK,
|
||||
DSPCLK_PIXCLK,
|
||||
DSPCLK_PHYCLK,
|
||||
DSPCLK_COUNT,
|
||||
} DSPCLK_e;
|
||||
|
||||
typedef struct {
|
||||
uint16_t Freq; // in MHz
|
||||
uint16_t Vid; // min voltage in SVI3 VID
|
||||
} DisplayClockTable_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MinMclk;
|
||||
uint16_t MaxMclk;
|
||||
|
||||
uint8_t WmSetting;
|
||||
uint8_t WmType; // Used for normal pstate change or memory retraining
|
||||
uint8_t Padding[2];
|
||||
} WatermarkRowGeneric_t;
|
||||
|
||||
#define NUM_WM_RANGES 4
|
||||
#define WM_PSTATE_CHG 0
|
||||
#define WM_RETRAINING 1
|
||||
|
||||
typedef enum {
|
||||
WM_SOCCLK = 0,
|
||||
WM_DCFCLK,
|
||||
WM_COUNT,
|
||||
} WM_CLOCK_e;
|
||||
|
||||
typedef struct {
|
||||
// Watermarks
|
||||
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
|
||||
|
||||
uint32_t MmHubPadding[7]; // SMU internal use
|
||||
} Watermarks_t;
|
||||
|
||||
typedef enum {
|
||||
CUSTOM_DPM_SETTING_GFXCLK,
|
||||
CUSTOM_DPM_SETTING_CCLK,
|
||||
CUSTOM_DPM_SETTING_FCLK_CCX,
|
||||
CUSTOM_DPM_SETTING_FCLK_GFX,
|
||||
CUSTOM_DPM_SETTING_FCLK_STALLS,
|
||||
CUSTOM_DPM_SETTING_LCLK,
|
||||
CUSTOM_DPM_SETTING_COUNT,
|
||||
} CUSTOM_DPM_SETTING_e;
|
||||
|
||||
typedef struct {
|
||||
uint8_t ActiveHystLimit;
|
||||
uint8_t IdleHystLimit;
|
||||
uint8_t FPS;
|
||||
uint8_t MinActiveFreqType;
|
||||
FloatInIntFormat_t MinActiveFreq;
|
||||
FloatInIntFormat_t PD_Data_limit;
|
||||
FloatInIntFormat_t PD_Data_time_constant;
|
||||
FloatInIntFormat_t PD_Data_error_coeff;
|
||||
FloatInIntFormat_t PD_Data_error_rate_coeff;
|
||||
} DpmActivityMonitorCoeffExt_t;
|
||||
|
||||
typedef struct {
|
||||
DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
|
||||
} CustomDpmSettings_t;
|
||||
|
||||
#define NUM_DCFCLK_DPM_LEVELS 8
|
||||
#define NUM_DISPCLK_DPM_LEVELS 8
|
||||
#define NUM_DPPCLK_DPM_LEVELS 8
|
||||
#define NUM_SOCCLK_DPM_LEVELS 8
|
||||
#define NUM_VCN_DPM_LEVELS 8
|
||||
#define NUM_SOC_VOLTAGE_LEVELS 8
|
||||
#define NUM_VPE_DPM_LEVELS 8
|
||||
#define NUM_FCLK_DPM_LEVELS 8
|
||||
#define NUM_MEM_PSTATE_LEVELS 4
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t UClk;
|
||||
uint32_t MemClk;
|
||||
uint32_t Voltage;
|
||||
uint8_t WckRatio;
|
||||
uint8_t Spare[3];
|
||||
} MemPstateTable_t;
|
||||
|
||||
//Freq in MHz
|
||||
//Voltage in milli volts with 2 fractional bits
|
||||
typedef struct {
|
||||
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
|
||||
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
|
||||
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
|
||||
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
|
||||
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
|
||||
MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
|
||||
|
||||
uint8_t NumDcfClkLevelsEnabled;
|
||||
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
|
||||
uint8_t NumSocClkLevelsEnabled;
|
||||
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
|
||||
uint8_t VpeClkLevelsEnabled;
|
||||
|
||||
uint8_t NumMemPstatesEnabled;
|
||||
uint8_t NumFclkLevelsEnabled;
|
||||
uint8_t spare[2];
|
||||
|
||||
uint32_t MinGfxClk;
|
||||
uint32_t MaxGfxClk;
|
||||
} DpmClocks_t;
|
||||
|
||||
//Freq in MHz
|
||||
//Voltage in milli volts with 2 fractional bits
|
||||
typedef struct {
|
||||
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
|
||||
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
|
||||
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
|
||||
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
|
||||
uint32_t VClocks0[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t VClocks1[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks0[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks1[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
|
||||
MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
|
||||
|
||||
uint8_t NumDcfClkLevelsEnabled;
|
||||
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
|
||||
uint8_t NumSocClkLevelsEnabled;
|
||||
uint8_t Vcn0ClkLevelsEnabled; //Applies to both Vclk0 and Dclk0
|
||||
uint8_t Vcn1ClkLevelsEnabled; //Applies to both Vclk1 and Dclk1
|
||||
uint8_t VpeClkLevelsEnabled;
|
||||
uint8_t NumMemPstatesEnabled;
|
||||
uint8_t NumFclkLevelsEnabled;
|
||||
|
||||
uint32_t MinGfxClk;
|
||||
uint32_t MaxGfxClk;
|
||||
} DpmClocks_t_v14_0_1;
|
||||
|
||||
typedef struct {
|
||||
uint16_t CoreFrequency[16]; //Target core frequency [MHz]
|
||||
uint16_t CorePower[16]; //CAC calculated core power [mW]
|
||||
uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C]
|
||||
uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C]
|
||||
uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C]
|
||||
uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW]
|
||||
uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW]
|
||||
uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
|
||||
uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
|
||||
uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]
|
||||
uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
|
||||
uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz]
|
||||
uint16_t GfxActivity; //Time filtered GFX busy % [0-100]
|
||||
uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz]
|
||||
uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz]
|
||||
uint16_t VcnActivity; //Time filtered VCN busy % [0-100]
|
||||
uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz]
|
||||
uint16_t IpuclkFrequency; //Time filtered target IPUCLK frequency [MHz]
|
||||
uint16_t IpuBusy[8]; //Time filtered IPU per-column busy % [0-100]
|
||||
uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec]
|
||||
uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec]
|
||||
uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100]
|
||||
uint16_t IpuPower; //Time filtered IPU power [mW]
|
||||
uint32_t ApuPower; //Time filtered APU power [mW]
|
||||
uint32_t GfxPower; //Time filtered GFX power [mW]
|
||||
uint32_t dGpuPower; //Time filtered dGPU power [mW]
|
||||
uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
|
||||
uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]
|
||||
uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us]
|
||||
uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles]
|
||||
uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz]
|
||||
uint16_t MpipuclkFrequency; //Time filtered target MPIPUCLK frequency [MHz]
|
||||
uint16_t IpuReads; //Time filtered IPU read bandwidth [MB/sec]
|
||||
uint16_t IpuWrites; //Time filtered IPU write bandwidth [MB/sec]
|
||||
uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_GFX; //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles]
|
||||
uint16_t Psys; //Time filtered Psys power [mW]
|
||||
uint16_t spare1;
|
||||
uint32_t spare[6];
|
||||
} SmuMetrics_t;
|
||||
|
||||
//ISP tile definitions
|
||||
typedef enum {
|
||||
TILE_XTILE = 0, //ONO0
|
||||
TILE_MTILE, //ONO1
|
||||
TILE_PDP, //ONO2
|
||||
TILE_CSTAT, //ONO2
|
||||
TILE_LME, //ONO3
|
||||
TILE_BYRP, //ONO4
|
||||
TILE_GRBP, //ONO4
|
||||
TILE_MCFP, //ONO4
|
||||
TILE_YUVP, //ONO4
|
||||
TILE_MCSC, //ONO4
|
||||
TILE_GDC, //ONO5
|
||||
TILE_MAX
|
||||
} TILE_NUM_e;
|
||||
|
||||
// Tile Selection (Based on arguments)
|
||||
#define ISP_TILE_SEL(tile) (1<<tile)
|
||||
#define ISP_TILE_SEL_ALL 0x7FF
|
||||
|
||||
// Workload bits
|
||||
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
|
||||
#define WORKLOAD_PPLIB_VIDEO_BIT 2
|
||||
#define WORKLOAD_PPLIB_VR_BIT 3
|
||||
#define WORKLOAD_PPLIB_COMPUTE_BIT 4
|
||||
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
|
||||
#define WORKLOAD_PPLIB_COUNT 6
|
||||
|
||||
#define TABLE_BIOS_IF 0 // Called by BIOS
|
||||
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
|
||||
#define TABLE_CUSTOM_DPM 2 // Called by Driver
|
||||
#define TABLE_BIOS_GPIO_CONFIG 3 // Called by BIOS
|
||||
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
|
||||
#define TABLE_MOMENTARY_PM 5 // Called by Tools
|
||||
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
|
||||
#define TABLE_SMU_METRICS 7 // Called by Driver and SMF/PMF
|
||||
#define TABLE_COUNT 8
|
||||
|
||||
#endif
|
||||
194
extra/amdpci/headers/smu_v14_0_0_pmfw.h
Normal file
194
extra/amdpci/headers/smu_v14_0_0_pmfw.h
Normal file
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SMU_V14_0_0_PMFW_H__
|
||||
#define __SMU_V14_0_0_PMFW_H__
|
||||
|
||||
#include "smu14_driver_if_v14_0_0.h"
|
||||
|
||||
#pragma pack(push, 1)
|
||||
|
||||
#define ENABLE_DEBUG_FEATURES
|
||||
|
||||
// Firmware features
|
||||
// Feature Control Defines
|
||||
#define FEATURE_CCLK_DPM_BIT 0
|
||||
#define FEATURE_FAN_CONTROLLER_BIT 1
|
||||
#define FEATURE_DATA_CALCULATION_BIT 2
|
||||
#define FEATURE_PPT_BIT 3
|
||||
#define FEATURE_TDC_BIT 4
|
||||
#define FEATURE_THERMAL_BIT 5
|
||||
#define FEATURE_FIT_BIT 6
|
||||
#define FEATURE_EDC_BIT 7
|
||||
#define FEATURE_PLL_POWER_DOWN_BIT 8
|
||||
#define FEATURE_VDDOFF_BIT 9
|
||||
#define FEATURE_VCN_DPM_BIT 10 /* this is for both VCN0 and VCN1 */
|
||||
#define FEATURE_DS_MPM_BIT 11
|
||||
#define FEATURE_FCLK_DPM_BIT 12
|
||||
#define FEATURE_SOCCLK_DPM_BIT 13
|
||||
#define FEATURE_DS_MPIO_BIT 14
|
||||
#define FEATURE_LCLK_DPM_BIT 15
|
||||
#define FEATURE_SHUBCLK_DPM_BIT 16
|
||||
#define FEATURE_DCFCLK_DPM_BIT 17
|
||||
#define FEATURE_ISP_DPM_BIT 18
|
||||
#define FEATURE_IPU_DPM_BIT 19
|
||||
#define FEATURE_GFX_DPM_BIT 20
|
||||
#define FEATURE_DS_GFXCLK_BIT 21
|
||||
#define FEATURE_DS_SOCCLK_BIT 22
|
||||
#define FEATURE_DS_LCLK_BIT 23
|
||||
#define FEATURE_LOW_POWER_DCNCLKS_BIT 24
|
||||
#define FEATURE_DS_SHUBCLK_BIT 25
|
||||
#define FEATURE_RESERVED0_BIT 26
|
||||
#define FEATURE_ZSTATES_BIT 27
|
||||
#define FEATURE_IOMMUL2_PG_BIT 28
|
||||
#define FEATURE_DS_FCLK_BIT 29
|
||||
#define FEATURE_DS_SMNCLK_BIT 30
|
||||
#define FEATURE_DS_MP1CLK_BIT 31
|
||||
#define FEATURE_WHISPER_MODE_BIT 32
|
||||
#define FEATURE_SMU_LOW_POWER_BIT 33
|
||||
#define FEATURE_RESERVED1_BIT 34 /* v14_0_0 SMART_L3_RINSER; v14_0_1 RESERVED1 */
|
||||
#define FEATURE_GFX_DEM_BIT 35 /* v14_0_0 SPARE; v14_0_1 GFX_DEM */
|
||||
#define FEATURE_PSI_BIT 36
|
||||
#define FEATURE_PROCHOT_BIT 37
|
||||
#define FEATURE_CPUOFF_BIT 38
|
||||
#define FEATURE_STAPM_BIT 39
|
||||
#define FEATURE_S0I3_BIT 40
|
||||
#define FEATURE_DF_LIGHT_CSTATE 41
|
||||
#define FEATURE_PERF_LIMIT_BIT 42
|
||||
#define FEATURE_CORE_DLDO_BIT 43
|
||||
#define FEATURE_DVO_BIT 44
|
||||
#define FEATURE_DS_VCN_BIT 45 /* v14_0_1 this is for both VCN0 and VCN1 */
|
||||
#define FEATURE_CPPC_BIT 46
|
||||
#define FEATURE_CPPC_PREFERRED_CORES 47
|
||||
#define FEATURE_DF_CSTATES_BIT 48
|
||||
#define FEATURE_FAST_PSTATE_CLDO_BIT 49 /* v14_0_0 SPARE */
|
||||
#define FEATURE_ATHUB_PG_BIT 50
|
||||
#define FEATURE_VDDOFF_ECO_BIT 51
|
||||
#define FEATURE_ZSTATES_ECO_BIT 52
|
||||
#define FEATURE_CC6_BIT 53
|
||||
#define FEATURE_DS_UMCCLK_BIT 54
|
||||
#define FEATURE_DS_ISPCLK_BIT 55
|
||||
#define FEATURE_DS_HSPCLK_BIT 56
|
||||
#define FEATURE_P3T_BIT 57
|
||||
#define FEATURE_DS_IPUCLK_BIT 58
|
||||
#define FEATURE_DS_VPECLK_BIT 59
|
||||
#define FEATURE_VPE_DPM_BIT 60
|
||||
#define FEATURE_SMART_L3_RINSER_BIT 61 /* v14_0_0 SPARE*/
|
||||
#define FEATURE_PCC_BIT 62 /* v14_0_0 FP_DIDT v14_0_1 PCC_BIT */
|
||||
#define NUM_FEATURES 63
|
||||
|
||||
// Firmware Header/Footer
|
||||
struct SMU14_Firmware_Footer {
|
||||
uint32_t Signature;
|
||||
};
|
||||
typedef struct SMU14_Firmware_Footer SMU14_Firmware_Footer;
|
||||
|
||||
// PSP3.0 Header Definition
|
||||
typedef struct {
|
||||
uint32_t ImageVersion;
|
||||
uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug.
|
||||
uint32_t Padding0[3];
|
||||
uint32_t SizeFWSigned;
|
||||
uint32_t Padding1[25];
|
||||
uint32_t FirmwareType;
|
||||
uint32_t Filler[32];
|
||||
} SMU_Firmware_Header;
|
||||
|
||||
typedef struct {
|
||||
// MP1_EXT_SCRATCH0
|
||||
uint32_t DpmHandlerID : 8;
|
||||
uint32_t ActivityMonitorID : 8;
|
||||
uint32_t DpmTimerID : 8;
|
||||
uint32_t DpmHubID : 4;
|
||||
uint32_t DpmHubTask : 4;
|
||||
// MP1_EXT_SCRATCH1
|
||||
uint32_t CclkSyncStatus : 8;
|
||||
uint32_t Ccx0CpuOff : 2;
|
||||
uint32_t Ccx1CpuOff : 2;
|
||||
uint32_t GfxOffStatus : 2;
|
||||
uint32_t VddOff : 1;
|
||||
uint32_t InWhisperMode : 1;
|
||||
uint32_t ZstateStatus : 4;
|
||||
uint32_t spare0 : 4;
|
||||
uint32_t DstateFun : 4;
|
||||
uint32_t DstateDev : 4;
|
||||
// MP1_EXT_SCRATCH2
|
||||
uint32_t P2JobHandler :24;
|
||||
uint32_t RsmuPmiP2PendingCnt : 8;
|
||||
// MP1_EXT_SCRATCH3
|
||||
uint32_t PostCode :32;
|
||||
// MP1_EXT_SCRATCH4
|
||||
uint32_t MsgPortBusy :24;
|
||||
uint32_t RsmuPmiP1Pending : 1;
|
||||
uint32_t DfCstateExitPending : 1;
|
||||
uint32_t Ccx0Pc6ExitPending : 1;
|
||||
uint32_t Ccx1Pc6ExitPending : 1;
|
||||
uint32_t WarmResetPending : 1;
|
||||
uint32_t spare1 : 3;
|
||||
// MP1_EXT_SCRATCH5
|
||||
uint32_t IdleMask :32;
|
||||
// MP1_EXT_SCRATCH6 = RTOS threads' status
|
||||
// MP1_EXT_SCRATCH7 = RTOS Current Job
|
||||
} FwStatus_t;
|
||||
|
||||
typedef struct {
|
||||
// MP1_EXT_SCRATCH0
|
||||
uint32_t DpmHandlerID : 8;
|
||||
uint32_t ActivityMonitorID : 8;
|
||||
uint32_t DpmTimerID : 8;
|
||||
uint32_t DpmHubID : 4;
|
||||
uint32_t DpmHubTask : 4;
|
||||
// MP1_EXT_SCRATCH1
|
||||
uint32_t CclkSyncStatus : 8;
|
||||
uint32_t ZstateStatus : 4;
|
||||
uint32_t Cpu1VddOff : 4;
|
||||
uint32_t DstateFun : 4;
|
||||
uint32_t DstateDev : 4;
|
||||
uint32_t GfxOffStatus : 2;
|
||||
uint32_t Cpu0Off : 2;
|
||||
uint32_t Cpu1Off : 2;
|
||||
uint32_t Cpu0VddOff : 2;
|
||||
// MP1_EXT_SCRATCH2
|
||||
uint32_t P2JobHandler :32;
|
||||
// MP1_EXT_SCRATCH3
|
||||
uint32_t PostCode :32;
|
||||
// MP1_EXT_SCRATCH4
|
||||
uint32_t MsgPortBusy :15;
|
||||
uint32_t RsmuPmiP1Pending : 1;
|
||||
uint32_t RsmuPmiP2PendingCnt : 8;
|
||||
uint32_t DfCstateExitPending : 1;
|
||||
uint32_t Pc6EntryPending : 1;
|
||||
uint32_t Pc6ExitPending : 1;
|
||||
uint32_t WarmResetPending : 1;
|
||||
uint32_t Mp0ClkPending : 1;
|
||||
uint32_t InWhisperMode : 1;
|
||||
uint32_t spare2 : 2;
|
||||
// MP1_EXT_SCRATCH5
|
||||
uint32_t IdleMask :32;
|
||||
// MP1_EXT_SCRATCH6 = RTOS threads' status
|
||||
// MP1_EXT_SCRATCH7 = RTOS Current Job
|
||||
} FwStatus_t_v14_0_1;
|
||||
|
||||
#pragma pack(pop)
|
||||
|
||||
#endif
|
||||
141
extra/amdpci/headers/smu_v14_0_0_ppsmc.h
Normal file
141
extra/amdpci/headers/smu_v14_0_0_ppsmc.h
Normal file
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SMU_V14_0_0_PPSMC_H__
|
||||
#define __SMU_V14_0_0_PPSMC_H__
|
||||
|
||||
/*! @mainpage PMFW-PPS (PPLib) Message Interface
|
||||
This documentation contains the subsections:\n\n
|
||||
@ref ResponseCodes\n
|
||||
@ref definitions\n
|
||||
@ref enums\n
|
||||
*/
|
||||
|
||||
/** @def PPS_PMFW_IF_VER
|
||||
* PPS (PPLib) to PMFW IF version 1.0
|
||||
*/
|
||||
#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor
|
||||
|
||||
/** @defgroup ResponseCodes PMFW Response Codes
|
||||
* @{
|
||||
*/
|
||||
// SMU Response Codes:
|
||||
#define PPSMC_Result_OK 0x1 ///< Message Response OK
|
||||
#define PPSMC_Result_Failed 0xFF ///< Message Response Failed
|
||||
#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
|
||||
#define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
|
||||
#define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
|
||||
/** @}*/
|
||||
|
||||
/** @defgroup definitions Message definitions
|
||||
* @{
|
||||
*/
|
||||
// Message Definitions:
|
||||
#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
|
||||
#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
|
||||
#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
|
||||
#define PPSMC_MSG_PowerDownVcn1 0x04 ///< Power down VCN1
|
||||
#define PPSMC_MSG_PowerUpVcn1 0x05 ///< Power up VCN1; VCN1 is power gated by default
|
||||
#define PPSMC_MSG_PowerDownVcn0 0x06 ///< Power down VCN0
|
||||
#define PPSMC_MSG_PowerUpVcn0 0x07 ///< Power up VCN0; VCN0 is power gated by default
|
||||
#define PPSMC_MSG_SetHardMinVcn0 0x08 ///< For wireless display
|
||||
#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
|
||||
#define PPSMC_MSG_SetHardMinVcn1 0x0A ///< For wireless display
|
||||
#define PPSMC_MSG_SetSoftMinVcn1 0x0B ///< Set soft min for VCN1 clocks (VCLK1 and DCLK1)
|
||||
#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
|
||||
#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
|
||||
#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
|
||||
#define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM
|
||||
#define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM
|
||||
#define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
|
||||
#define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW
|
||||
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
|
||||
#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
|
||||
#define PPSMC_MSG_SetSoftMinVcn0 0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)
|
||||
#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
|
||||
#define PPSMC_MSG_spare_0x17 0x17 ///< Get GFX clock frequency
|
||||
#define PPSMC_MSG_spare_0x18 0x18 ///< Get FCLK frequency
|
||||
#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry
|
||||
#define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry
|
||||
#define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
|
||||
#define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
|
||||
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
|
||||
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
|
||||
#define PPSMC_MSG_SetSoftMaxVcn0 0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)
|
||||
#define PPSMC_MSG_spare_0x20 0x20 ///< Set power limit percentage
|
||||
#define PPSMC_MSG_PowerDownJpeg0 0x21 ///< Power down Jpeg of VCN0
|
||||
#define PPSMC_MSG_PowerUpJpeg0 0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default
|
||||
#define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
|
||||
#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
|
||||
#define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
|
||||
#define PPSMC_MSG_PowerDownJpeg1 0x26 ///< Power down Jpeg of VCN1
|
||||
#define PPSMC_MSG_PowerUpJpeg1 0x27 ///< Power up Jpeg of VCN1; VCN1 is power gated by default
|
||||
#define PPSMC_MSG_SetSoftMaxVcn1 0x28 ///< Set soft max for VCN1 clocks (VCLK1 and DCLK1)
|
||||
#define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
|
||||
#define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
|
||||
#define PPSMC_MSG_SetHardMinIspiclkByFreq 0x2B ///< Set HardMin by frequency for ISPICLK
|
||||
#define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK
|
||||
#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN0.UMSCH (aka VSCH) scheduler
|
||||
#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN0.UMSCH (aka VSCH) scheduler
|
||||
#define PPSMC_Message_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
|
||||
#define PPSMC_Message_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
|
||||
#define PPSMC_MSG_PowerUpVpe 0x31 ///< Power up VPE
|
||||
#define PPSMC_MSG_PowerDownVpe 0x32 ///< Power down VPE
|
||||
#define PPSMC_MSG_GetVpeDpmTable 0x33 ///< Get VPE DPM table
|
||||
#define PPSMC_MSG_EnableLSdma 0x34 ///< Enable LSDMA
|
||||
#define PPSMC_MSG_DisableLSdma 0x35 ///< Disable LSDMA
|
||||
#define PPSMC_MSG_SetSoftMaxVpe 0x36 ///<
|
||||
#define PPSMC_MSG_SetSoftMinVpe 0x37 ///<
|
||||
#define PPSMC_MSG_MALLPowerController 0x38 ///< Set MALL control
|
||||
#define PPSMC_MSG_MALLPowerState 0x39 ///< Enter/Exit MALL PG
|
||||
#define PPSMC_Message_Count 0x3A ///< Total number of PPSMC messages
|
||||
/** @}*/
|
||||
|
||||
/**
|
||||
* @defgroup enums Enum Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @enum Mode_Reset_e
|
||||
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
|
||||
*/
|
||||
//argument for PPSMC_MSG_GfxDeviceDriverReset
|
||||
typedef enum {
|
||||
MODE1_RESET = 1, ///< Mode reset type 1
|
||||
MODE2_RESET = 2 ///< Mode reset type 2
|
||||
} Mode_Reset_e;
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @enum ZStates_e
|
||||
* Zstate types, argument for PPSMC_MSG_AllowZstates
|
||||
*/
|
||||
//Argument for PPSMC_MSG_AllowZstates
|
||||
typedef enum {
|
||||
DISALLOW_ZSTATES = 0, ///< Disallow Zstates
|
||||
ALLOW_ZSTATES_Z8 = 8, ///< Allows Z8 only
|
||||
ALLOW_ZSTATES_Z9 = 9, ///< Allows Z9 and Z8
|
||||
} ZStates_e;
|
||||
|
||||
/** @}*/
|
||||
#endif
|
||||
150
extra/amdpci/headers/smu_v14_0_2_ppsmc.h
Normal file
150
extra/amdpci/headers/smu_v14_0_2_ppsmc.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SMU_V14_0_2_PPSMC_H
|
||||
#define SMU_V14_0_2_PPSMC_H
|
||||
|
||||
#define PPSMC_VERSION 0x1
|
||||
|
||||
// SMU Response Codes:
|
||||
#define PPSMC_Result_OK 0x1
|
||||
#define PPSMC_Result_Failed 0xFF
|
||||
#define PPSMC_Result_UnknownCmd 0xFE
|
||||
#define PPSMC_Result_CmdRejectedPrereq 0xFD
|
||||
#define PPSMC_Result_CmdRejectedBusy 0xFC
|
||||
|
||||
// Message Definitions:
|
||||
// BASIC
|
||||
#define PPSMC_MSG_TestMessage 0x1
|
||||
#define PPSMC_MSG_GetSmuVersion 0x2
|
||||
#define PPSMC_MSG_GetDriverIfVersion 0x3
|
||||
#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
|
||||
#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
|
||||
#define PPSMC_MSG_EnableAllSmuFeatures 0x6
|
||||
#define PPSMC_MSG_DisableAllSmuFeatures 0x7
|
||||
#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
|
||||
#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
|
||||
#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
|
||||
#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
|
||||
#define PPSMC_MSG_GetRunningSmuFeaturesLow 0xC
|
||||
#define PPSMC_MSG_GetRunningSmuFeaturesHigh 0xD
|
||||
#define PPSMC_MSG_SetDriverDramAddrHigh 0xE
|
||||
#define PPSMC_MSG_SetDriverDramAddrLow 0xF
|
||||
#define PPSMC_MSG_SetToolsDramAddrHigh 0x10
|
||||
#define PPSMC_MSG_SetToolsDramAddrLow 0x11
|
||||
#define PPSMC_MSG_TransferTableSmu2Dram 0x12
|
||||
#define PPSMC_MSG_TransferTableDram2Smu 0x13
|
||||
#define PPSMC_MSG_UseDefaultPPTable 0x14
|
||||
|
||||
//BACO/BAMACO/BOMACO
|
||||
#define PPSMC_MSG_EnterBaco 0x15
|
||||
#define PPSMC_MSG_ExitBaco 0x16
|
||||
#define PPSMC_MSG_ArmD3 0x17
|
||||
#define PPSMC_MSG_BacoAudioD3PME 0x18
|
||||
|
||||
//DPM
|
||||
#define PPSMC_MSG_SetSoftMinByFreq 0x19
|
||||
#define PPSMC_MSG_SetSoftMaxByFreq 0x1A
|
||||
#define PPSMC_MSG_SetHardMinByFreq 0x1B
|
||||
#define PPSMC_MSG_SetHardMaxByFreq 0x1C
|
||||
#define PPSMC_MSG_GetMinDpmFreq 0x1D
|
||||
#define PPSMC_MSG_GetMaxDpmFreq 0x1E
|
||||
#define PPSMC_MSG_GetDpmFreqByIndex 0x1F
|
||||
#define PPSMC_MSG_OverridePcieParameters 0x20
|
||||
|
||||
//DramLog Set DramAddr
|
||||
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x21
|
||||
#define PPSMC_MSG_DramLogSetDramAddrLow 0x22
|
||||
#define PPSMC_MSG_DramLogSetDramSize 0x23
|
||||
#define PPSMC_MSG_SetWorkloadMask 0x24
|
||||
|
||||
#define PPSMC_MSG_GetVoltageByDpm 0x25 // Can be removed
|
||||
#define PPSMC_MSG_SetVideoFps 0x26 // Can be removed
|
||||
#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x27
|
||||
|
||||
//Power Gating
|
||||
#define PPSMC_MSG_AllowGfxOff 0x28
|
||||
#define PPSMC_MSG_DisallowGfxOff 0x29
|
||||
#define PPSMC_MSG_PowerUpVcn 0x2A
|
||||
#define PPSMC_MSG_PowerDownVcn 0x2B
|
||||
#define PPSMC_MSG_PowerUpJpeg 0x2C
|
||||
#define PPSMC_MSG_PowerDownJpeg 0x2D
|
||||
|
||||
//Resets
|
||||
#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
|
||||
|
||||
//Set SystemVirtual DramAddrHigh
|
||||
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30
|
||||
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x31
|
||||
//ACDC Power Source
|
||||
#define PPSMC_MSG_SetPptLimit 0x32
|
||||
#define PPSMC_MSG_GetPptLimit 0x33
|
||||
#define PPSMC_MSG_ReenableAcDcInterrupt 0x34
|
||||
#define PPSMC_MSG_NotifyPowerSource 0x35
|
||||
|
||||
//BTC
|
||||
#define PPSMC_MSG_RunDcBtc 0x36
|
||||
|
||||
// 0x37
|
||||
|
||||
//Others
|
||||
#define PPSMC_MSG_SetTemperatureInputSelect 0x38 // Can be removed
|
||||
#define PPSMC_MSG_SetFwDstatesMask 0x39
|
||||
#define PPSMC_MSG_SetThrottlerMask 0x3A
|
||||
|
||||
#define PPSMC_MSG_SetExternalClientDfCstateAllow 0x3B
|
||||
|
||||
#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x3C
|
||||
|
||||
//STB to dram log
|
||||
#define PPSMC_MSG_DumpSTBtoDram 0x3D
|
||||
#define PPSMC_MSG_STBtoDramLogSetDramAddress 0x3E
|
||||
#define PPSMC_MSG_DummyUndefined 0x3F
|
||||
#define PPSMC_MSG_STBtoDramLogSetDramSize 0x40
|
||||
#define PPSMC_MSG_SetOBMTraceBufferLogging 0x41
|
||||
|
||||
#define PPSMC_MSG_UseProfilingMode 0x42
|
||||
#define PPSMC_MSG_AllowGfxDcs 0x43
|
||||
#define PPSMC_MSG_DisallowGfxDcs 0x44
|
||||
#define PPSMC_MSG_EnableAudioStutterWA 0x45
|
||||
#define PPSMC_MSG_PowerUpUmsch 0x46
|
||||
#define PPSMC_MSG_PowerDownUmsch 0x47
|
||||
#define PPSMC_MSG_SetDcsArch 0x48
|
||||
#define PPSMC_MSG_TriggerVFFLR 0x49
|
||||
#define PPSMC_MSG_SetNumBadMemoryPagesRetired 0x4A
|
||||
#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4B
|
||||
#define PPSMC_MSG_SetPriorityDeltaGain 0x4C
|
||||
#define PPSMC_MSG_AllowIHHostInterrupt 0x4D
|
||||
#define PPSMC_MSG_EnableShadowDpm 0x4E
|
||||
#define PPSMC_MSG_Mode3Reset 0x4F
|
||||
#define PPSMC_MSG_SetDriverDramAddr 0x50
|
||||
#define PPSMC_MSG_SetToolsDramAddr 0x51
|
||||
#define PPSMC_MSG_TransferTableSmu2DramWithAddr 0x52
|
||||
#define PPSMC_MSG_TransferTableDram2SmuWithAddr 0x53
|
||||
#define PPSMC_MSG_GetAllRunningSmuFeatures 0x54
|
||||
#define PPSMC_MSG_GetSvi3Voltage 0x55
|
||||
#define PPSMC_MSG_UpdatePolicy 0x56
|
||||
#define PPSMC_MSG_ExtPwrConnSupport 0x57
|
||||
#define PPSMC_MSG_PreloadSwPstateForUclkOverDrive 0x58
|
||||
#define PPSMC_Message_Count 0x59
|
||||
#endif
|
||||
1191
extra/amdpci/headers/v12_structs.h
Normal file
1191
extra/amdpci/headers/v12_structs.h
Normal file
File diff suppressed because it is too large
Load Diff
7
test/external/external_test_am.py
vendored
7
test/external/external_test_am.py
vendored
@@ -2,10 +2,12 @@ import unittest
|
||||
from tinygrad.runtime.support.am.amdev import AMMemoryManager, AMPageTableTraverseContext
|
||||
from tinygrad.runtime.support.am.ip import AM_GMC
|
||||
from tinygrad.runtime.support.amd import import_module
|
||||
from tinygrad.runtime.autogen.am import am
|
||||
from tinygrad.helpers import mv_address
|
||||
|
||||
class FakeGMC(AM_GMC):
|
||||
def __init__(self):
|
||||
def __init__(self, adev):
|
||||
self.adev = adev
|
||||
self.vm_base = 0x0
|
||||
self.address_space_mask = (1 << 44) - 1
|
||||
def init_hw(self): pass
|
||||
@@ -19,9 +21,10 @@ class FakeAM:
|
||||
self.is_booting, self.smi_dev = True, False
|
||||
self.pcidev = FakePCIDev()
|
||||
self.vram = memoryview(bytearray(4 << 30))
|
||||
self.gmc = FakeGMC()
|
||||
self.gmc = FakeGMC(self)
|
||||
self.mm = AMMemoryManager(self, vram_size=4 << 30)
|
||||
self.is_booting = False
|
||||
self.ip_ver = {am.GC_HWIP: (11, 0, 0)}
|
||||
def paddr2cpu(self, paddr:int) -> int: return paddr + mv_address(self.vram)
|
||||
def paddr2mc(self, paddr:int) -> int: return paddr
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
1505
tinygrad/runtime/autogen/am/hdp_7_0_0.py
Normal file
1505
tinygrad/runtime/autogen/am/hdp_7_0_0.py
Normal file
File diff suppressed because it is too large
Load Diff
14362
tinygrad/runtime/autogen/am/mmhub_4_1_0.py
Normal file
14362
tinygrad/runtime/autogen/am/mmhub_4_1_0.py
Normal file
File diff suppressed because it is too large
Load Diff
1542
tinygrad/runtime/autogen/am/mp_14_0_3.py
Normal file
1542
tinygrad/runtime/autogen/am/mp_14_0_3.py
Normal file
File diff suppressed because it is too large
Load Diff
2063
tinygrad/runtime/autogen/am/osssys_7_0_0.py
Normal file
2063
tinygrad/runtime/autogen/am/osssys_7_0_0.py
Normal file
File diff suppressed because it is too large
Load Diff
3839
tinygrad/runtime/autogen/am/smu_v14_0_3.py
Normal file
3839
tinygrad/runtime/autogen/am/smu_v14_0_3.py
Normal file
File diff suppressed because it is too large
Load Diff
@@ -808,7 +808,7 @@ class AMDDevice(HCQCompiled):
|
||||
|
||||
self.soc = importlib.import_module(f"tinygrad.runtime.autogen.am.{({9: 'vega10', 10: 'navi10', 11: 'soc21', 12: 'soc24'}[self.gfxver])}")
|
||||
self.pm4 = importlib.import_module(f"tinygrad.runtime.autogen.am.pm4_{'nv' if self.gfxver >= 10 else 'soc15'}")
|
||||
self.sdma = import_module('sdma', self.dev_iface.ip_versions[am.SDMA0_HWIP])
|
||||
self.sdma = import_module('sdma', min(self.dev_iface.ip_versions[am.SDMA0_HWIP], (6, 0, 0)))
|
||||
self.gc = AMDIP('gc', self.dev_iface.ip_versions[am.GC_HWIP], self.dev_iface.ip_offsets[am.GC_HWIP])
|
||||
pad = (0,) if self.gfxver == 9 else () # ?!?!?!?!??!?!?!
|
||||
self.nbio = AMDIP('nbio' if self.gfxver < 12 else 'nbif', self.dev_iface.ip_versions[am.NBIF_HWIP], pad+self.dev_iface.ip_offsets[am.NBIF_HWIP])
|
||||
|
||||
@@ -45,9 +45,12 @@ class AMFirmware:
|
||||
self.smu_psp_desc = self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes, am.GFX_FW_TYPE_SMU)
|
||||
|
||||
# SDMA firmware
|
||||
blob, hdr = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", am.struct_sdma_firmware_header_v2_0)
|
||||
self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)]
|
||||
self.descs += [self.desc(blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH1)]
|
||||
blob, hdr = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", am.struct_sdma_firmware_header_v3_0)
|
||||
if hdr.header.header_version_major < 3:
|
||||
blob, hdr = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", am.struct_sdma_firmware_header_v2_0)
|
||||
self.descs += [self.desc(blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH1)]
|
||||
self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)]
|
||||
else: self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)]
|
||||
|
||||
# PFP, ME, MEC firmware
|
||||
for (fw_name, fw_cnt) in [('PFP', 2), ('ME', 2), ('MEC', 4)]:
|
||||
@@ -78,9 +81,10 @@ class AMFirmware:
|
||||
off, sz = getattr(hdr2, f'rlc_{fmem}_ucode_offset_bytes'), getattr(hdr2, f'rlc_{fmem}_ucode_size_bytes')
|
||||
self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))]
|
||||
|
||||
for mem in ['P', 'V']:
|
||||
off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes')
|
||||
self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))]
|
||||
if hdr0.header.header_version_minor == 3:
|
||||
for mem in ['P', 'V']:
|
||||
off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes')
|
||||
self.descs += [self.desc(blob, off, sz, getattr(am, f'GFX_FW_TYPE_RLC_{mem}'))]
|
||||
|
||||
self.descs += [self.desc(blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes, am.GFX_FW_TYPE_RLC_G)]
|
||||
|
||||
@@ -384,9 +388,9 @@ class AMDev:
|
||||
def _ip_module(self, prefix:str, hwip, prever_prefix:str=""): return import_module(prefix, self.ip_ver[hwip], prever_prefix)
|
||||
|
||||
def _build_regs(self):
|
||||
mods = [("MP0", self._ip_module("mp", am.MP0_HWIP)), ("NBIO", self._ip_module("nbio", am.NBIO_HWIP)), ("GC", self._ip_module("gc", am.GC_HWIP)),
|
||||
mods = [("MP0", self._ip_module("mp", am.MP0_HWIP)), ("HDP", self._ip_module("hdp", am.HDP_HWIP)), ("GC", self._ip_module("gc", am.GC_HWIP)),
|
||||
("MP1", mp_11_0), ("MMHUB", self._ip_module("mmhub", am.MMHUB_HWIP)), ("OSSSYS", self._ip_module("osssys", am.OSSSYS_HWIP)),
|
||||
("HDP", self._ip_module("hdp", am.HDP_HWIP))]
|
||||
("NBIO", self._ip_module("nbio" if self.ip_ver[am.GC_HWIP] < (12,0,0) else "nbif", am.NBIO_HWIP))]
|
||||
|
||||
for ip, module in mods:
|
||||
self.__dict__.update(collect_registers(module, cls=functools.partial(AMRegister, adev=self, hwip=getattr(am, f"{ip}_HWIP"))))
|
||||
|
||||
@@ -11,7 +11,9 @@ class AM_IP:
|
||||
def set_clockgating_state(self): pass # Set clockgating state for this IP
|
||||
|
||||
class AM_SOC(AM_IP):
|
||||
def init_sw(self): self.module = importlib.import_module("tinygrad.runtime.autogen.am.soc21")
|
||||
def init_sw(self):
|
||||
self.soc_ver = 24 if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else 21
|
||||
self.module = importlib.import_module(f"tinygrad.runtime.autogen.am.soc{self.soc_ver}")
|
||||
|
||||
def init_hw(self):
|
||||
self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0)
|
||||
@@ -19,9 +21,9 @@ class AM_SOC(AM_IP):
|
||||
def set_clockgating_state(self): self.adev.regHDP_MEM_POWER_CTRL.update(atomic_mem_power_ctrl_en=1, atomic_mem_power_ds_en=1)
|
||||
|
||||
def doorbell_enable(self, port, awid=0, awaddr_31_28_value=0, offset=0, size=0):
|
||||
self.adev.reg(f"regS2A_DOORBELL_ENTRY_{port}_CTRL").update(**{f"s2a_doorbell_port{port}_enable": 1, f"s2a_doorbell_port{port}_awid": awid,
|
||||
f"s2a_doorbell_port{port}_awaddr_31_28_value": awaddr_31_28_value, f"s2a_doorbell_port{port}_range_offset": offset,
|
||||
f"s2a_doorbell_port{port}_range_size": size})
|
||||
self.adev.reg(f"{'regGDC_S2A0_S2A' if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else 'regS2A'}_DOORBELL_ENTRY_{port}_CTRL").update(
|
||||
**{f"s2a_doorbell_port{port}_enable":1, f"s2a_doorbell_port{port}_awid":awid, f"s2a_doorbell_port{port}_awaddr_31_28_value":awaddr_31_28_value,
|
||||
f"s2a_doorbell_port{port}_range_offset":offset, f"s2a_doorbell_port{port}_range_size":size})
|
||||
|
||||
class AM_GMC(AM_IP):
|
||||
def init_sw(self):
|
||||
@@ -112,16 +114,22 @@ class AM_GMC(AM_IP):
|
||||
|
||||
def get_pte_flags(self, pte_lv, is_table, frag, uncached, system, snooped, valid, extra=0):
|
||||
extra |= (am.AMDGPU_PTE_SYSTEM * system) | (am.AMDGPU_PTE_SNOOPED * snooped) | (am.AMDGPU_PTE_VALID * valid) | am.AMDGPU_PTE_FRAG(frag)
|
||||
extra |= am.AMDGPU_PTE_MTYPE_NV10(0, self.adev.soc.module.MTYPE_UC if uncached else 0)
|
||||
if not is_table: extra |= (am.AMDGPU_PTE_WRITEABLE | am.AMDGPU_PTE_READABLE | am.AMDGPU_PTE_EXECUTABLE)
|
||||
return extra | (am.AMDGPU_PDE_PTE if not is_table and pte_lv != am.AMDGPU_VM_PTB else 0)
|
||||
def is_pte_huge_page(self, pte): return pte & am.AMDGPU_PDE_PTE
|
||||
if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0):
|
||||
extra |= am.AMDGPU_PTE_MTYPE_GFX12(0, self.adev.soc.module.MTYPE_UC if uncached else 0)
|
||||
extra |= (am.AMDGPU_PDE_PTE_GFX12 if not is_table and pte_lv != am.AMDGPU_VM_PTB else (am.AMDGPU_PTE_IS_PTE if not is_table else 0))
|
||||
else:
|
||||
extra |= am.AMDGPU_PTE_MTYPE_NV10(0, self.adev.soc.module.MTYPE_UC if uncached else 0)
|
||||
extra |= (am.AMDGPU_PDE_PTE if not is_table and pte_lv != am.AMDGPU_VM_PTB else 0)
|
||||
return extra
|
||||
def is_pte_huge_page(self, pte): return pte & (am.AMDGPU_PDE_PTE_GFX12 if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else am.AMDGPU_PDE_PTE)
|
||||
|
||||
def on_interrupt(self):
|
||||
for ip in ["MM", "GC"]:
|
||||
st, va = self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_STATUS').read(), self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_LO32').read()
|
||||
va = (va | (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_HI32').read()) << 32) << 12
|
||||
if self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_STATUS").read(): raise RuntimeError(f"{ip}VM_L2_PROTECTION_FAULT_STATUS: {st:#x} {va:#x}")
|
||||
st = self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_STATUS{'_LO32' if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else ''}").read()
|
||||
va = (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_LO32').read()
|
||||
| (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_HI32').read()) << 32) << 12
|
||||
if st: raise RuntimeError(f"{ip}VM_L2_PROTECTION_FAULT_STATUS: {st:#x} {va:#x}")
|
||||
|
||||
class AM_SMU(AM_IP):
|
||||
def init_sw(self):
|
||||
@@ -129,9 +137,9 @@ class AM_SMU(AM_IP):
|
||||
self.driver_table_paddr = self.adev.mm.palloc(0x4000, zero=not self.adev.partial_boot, boot=True)
|
||||
|
||||
def init_hw(self):
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrHigh, hi32(self.adev.paddr2mc(self.driver_table_paddr)), poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrLow, lo32(self.adev.paddr2mc(self.driver_table_paddr)), poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_EnableAllSmuFeatures, 0, poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrHigh, hi32(self.adev.paddr2mc(self.driver_table_paddr)))
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetDriverDramAddrLow, lo32(self.adev.paddr2mc(self.driver_table_paddr)))
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_EnableAllSmuFeatures, 0)
|
||||
|
||||
def is_smu_alive(self):
|
||||
with contextlib.suppress(RuntimeError): self._send_msg(self.smu_mod.PPSMC_MSG_GetSmuVersion, 0, timeout=100)
|
||||
@@ -139,11 +147,12 @@ class AM_SMU(AM_IP):
|
||||
|
||||
def mode1_reset(self):
|
||||
if DEBUG >= 2: print(f"am {self.adev.devfmt}: mode1 reset")
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_Mode1Reset, 0, poll=True)
|
||||
if self.adev.ip_ver[am.MP0_HWIP] >= (14,0,0): self._send_msg(__DEBUGSMC_MSG_Mode1Reset:=2, 0, debug=True)
|
||||
else: self._send_msg(self.smu_mod.PPSMC_MSG_Mode1Reset, 0)
|
||||
time.sleep(0.5) # 500ms
|
||||
|
||||
def read_table(self, table_t, cmd):
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_TransferTableSmu2Dram, cmd, poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_TransferTableSmu2Dram, cmd)
|
||||
return table_t.from_buffer(to_mv(self.adev.paddr2cpu(self.driver_table_paddr), ctypes.sizeof(table_t)))
|
||||
def read_metrics(self): return self.read_table(self.smu_mod.SmuMetricsExternal_t, self.smu_mod.TABLE_SMU_METRICS)
|
||||
|
||||
@@ -155,21 +164,18 @@ class AM_SMU(AM_IP):
|
||||
self.clcks[clck] = [self._send_msg(self.smu_mod.PPSMC_MSG_GetDpmFreqByIndex, (clck<<16)|i, read_back_arg=True)&0x7fffffff for i in range(cnt)]
|
||||
|
||||
for clck, vals in self.clcks.items():
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMinByFreq, clck << 16 | (vals[level]), poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMaxByFreq, clck << 16 | (vals[level]), poll=True)
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMinByFreq, clck << 16 | (vals[level]))
|
||||
self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMaxByFreq, clck << 16 | (vals[level]))
|
||||
|
||||
def _smu_cmn_poll_stat(self, timeout=10000): self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90, mask=0xFFFFFFFF, value=1, timeout=timeout)
|
||||
def _smu_cmn_send_msg(self, msg, param=0):
|
||||
self.adev.mmMP1_SMN_C2PMSG_90.write(0) # resp reg
|
||||
self.adev.mmMP1_SMN_C2PMSG_82.write(param)
|
||||
self.adev.mmMP1_SMN_C2PMSG_66.write(msg)
|
||||
def _smu_cmn_send_msg(self, msg, param=0, debug=False):
|
||||
(self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54).write(0) # resp reg
|
||||
(self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).write(param)
|
||||
(self.adev.mmMP1_SMN_C2PMSG_66 if not debug else self.adev.mmMP1_SMN_C2PMSG_75).write(msg)
|
||||
|
||||
def _send_msg(self, msg, param, poll=True, read_back_arg=False, timeout=10000): # 10s
|
||||
if poll: self._smu_cmn_poll_stat(timeout=timeout)
|
||||
|
||||
self._smu_cmn_send_msg(msg, param)
|
||||
self._smu_cmn_poll_stat(timeout=timeout)
|
||||
return self.adev.mmMP1_SMN_C2PMSG_82.read() if read_back_arg else None
|
||||
def _send_msg(self, msg, param, read_back_arg=False, timeout=10000, debug=False): # 10s
|
||||
self._smu_cmn_send_msg(msg, param, debug=debug)
|
||||
self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54, mask=0xFFFFFFFF, value=1, timeout=timeout)
|
||||
return (self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).read() if read_back_arg else None
|
||||
|
||||
class AM_GFX(AM_IP):
|
||||
def init_hw(self):
|
||||
@@ -181,6 +187,7 @@ class AM_GFX(AM_IP):
|
||||
|
||||
# NOTE: Golden reg for gfx11. No values for this reg provided. The kernel just ors 0x20000000 to this reg.
|
||||
self.adev.regTCP_CNTL.write(self.adev.regTCP_CNTL.read() | 0x20000000)
|
||||
|
||||
self.adev.regRLC_SRM_CNTL.update(srm_enable=1, auto_incr_addr=1)
|
||||
|
||||
self.adev.soc.doorbell_enable(port=0, awid=0x3, awaddr_31_28_value=0x3)
|
||||
@@ -219,7 +226,8 @@ class AM_GFX(AM_IP):
|
||||
def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int):
|
||||
mqd = self.adev.mm.valloc(0x1000, uncached=True, contigous=True)
|
||||
|
||||
mqd_struct = am.struct_v11_compute_mqd(header=0xC0310800, cp_mqd_base_addr_lo=lo32(mqd.va_addr), cp_mqd_base_addr_hi=hi32(mqd.va_addr),
|
||||
struct_t = getattr(am, f"struct_v{self.adev.ip_ver[am.GC_HWIP][0]}_compute_mqd")
|
||||
mqd_struct = struct_t(header=0xC0310800, cp_mqd_base_addr_lo=lo32(mqd.va_addr), cp_mqd_base_addr_hi=hi32(mqd.va_addr),
|
||||
cp_hqd_persistent_state=self.adev.regCP_HQD_PERSISTENT_STATE.encode(preload_size=0x55, preload_req=1),
|
||||
cp_hqd_pipe_priority=0x2, cp_hqd_queue_priority=0xf, cp_hqd_quantum=0x111,
|
||||
cp_hqd_pq_base_lo=lo32(ring_addr>>8), cp_hqd_pq_base_hi=hi32(ring_addr>>8),
|
||||
@@ -322,12 +330,15 @@ class AM_IH(AM_IP):
|
||||
self.adev.regIH_RB_RPTR.write(wptr % self.ring_size)
|
||||
|
||||
class AM_SDMA(AM_IP):
|
||||
def init_sw(self): self.sdma_name = "F32" if self.adev.ip_ver[am.SDMA0_HWIP] < (7,0,0) else "MCU"
|
||||
def init_hw(self):
|
||||
for pipe in range(2):
|
||||
self.adev.reg(f"regSDMA{pipe}_WATCHDOG_CNTL").update(queue_hang_count=100) # 10s, 100ms per unit
|
||||
self.adev.reg(f"regSDMA{pipe}_UTCL1_CNTL").update(resp_mode=3, redo_delay=9)
|
||||
self.adev.reg(f"regSDMA{pipe}_UTCL1_PAGE").update(rd_l2_policy=0x2, wr_l2_policy=0x3, llc_noalloc=1) # rd=noa, wr=bypass
|
||||
self.adev.reg(f"regSDMA{pipe}_F32_CNTL").update(halt=0, th1_reset=0)
|
||||
|
||||
# rd=noa, wr=bypass
|
||||
self.adev.reg(f"regSDMA{pipe}_UTCL1_PAGE").update(rd_l2_policy=0x2, wr_l2_policy=0x3, **({'llc_noalloc':1} if self.sdma_name == "F32" else {}))
|
||||
self.adev.reg(f"regSDMA{pipe}_{self.sdma_name}_CNTL").update(halt=0, **{f"{'th1_' if self.sdma_name == 'F32' else ''}reset":0})
|
||||
self.adev.reg(f"regSDMA{pipe}_CNTL").update(ctxempty_int_enable=1, trap_enable=1)
|
||||
self.adev.soc.doorbell_enable(port=2, awid=0xe, awaddr_31_28_value=0x3, offset=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0*2, size=4)
|
||||
|
||||
@@ -350,11 +361,12 @@ class AM_SDMA(AM_IP):
|
||||
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL").update(enable=1)
|
||||
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_MINOR_PTR_UPDATE").write(0x0)
|
||||
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").write(rb_vmid=0, rptr_writeback_enable=1, rptr_writeback_timer=4,
|
||||
f32_wptr_poll_enable=1, rb_size=(ring_size//4).bit_length()-1, rb_enable=1, rb_priv=1)
|
||||
**{f'{self.sdma_name.lower()}_wptr_poll_enable':1}, rb_size=(ring_size//4).bit_length()-1, rb_enable=1, rb_priv=1)
|
||||
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_IB_CNTL").update(ib_enable=1)
|
||||
|
||||
class AM_PSP(AM_IP):
|
||||
def init_sw(self):
|
||||
self.reg_pref = "regMP0_SMN_C2PMSG" if self.adev.ip_ver[am.MP0_HWIP] < (14,0,0) else "regMPASP_SMN_C2PMSG"
|
||||
self.msg1_paddr = self.adev.mm.palloc(am.PSP_1_MEG, align=am.PSP_1_MEG, zero=not self.adev.partial_boot, boot=True)
|
||||
self.cmd_paddr = self.adev.mm.palloc(am.PSP_CMD_BUFFER_SIZE, zero=not self.adev.partial_boot, boot=True)
|
||||
self.fence_paddr = self.adev.mm.palloc(am.PSP_FENCE_BUFFER_SIZE, zero=not self.adev.partial_boot, boot=True)
|
||||
@@ -363,11 +375,14 @@ class AM_PSP(AM_IP):
|
||||
self.ring_paddr = self.adev.mm.palloc(self.ring_size, zero=not self.adev.partial_boot, boot=True)
|
||||
|
||||
self.max_tmr_size = 0x1300000
|
||||
self.tmr_paddr = self.adev.mm.palloc(self.max_tmr_size, align=am.PSP_TMR_ALIGNMENT, zero=not self.adev.partial_boot, boot=True)
|
||||
self.boot_time_tmr = self.adev.ip_ver[am.GC_HWIP] >= (12,0,0)
|
||||
if not self.boot_time_tmr:
|
||||
self.tmr_paddr = self.adev.mm.palloc(self.max_tmr_size, align=am.PSP_TMR_ALIGNMENT, zero=not self.adev.partial_boot, boot=True)
|
||||
|
||||
def init_hw(self):
|
||||
spl_key = am.PSP_FW_TYPE_PSP_SPL if self.adev.ip_ver[am.MP0_HWIP] >= (14,0,0) else am.PSP_FW_TYPE_PSP_KDB
|
||||
sos_components_load_order = [
|
||||
(am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_KEY_DATABASE), (am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_TOS_SPL_TABLE),
|
||||
(am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_KEY_DATABASE), (spl_key, am.PSP_BL__LOAD_TOS_SPL_TABLE),
|
||||
(am.PSP_FW_TYPE_PSP_SYS_DRV, am.PSP_BL__LOAD_SYSDRV), (am.PSP_FW_TYPE_PSP_SOC_DRV, am.PSP_BL__LOAD_SOCDRV),
|
||||
(am.PSP_FW_TYPE_PSP_INTF_DRV, am.PSP_BL__LOAD_INTFDRV), (am.PSP_FW_TYPE_PSP_DBG_DRV, am.PSP_BL__LOAD_DBGDRV),
|
||||
(am.PSP_FW_TYPE_PSP_RAS_DRV, am.PSP_BL__LOAD_RASDRV), (am.PSP_FW_TYPE_PSP_SOS, am.PSP_BL__LOAD_SOSDRV)]
|
||||
@@ -381,14 +396,14 @@ class AM_PSP(AM_IP):
|
||||
|
||||
# SMU fw should be loaded before TMR.
|
||||
self._load_ip_fw_cmd(*self.adev.fw.smu_psp_desc)
|
||||
self._tmr_load_cmd()
|
||||
if not self.boot_time_tmr: self._tmr_load_cmd()
|
||||
|
||||
for psp_desc in self.adev.fw.descs: self._load_ip_fw_cmd(*psp_desc)
|
||||
self._rlc_autoload_cmd()
|
||||
|
||||
def is_sos_alive(self): return self.adev.regMP0_SMN_C2PMSG_81.read() != 0x0
|
||||
def is_sos_alive(self): return self.adev.reg(f"{self.reg_pref}_81").read() != 0x0
|
||||
|
||||
def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_35, mask=0xFFFFFFFF, value=0x80000000)
|
||||
def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_35"), mask=0x80000000, value=0x80000000)
|
||||
|
||||
def _prep_msg1(self, data):
|
||||
ctypes.memset(cpu_addr:=self.adev.paddr2cpu(self.msg1_paddr), 0, am.PSP_1_MEG)
|
||||
@@ -400,11 +415,13 @@ class AM_PSP(AM_IP):
|
||||
|
||||
self._wait_for_bootloader()
|
||||
|
||||
self._prep_msg1(self.adev.fw.sos_fw[fw])
|
||||
self.adev.regMP0_SMN_C2PMSG_36.write(self.adev.paddr2mc(self.msg1_paddr) >> 20)
|
||||
self.adev.regMP0_SMN_C2PMSG_35.write(compid)
|
||||
if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading sos component: {am.psp_fw_type__enumvalues[fw]}")
|
||||
|
||||
return self._wait_for_bootloader()
|
||||
self._prep_msg1(self.adev.fw.sos_fw[fw])
|
||||
self.adev.reg(f"{self.reg_pref}_36").write(self.adev.paddr2mc(self.msg1_paddr) >> 20)
|
||||
self.adev.reg(f"{self.reg_pref}_35").write(compid)
|
||||
|
||||
return self._wait_for_bootloader() if compid != am.PSP_BL__LOAD_SOSDRV else 0
|
||||
|
||||
def _tmr_init(self):
|
||||
# Load TOC and calculate TMR size
|
||||
@@ -414,26 +431,26 @@ class AM_PSP(AM_IP):
|
||||
|
||||
def _ring_create(self):
|
||||
# If the ring is already created, destroy it
|
||||
if self.adev.regMP0_SMN_C2PMSG_71.read() != 0:
|
||||
self.adev.regMP0_SMN_C2PMSG_64.write(am.GFX_CTRL_CMD_ID_DESTROY_RINGS)
|
||||
if self.adev.reg(f"{self.reg_pref}_71").read() != 0:
|
||||
self.adev.reg(f"{self.reg_pref}_64").write(am.GFX_CTRL_CMD_ID_DESTROY_RINGS)
|
||||
|
||||
# There might be handshake issue with hardware which needs delay
|
||||
time.sleep(0.02)
|
||||
|
||||
# Wait until the sOS is ready
|
||||
self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x80000000, value=0x80000000)
|
||||
self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x80000000, value=0x80000000)
|
||||
|
||||
self.adev.wreg_pair("regMP0_SMN_C2PMSG", "_69", "_70", self.adev.paddr2mc(self.ring_paddr))
|
||||
self.adev.regMP0_SMN_C2PMSG_71.write(self.ring_size)
|
||||
self.adev.regMP0_SMN_C2PMSG_64.write(am.PSP_RING_TYPE__KM << 16)
|
||||
self.adev.wreg_pair(self.reg_pref, "_69", "_70", self.adev.paddr2mc(self.ring_paddr))
|
||||
self.adev.reg(f"{self.reg_pref}_71").write(self.ring_size)
|
||||
self.adev.reg(f"{self.reg_pref}_64").write(am.PSP_RING_TYPE__KM << 16)
|
||||
|
||||
# There might be handshake issue with hardware which needs delay
|
||||
time.sleep(0.02)
|
||||
|
||||
self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x8000FFFF, value=0x80000000)
|
||||
self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x8000FFFF, value=0x80000000)
|
||||
|
||||
def _ring_submit(self):
|
||||
prev_wptr = self.adev.regMP0_SMN_C2PMSG_67.read()
|
||||
prev_wptr = self.adev.reg(f"{self.reg_pref}_67").read()
|
||||
ring_entry_addr = self.adev.paddr2cpu(self.ring_paddr) + prev_wptr * 4
|
||||
|
||||
ctypes.memset(ring_entry_addr, 0, ctypes.sizeof(am.struct_psp_gfx_rb_frame))
|
||||
@@ -443,7 +460,7 @@ class AM_PSP(AM_IP):
|
||||
write_loc.fence_value = prev_wptr
|
||||
|
||||
# Move the wptr
|
||||
self.adev.regMP0_SMN_C2PMSG_67.write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4)
|
||||
self.adev.reg(f"{self.reg_pref}_67").write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4)
|
||||
|
||||
while to_mv(self.adev.paddr2cpu(self.fence_paddr), 4).cast('I')[0] != prev_wptr: pass
|
||||
time.sleep(0.005)
|
||||
|
||||
Reference in New Issue
Block a user