mirror of
https://github.com/tinygrad/tinygrad.git
synced 2026-04-29 03:00:14 -04:00
good tests
This commit is contained in:
George Hotz
@@ -1,22 +1,17 @@
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#!/usr/bin/env python3
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"""Tests for SQTT emulator correctness against known hardware patterns.
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These tests define the CORRECT behavior based on hardware traces.
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When run against hardware (SQTT_HW=1), all tests should pass.
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When run against the emulator, tests FAIL where the emulator is wrong.
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NOTE: This file only tests NOP and VALU behavior. For WMMA/DP/trans tests,
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see test_sqtt_compare.py.
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Run emulator tests (expect failures - shows emulator bugs):
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PYTHONPATH="." python3 extra/assembly/amd/test/test_sqtt_correct.py
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Run against real hardware (all tests should pass):
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SQTT_HW=1 PYTHONPATH="." python3 extra/assembly/amd/test/test_sqtt_correct.py
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Run emulator tests: PYTHONPATH="." python3 extra/assembly/amd/test/test_sqtt_correct.py
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Run hardware tests: SQTT_HW=1 PYTHONPATH="." python3 extra/assembly/amd/test/test_sqtt_correct.py
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"""
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import os
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import unittest
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USE_HW = os.environ.get("SQTT_HW", "0") == "1"
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# Must set SQTT env vars before importing tinygrad device
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if USE_HW:
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os.environ["SQTT"] = "1"
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os.environ["PROFILE"] = "1"
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@@ -24,10 +19,9 @@ if USE_HW:
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os.environ["SQTT_TOKEN_EXCLUDE"] = "3784"
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from extra.assembly.amd.emu import SQTTState, decode_program, exec_wave, WaveState, LDSMem
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from extra.assembly.amd.sqtt import WAVESTART, WAVEEND, IMMEDIATE, VALUINST, ALUEXEC, PacketType
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from extra.assembly.amd.autogen.rdna3.ins import (v_mov_b32_e32, v_add_f32_e32, v_rcp_f32_e32, v_sqrt_f32_e32,
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v_exp_f32_e32, s_mov_b32, s_nop, s_endpgm, s_delay_alu, v_mul_f32_e32)
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from extra.assembly.amd.dsl import v, s
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from extra.assembly.amd.sqtt import WAVESTART, WAVEEND
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from extra.assembly.amd.autogen.rdna3.ins import v_mov_b32_e32, v_add_f32_e32, s_nop, s_endpgm
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from extra.assembly.amd.dsl import v
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def assemble(instructions: list) -> bytes:
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return b''.join(inst.to_bytes() for inst in instructions)
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@@ -36,7 +30,6 @@ def wrap_with_nops(instructions: list, nops=16) -> list:
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return instructions + [s_nop(0)]*nops + [s_endpgm()]
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def get_wave_packets(packets: list) -> list:
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"""Extract packets from first WAVESTART to WAVEEND on simd 0."""
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result, in_wave = [], False
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for p in packets:
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if isinstance(p, WAVESTART) and p.simd == 0:
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@@ -47,20 +40,15 @@ def get_wave_packets(packets: list) -> list:
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return result
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def get_timing_deltas(packets: list) -> list[tuple[str, int]]:
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"""Extract (packet_type, delta_from_previous) for non-timing packets."""
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skip_types = {"NOP", "TS_DELTA_SHORT", "TS_WAVE_STATE", "TS_DELTA_OR_MARK", "TS_DELTA_S5_W2", "TS_DELTA_S5_W3", "TS_DELTA_S8_W3", "REG"}
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filtered = [p for p in packets if type(p).__name__ not in skip_types]
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if not filtered: return []
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result = [(type(filtered[0]).__name__, 0)]
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for i in range(1, len(filtered)):
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result.append((type(filtered[i]).__name__, filtered[i]._time - filtered[i-1]._time))
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if result and result[-1][0] == 'WAVEEND':
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result[-1] = ('WAVEEND', 0) # normalize WAVEEND timing
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return result
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def run_emulator(instructions: list) -> list:
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"""Run instructions through emulator and return wave packets."""
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instructions = wrap_with_nops(instructions)
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code = assemble(instructions)
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program = decode_program(code)
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st = WaveState()
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@@ -70,255 +58,237 @@ def run_emulator(instructions: list) -> list:
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exec_wave(program, st, lds, 32, trace)
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return get_wave_packets(trace.packets)
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def get_all_waves(packets: list) -> list[list]:
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"""Extract all WAVESTART..WAVEEND ranges on simd 0."""
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waves, in_wave, current = [], False, []
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for p in packets:
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if isinstance(p, WAVESTART) and p.simd == 0:
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in_wave, current = True, [p]
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elif in_wave:
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current.append(p)
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if isinstance(p, WAVEEND):
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waves.append(current)
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in_wave, current = False, []
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return waves
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def run_hardware(instructions: list) -> list:
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"""Run on real hardware, return most common wave packet sequence."""
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from extra.assembly.amd.test.test_sqtt_hw import compile_asm_sqtt, run_prg_sqtt_batch
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from extra.assembly.amd.sqtt import decode
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from collections import Counter
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instructions = wrap_with_nops(instructions)
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prg = compile_asm_sqtt(instructions, alu_only=True)
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for _ in range(10):
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blobs = run_prg_sqtt_batch(prg, n_runs=200)
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traces = [get_wave_packets(decode(blob)) for blob in blobs]
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traces = [t for t in traces if t] # filter empty
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if traces:
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# Return most common pattern
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delta_sets = [tuple(get_timing_deltas(t)) for t in traces]
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most_common = Counter(delta_sets).most_common(1)[0][0]
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# Find a trace matching that pattern
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for t in traces:
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if tuple(get_timing_deltas(t)) == most_common:
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return t
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# Extract all waves from all blobs
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traces = []
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for blob in blobs:
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traces.extend(get_all_waves(decode(blob)))
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if not traces:
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continue
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# Find most common pattern
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delta_sets = [tuple(get_timing_deltas(t)) for t in traces]
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most_common = Counter(delta_sets).most_common(1)[0][0]
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for t in traces:
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if tuple(get_timing_deltas(t)) == most_common:
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return t
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return []
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def run_sqtt(instructions: list) -> list:
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"""Run on HW or emulator based on SQTT_HW env var, return wave packets."""
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instructions = wrap_with_nops(instructions)
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return run_hardware(instructions) if USE_HW else run_emulator(instructions)
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def run_test(instructions: list) -> list[tuple[str, int]]:
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"""Run and return timing deltas."""
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return get_timing_deltas(run_sqtt(instructions))
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def get_deltas(instructions: list) -> tuple[list[int], list[int]]:
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"""Run and return (issue deltas, exec deltas).
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Issue = IMMEDIATE + VALUINST, Exec = ALUEXEC.
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Deltas are between consecutive packets of same stream."""
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deltas = get_timing_deltas(run_sqtt(instructions))
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time = 0
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issue_times, exec_times = [], []
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for ptype, delta in deltas:
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time += delta
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if ptype in ('IMMEDIATE', 'VALUINST'):
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issue_times.append(time)
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elif ptype == 'ALUEXEC':
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exec_times.append(time)
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issue = [issue_times[i] - issue_times[i-1] for i in range(1, len(issue_times))]
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execd = [exec_times[i] - exec_times[i-1] for i in range(1, len(exec_times))]
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return issue, execd
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# Hardware ALUEXEC delta patterns:
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# chain: forwarding (6,5,5...) then stalls when exhausted (9,9,9...)
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# ind: no dependencies, exec follows issue by 1 cycle
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# snop: n+4 baseline, but +4 extra for 11 <= n <= 22
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CHAIN_ISSUE = {
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2: [1],
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3: [1, 1],
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4: [1, 1, 1],
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5: [1, 1, 1, 1],
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6: [1, 1, 1, 1, 1],
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7: [1, 1, 1, 1, 1, 1],
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8: [1, 1, 1, 1, 1, 1, 1],
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12: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
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14: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
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15: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3], # issue stalls start here
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16: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 5],
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18: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5],
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20: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 5, 5],
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}
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CHAIN_EXEC = {
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2: [6],
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3: [6, 5],
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4: [6, 5, 5],
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5: [6, 5, 5, 9],
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6: [6, 5, 5, 9, 9],
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7: [6, 5, 5, 5, 9, 9],
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8: [6, 5, 5, 5, 9, 9, 9],
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12: [6, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9],
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14: [6, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9],
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15: [6, 5, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9],
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16: [6, 5, 5, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9],
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18: [6, 5, 5, 5, 5, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9],
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20: [6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 9, 9, 9, 9, 9, 9, 9, 9],
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}
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IND_EXEC = {
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2: [1],
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3: [1, 1],
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4: [1, 1, 1],
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5: [1, 1, 1, 1],
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6: [1, 1, 1, 1, 1],
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7: [1, 1, 1, 1, 1, 1],
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8: [1, 1, 1, 1, 1, 1, 1],
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}
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SNOP_EXEC = {
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0: 4, 1: 5, 2: 6, 3: 7, 4: 8, 5: 9, 6: 10, 7: 11, 8: 12, 9: 13, 10: 14,
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11: 19, 12: 20, 13: 21, 14: 22, 15: 23, 16: 24, 17: 25, 18: 26, 19: 27, 20: 28, 21: 29, 22: 30, # +4 extra
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23: 27, 24: 28, 25: 29, 26: 30, 27: 31, 28: 32, 29: 33, 30: 34, 31: 35,
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32: 36, 33: 37, 34: 38, 35: 39, 36: 40, 37: 41, 38: 42, 39: 43,
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40: 44, 41: 45, 42: 46, 43: 47, 44: 48, 45: 49, 46: 50, 47: 51,
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48: 52, 49: 53, 50: 54, 51: 55, 52: 56, 53: 57, 54: 58, 55: 59,
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56: 60, 57: 61, 58: 62, 59: 63, 60: 64, 61: 65, 62: 66, 63: 67,
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}
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class TestVALUChains(unittest.TestCase):
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"""VALU dependency chains."""
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def _chain(self, n):
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instrs = [v_mov_b32_e32(v[0], 1.0)] + [v_add_f32_e32(v[i], v[i-1], v[i-1]) for i in range(1, n)]
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issue, execd = get_deltas(instrs)
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self.assertEqual(issue[:n-1], CHAIN_ISSUE[n])
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self.assertEqual(execd, CHAIN_EXEC[n])
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def test_chain_2(self): self._chain(2)
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def test_chain_3(self): self._chain(3)
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def test_chain_4(self): self._chain(4)
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def test_chain_5(self): self._chain(5)
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def test_chain_6(self): self._chain(6)
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def test_chain_7(self): self._chain(7)
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def test_chain_8(self): self._chain(8)
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def test_chain_12(self): self._chain(12)
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def test_chain_14(self): self._chain(14)
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def test_chain_15(self): self._chain(15) # issue stalls start here
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def test_chain_16(self): self._chain(16)
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def test_chain_18(self): self._chain(18)
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def test_chain_20(self): self._chain(20)
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class TestTranscendentals(unittest.TestCase):
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"""Tests for transcendental instruction (v_rcp, v_sqrt, v_exp, v_log) tracing.
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class TestVALUIndependent(unittest.TestCase):
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"""Independent VALU instructions."""
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def _ind(self, n):
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instrs = [v_mov_b32_e32(v[i], float(i)) for i in range(n)]
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issue, execd = get_deltas(instrs)
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self.assertEqual(issue[:n-1], [1]*(n-1))
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self.assertEqual(execd, IND_EXEC[n])
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Hardware behavior:
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- Transcendentals emit INST packets (not VALUINST) - they use a separate unit
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- Issue interval is 4 cycles (vs 1 cycle for regular VALU)
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- Latency is higher (~8 cycles vs ~6 for VALU)
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"""
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def test_trans_emits_inst_not_valuinst(self):
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"""Transcendentals should emit INST packets, not VALUINST.
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Hardware uses a separate transcendental unit that traces as INST.
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"""
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deltas = run_test([v_rcp_f32_e32(v[0], v[0])])
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types = [d[0] for d in deltas]
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self.assertIn('INST', types, "Transcendental should emit INST")
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self.assertNotIn('VALUINST', types, "Transcendental should not emit VALUINST")
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def test_trans_4_cycle_issue_interval(self):
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"""Independent transcendentals issue 4 cycles apart (not 1 like VALU).
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The transcendental unit is narrower and takes 4 cycles per instruction.
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"""
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deltas = run_test([
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v_rcp_f32_e32(v[0], v[0]),
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v_sqrt_f32_e32(v[1], v[1]),
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v_exp_f32_e32(v[2], v[2]),
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])
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# Find INST packets (transcendentals)
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inst_deltas = [d for d in deltas if d[0] == 'INST']
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self.assertEqual(len(inst_deltas), 3, "Should have 3 INST packets for 3 transcendentals")
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# Hardware: 4-cycle interval between transcendentals
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for d in inst_deltas[1:]:
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self.assertEqual(d[1], 4, "Trans should issue 4 cycles apart")
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def test_ind_2(self): self._ind(2)
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def test_ind_3(self): self._ind(3)
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def test_ind_4(self): self._ind(4)
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def test_ind_5(self): self._ind(5)
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def test_ind_6(self): self._ind(6)
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def test_ind_7(self): self._ind(7)
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def test_ind_8(self): self._ind(8)
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class TestSALUTracing(unittest.TestCase):
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"""Tests for SALU instruction tracing.
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class TestChainWithNop(unittest.TestCase):
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"""Dependency chain with s_nop between instructions."""
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def _test(self, nop_val, expected_issue, expected_exec):
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issue, execd = get_deltas([v_mov_b32_e32(v[0], 1.0), s_nop(nop_val), v_add_f32_e32(v[1], v[0], v[0])])
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self.assertEqual(issue[:2], expected_issue)
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self.assertEqual(execd, expected_exec)
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Hardware behavior:
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- SALU instructions (s_mov, s_add, etc.) emit INST packets
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- They execute on the scalar unit, separate from VALU
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"""
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def test_salu_emits_inst(self):
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"""SALU instructions should emit INST packets.
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Hardware traces scalar ALU operations with INST packets.
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"""
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deltas = run_test([s_mov_b32(s[4], 1)])
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types = [d[0] for d in deltas]
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self.assertIn('INST', types, "SALU should emit INST")
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def test_mixed_salu_valu_interleaving(self):
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"""Mixed SALU/VALU sequence should show interleaved INST and VALUINST.
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Hardware can issue SALU and VALU in parallel on different units.
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The trace shows both instruction types interleaved.
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"""
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deltas = run_test([
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s_mov_b32(s[4], 1),
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v_mov_b32_e32(v[0], 1.0),
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s_mov_b32(s[5], 2),
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v_mov_b32_e32(v[1], 2.0),
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])
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types = [d[0] for d in deltas]
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self.assertIn('INST', types, "Should have INST for SALU")
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self.assertIn('VALUINST', types, "Should have VALUINST for VALU")
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inst_count = types.count('INST')
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valuinst_count = types.count('VALUINST')
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self.assertEqual(inst_count, 2, "Should have 2 INST packets for 2 SALUs")
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self.assertEqual(valuinst_count, 2, "Should have 2 VALUINST packets for 2 VALUs")
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def test_nop0(self): self._test(0, [3, 1], [6])
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def test_nop1(self): self._test(1, [4, 1], [7])
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def test_nop2(self): self._test(2, [5, 1], [9])
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def test_nop3(self): self._test(3, [6, 1], [9])
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def test_nop4(self): self._test(4, [11, 1], [10])
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def test_nop5(self): self._test(5, [12, 1], [11])
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class TestLongDependencyChains(unittest.TestCase):
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"""Tests for long VALU dependency chains.
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class TestIndWithNop(unittest.TestCase):
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"""Independent instructions with s_nop between."""
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def _test(self, nop_val, expected_issue, expected_exec):
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issue, execd = get_deltas([v_mov_b32_e32(v[0], 1.0), s_nop(nop_val), v_mov_b32_e32(v[1], 2.0)])
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self.assertEqual(issue[:2], expected_issue)
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self.assertEqual(execd, expected_exec)
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Hardware behavior:
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- Chains exhaust forwarding network after ~4-5 instructions
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- Once exhausted, instructions must wait for register writeback
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- This causes ALUEXEC timing to change at the boundary
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"""
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def test_5_chain_aluexec_timing(self):
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"""5-instruction dependency chain has specific ALUEXEC timing pattern.
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Hardware: First 4 ALUEXECs use forwarding, 5th waits for writeback.
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This shows up as 9-cycle delta before the last ALUEXEC.
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"""
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deltas = run_test([
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v_mov_b32_e32(v[0], 1.0),
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v_add_f32_e32(v[1], v[0], v[0]),
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v_add_f32_e32(v[2], v[1], v[1]),
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v_add_f32_e32(v[3], v[2], v[2]),
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v_add_f32_e32(v[4], v[3], v[3]),
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])
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aluexec_deltas = [d for d in deltas if d[0] == 'ALUEXEC']
|
||||
self.assertEqual(len(aluexec_deltas), 5, "Should have 5 ALUEXECs")
|
||||
|
||||
# HW: last ALUEXEC has delta=9 (waiting for writeback after forwarding exhausted)
|
||||
self.assertEqual(aluexec_deltas[-1][1], 9, "Last ALUEXEC should wait 9 cycles")
|
||||
def test_nop0(self): self._test(0, [3, 1], [4])
|
||||
def test_nop1(self): self._test(1, [4, 1], [5])
|
||||
def test_nop3(self): self._test(3, [6, 1], [7])
|
||||
def test_nop4(self): self._test(4, [11, 1], [8])
|
||||
def test_nop5(self): self._test(5, [12, 1], [9])
|
||||
|
||||
|
||||
class TestDelayALU(unittest.TestCase):
|
||||
"""Tests for s_delay_alu instruction effects.
|
||||
class TestChain3NopMid(unittest.TestCase):
|
||||
"""3-instruction chain with s_nop in middle."""
|
||||
def _test(self, nop_val, expected_issue, expected_exec):
|
||||
issue, execd = get_deltas([
|
||||
v_mov_b32_e32(v[0], 1.0), v_add_f32_e32(v[1], v[0], v[0]),
|
||||
s_nop(nop_val), v_add_f32_e32(v[2], v[1], v[1])])
|
||||
self.assertEqual(issue[:3], expected_issue)
|
||||
self.assertEqual(execd, expected_exec)
|
||||
|
||||
Hardware behavior:
|
||||
- s_delay_alu tells hardware about upcoming dependencies
|
||||
- It affects when the next instruction can issue
|
||||
- The encoding specifies which previous instruction to wait for
|
||||
"""
|
||||
|
||||
def test_delay_alu_affects_valuinst_timing(self):
|
||||
"""s_delay_alu(1) delays next VALUINST to wait for VALU_DEP_1.
|
||||
|
||||
Should show ~5-cycle gap between VALUINSTs when delay_alu is used.
|
||||
"""
|
||||
deltas = run_test([
|
||||
v_mov_b32_e32(v[0], 1.0),
|
||||
s_delay_alu(1), # VALU_DEP_1
|
||||
v_add_f32_e32(v[1], v[0], v[0]),
|
||||
])
|
||||
|
||||
valuinst_deltas = [d for d in deltas if d[0] == 'VALUINST']
|
||||
self.assertEqual(len(valuinst_deltas), 2, "Should have 2 VALUINSTs")
|
||||
|
||||
# delay_alu should cause ~5 cycle gap
|
||||
self.assertGreaterEqual(valuinst_deltas[1][1], 4, "delay_alu should cause ~5 cycle gap")
|
||||
|
||||
def test_delay_alu_aluexec_position(self):
|
||||
"""ALUEXEC timing after delay_alu - second ALUEXEC preceded by IMMEDIATE.
|
||||
|
||||
Hardware pattern: ..., IMMEDIATE, ALUEXEC (second one)
|
||||
"""
|
||||
deltas = run_test([
|
||||
v_mov_b32_e32(v[0], 1.0),
|
||||
s_delay_alu(1),
|
||||
v_add_f32_e32(v[1], v[0], v[0]),
|
||||
])
|
||||
|
||||
# Find position of second ALUEXEC
|
||||
aluexec_indices = [i for i, d in enumerate(deltas) if d[0] == 'ALUEXEC']
|
||||
self.assertEqual(len(aluexec_indices), 2, "Should have 2 ALUEXECs")
|
||||
|
||||
# On HW, there's an IMMEDIATE before the second ALUEXEC
|
||||
second_aluexec_idx = aluexec_indices[1]
|
||||
prev_type = deltas[second_aluexec_idx - 1][0]
|
||||
self.assertEqual(prev_type, 'IMMEDIATE', "Should have IMMEDIATE before second ALUEXEC")
|
||||
def test_nop0(self): self._test(0, [1, 3, 1], [6, 5])
|
||||
def test_nop1(self): self._test(1, [1, 4, 1], [6, 5])
|
||||
def test_nop2(self): self._test(2, [1, 5, 1], [6, 5])
|
||||
def test_nop3(self): self._test(3, [1, 10, 1], [6, 5])
|
||||
|
||||
|
||||
class TestVALUAfterTrans(unittest.TestCase):
|
||||
"""Tests for VALU instructions following transcendentals.
|
||||
class TestInd3NopMid(unittest.TestCase):
|
||||
"""3 independent instructions with s_nop in middle."""
|
||||
def _test(self, nop_val, expected_issue, expected_exec):
|
||||
issue, execd = get_deltas([
|
||||
v_mov_b32_e32(v[0], 1.0), v_mov_b32_e32(v[1], 2.0),
|
||||
s_nop(nop_val), v_mov_b32_e32(v[2], 3.0)])
|
||||
self.assertEqual(issue[:3], expected_issue)
|
||||
self.assertEqual(execd, expected_exec)
|
||||
|
||||
Hardware behavior:
|
||||
- Transcendental completes later than regular VALU
|
||||
- Following VALUs can issue while trans is in flight
|
||||
- First packet should be INST (trans), followed by VALUINSTs
|
||||
"""
|
||||
|
||||
def test_valu_after_trans_packet_types(self):
|
||||
"""VALUs after trans: first is INST (trans), rest are VALUINST.
|
||||
|
||||
Trans has ~8 cycle latency, VALU has ~6 cycle.
|
||||
Trans issues first as INST, then VALUs as VALUINST.
|
||||
"""
|
||||
deltas = run_test([
|
||||
v_rcp_f32_e32(v[0], v[0]), # trans
|
||||
v_mov_b32_e32(v[1], 1.0), # valu
|
||||
v_mov_b32_e32(v[2], 2.0), # valu
|
||||
])
|
||||
types = [d[0] for d in deltas]
|
||||
|
||||
# First instruction (after WAVESTART) should be INST (trans)
|
||||
self.assertEqual(types[1], 'INST', "First instruction should be INST (trans)")
|
||||
self.assertEqual(types[2], 'VALUINST', "Second should be VALUINST")
|
||||
self.assertEqual(types[3], 'VALUINST', "Third should be VALUINST")
|
||||
def test_nop0(self): self._test(0, [1, 3, 1], [1, 4])
|
||||
def test_nop1(self): self._test(1, [1, 4, 1], [1, 5])
|
||||
def test_nop2(self): self._test(2, [1, 5, 1], [1, 6])
|
||||
def test_nop3(self): self._test(3, [1, 10, 1], [1, 7])
|
||||
|
||||
|
||||
class TestBasicPatterns(unittest.TestCase):
|
||||
"""Tests for basic patterns that work correctly."""
|
||||
class TestSNopDelay(unittest.TestCase):
|
||||
"""Single s_nop delay between two independent v_movs."""
|
||||
def _test(self, n):
|
||||
_, execd = get_deltas([v_mov_b32_e32(v[0], 1.0), s_nop(n), v_mov_b32_e32(v[1], 2.0)])
|
||||
self.assertEqual(execd, [SNOP_EXEC[n]])
|
||||
|
||||
def test_empty_program(self):
|
||||
"""Empty program (just epilogue) produces WAVESTART, IMMEDIATEs, WAVEEND."""
|
||||
deltas = run_test([])
|
||||
types = [d[0] for d in deltas]
|
||||
self.assertEqual(types[0], 'WAVESTART')
|
||||
self.assertEqual(types[-1], 'WAVEEND')
|
||||
self.assertTrue(all(t == 'IMMEDIATE' for t in types[1:-1]))
|
||||
|
||||
def test_single_valu(self):
|
||||
"""Single VALU should produce VALUINST + ALUEXEC."""
|
||||
deltas = run_test([v_mov_b32_e32(v[0], 1.0)])
|
||||
types = [d[0] for d in deltas]
|
||||
self.assertEqual(types.count('VALUINST'), 1)
|
||||
self.assertEqual(types.count('ALUEXEC'), 1)
|
||||
|
||||
def test_independent_valus(self):
|
||||
"""Independent VALUs issue 1 cycle apart."""
|
||||
deltas = run_test([v_mov_b32_e32(v[i], float(i)) for i in range(4)])
|
||||
valuinst_deltas = [d for d in deltas if d[0] == 'VALUINST']
|
||||
for vd in valuinst_deltas[1:]:
|
||||
self.assertEqual(vd[1], 1)
|
||||
|
||||
def test_snop_timing(self):
|
||||
"""s_nop(7) produces larger delay than s_nop(0)."""
|
||||
snop0 = run_test([s_nop(0)])
|
||||
snop7 = run_test([s_nop(7)])
|
||||
imm0 = next(d for d in snop0 if d[0] == 'IMMEDIATE')
|
||||
imm7 = next(d for d in snop7 if d[0] == 'IMMEDIATE')
|
||||
self.assertGreater(imm7[1], imm0[1])
|
||||
def test_snop_0(self): self._test(0)
|
||||
def test_snop_1(self): self._test(1)
|
||||
def test_snop_2(self): self._test(2)
|
||||
def test_snop_3(self): self._test(3)
|
||||
def test_snop_4(self): self._test(4)
|
||||
def test_snop_5(self): self._test(5)
|
||||
def test_snop_6(self): self._test(6)
|
||||
def test_snop_7(self): self._test(7)
|
||||
def test_snop_10(self): self._test(10)
|
||||
def test_snop_11(self): self._test(11) # +4 extra starts here
|
||||
def test_snop_15(self): self._test(15)
|
||||
def test_snop_22(self): self._test(22) # +4 extra ends here
|
||||
def test_snop_23(self): self._test(23)
|
||||
def test_snop_31(self): self._test(31)
|
||||
def test_snop_32(self): self._test(32)
|
||||
def test_snop_63(self): self._test(63)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
||||
Reference in New Issue
Block a user