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autogen: download linux sources (#14714)
This commit is contained in:
Christopher Milan
committed by
GitHub
GitHub
parent
084d0d0103
commit
d4bc5ab609
@@ -1,4 +1,4 @@
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import glob, importlib, pathlib, subprocess, tarfile
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import glob, importlib, os, pathlib, shutil, subprocess, tarfile
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from tinygrad.helpers import fetch, flatten, system, getenv
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root = (here:=pathlib.Path(__file__).parent).parents[2]
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@@ -6,6 +6,8 @@ nv_src = {"nv_570": "https://github.com/NVIDIA/open-gpu-kernel-modules/archive/8
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"nv_580": "https://github.com/NVIDIA/open-gpu-kernel-modules/archive/2af9f1f0f7de4988432d4ae875b5858ffdb09cc2.tar.gz"}
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ffmpeg_src = "https://ffmpeg.org/releases/ffmpeg-8.0.1.tar.gz"
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rocr_src = "https://github.com/ROCm/rocm-systems/archive/refs/tags/rocm-7.1.1.tar.gz"
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linux_src = "https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.19.tar.xz"
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liburing_src = "https://raw.githubusercontent.com/axboe/liburing/refs/tags/liburing-2.14/src/include/liburing.h"
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macossdk = "/var/db/xcode_select_link/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk"
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llvm_lib = (r"'C:\\Program Files\\LLVM\\bin\\LLVM-C.dll' if WIN else '/opt/homebrew/opt/llvm@20/lib/libLLVM.dylib' if OSX else " +
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@@ -18,17 +20,23 @@ nv_lib_path = "[f'/{pre}/cuda/targets/{sysconfig.get_config_vars().get(\"MULTIAR
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def load(name, dll, files, **kwargs):
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if not (f:=(root/(path:=kwargs.pop("path", __name__)).replace('.','/')/f"{name}.py")).exists() or getenv('REGEN'):
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files, kwargs['args'] = files() if callable(files) else files, args() if callable(args:=kwargs.get('args', [])) else args
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if (tarball:=kwargs.pop('tarball', None)):
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# dangerous for arbitrary urls!
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with tarfile.open(fetch(tarball, gunzip=tarball.endswith("gz"))) as tf:
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tf.extractall("/tmp")
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base = f"/tmp/{tf.getnames()[0]}"
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files, kwargs['args'] = [str(f).format(base) for f in files], [a.format(base) for a in kwargs.get('args', [])]
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kwargs['anon_names'] = {k.format(base):v for k,v in kwargs.get('anon_names', {}).items()}
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if (preprocess:=kwargs.pop('preprocess', None)): preprocess(base)
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if (srcs:=kwargs.pop('srcs', None)):
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shutil.rmtree(srcpath:=f"/tmp/tinyautogen-src-{name}/", ignore_errors=True)
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os.makedirs(srcpath)
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for src in (srcs if isinstance(srcs, list) else [srcs]):
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if 'tar' in src:
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# dangerous for arbitrary urls!
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with tarfile.open(fetch(src, gunzip=src.endswith("gz"))) as tf:
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tf.extractall(srcpath)
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if not isinstance(srcs, list): srcpath += tf.getnames()[0] # if we just have a single tarball, make this the root
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else: fetch(src, name=srcpath + src.split('/')[-1])
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files, kwargs['args'] = [str(f).format(srcpath) for f in files], [a.format(srcpath) for a in kwargs.get('args', [])]
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kwargs['anon_names'] = {k.format(srcpath):v for k,v in kwargs.get('anon_names', {}).items()}
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if (preprocess:=kwargs.pop('preprocess', None)): preprocess(srcpath)
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files = flatten(sorted(glob.glob(p, recursive=True)) if isinstance(p, str) and '*' in p else [p] for p in files)
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kwargs['epilog'] = (epi(base) if tarball else epi()) if callable(epi:=kwargs.get('epilog', [])) else epi
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kwargs['epilog'] = (epi(srcpath) if srcs else epi()) if callable(epi:=kwargs.get('epilog', [])) else epi
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f.write_text(importlib.import_module("tinygrad.runtime.support.autogen").gen(name, dll, files, **kwargs))
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if srcs: shutil.rmtree(srcpath)
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return importlib.import_module(f"{path}.{name.replace('/', '.')}")
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def __getattr__(nm):
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@@ -36,7 +44,7 @@ def __getattr__(nm):
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case "libc": return load("libc", "'c'", lambda: (
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[i for i in system("dpkg -L libc6-dev").split() if 'sys/mman.h' in i or 'sys/syscall.h' in i] +
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["/usr/include/string.h", "/usr/include/elf.h", "/usr/include/unistd.h", "/usr/include/asm-generic/mman-common.h"]), errno=True)
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case "avcodec": return load("avcodec", None, ["{}/libavcodec/hevc/hevc.h", "{}/libavcodec/cbs_h265.h"], tarball=ffmpeg_src)
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case "avcodec": return load("avcodec", None, ["{}/libavcodec/hevc/hevc.h", "{}/libavcodec/cbs_h265.h"], srcs=ffmpeg_src)
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case "opencl": return load("opencl", "'OpenCL'", ["/usr/include/CL/cl.h"])
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case "cuda": return load("cuda", "'cuda'", ["/usr/include/cuda.h"], args=["-D__CUDA_API_VERSION_INTERNAL"], parse_macros=False)
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case "nvrtc": return load("nvrtc", "'nvrtc'", ["/usr/include/nvrtc.h"], paths=nv_lib_path, prolog=["import sysconfig"])
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@@ -57,7 +65,7 @@ def __getattr__(nm):
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], args=[
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"-include", "{}/src/common/sdk/nvidia/inc/nvtypes.h", "-I{}/src/common/inc", "-I{}/kernel-open/nvidia-uvm", "-I{}/kernel-open/common/inc",
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"-I{}/src/common/sdk/nvidia/inc", "-I{}/src/nvidia/arch/nvalloc/unix/include", "-I{}/src/common/sdk/nvidia/inc/ctrl"
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], rules=[(r'MW\(([^:]+):(.+)\)',r'(\1, \2)'), (r'(\d+):(\d+)', r'(\1, \2)')], tarball=nv_src[nm], anon_names={"{}/kernel-open/common/inc/nvstatus.h:37":"nv_status_codes"})
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], rules=[(r'MW\(([^:]+):(.+)\)',r'(\1, \2)'), (r'(\d+):(\d+)', r'(\1, \2)')], srcs=nv_src[nm], anon_names={"{}/kernel-open/common/inc/nvstatus.h:37":"nv_status_codes"})
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case "nv": return load("nv", None, [
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*[f"{{}}/src/nvidia/inc/kernel/gpu/{s}.h" for s in ["fsp/kern_fsp_cot_payload", "gsp/gsp_init_args"]],
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*[f"{{}}/src/nvidia/arch/nvalloc/common/inc/{s}.h" for s in ["gsp/gspifpub", "gsp/gsp_fw_wpr_meta", "gsp/gsp_fw_sr_meta", "rmRiscvUcode",
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@@ -71,19 +79,23 @@ def __getattr__(nm):
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"-I{}/src/common/inc", "-I{}/src/nvidia/inc", "-I{}/src/nvidia/interface/", "-I{}/src/nvidia/inc/kernel", "-I{}/src/nvidia/inc/libraries",
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"-I{}/src/nvidia/arch/nvalloc/common/inc", "-I{}/kernel-open/nvidia-uvm", "-I{}/kernel-open/common/inc", "-I{}/src/common/sdk/nvidia/inc",
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"-I{}/src/nvidia/arch/nvalloc/unix/include", "-I{}/src/common/sdk/nvidia/inc/ctrl"
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], tarball=nv_src["nv_570"], anon_names={
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], srcs=nv_src["nv_570"], anon_names={
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"{}/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h:8": "rpc_fns",
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"{}/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h:244": "rpc_events"
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})
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# this defines all syscall numbers. should probably unify linux autogen?
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case "io_uring": return load("io_uring", None, ["/usr/include/liburing.h", "/usr/include/linux/io_uring.h", "/usr/include/asm-generic/unistd.h"],
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rules=[('__NR', 'NR')])
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case "io_uring":
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return load("io_uring", None, ["{}/liburing.h", "{}/linux-6.19/gen/include/linux/io_uring.h", "{}/linux-6.19/gen/include/asm-generic/unistd.h"],
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args=["-I{}/linux-6.19/gen"], srcs=[linux_src, liburing_src], rules=[('__NR', 'NR')],
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preprocess=lambda path: system("make headers_install INSTALL_HDR_PATH=./gen", cwd=path + 'linux-6.19'))
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case "ib": return load("ib", "'ibverbs'", ["/usr/include/infiniband/verbs.h", "/usr/include/infiniband/verbs_api.h",
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"/usr/include/infiniband/ib_user_ioctl_verbs.h","/usr/include/rdma/ib_user_verbs.h"], errno=True)
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case "llvm": return load("llvm", llvm_lib, lambda: [system("llvm-config-20 --includedir")+"/llvm-c/**/*.h"],
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args=lambda: system("llvm-config-20 --cflags").split(), recsym=True, prolog=["from tinygrad.helpers import WIN, OSX"])
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case "pci": return load("pci", None, ["/usr/include/linux/pci_regs.h"])
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case "vfio": return load("vfio", None, ["/usr/include/linux/vfio.h"])
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case "pci": return load("pci", None, ["{}/gen/include/linux/pci_regs.h"], args=["-I{}/gen/include"], srcs=linux_src,
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preprocess=lambda path: system("make headers_install INSTALL_HDR_PATH=./gen", cwd=path))
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case "vfio": return load("vfio", None, ["{}/gen/include/linux/vfio.h"], args=["-I{}/gen/include"], srcs=linux_src,
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preprocess=lambda path: system("make headers_install INSTALL_HDR_PATH=./gen", cwd=path))
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# could add rule: WGPU_COMMA -> ','
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case "webgpu": return load("webgpu", webgpu_lib, [root/"extra/webgpu/webgpu.h"],
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prolog=["from tinygrad.helpers import WIN, OSX", "import sysconfig, os"])
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@@ -100,7 +112,7 @@ def __getattr__(nm):
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*[f"{{}}/projects/rocr-runtime/runtime/hsa-runtime/inc/{s}.h" for s in ["hsa", "hsa_ext_amd", "amd_hsa_signal", "amd_hsa_queue",
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"amd_hsa_kernel_code", "hsa_ext_finalize",
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"hsa_ext_image", "hsa_ven_amd_aqlprofile"]]],
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tarball=rocr_src, args=["-DLITTLEENDIAN_CPU"], prolog=["import os"])
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srcs=rocr_src, args=["-DLITTLEENDIAN_CPU"], prolog=["import os"])
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case "amdgpu_kd": return load("amdgpu_kd", None, lambda: [f"{system('llvm-config-20 --includedir')}/llvm/Support/AMDHSAKernelDescriptor.h"],
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args=lambda: system("llvm-config-20 --cflags").split() + ["-x", "c++"], recsym=True, parse_macros=False)
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case "amd_gpu": return load("amd_gpu", None, [root/f"extra/hip_gpu_driver/{s}.h" for s in ["sdma_registers", "nvd", "gc_11_0_0_offset",
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@@ -114,7 +126,7 @@ def __getattr__(nm):
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case "rocprof":
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return load("rocprof", "['rocprof-trace-decoder', p:='/usr/local/lib/rocprof-trace-decoder.so', p.replace('so','dylib')]",
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[f"{{}}/include/{s}.h" for s in ["rocprof_trace_decoder", "trace_decoder_instrument", "trace_decoder_types"]],
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tarball="https://github.com/ROCm/rocprof-trace-decoder/archive/dd0485100971522cc4cd8ae136bdda431061a04d.tar.gz")
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srcs="https://github.com/ROCm/rocprof-trace-decoder/archive/dd0485100971522cc4cd8ae136bdda431061a04d.tar.gz")
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case "mesa": return load("mesa", "([] if CPU_CC.value == 'LVP' or bool(CPU_LVP) else ['tinymesa']) + ['tinymesa_cpu']", [
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*[f"{{}}/src/compiler/nir/{s}.h" for s in ["nir", "nir_builder", "nir_shader_compiler_options", "nir_serialize"]], "{}/gen/nir_intrinsics.h",
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*[f"{{}}/src/nouveau/{s}.h" for s in ["headers/nv_device_info", "compiler/nak"]],
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@@ -133,7 +145,7 @@ def __getattr__(nm):
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f"src/freedreno/registers/adreno/{s}.xml c-defines > gen/{s}.xml.h" for s in ["a6xx", "adreno_pm4", "a6xx_enums", "a6xx_descriptors"]],
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*[f"python3 src/compiler/{s}_h.py > gen/{s.split('/')[-1]}.h" for s in ["nir/nir_opcodes", "nir/nir_builder_opcodes"]],
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*[f"python3 src/compiler/nir/nir_{s}_h.py --outdir gen" for s in ["intrinsics", "intrinsics_indices"]]]), cwd=path, shell=True, check=True),
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tarball="https://gitlab.freedesktop.org/mesa/mesa/-/archive/mesa-25.2.7/mesa-25.2.7.tar.gz",
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srcs="https://gitlab.freedesktop.org/mesa/mesa/-/archive/mesa-25.2.7/mesa-25.2.7.tar.gz",
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prolog=["from tinygrad.helpers import CPU_CC, CPU_LVP", "import gzip, base64"],
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epilog=lambda path: [system(f"{root}/extra/mesa/lvp_nir_options.sh {path}")])
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case "libclang":
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@@ -9,19 +9,19 @@ def __getattr__(nm):
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case "am": return load("am/am", [], [root/f"extra/amdpci/headers/{s}.h" for s in ["v11_structs", "v12_structs", "amdgpu_vm",
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"discovery", "amdgpu_ucode", "psp_gfx_if", "amdgpu_psp", "amdgpu_irq", "amdgpu_doorbell"]] + [f"{AMD}/amdkfd/soc15_int.h"] + \
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[f"{AMDINC}/ivsrcid/{s}.h" for s in [f"gfx/irqsrcs_gfx_{x}_0" for x in ('9','11_0','12_0')] + [f"sdma0/irqsrcs_sdma0_{x}_0" for x in (4,5)]] + \
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[f"{AMDINC}/{s}.h" for s in ["v9_structs", "soc15_ih_clientid"]], args=inc, tarball=am_src, rules=kern_rules)
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case "pm4_soc15": return load("am/pm4_soc15", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], tarball=am_src)
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case "pm4_nv": return load("am/pm4_nv", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], tarball=am_src)
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[f"{AMDINC}/{s}.h" for s in ["v9_structs", "soc15_ih_clientid"]], args=inc, srcs=am_src, rules=kern_rules)
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case "pm4_soc15": return load("am/pm4_soc15", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/soc15d.h"], srcs=am_src)
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case "pm4_nv": return load("am/pm4_nv", [], [f"{AMD}/amdkfd/kfd_pm4_headers_ai.h", f"{AMD}/amdgpu/nvd.h"], srcs=am_src)
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case "sdma_4_0_0": return load("am/sdma_4_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/vega10_sdma_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src)
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "sdma_5_0_0": return load("am/sdma_5_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/navi10_sdma_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src)
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "sdma_6_0_0": return load("am/sdma_6_0_0", [], [root/"extra/hip_gpu_driver/sdma_registers.h", f"{AMD}/amdgpu/sdma_v6_0_0_pkt_open.h"],
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args=["-I/opt/rocm/include", "-x", "c++"], tarball=am_src)
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args=["-I/opt/rocm/include", "-x", "c++"], srcs=am_src)
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case "smu_v13_0_0": return load("am/smu_v13_0_0",[],[f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_0_ppsmc","smu13_driver_if_v13_0_0"]]
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+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, tarball=am_src)
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+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case "smu_v13_0_6": return load("am/smu_v13_0_6",[],[f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v13_0_6_ppsmc","smu_v13_0_6_pmfw", \
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"smu13_driver_if_v13_0_6"]] +[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, tarball=am_src)
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"smu13_driver_if_v13_0_6"]] +[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case "smu_v14_0_2": return load("am/smu_v14_0_2", [], [f"{AMD}/pm/swsmu/inc/pmfw_if/{s}.h" for s in ["smu_v14_0_0_pmfw", "smu_v14_0_2_ppsmc",
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"smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, tarball=am_src)
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"smu14_driver_if_v14_0"]]+[root/"extra/amdpci/headers/amdgpu_smu.h"], args=inc, srcs=am_src)
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case _: raise AttributeError(f"no such autogen: {nm}")
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@@ -21,7 +21,8 @@ class struct_io_uring_sq(c.Struct):
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ring_ptr: Annotated[ctypes.c_void_p, 80]
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ring_mask: Annotated[Annotated[int, ctypes.c_uint32], 88]
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ring_entries: Annotated[Annotated[int, ctypes.c_uint32], 92]
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pad: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[2]], 96]
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sqes_sz: Annotated[Annotated[int, ctypes.c_uint32], 96]
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pad: Annotated[Annotated[int, ctypes.c_uint32], 100]
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@c.record
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class struct_io_uring_sqe(c.Struct):
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SIZE = 64
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@@ -108,48 +109,48 @@ class struct_io_uring(c.Struct):
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pad: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[3]], 209]
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pad2: Annotated[Annotated[int, ctypes.c_uint32], 212]
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@c.record
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class struct_statx(c.Struct):
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SIZE = 256
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stx_mask: Annotated[Annotated[int, ctypes.c_uint32], 0]
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stx_blksize: Annotated[Annotated[int, ctypes.c_uint32], 4]
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stx_attributes: Annotated[Annotated[int, ctypes.c_uint64], 8]
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stx_nlink: Annotated[Annotated[int, ctypes.c_uint32], 16]
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stx_uid: Annotated[Annotated[int, ctypes.c_uint32], 20]
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stx_gid: Annotated[Annotated[int, ctypes.c_uint32], 24]
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stx_mode: Annotated[Annotated[int, ctypes.c_uint16], 28]
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__spare0: Annotated[c.Array[Annotated[int, ctypes.c_uint16], Literal[1]], 30]
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stx_ino: Annotated[Annotated[int, ctypes.c_uint64], 32]
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stx_size: Annotated[Annotated[int, ctypes.c_uint64], 40]
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stx_blocks: Annotated[Annotated[int, ctypes.c_uint64], 48]
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stx_attributes_mask: Annotated[Annotated[int, ctypes.c_uint64], 56]
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stx_atime: Annotated[struct_statx_timestamp, 64]
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stx_btime: Annotated[struct_statx_timestamp, 80]
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stx_ctime: Annotated[struct_statx_timestamp, 96]
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stx_mtime: Annotated[struct_statx_timestamp, 112]
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stx_rdev_major: Annotated[Annotated[int, ctypes.c_uint32], 128]
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stx_rdev_minor: Annotated[Annotated[int, ctypes.c_uint32], 132]
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stx_dev_major: Annotated[Annotated[int, ctypes.c_uint32], 136]
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stx_dev_minor: Annotated[Annotated[int, ctypes.c_uint32], 140]
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stx_mnt_id: Annotated[Annotated[int, ctypes.c_uint64], 144]
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stx_dio_mem_align: Annotated[Annotated[int, ctypes.c_uint32], 152]
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stx_dio_offset_align: Annotated[Annotated[int, ctypes.c_uint32], 156]
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__spare3: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[12]], 160]
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class struct_io_uring_zcrx_rq(c.Struct):
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SIZE = 40
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khead: Annotated[c.POINTER[Annotated[int, ctypes.c_uint32]], 0]
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ktail: Annotated[c.POINTER[Annotated[int, ctypes.c_uint32]], 8]
|
||||
rq_tail: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
||||
ring_entries: Annotated[Annotated[int, ctypes.c_uint32], 20]
|
||||
rqes: Annotated[c.POINTER[struct_io_uring_zcrx_rqe], 24]
|
||||
ring_ptr: Annotated[ctypes.c_void_p, 32]
|
||||
@c.record
|
||||
class struct_statx_timestamp(c.Struct):
|
||||
class struct_io_uring_zcrx_rqe(c.Struct):
|
||||
SIZE = 16
|
||||
tv_sec: Annotated[Annotated[int, ctypes.c_int64], 0]
|
||||
tv_nsec: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
__reserved: Annotated[Annotated[int, ctypes.c_int32], 12]
|
||||
__s64: TypeAlias = Annotated[int, ctypes.c_int64]
|
||||
off: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
len: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
__pad: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
@c.record
|
||||
class struct_io_uring_cqe_iter(c.Struct):
|
||||
SIZE = 24
|
||||
cqes: Annotated[c.POINTER[struct_io_uring_cqe], 0]
|
||||
mask: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
shift: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
head: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
||||
tail: Annotated[Annotated[int, ctypes.c_uint32], 20]
|
||||
class struct_epoll_event(ctypes.Structure): pass
|
||||
class _anonenum0(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IOSQE_FIXED_FILE_BIT = _anonenum0.define('IOSQE_FIXED_FILE_BIT', 0)
|
||||
IOSQE_IO_DRAIN_BIT = _anonenum0.define('IOSQE_IO_DRAIN_BIT', 1)
|
||||
IOSQE_IO_LINK_BIT = _anonenum0.define('IOSQE_IO_LINK_BIT', 2)
|
||||
IOSQE_IO_HARDLINK_BIT = _anonenum0.define('IOSQE_IO_HARDLINK_BIT', 3)
|
||||
IOSQE_ASYNC_BIT = _anonenum0.define('IOSQE_ASYNC_BIT', 4)
|
||||
IOSQE_BUFFER_SELECT_BIT = _anonenum0.define('IOSQE_BUFFER_SELECT_BIT', 5)
|
||||
IOSQE_CQE_SKIP_SUCCESS_BIT = _anonenum0.define('IOSQE_CQE_SKIP_SUCCESS_BIT', 6)
|
||||
class struct_statx(ctypes.Structure): pass
|
||||
class struct_futex_waitv(ctypes.Structure): pass
|
||||
@c.record
|
||||
class struct_io_uring_attr_pi(c.Struct):
|
||||
SIZE = 32
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint16], 0]
|
||||
app_tag: Annotated[Annotated[int, ctypes.c_uint16], 2]
|
||||
len: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
addr: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
seed: Annotated[Annotated[int, ctypes.c_uint64], 16]
|
||||
rsvd: Annotated[Annotated[int, ctypes.c_uint64], 24]
|
||||
class enum_io_uring_sqe_flags_bit(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IOSQE_FIXED_FILE_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_FIXED_FILE_BIT', 0)
|
||||
IOSQE_IO_DRAIN_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_IO_DRAIN_BIT', 1)
|
||||
IOSQE_IO_LINK_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_IO_LINK_BIT', 2)
|
||||
IOSQE_IO_HARDLINK_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_IO_HARDLINK_BIT', 3)
|
||||
IOSQE_ASYNC_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_ASYNC_BIT', 4)
|
||||
IOSQE_BUFFER_SELECT_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_BUFFER_SELECT_BIT', 5)
|
||||
IOSQE_CQE_SKIP_SUCCESS_BIT = enum_io_uring_sqe_flags_bit.define('IOSQE_CQE_SKIP_SUCCESS_BIT', 6)
|
||||
|
||||
class enum_io_uring_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_OP_NOP = enum_io_uring_op.define('IORING_OP_NOP', 0)
|
||||
@@ -207,14 +208,21 @@ IORING_OP_FUTEX_WAIT = enum_io_uring_op.define('IORING_OP_FUTEX_WAIT', 51)
|
||||
IORING_OP_FUTEX_WAKE = enum_io_uring_op.define('IORING_OP_FUTEX_WAKE', 52)
|
||||
IORING_OP_FUTEX_WAITV = enum_io_uring_op.define('IORING_OP_FUTEX_WAITV', 53)
|
||||
IORING_OP_FIXED_FD_INSTALL = enum_io_uring_op.define('IORING_OP_FIXED_FD_INSTALL', 54)
|
||||
IORING_OP_LAST = enum_io_uring_op.define('IORING_OP_LAST', 55)
|
||||
IORING_OP_FTRUNCATE = enum_io_uring_op.define('IORING_OP_FTRUNCATE', 55)
|
||||
IORING_OP_BIND = enum_io_uring_op.define('IORING_OP_BIND', 56)
|
||||
IORING_OP_LISTEN = enum_io_uring_op.define('IORING_OP_LISTEN', 57)
|
||||
IORING_OP_RECV_ZC = enum_io_uring_op.define('IORING_OP_RECV_ZC', 58)
|
||||
IORING_OP_EPOLL_WAIT = enum_io_uring_op.define('IORING_OP_EPOLL_WAIT', 59)
|
||||
IORING_OP_READV_FIXED = enum_io_uring_op.define('IORING_OP_READV_FIXED', 60)
|
||||
IORING_OP_WRITEV_FIXED = enum_io_uring_op.define('IORING_OP_WRITEV_FIXED', 61)
|
||||
IORING_OP_PIPE = enum_io_uring_op.define('IORING_OP_PIPE', 62)
|
||||
IORING_OP_NOP128 = enum_io_uring_op.define('IORING_OP_NOP128', 63)
|
||||
IORING_OP_URING_CMD128 = enum_io_uring_op.define('IORING_OP_URING_CMD128', 64)
|
||||
IORING_OP_LAST = enum_io_uring_op.define('IORING_OP_LAST', 65)
|
||||
|
||||
class _anonenum1(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_MSG_DATA = _anonenum1.define('IORING_MSG_DATA', 0)
|
||||
IORING_MSG_SEND_FD = _anonenum1.define('IORING_MSG_SEND_FD', 1)
|
||||
|
||||
class _anonenum2(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_CQE_BUFFER_SHIFT = _anonenum2.define('IORING_CQE_BUFFER_SHIFT', 16)
|
||||
class enum_io_uring_msg_ring_flags(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_MSG_DATA = enum_io_uring_msg_ring_flags.define('IORING_MSG_DATA', 0)
|
||||
IORING_MSG_SEND_FD = enum_io_uring_msg_ring_flags.define('IORING_MSG_SEND_FD', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_sqring_offsets(c.Struct):
|
||||
@@ -253,40 +261,50 @@ class struct_io_uring_params(c.Struct):
|
||||
resv: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], 28]
|
||||
sq_off: Annotated[struct_io_sqring_offsets, 40]
|
||||
cq_off: Annotated[struct_io_cqring_offsets, 80]
|
||||
class _anonenum3(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_REGISTER_BUFFERS = _anonenum3.define('IORING_REGISTER_BUFFERS', 0)
|
||||
IORING_UNREGISTER_BUFFERS = _anonenum3.define('IORING_UNREGISTER_BUFFERS', 1)
|
||||
IORING_REGISTER_FILES = _anonenum3.define('IORING_REGISTER_FILES', 2)
|
||||
IORING_UNREGISTER_FILES = _anonenum3.define('IORING_UNREGISTER_FILES', 3)
|
||||
IORING_REGISTER_EVENTFD = _anonenum3.define('IORING_REGISTER_EVENTFD', 4)
|
||||
IORING_UNREGISTER_EVENTFD = _anonenum3.define('IORING_UNREGISTER_EVENTFD', 5)
|
||||
IORING_REGISTER_FILES_UPDATE = _anonenum3.define('IORING_REGISTER_FILES_UPDATE', 6)
|
||||
IORING_REGISTER_EVENTFD_ASYNC = _anonenum3.define('IORING_REGISTER_EVENTFD_ASYNC', 7)
|
||||
IORING_REGISTER_PROBE = _anonenum3.define('IORING_REGISTER_PROBE', 8)
|
||||
IORING_REGISTER_PERSONALITY = _anonenum3.define('IORING_REGISTER_PERSONALITY', 9)
|
||||
IORING_UNREGISTER_PERSONALITY = _anonenum3.define('IORING_UNREGISTER_PERSONALITY', 10)
|
||||
IORING_REGISTER_RESTRICTIONS = _anonenum3.define('IORING_REGISTER_RESTRICTIONS', 11)
|
||||
IORING_REGISTER_ENABLE_RINGS = _anonenum3.define('IORING_REGISTER_ENABLE_RINGS', 12)
|
||||
IORING_REGISTER_FILES2 = _anonenum3.define('IORING_REGISTER_FILES2', 13)
|
||||
IORING_REGISTER_FILES_UPDATE2 = _anonenum3.define('IORING_REGISTER_FILES_UPDATE2', 14)
|
||||
IORING_REGISTER_BUFFERS2 = _anonenum3.define('IORING_REGISTER_BUFFERS2', 15)
|
||||
IORING_REGISTER_BUFFERS_UPDATE = _anonenum3.define('IORING_REGISTER_BUFFERS_UPDATE', 16)
|
||||
IORING_REGISTER_IOWQ_AFF = _anonenum3.define('IORING_REGISTER_IOWQ_AFF', 17)
|
||||
IORING_UNREGISTER_IOWQ_AFF = _anonenum3.define('IORING_UNREGISTER_IOWQ_AFF', 18)
|
||||
IORING_REGISTER_IOWQ_MAX_WORKERS = _anonenum3.define('IORING_REGISTER_IOWQ_MAX_WORKERS', 19)
|
||||
IORING_REGISTER_RING_FDS = _anonenum3.define('IORING_REGISTER_RING_FDS', 20)
|
||||
IORING_UNREGISTER_RING_FDS = _anonenum3.define('IORING_UNREGISTER_RING_FDS', 21)
|
||||
IORING_REGISTER_PBUF_RING = _anonenum3.define('IORING_REGISTER_PBUF_RING', 22)
|
||||
IORING_UNREGISTER_PBUF_RING = _anonenum3.define('IORING_UNREGISTER_PBUF_RING', 23)
|
||||
IORING_REGISTER_SYNC_CANCEL = _anonenum3.define('IORING_REGISTER_SYNC_CANCEL', 24)
|
||||
IORING_REGISTER_FILE_ALLOC_RANGE = _anonenum3.define('IORING_REGISTER_FILE_ALLOC_RANGE', 25)
|
||||
IORING_REGISTER_PBUF_STATUS = _anonenum3.define('IORING_REGISTER_PBUF_STATUS', 26)
|
||||
IORING_REGISTER_LAST = _anonenum3.define('IORING_REGISTER_LAST', 27)
|
||||
IORING_REGISTER_USE_REGISTERED_RING = _anonenum3.define('IORING_REGISTER_USE_REGISTERED_RING', 2147483648)
|
||||
class enum_io_uring_register_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_REGISTER_BUFFERS = enum_io_uring_register_op.define('IORING_REGISTER_BUFFERS', 0)
|
||||
IORING_UNREGISTER_BUFFERS = enum_io_uring_register_op.define('IORING_UNREGISTER_BUFFERS', 1)
|
||||
IORING_REGISTER_FILES = enum_io_uring_register_op.define('IORING_REGISTER_FILES', 2)
|
||||
IORING_UNREGISTER_FILES = enum_io_uring_register_op.define('IORING_UNREGISTER_FILES', 3)
|
||||
IORING_REGISTER_EVENTFD = enum_io_uring_register_op.define('IORING_REGISTER_EVENTFD', 4)
|
||||
IORING_UNREGISTER_EVENTFD = enum_io_uring_register_op.define('IORING_UNREGISTER_EVENTFD', 5)
|
||||
IORING_REGISTER_FILES_UPDATE = enum_io_uring_register_op.define('IORING_REGISTER_FILES_UPDATE', 6)
|
||||
IORING_REGISTER_EVENTFD_ASYNC = enum_io_uring_register_op.define('IORING_REGISTER_EVENTFD_ASYNC', 7)
|
||||
IORING_REGISTER_PROBE = enum_io_uring_register_op.define('IORING_REGISTER_PROBE', 8)
|
||||
IORING_REGISTER_PERSONALITY = enum_io_uring_register_op.define('IORING_REGISTER_PERSONALITY', 9)
|
||||
IORING_UNREGISTER_PERSONALITY = enum_io_uring_register_op.define('IORING_UNREGISTER_PERSONALITY', 10)
|
||||
IORING_REGISTER_RESTRICTIONS = enum_io_uring_register_op.define('IORING_REGISTER_RESTRICTIONS', 11)
|
||||
IORING_REGISTER_ENABLE_RINGS = enum_io_uring_register_op.define('IORING_REGISTER_ENABLE_RINGS', 12)
|
||||
IORING_REGISTER_FILES2 = enum_io_uring_register_op.define('IORING_REGISTER_FILES2', 13)
|
||||
IORING_REGISTER_FILES_UPDATE2 = enum_io_uring_register_op.define('IORING_REGISTER_FILES_UPDATE2', 14)
|
||||
IORING_REGISTER_BUFFERS2 = enum_io_uring_register_op.define('IORING_REGISTER_BUFFERS2', 15)
|
||||
IORING_REGISTER_BUFFERS_UPDATE = enum_io_uring_register_op.define('IORING_REGISTER_BUFFERS_UPDATE', 16)
|
||||
IORING_REGISTER_IOWQ_AFF = enum_io_uring_register_op.define('IORING_REGISTER_IOWQ_AFF', 17)
|
||||
IORING_UNREGISTER_IOWQ_AFF = enum_io_uring_register_op.define('IORING_UNREGISTER_IOWQ_AFF', 18)
|
||||
IORING_REGISTER_IOWQ_MAX_WORKERS = enum_io_uring_register_op.define('IORING_REGISTER_IOWQ_MAX_WORKERS', 19)
|
||||
IORING_REGISTER_RING_FDS = enum_io_uring_register_op.define('IORING_REGISTER_RING_FDS', 20)
|
||||
IORING_UNREGISTER_RING_FDS = enum_io_uring_register_op.define('IORING_UNREGISTER_RING_FDS', 21)
|
||||
IORING_REGISTER_PBUF_RING = enum_io_uring_register_op.define('IORING_REGISTER_PBUF_RING', 22)
|
||||
IORING_UNREGISTER_PBUF_RING = enum_io_uring_register_op.define('IORING_UNREGISTER_PBUF_RING', 23)
|
||||
IORING_REGISTER_SYNC_CANCEL = enum_io_uring_register_op.define('IORING_REGISTER_SYNC_CANCEL', 24)
|
||||
IORING_REGISTER_FILE_ALLOC_RANGE = enum_io_uring_register_op.define('IORING_REGISTER_FILE_ALLOC_RANGE', 25)
|
||||
IORING_REGISTER_PBUF_STATUS = enum_io_uring_register_op.define('IORING_REGISTER_PBUF_STATUS', 26)
|
||||
IORING_REGISTER_NAPI = enum_io_uring_register_op.define('IORING_REGISTER_NAPI', 27)
|
||||
IORING_UNREGISTER_NAPI = enum_io_uring_register_op.define('IORING_UNREGISTER_NAPI', 28)
|
||||
IORING_REGISTER_CLOCK = enum_io_uring_register_op.define('IORING_REGISTER_CLOCK', 29)
|
||||
IORING_REGISTER_CLONE_BUFFERS = enum_io_uring_register_op.define('IORING_REGISTER_CLONE_BUFFERS', 30)
|
||||
IORING_REGISTER_SEND_MSG_RING = enum_io_uring_register_op.define('IORING_REGISTER_SEND_MSG_RING', 31)
|
||||
IORING_REGISTER_ZCRX_IFQ = enum_io_uring_register_op.define('IORING_REGISTER_ZCRX_IFQ', 32)
|
||||
IORING_REGISTER_RESIZE_RINGS = enum_io_uring_register_op.define('IORING_REGISTER_RESIZE_RINGS', 33)
|
||||
IORING_REGISTER_MEM_REGION = enum_io_uring_register_op.define('IORING_REGISTER_MEM_REGION', 34)
|
||||
IORING_REGISTER_QUERY = enum_io_uring_register_op.define('IORING_REGISTER_QUERY', 35)
|
||||
IORING_REGISTER_ZCRX_CTRL = enum_io_uring_register_op.define('IORING_REGISTER_ZCRX_CTRL', 36)
|
||||
IORING_REGISTER_LAST = enum_io_uring_register_op.define('IORING_REGISTER_LAST', 37)
|
||||
IORING_REGISTER_USE_REGISTERED_RING = enum_io_uring_register_op.define('IORING_REGISTER_USE_REGISTERED_RING', 2147483648)
|
||||
|
||||
class _anonenum4(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IO_WQ_BOUND = _anonenum4.define('IO_WQ_BOUND', 0)
|
||||
IO_WQ_UNBOUND = _anonenum4.define('IO_WQ_UNBOUND', 1)
|
||||
class enum_io_wq_type(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IO_WQ_BOUND = enum_io_wq_type.define('IO_WQ_BOUND', 0)
|
||||
IO_WQ_UNBOUND = enum_io_wq_type.define('IO_WQ_UNBOUND', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_files_update(c.Struct):
|
||||
@@ -294,6 +312,27 @@ class struct_io_uring_files_update(c.Struct):
|
||||
offset: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
resv: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
fds: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
class _anonenum0(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_MEM_REGION_TYPE_USER = _anonenum0.define('IORING_MEM_REGION_TYPE_USER', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_region_desc(c.Struct):
|
||||
SIZE = 64
|
||||
user_addr: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
size: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
||||
id: Annotated[Annotated[int, ctypes.c_uint32], 20]
|
||||
mmap_offset: Annotated[Annotated[int, ctypes.c_uint64], 24]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[4]], 32]
|
||||
class _anonenum1(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_MEM_REGION_REG_WAIT_ARG = _anonenum1.define('IORING_MEM_REGION_REG_WAIT_ARG', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_mem_region_reg(c.Struct):
|
||||
SIZE = 32
|
||||
region_uptr: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[2]], 16]
|
||||
@c.record
|
||||
class struct_io_uring_rsrc_register(c.Struct):
|
||||
SIZE = 32
|
||||
@@ -342,6 +381,24 @@ class struct_io_uring_restriction(c.Struct):
|
||||
resv: Annotated[Annotated[int, ctypes.c_ubyte], 3]
|
||||
resv2: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], 4]
|
||||
@c.record
|
||||
class struct_io_uring_clock_register(c.Struct):
|
||||
SIZE = 16
|
||||
clockid: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], 4]
|
||||
class _anonenum2(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_REGISTER_SRC_REGISTERED = _anonenum2.define('IORING_REGISTER_SRC_REGISTERED', 1)
|
||||
IORING_REGISTER_DST_REPLACE = _anonenum2.define('IORING_REGISTER_DST_REPLACE', 2)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_clone_buffers(c.Struct):
|
||||
SIZE = 32
|
||||
src_fd: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
src_off: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
dst_off: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
nr: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
||||
pad: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], 20]
|
||||
@c.record
|
||||
class struct_io_uring_buf(c.Struct):
|
||||
SIZE = 16
|
||||
addr: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
@@ -358,8 +415,9 @@ class struct_io_uring_buf_ring(c.Struct):
|
||||
__empty_bufs: Annotated[struct_io_uring_buf_ring___empty_bufs, 0]
|
||||
bufs: Annotated[c.Array[struct_io_uring_buf, Literal[0]], 0]
|
||||
class struct_io_uring_buf_ring___empty_bufs(ctypes.Structure): pass
|
||||
class _anonenum5(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IOU_PBUF_RING_MMAP = _anonenum5.define('IOU_PBUF_RING_MMAP', 1)
|
||||
class enum_io_uring_register_pbuf_ring_flags(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IOU_PBUF_RING_MMAP = enum_io_uring_register_pbuf_ring_flags.define('IOU_PBUF_RING_MMAP', 1)
|
||||
IOU_PBUF_RING_INC = enum_io_uring_register_pbuf_ring_flags.define('IOU_PBUF_RING_INC', 2)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_buf_reg(c.Struct):
|
||||
@@ -375,19 +433,57 @@ class struct_io_uring_buf_status(c.Struct):
|
||||
buf_group: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
head: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
resv: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[8]], 8]
|
||||
class _anonenum6(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_RESTRICTION_REGISTER_OP = _anonenum6.define('IORING_RESTRICTION_REGISTER_OP', 0)
|
||||
IORING_RESTRICTION_SQE_OP = _anonenum6.define('IORING_RESTRICTION_SQE_OP', 1)
|
||||
IORING_RESTRICTION_SQE_FLAGS_ALLOWED = _anonenum6.define('IORING_RESTRICTION_SQE_FLAGS_ALLOWED', 2)
|
||||
IORING_RESTRICTION_SQE_FLAGS_REQUIRED = _anonenum6.define('IORING_RESTRICTION_SQE_FLAGS_REQUIRED', 3)
|
||||
IORING_RESTRICTION_LAST = _anonenum6.define('IORING_RESTRICTION_LAST', 4)
|
||||
class enum_io_uring_napi_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IO_URING_NAPI_REGISTER_OP = enum_io_uring_napi_op.define('IO_URING_NAPI_REGISTER_OP', 0)
|
||||
IO_URING_NAPI_STATIC_ADD_ID = enum_io_uring_napi_op.define('IO_URING_NAPI_STATIC_ADD_ID', 1)
|
||||
IO_URING_NAPI_STATIC_DEL_ID = enum_io_uring_napi_op.define('IO_URING_NAPI_STATIC_DEL_ID', 2)
|
||||
|
||||
class enum_io_uring_napi_tracking_strategy(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IO_URING_NAPI_TRACKING_DYNAMIC = enum_io_uring_napi_tracking_strategy.define('IO_URING_NAPI_TRACKING_DYNAMIC', 0)
|
||||
IO_URING_NAPI_TRACKING_STATIC = enum_io_uring_napi_tracking_strategy.define('IO_URING_NAPI_TRACKING_STATIC', 1)
|
||||
IO_URING_NAPI_TRACKING_INACTIVE = enum_io_uring_napi_tracking_strategy.define('IO_URING_NAPI_TRACKING_INACTIVE', 255)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_napi(c.Struct):
|
||||
SIZE = 16
|
||||
busy_poll_to: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
prefer_busy_poll: Annotated[Annotated[int, ctypes.c_ubyte], 4]
|
||||
opcode: Annotated[Annotated[int, ctypes.c_ubyte], 5]
|
||||
pad: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[2]], 6]
|
||||
op_param: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
resv: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
class enum_io_uring_register_restriction_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_RESTRICTION_REGISTER_OP = enum_io_uring_register_restriction_op.define('IORING_RESTRICTION_REGISTER_OP', 0)
|
||||
IORING_RESTRICTION_SQE_OP = enum_io_uring_register_restriction_op.define('IORING_RESTRICTION_SQE_OP', 1)
|
||||
IORING_RESTRICTION_SQE_FLAGS_ALLOWED = enum_io_uring_register_restriction_op.define('IORING_RESTRICTION_SQE_FLAGS_ALLOWED', 2)
|
||||
IORING_RESTRICTION_SQE_FLAGS_REQUIRED = enum_io_uring_register_restriction_op.define('IORING_RESTRICTION_SQE_FLAGS_REQUIRED', 3)
|
||||
IORING_RESTRICTION_LAST = enum_io_uring_register_restriction_op.define('IORING_RESTRICTION_LAST', 4)
|
||||
|
||||
class _anonenum3(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_REG_WAIT_TS = _anonenum3.define('IORING_REG_WAIT_TS', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_reg_wait(c.Struct):
|
||||
SIZE = 64
|
||||
ts: Annotated[struct___kernel_timespec, 0]
|
||||
min_wait_usec: Annotated[Annotated[int, ctypes.c_uint32], 16]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 20]
|
||||
sigmask: Annotated[Annotated[int, ctypes.c_uint64], 24]
|
||||
sigmask_sz: Annotated[Annotated[int, ctypes.c_uint32], 32]
|
||||
pad: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[3]], 36]
|
||||
pad2: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[2]], 48]
|
||||
@c.record
|
||||
class struct___kernel_timespec(c.Struct):
|
||||
SIZE = 16
|
||||
tv_sec: Annotated[Annotated[int, ctypes.c_int64], 0]
|
||||
tv_nsec: Annotated[Annotated[int, ctypes.c_int64], 8]
|
||||
__kernel_time64_t: TypeAlias = Annotated[int, ctypes.c_int64]
|
||||
@c.record
|
||||
class struct_io_uring_getevents_arg(c.Struct):
|
||||
SIZE = 24
|
||||
sigmask: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
sigmask_sz: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
pad: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
min_wait_usec: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
ts: Annotated[Annotated[int, ctypes.c_uint64], 16]
|
||||
@c.record
|
||||
class struct_io_uring_sync_cancel_reg(c.Struct):
|
||||
@@ -400,12 +496,6 @@ class struct_io_uring_sync_cancel_reg(c.Struct):
|
||||
pad: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[7]], 33]
|
||||
pad2: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[3]], 40]
|
||||
@c.record
|
||||
class struct___kernel_timespec(c.Struct):
|
||||
SIZE = 16
|
||||
tv_sec: Annotated[Annotated[int, ctypes.c_int64], 0]
|
||||
tv_nsec: Annotated[Annotated[int, ctypes.c_int64], 8]
|
||||
__kernel_time64_t: TypeAlias = Annotated[int, ctypes.c_int64]
|
||||
@c.record
|
||||
class struct_io_uring_file_index_range(c.Struct):
|
||||
SIZE = 16
|
||||
off: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
@@ -418,22 +508,90 @@ class struct_io_uring_recvmsg_out(c.Struct):
|
||||
controllen: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
payloadlen: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
class _anonenum7(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
SOCKET_URING_OP_SIOCINQ = _anonenum7.define('SOCKET_URING_OP_SIOCINQ', 0)
|
||||
SOCKET_URING_OP_SIOCOUTQ = _anonenum7.define('SOCKET_URING_OP_SIOCOUTQ', 1)
|
||||
SOCKET_URING_OP_GETSOCKOPT = _anonenum7.define('SOCKET_URING_OP_GETSOCKOPT', 2)
|
||||
SOCKET_URING_OP_SETSOCKOPT = _anonenum7.define('SOCKET_URING_OP_SETSOCKOPT', 3)
|
||||
class enum_io_uring_socket_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
SOCKET_URING_OP_SIOCINQ = enum_io_uring_socket_op.define('SOCKET_URING_OP_SIOCINQ', 0)
|
||||
SOCKET_URING_OP_SIOCOUTQ = enum_io_uring_socket_op.define('SOCKET_URING_OP_SIOCOUTQ', 1)
|
||||
SOCKET_URING_OP_GETSOCKOPT = enum_io_uring_socket_op.define('SOCKET_URING_OP_GETSOCKOPT', 2)
|
||||
SOCKET_URING_OP_SETSOCKOPT = enum_io_uring_socket_op.define('SOCKET_URING_OP_SETSOCKOPT', 3)
|
||||
SOCKET_URING_OP_TX_TIMESTAMP = enum_io_uring_socket_op.define('SOCKET_URING_OP_TX_TIMESTAMP', 4)
|
||||
SOCKET_URING_OP_GETSOCKNAME = enum_io_uring_socket_op.define('SOCKET_URING_OP_GETSOCKNAME', 5)
|
||||
|
||||
@c.record
|
||||
class struct_io_timespec(c.Struct):
|
||||
SIZE = 16
|
||||
tv_sec: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
tv_nsec: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
@c.record
|
||||
class struct_io_uring_zcrx_cqe(c.Struct):
|
||||
SIZE = 16
|
||||
off: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
__pad: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
@c.record
|
||||
class struct_io_uring_zcrx_offsets(c.Struct):
|
||||
SIZE = 32
|
||||
head: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
tail: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
rqes: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
__resv2: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[2]], 16]
|
||||
class enum_io_uring_zcrx_area_flags(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
IORING_ZCRX_AREA_DMABUF = enum_io_uring_zcrx_area_flags.define('IORING_ZCRX_AREA_DMABUF', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_zcrx_area_reg(c.Struct):
|
||||
SIZE = 48
|
||||
addr: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
len: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
rq_area_token: Annotated[Annotated[int, ctypes.c_uint64], 16]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 24]
|
||||
dmabuf_fd: Annotated[Annotated[int, ctypes.c_uint32], 28]
|
||||
__resv2: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[2]], 32]
|
||||
class enum_zcrx_reg_flags(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
ZCRX_REG_IMPORT = enum_zcrx_reg_flags.define('ZCRX_REG_IMPORT', 1)
|
||||
|
||||
@c.record
|
||||
class struct_io_uring_zcrx_ifq_reg(c.Struct):
|
||||
SIZE = 96
|
||||
if_idx: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
if_rxq: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
rq_entries: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
area_ptr: Annotated[Annotated[int, ctypes.c_uint64], 16]
|
||||
region_ptr: Annotated[Annotated[int, ctypes.c_uint64], 24]
|
||||
offsets: Annotated[struct_io_uring_zcrx_offsets, 32]
|
||||
zcrx_id: Annotated[Annotated[int, ctypes.c_uint32], 64]
|
||||
__resv2: Annotated[Annotated[int, ctypes.c_uint32], 68]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[3]], 72]
|
||||
class enum_zcrx_ctrl_op(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
ZCRX_CTRL_FLUSH_RQ = enum_zcrx_ctrl_op.define('ZCRX_CTRL_FLUSH_RQ', 0)
|
||||
ZCRX_CTRL_EXPORT = enum_zcrx_ctrl_op.define('ZCRX_CTRL_EXPORT', 1)
|
||||
__ZCRX_CTRL_LAST = enum_zcrx_ctrl_op.define('__ZCRX_CTRL_LAST', 2)
|
||||
|
||||
@c.record
|
||||
class struct_zcrx_ctrl_flush_rq(c.Struct):
|
||||
SIZE = 48
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[6]], 0]
|
||||
@c.record
|
||||
class struct_zcrx_ctrl_export(c.Struct):
|
||||
SIZE = 48
|
||||
zcrx_fd: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
__resv1: Annotated[c.Array[Annotated[int, ctypes.c_uint32], Literal[11]], 4]
|
||||
@c.record
|
||||
class struct_zcrx_ctrl(c.Struct):
|
||||
SIZE = 72
|
||||
zcrx_id: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
op: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
__resv: Annotated[c.Array[Annotated[int, ctypes.c_uint64], Literal[2]], 8]
|
||||
zc_export: Annotated[struct_zcrx_ctrl_export, 24]
|
||||
zc_flush: Annotated[struct_zcrx_ctrl_flush_rq, 24]
|
||||
c.init_records()
|
||||
_XOPEN_SOURCE = 500 # type: ignore
|
||||
uring_unlikely = lambda cond: __builtin_expect( not not (cond), 0) # type: ignore
|
||||
uring_likely = lambda cond: __builtin_expect( not not (cond), 1) # type: ignore
|
||||
NR_io_uring_setup = 425 # type: ignore
|
||||
NR_io_uring_enter = 426 # type: ignore
|
||||
NR_io_uring_register = 427 # type: ignore
|
||||
io_uring_cqe_index = lambda ring,ptr,mask: (((ptr) & (mask)) << io_uring_cqe_shift(ring)) # type: ignore
|
||||
UNUSED = lambda x: (void)(x) # type: ignore
|
||||
IO_URING_CHECK_VERSION = lambda major,minor: (major > IO_URING_VERSION_MAJOR or (major == IO_URING_VERSION_MAJOR and minor >= IO_URING_VERSION_MINOR)) # type: ignore
|
||||
IO_URING_CHECK_VERSION = lambda major,minor: (major > IO_URING_VERSION_MAJOR or (major == IO_URING_VERSION_MAJOR and minor > IO_URING_VERSION_MINOR)) # type: ignore
|
||||
IORING_RW_ATTR_FLAG_PI = (1 << 0) # type: ignore
|
||||
IORING_FILE_INDEX_ALLOC = (~0) # type: ignore
|
||||
IOSQE_FIXED_FILE = (1 << IOSQE_FIXED_FILE_BIT) # type: ignore
|
||||
IOSQE_IO_DRAIN = (1 << IOSQE_IO_DRAIN_BIT) # type: ignore
|
||||
@@ -459,8 +617,12 @@ IORING_SETUP_DEFER_TASKRUN = (1 << 13) # type: ignore
|
||||
IORING_SETUP_NO_MMAP = (1 << 14) # type: ignore
|
||||
IORING_SETUP_REGISTERED_FD_ONLY = (1 << 15) # type: ignore
|
||||
IORING_SETUP_NO_SQARRAY = (1 << 16) # type: ignore
|
||||
IORING_SETUP_HYBRID_IOPOLL = (1 << 17) # type: ignore
|
||||
IORING_SETUP_CQE_MIXED = (1 << 18) # type: ignore
|
||||
IORING_SETUP_SQE_MIXED = (1 << 19) # type: ignore
|
||||
IORING_URING_CMD_FIXED = (1 << 0) # type: ignore
|
||||
IORING_URING_CMD_MASK = IORING_URING_CMD_FIXED # type: ignore
|
||||
IORING_URING_CMD_MULTISHOT = (1 << 1) # type: ignore
|
||||
IORING_URING_CMD_MASK = (IORING_URING_CMD_FIXED | IORING_URING_CMD_MULTISHOT) # type: ignore
|
||||
IORING_FSYNC_DATASYNC = (1 << 0) # type: ignore
|
||||
IORING_TIMEOUT_ABS = (1 << 0) # type: ignore
|
||||
IORING_TIMEOUT_UPDATE = (1 << 1) # type: ignore
|
||||
@@ -486,15 +648,29 @@ IORING_RECVSEND_POLL_FIRST = (1 << 0) # type: ignore
|
||||
IORING_RECV_MULTISHOT = (1 << 1) # type: ignore
|
||||
IORING_RECVSEND_FIXED_BUF = (1 << 2) # type: ignore
|
||||
IORING_SEND_ZC_REPORT_USAGE = (1 << 3) # type: ignore
|
||||
IORING_RECVSEND_BUNDLE = (1 << 4) # type: ignore
|
||||
IORING_SEND_VECTORIZED = (1 << 5) # type: ignore
|
||||
IORING_NOTIF_USAGE_ZC_COPIED = (1 << 31) # type: ignore
|
||||
IORING_ACCEPT_MULTISHOT = (1 << 0) # type: ignore
|
||||
IORING_ACCEPT_DONTWAIT = (1 << 1) # type: ignore
|
||||
IORING_ACCEPT_POLL_FIRST = (1 << 2) # type: ignore
|
||||
IORING_MSG_RING_CQE_SKIP = (1 << 0) # type: ignore
|
||||
IORING_MSG_RING_FLAGS_PASS = (1 << 1) # type: ignore
|
||||
IORING_FIXED_FD_NO_CLOEXEC = (1 << 0) # type: ignore
|
||||
IORING_NOP_INJECT_RESULT = (1 << 0) # type: ignore
|
||||
IORING_NOP_FILE = (1 << 1) # type: ignore
|
||||
IORING_NOP_FIXED_FILE = (1 << 2) # type: ignore
|
||||
IORING_NOP_FIXED_BUFFER = (1 << 3) # type: ignore
|
||||
IORING_NOP_TW = (1 << 4) # type: ignore
|
||||
IORING_NOP_CQE32 = (1 << 5) # type: ignore
|
||||
IORING_CQE_F_BUFFER = (1 << 0) # type: ignore
|
||||
IORING_CQE_F_MORE = (1 << 1) # type: ignore
|
||||
IORING_CQE_F_SOCK_NONEMPTY = (1 << 2) # type: ignore
|
||||
IORING_CQE_F_NOTIF = (1 << 3) # type: ignore
|
||||
IORING_CQE_F_BUF_MORE = (1 << 4) # type: ignore
|
||||
IORING_CQE_F_SKIP = (1 << 5) # type: ignore
|
||||
IORING_CQE_F_32 = (1 << 15) # type: ignore
|
||||
IORING_CQE_BUFFER_SHIFT = 16 # type: ignore
|
||||
IORING_OFF_SQ_RING = 0 # type: ignore
|
||||
IORING_OFF_CQ_RING = 0x8000000 # type: ignore
|
||||
IORING_OFF_SQES = 0x10000000 # type: ignore
|
||||
@@ -510,6 +686,9 @@ IORING_ENTER_SQ_WAKEUP = (1 << 1) # type: ignore
|
||||
IORING_ENTER_SQ_WAIT = (1 << 2) # type: ignore
|
||||
IORING_ENTER_EXT_ARG = (1 << 3) # type: ignore
|
||||
IORING_ENTER_REGISTERED_RING = (1 << 4) # type: ignore
|
||||
IORING_ENTER_ABS_TIMER = (1 << 5) # type: ignore
|
||||
IORING_ENTER_EXT_ARG_REG = (1 << 6) # type: ignore
|
||||
IORING_ENTER_NO_IOWAIT = (1 << 7) # type: ignore
|
||||
IORING_FEAT_SINGLE_MMAP = (1 << 0) # type: ignore
|
||||
IORING_FEAT_NODROP = (1 << 1) # type: ignore
|
||||
IORING_FEAT_SUBMIT_STABLE = (1 << 2) # type: ignore
|
||||
@@ -524,9 +703,16 @@ IORING_FEAT_RSRC_TAGS = (1 << 10) # type: ignore
|
||||
IORING_FEAT_CQE_SKIP = (1 << 11) # type: ignore
|
||||
IORING_FEAT_LINKED_FILE = (1 << 12) # type: ignore
|
||||
IORING_FEAT_REG_REG_RING = (1 << 13) # type: ignore
|
||||
IORING_FEAT_RECVSEND_BUNDLE = (1 << 14) # type: ignore
|
||||
IORING_FEAT_MIN_TIMEOUT = (1 << 15) # type: ignore
|
||||
IORING_FEAT_RW_ATTR = (1 << 16) # type: ignore
|
||||
IORING_FEAT_NO_IOWAIT = (1 << 17) # type: ignore
|
||||
IORING_RSRC_REGISTER_SPARSE = (1 << 0) # type: ignore
|
||||
IORING_REGISTER_FILES_SKIP = (-2) # type: ignore
|
||||
IO_URING_OP_SUPPORTED = (1 << 0) # type: ignore
|
||||
IORING_TIMESTAMP_HW_SHIFT = 16 # type: ignore
|
||||
IORING_TIMESTAMP_TYPE_SHIFT = (IORING_TIMESTAMP_HW_SHIFT + 1) # type: ignore
|
||||
IORING_ZCRX_AREA_SHIFT = 48 # type: ignore
|
||||
__SC_3264 = lambda _nr,_32,_64: __SYSCALL(_nr, _64) # type: ignore
|
||||
__SC_COMP = lambda _nr,_sys,_comp: __SYSCALL(_nr, _sys) # type: ignore
|
||||
__SC_COMP_3264 = lambda _nr,_32,_64,_comp: __SC_3264(_nr, _32, _64) # type: ignore
|
||||
@@ -816,6 +1002,7 @@ NR_fsconfig = 431 # type: ignore
|
||||
NR_fsmount = 432 # type: ignore
|
||||
NR_fspick = 433 # type: ignore
|
||||
NR_pidfd_open = 434 # type: ignore
|
||||
NR_clone3 = 435 # type: ignore
|
||||
NR_close_range = 436 # type: ignore
|
||||
NR_openat2 = 437 # type: ignore
|
||||
NR_pidfd_getfd = 438 # type: ignore
|
||||
@@ -841,7 +1028,16 @@ NR_listmount = 458 # type: ignore
|
||||
NR_lsm_get_self_attr = 459 # type: ignore
|
||||
NR_lsm_set_self_attr = 460 # type: ignore
|
||||
NR_lsm_list_modules = 461 # type: ignore
|
||||
NR_syscalls = 462 # type: ignore
|
||||
NR_mseal = 462 # type: ignore
|
||||
NR_setxattrat = 463 # type: ignore
|
||||
NR_getxattrat = 464 # type: ignore
|
||||
NR_listxattrat = 465 # type: ignore
|
||||
NR_removexattrat = 466 # type: ignore
|
||||
NR_open_tree_attr = 467 # type: ignore
|
||||
NR_file_getattr = 468 # type: ignore
|
||||
NR_file_setattr = 469 # type: ignore
|
||||
NR_listns = 470 # type: ignore
|
||||
NR_syscalls = 471 # type: ignore
|
||||
NR_fcntl = NR3264_fcntl # type: ignore
|
||||
NR_statfs = NR3264_statfs # type: ignore
|
||||
NR_fstatfs = NR3264_fstatfs # type: ignore
|
||||
|
||||
@@ -151,6 +151,8 @@ PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400 # type: ignore
|
||||
PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40 # type: ignore
|
||||
PCI_CB_SUBSYSTEM_ID = 0x42 # type: ignore
|
||||
PCI_CB_LEGACY_MODE_BASE = 0x44 # type: ignore
|
||||
PCI_CAP_ID_MASK = 0x00ff # type: ignore
|
||||
PCI_CAP_LIST_NEXT_MASK = 0xff00 # type: ignore
|
||||
PCI_CAP_LIST_ID = 0 # type: ignore
|
||||
PCI_CAP_ID_PM = 0x01 # type: ignore
|
||||
PCI_CAP_ID_AGP = 0x02 # type: ignore
|
||||
@@ -266,6 +268,7 @@ PCI_MSIX_ENTRY_UPPER_ADDR = 0x4 # type: ignore
|
||||
PCI_MSIX_ENTRY_DATA = 0x8 # type: ignore
|
||||
PCI_MSIX_ENTRY_VECTOR_CTRL = 0xc # type: ignore
|
||||
PCI_MSIX_ENTRY_CTRL_MASKBIT = 0x00000001 # type: ignore
|
||||
PCI_MSIX_ENTRY_CTRL_ST = 0xffff0000 # type: ignore
|
||||
PCI_CHSWP_CSR = 2 # type: ignore
|
||||
PCI_CHSWP_DHA = 0x01 # type: ignore
|
||||
PCI_CHSWP_EIM = 0x02 # type: ignore
|
||||
@@ -381,6 +384,7 @@ PCI_EXP_TYPE_RC_END = 0x9 # type: ignore
|
||||
PCI_EXP_TYPE_RC_EC = 0xa # type: ignore
|
||||
PCI_EXP_FLAGS_SLOT = 0x0100 # type: ignore
|
||||
PCI_EXP_FLAGS_IRQ = 0x3e00 # type: ignore
|
||||
PCI_EXP_FLAGS_FLIT = 0x8000 # type: ignore
|
||||
PCI_EXP_DEVCAP = 0x04 # type: ignore
|
||||
PCI_EXP_DEVCAP_PAYLOAD = 0x00000007 # type: ignore
|
||||
PCI_EXP_DEVCAP_PHANTOM = 0x00000018 # type: ignore
|
||||
@@ -394,6 +398,7 @@ PCI_EXP_DEVCAP_RBER = 0x00008000 # type: ignore
|
||||
PCI_EXP_DEVCAP_PWR_VAL = 0x03fc0000 # type: ignore
|
||||
PCI_EXP_DEVCAP_PWR_SCL = 0x0c000000 # type: ignore
|
||||
PCI_EXP_DEVCAP_FLR = 0x10000000 # type: ignore
|
||||
PCI_EXP_DEVCAP_TEE = 0x40000000 # type: ignore
|
||||
PCI_EXP_DEVCTL = 0x08 # type: ignore
|
||||
PCI_EXP_DEVCTL_CERE = 0x0001 # type: ignore
|
||||
PCI_EXP_DEVCTL_NFERE = 0x0002 # type: ignore
|
||||
@@ -530,9 +535,11 @@ PCI_EXP_RTCTL_SECEE = 0x0001 # type: ignore
|
||||
PCI_EXP_RTCTL_SENFEE = 0x0002 # type: ignore
|
||||
PCI_EXP_RTCTL_SEFEE = 0x0004 # type: ignore
|
||||
PCI_EXP_RTCTL_PMEIE = 0x0008 # type: ignore
|
||||
PCI_EXP_RTCTL_CRSSVE = 0x0010 # type: ignore
|
||||
PCI_EXP_RTCTL_RRS_SVE = 0x0010 # type: ignore
|
||||
PCI_EXP_RTCTL_CRSSVE = PCI_EXP_RTCTL_RRS_SVE # type: ignore
|
||||
PCI_EXP_RTCAP = 0x1e # type: ignore
|
||||
PCI_EXP_RTCAP_CRSVIS = 0x0001 # type: ignore
|
||||
PCI_EXP_RTCAP_RRS_SV = 0x0001 # type: ignore
|
||||
PCI_EXP_RTCAP_CRSVIS = PCI_EXP_RTCAP_RRS_SV # type: ignore
|
||||
PCI_EXP_RTSTA = 0x20 # type: ignore
|
||||
PCI_EXP_RTSTA_PME_RQ_ID = 0x0000ffff # type: ignore
|
||||
PCI_EXP_RTSTA_PME = 0x00010000 # type: ignore
|
||||
@@ -545,10 +552,12 @@ PCI_EXP_DEVCAP2_ATOMIC_COMP32 = 0x00000080 # type: ignore
|
||||
PCI_EXP_DEVCAP2_ATOMIC_COMP64 = 0x00000100 # type: ignore
|
||||
PCI_EXP_DEVCAP2_ATOMIC_COMP128 = 0x00000200 # type: ignore
|
||||
PCI_EXP_DEVCAP2_LTR = 0x00000800 # type: ignore
|
||||
PCI_EXP_DEVCAP2_TPH_COMP_MASK = 0x00003000 # type: ignore
|
||||
PCI_EXP_DEVCAP2_OBFF_MASK = 0x000c0000 # type: ignore
|
||||
PCI_EXP_DEVCAP2_OBFF_MSG = 0x00040000 # type: ignore
|
||||
PCI_EXP_DEVCAP2_OBFF_WAKE = 0x00080000 # type: ignore
|
||||
PCI_EXP_DEVCAP2_EE_PREFIX = 0x00200000 # type: ignore
|
||||
PCI_EXP_DEVCAP2_EE_PREFIX_MAX = 0x00c00000 # type: ignore
|
||||
PCI_EXP_DEVCTL2 = 0x28 # type: ignore
|
||||
PCI_EXP_DEVCTL2_COMP_TIMEOUT = 0x000f # type: ignore
|
||||
PCI_EXP_DEVCTL2_COMP_TMOUT_DIS = 0x0010 # type: ignore
|
||||
@@ -564,6 +573,7 @@ PCI_EXP_DEVCTL2_OBFF_WAKE_EN = 0x6000 # type: ignore
|
||||
PCI_EXP_DEVSTA2 = 0x2a # type: ignore
|
||||
PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 = 0x2c # type: ignore
|
||||
PCI_EXP_LNKCAP2 = 0x2c # type: ignore
|
||||
PCI_EXP_LNKCAP2_SLS = 0x000000fe # type: ignore
|
||||
PCI_EXP_LNKCAP2_SLS_2_5GB = 0x00000002 # type: ignore
|
||||
PCI_EXP_LNKCAP2_SLS_5_0GB = 0x00000004 # type: ignore
|
||||
PCI_EXP_LNKCAP2_SLS_8_0GB = 0x00000008 # type: ignore
|
||||
@@ -623,11 +633,16 @@ PCI_EXT_CAP_ID_DPC = 0x1D # type: ignore
|
||||
PCI_EXT_CAP_ID_L1SS = 0x1E # type: ignore
|
||||
PCI_EXT_CAP_ID_PTM = 0x1F # type: ignore
|
||||
PCI_EXT_CAP_ID_DVSEC = 0x23 # type: ignore
|
||||
PCI_EXT_CAP_ID_VF_REBAR = 0x24 # type: ignore
|
||||
PCI_EXT_CAP_ID_DLF = 0x25 # type: ignore
|
||||
PCI_EXT_CAP_ID_PL_16GT = 0x26 # type: ignore
|
||||
PCI_EXT_CAP_ID_NPEM = 0x29 # type: ignore
|
||||
PCI_EXT_CAP_ID_PL_32GT = 0x2A # type: ignore
|
||||
PCI_EXT_CAP_ID_DOE = 0x2E # type: ignore
|
||||
PCI_EXT_CAP_ID_MAX = PCI_EXT_CAP_ID_DOE # type: ignore
|
||||
PCI_EXT_CAP_ID_DEV3 = 0x2F # type: ignore
|
||||
PCI_EXT_CAP_ID_IDE = 0x30 # type: ignore
|
||||
PCI_EXT_CAP_ID_PL_64GT = 0x31 # type: ignore
|
||||
PCI_EXT_CAP_ID_MAX = PCI_EXT_CAP_ID_PL_64GT # type: ignore
|
||||
PCI_EXT_CAP_DSN_SIZEOF = 12 # type: ignore
|
||||
PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF = 40 # type: ignore
|
||||
PCI_ERR_UNCOR_STATUS = 0x04 # type: ignore
|
||||
@@ -648,6 +663,12 @@ PCI_ERR_UNC_INTN = 0x00400000 # type: ignore
|
||||
PCI_ERR_UNC_MCBTLP = 0x00800000 # type: ignore
|
||||
PCI_ERR_UNC_ATOMEG = 0x01000000 # type: ignore
|
||||
PCI_ERR_UNC_TLPPRE = 0x02000000 # type: ignore
|
||||
PCI_ERR_UNC_POISON_BLK = 0x04000000 # type: ignore
|
||||
PCI_ERR_UNC_DMWR_BLK = 0x08000000 # type: ignore
|
||||
PCI_ERR_UNC_IDE_CHECK = 0x10000000 # type: ignore
|
||||
PCI_ERR_UNC_MISR_IDE = 0x20000000 # type: ignore
|
||||
PCI_ERR_UNC_PCRC_CHECK = 0x40000000 # type: ignore
|
||||
PCI_ERR_UNC_XLAT_BLK = 0x80000000 # type: ignore
|
||||
PCI_ERR_UNCOR_MASK = 0x08 # type: ignore
|
||||
PCI_ERR_UNCOR_SEVER = 0x0c # type: ignore
|
||||
PCI_ERR_COR_STATUS = 0x10 # type: ignore
|
||||
@@ -666,6 +687,10 @@ PCI_ERR_CAP_ECRC_GENC = 0x00000020 # type: ignore
|
||||
PCI_ERR_CAP_ECRC_GENE = 0x00000040 # type: ignore
|
||||
PCI_ERR_CAP_ECRC_CHKC = 0x00000080 # type: ignore
|
||||
PCI_ERR_CAP_ECRC_CHKE = 0x00000100 # type: ignore
|
||||
PCI_ERR_CAP_PREFIX_LOG_PRESENT = 0x00000800 # type: ignore
|
||||
PCI_ERR_CAP_COMP_TIME_LOG = 0x00001000 # type: ignore
|
||||
PCI_ERR_CAP_TLP_LOG_FLIT = 0x00040000 # type: ignore
|
||||
PCI_ERR_CAP_TLP_LOG_SIZE = 0x00f80000 # type: ignore
|
||||
PCI_ERR_HEADER_LOG = 0x1c # type: ignore
|
||||
PCI_ERR_ROOT_COMMAND = 0x2c # type: ignore
|
||||
PCI_ERR_ROOT_CMD_COR_EN = 0x00000001 # type: ignore
|
||||
@@ -681,6 +706,7 @@ PCI_ERR_ROOT_NONFATAL_RCV = 0x00000020 # type: ignore
|
||||
PCI_ERR_ROOT_FATAL_RCV = 0x00000040 # type: ignore
|
||||
PCI_ERR_ROOT_AER_IRQ = 0xf8000000 # type: ignore
|
||||
PCI_ERR_ROOT_ERR_SRC = 0x34 # type: ignore
|
||||
PCI_ERR_PREFIX_LOG = 0x38 # type: ignore
|
||||
PCI_VC_PORT_CAP1 = 0x04 # type: ignore
|
||||
PCI_VC_CAP1_EVCC = 0x00000007 # type: ignore
|
||||
PCI_VC_CAP1_LPEVCC = 0x00000070 # type: ignore
|
||||
@@ -842,15 +868,13 @@ PCI_ACS_DT = 0x0040 # type: ignore
|
||||
PCI_ACS_EGRESS_BITS = 0x05 # type: ignore
|
||||
PCI_ACS_CTRL = 0x06 # type: ignore
|
||||
PCI_ACS_EGRESS_CTL_V = 0x08 # type: ignore
|
||||
PCI_VSEC_HDR = 4 # type: ignore
|
||||
PCI_VSEC_HDR_LEN_SHIFT = 20 # type: ignore
|
||||
PCI_SATA_REGS = 4 # type: ignore
|
||||
PCI_SATA_REGS_MASK = 0xF # type: ignore
|
||||
PCI_SATA_REGS_INLINE = 0xF # type: ignore
|
||||
PCI_SATA_SIZEOF_SHORT = 8 # type: ignore
|
||||
PCI_SATA_SIZEOF_LONG = 16 # type: ignore
|
||||
PCI_REBAR_CAP = 4 # type: ignore
|
||||
PCI_REBAR_CAP_SIZES = 0x00FFFFF0 # type: ignore
|
||||
PCI_REBAR_CAP_SIZES = 0xFFFFFFF0 # type: ignore
|
||||
PCI_REBAR_CTRL = 8 # type: ignore
|
||||
PCI_REBAR_CTRL_BAR_IDX = 0x00000007 # type: ignore
|
||||
PCI_REBAR_CTRL_NBAR_MASK = 0x000000E0 # type: ignore
|
||||
@@ -860,14 +884,30 @@ PCI_REBAR_CTRL_BAR_SHIFT = 8 # type: ignore
|
||||
PCI_DPA_CAP = 4 # type: ignore
|
||||
PCI_DPA_CAP_SUBSTATE_MASK = 0x1F # type: ignore
|
||||
PCI_DPA_BASE_SIZEOF = 16 # type: ignore
|
||||
PCI_EXP_DEVCAP2_TPH_COMP_NONE = 0x0 # type: ignore
|
||||
PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY = 0x1 # type: ignore
|
||||
PCI_EXP_DEVCAP2_TPH_COMP_EXT_TPH = 0x3 # type: ignore
|
||||
PCI_TPH_CAP = 4 # type: ignore
|
||||
PCI_TPH_CAP_LOC_MASK = 0x600 # type: ignore
|
||||
PCI_TPH_LOC_NONE = 0x000 # type: ignore
|
||||
PCI_TPH_LOC_CAP = 0x200 # type: ignore
|
||||
PCI_TPH_LOC_MSIX = 0x400 # type: ignore
|
||||
PCI_TPH_CAP_ST_NS = 0x00000001 # type: ignore
|
||||
PCI_TPH_CAP_ST_IV = 0x00000002 # type: ignore
|
||||
PCI_TPH_CAP_ST_DS = 0x00000004 # type: ignore
|
||||
PCI_TPH_CAP_EXT_TPH = 0x00000100 # type: ignore
|
||||
PCI_TPH_CAP_LOC_MASK = 0x00000600 # type: ignore
|
||||
PCI_TPH_LOC_NONE = 0x00000000 # type: ignore
|
||||
PCI_TPH_LOC_CAP = 0x00000200 # type: ignore
|
||||
PCI_TPH_LOC_MSIX = 0x00000400 # type: ignore
|
||||
PCI_TPH_CAP_ST_MASK = 0x07FF0000 # type: ignore
|
||||
PCI_TPH_CAP_ST_SHIFT = 16 # type: ignore
|
||||
PCI_TPH_BASE_SIZEOF = 0xc # type: ignore
|
||||
PCI_TPH_CTRL = 8 # type: ignore
|
||||
PCI_TPH_CTRL_MODE_SEL_MASK = 0x00000007 # type: ignore
|
||||
PCI_TPH_ST_NS_MODE = 0x0 # type: ignore
|
||||
PCI_TPH_ST_IV_MODE = 0x1 # type: ignore
|
||||
PCI_TPH_ST_DS_MODE = 0x2 # type: ignore
|
||||
PCI_TPH_CTRL_REQ_EN_MASK = 0x00000300 # type: ignore
|
||||
PCI_TPH_REQ_DISABLE = 0x0 # type: ignore
|
||||
PCI_TPH_REQ_TPH_ONLY = 0x1 # type: ignore
|
||||
PCI_TPH_REQ_EXT_TPH = 0x3 # type: ignore
|
||||
PCI_EXP_DPC_CAP = 0x04 # type: ignore
|
||||
PCI_EXP_DPC_IRQ = 0x001F # type: ignore
|
||||
PCI_EXP_DPC_CAP_RP_EXT = 0x0020 # type: ignore
|
||||
@@ -875,6 +915,7 @@ PCI_EXP_DPC_CAP_POISONED_TLP = 0x0040 # type: ignore
|
||||
PCI_EXP_DPC_CAP_SW_TRIGGER = 0x0080 # type: ignore
|
||||
PCI_EXP_DPC_RP_PIO_LOG_SIZE = 0x0F00 # type: ignore
|
||||
PCI_EXP_DPC_CAP_DL_ACTIVE = 0x1000 # type: ignore
|
||||
PCI_EXP_DPC_RP_PIO_LOG_SIZE4 = 0x2000 # type: ignore
|
||||
PCI_EXP_DPC_CTL = 0x06 # type: ignore
|
||||
PCI_EXP_DPC_CTL_EN_FATAL = 0x0001 # type: ignore
|
||||
PCI_EXP_DPC_CTL_EN_NONFATAL = 0x0002 # type: ignore
|
||||
@@ -937,12 +978,46 @@ PCI_DVSEC_HEADER1_REV = lambda x: (((x) >> 16) & 0xf) # type: ignore
|
||||
PCI_DVSEC_HEADER1_LEN = lambda x: (((x) >> 20) & 0xfff) # type: ignore
|
||||
PCI_DVSEC_HEADER2 = 0x8 # type: ignore
|
||||
PCI_DVSEC_HEADER2_ID = lambda x: ((x) & 0xffff) # type: ignore
|
||||
PCI_VF_REBAR_CAP = PCI_REBAR_CAP # type: ignore
|
||||
PCI_VF_REBAR_CAP_SIZES = PCI_REBAR_CAP_SIZES # type: ignore
|
||||
PCI_VF_REBAR_CTRL = PCI_REBAR_CTRL # type: ignore
|
||||
PCI_VF_REBAR_CTRL_BAR_IDX = PCI_REBAR_CTRL_BAR_IDX # type: ignore
|
||||
PCI_VF_REBAR_CTRL_NBAR_MASK = PCI_REBAR_CTRL_NBAR_MASK # type: ignore
|
||||
PCI_VF_REBAR_CTRL_BAR_SIZE = PCI_REBAR_CTRL_BAR_SIZE # type: ignore
|
||||
PCI_DLF_CAP = 0x04 # type: ignore
|
||||
PCI_DLF_EXCHANGE_ENABLE = 0x80000000 # type: ignore
|
||||
PCI_SECPCI_LE_CTRL = 0x0c # type: ignore
|
||||
PCI_PL_16GT_LE_CTRL = 0x20 # type: ignore
|
||||
PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK = 0x0000000F # type: ignore
|
||||
PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK = 0x000000F0 # type: ignore
|
||||
PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT = 4 # type: ignore
|
||||
PCI_PL_32GT_LE_CTRL = 0x20 # type: ignore
|
||||
PCI_PL_64GT_LE_CTRL = 0x20 # type: ignore
|
||||
PCI_NPEM_CAP = 0x04 # type: ignore
|
||||
PCI_NPEM_CAP_CAPABLE = 0x00000001 # type: ignore
|
||||
PCI_NPEM_CTRL = 0x08 # type: ignore
|
||||
PCI_NPEM_CTRL_ENABLE = 0x00000001 # type: ignore
|
||||
PCI_NPEM_CMD_RESET = 0x00000002 # type: ignore
|
||||
PCI_NPEM_IND_OK = 0x00000004 # type: ignore
|
||||
PCI_NPEM_IND_LOCATE = 0x00000008 # type: ignore
|
||||
PCI_NPEM_IND_FAIL = 0x00000010 # type: ignore
|
||||
PCI_NPEM_IND_REBUILD = 0x00000020 # type: ignore
|
||||
PCI_NPEM_IND_PFA = 0x00000040 # type: ignore
|
||||
PCI_NPEM_IND_HOTSPARE = 0x00000080 # type: ignore
|
||||
PCI_NPEM_IND_ICA = 0x00000100 # type: ignore
|
||||
PCI_NPEM_IND_IFA = 0x00000200 # type: ignore
|
||||
PCI_NPEM_IND_IDT = 0x00000400 # type: ignore
|
||||
PCI_NPEM_IND_DISABLED = 0x00000800 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_0 = 0x01000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_1 = 0x02000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_2 = 0x04000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_3 = 0x08000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_4 = 0x10000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_5 = 0x20000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_6 = 0x40000000 # type: ignore
|
||||
PCI_NPEM_IND_SPEC_7 = 0x80000000 # type: ignore
|
||||
PCI_NPEM_STATUS = 0x0c # type: ignore
|
||||
PCI_NPEM_STATUS_CC = 0x00000001 # type: ignore
|
||||
PCI_DOE_CAP = 0x04 # type: ignore
|
||||
PCI_DOE_CAP_INT_SUP = 0x00000001 # type: ignore
|
||||
PCI_DOE_CAP_INT_MSG_NUM = 0x00000ffe # type: ignore
|
||||
@@ -962,6 +1037,56 @@ PCI_DOE_DATA_OBJECT_HEADER_1_VID = 0x0000ffff # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_HEADER_1_TYPE = 0x00ff0000 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH = 0x0003ffff # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX = 0x000000ff # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_REQ_3_VER = 0x0000ff00 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID = 0x0000ffff # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL = 0x00ff0000 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX = 0xff000000 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE = 0x00ff0000 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX = 0xff000000 # type: ignore
|
||||
PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL = PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE # type: ignore
|
||||
PCI_DEV3_CAP = 0x04 # type: ignore
|
||||
PCI_DEV3_CTL = 0x08 # type: ignore
|
||||
PCI_DEV3_STA = 0x0c # type: ignore
|
||||
PCI_DEV3_STA_SEGMENT = 0x8 # type: ignore
|
||||
PCI_DVSEC_CXL_PORT = 3 # type: ignore
|
||||
PCI_DVSEC_CXL_PORT_CTL = 0x0c # type: ignore
|
||||
PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR = 0x00000001 # type: ignore
|
||||
PCI_IDE_CAP = 0x04 # type: ignore
|
||||
PCI_IDE_CAP_LINK = 0x1 # type: ignore
|
||||
PCI_IDE_CAP_SELECTIVE = 0x2 # type: ignore
|
||||
PCI_IDE_CAP_FLOWTHROUGH = 0x4 # type: ignore
|
||||
PCI_IDE_CAP_PARTIAL_HEADER_ENC = 0x8 # type: ignore
|
||||
PCI_IDE_CAP_AGGREGATION = 0x10 # type: ignore
|
||||
PCI_IDE_CAP_PCRC = 0x20 # type: ignore
|
||||
PCI_IDE_CAP_IDE_KM = 0x40 # type: ignore
|
||||
PCI_IDE_CAP_SEL_CFG = 0x80 # type: ignore
|
||||
PCI_IDE_CAP_ALG_AES_GCM_256 = 0 # type: ignore
|
||||
PCI_IDE_CAP_TEE_LIMITED = 0x1000000 # type: ignore
|
||||
PCI_IDE_CTL = 0x08 # type: ignore
|
||||
PCI_IDE_CTL_FLOWTHROUGH_IDE = 0x4 # type: ignore
|
||||
PCI_IDE_LINK_STREAM_0 = 0xc # type: ignore
|
||||
PCI_IDE_LINK_BLOCK_SIZE = 8 # type: ignore
|
||||
PCI_IDE_LINK_CTL_0 = 0x00 # type: ignore
|
||||
PCI_IDE_LINK_CTL_EN = 0x1 # type: ignore
|
||||
PCI_IDE_LINK_CTL_PCRC_EN = 0x100 # type: ignore
|
||||
PCI_IDE_LINK_STS_0 = 0x4 # type: ignore
|
||||
PCI_IDE_LINK_STS_IDE_FAIL = 0x80000000 # type: ignore
|
||||
PCI_IDE_SEL_CAP = 0x00 # type: ignore
|
||||
PCI_IDE_SEL_CTL = 0x04 # type: ignore
|
||||
PCI_IDE_SEL_CTL_EN = 0x1 # type: ignore
|
||||
PCI_IDE_SEL_CTL_PCRC_EN = 0x100 # type: ignore
|
||||
PCI_IDE_SEL_CTL_CFG_EN = 0x200 # type: ignore
|
||||
PCI_IDE_SEL_CTL_DEFAULT = 0x400000 # type: ignore
|
||||
PCI_IDE_SEL_CTL_TEE_LIMITED = 0x800000 # type: ignore
|
||||
PCI_IDE_SEL_CTL_ID_MAX = 255 # type: ignore
|
||||
PCI_IDE_SEL_STS = 0x08 # type: ignore
|
||||
PCI_IDE_SEL_STS_STATE_INSECURE = 0 # type: ignore
|
||||
PCI_IDE_SEL_STS_STATE_SECURE = 2 # type: ignore
|
||||
PCI_IDE_SEL_STS_IDE_FAIL = 0x80000000 # type: ignore
|
||||
PCI_IDE_SEL_RID_1 = 0x0c # type: ignore
|
||||
PCI_IDE_SEL_RID_2 = 0x10 # type: ignore
|
||||
PCI_IDE_SEL_RID_2_VALID = 0x1 # type: ignore
|
||||
PCI_IDE_SEL_ADDR_BLOCK_SIZE = 12 # type: ignore
|
||||
PCI_IDE_SEL_ADDR_1 = lambda x: (20 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) # type: ignore
|
||||
PCI_IDE_SEL_ADDR_1_VALID = 0x1 # type: ignore
|
||||
PCI_IDE_SEL_ADDR_2 = lambda x: (24 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) # type: ignore
|
||||
PCI_IDE_SEL_ADDR_3 = lambda x: (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) # type: ignore
|
||||
PCI_IDE_SEL_BLOCK_SIZE = lambda nr_assoc: (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc)) # type: ignore
|
||||
@@ -137,7 +137,8 @@ VFIO_CCW_NUM_IRQS = _anonenum3.define('VFIO_CCW_NUM_IRQS', 3)
|
||||
|
||||
class _anonenum4(Annotated[int, ctypes.c_uint32], c.Enum): pass
|
||||
VFIO_AP_REQ_IRQ_INDEX = _anonenum4.define('VFIO_AP_REQ_IRQ_INDEX', 0)
|
||||
VFIO_AP_NUM_IRQS = _anonenum4.define('VFIO_AP_NUM_IRQS', 1)
|
||||
VFIO_AP_CFG_CHG_IRQ_INDEX = _anonenum4.define('VFIO_AP_CFG_CHG_IRQ_INDEX', 1)
|
||||
VFIO_AP_NUM_IRQS = _anonenum4.define('VFIO_AP_NUM_IRQS', 2)
|
||||
|
||||
@c.record
|
||||
class struct_vfio_pci_dependent_device(c.Struct):
|
||||
@@ -198,22 +199,25 @@ class struct_vfio_device_feature(c.Struct):
|
||||
data: Annotated[c.Array[Annotated[int, ctypes.c_ubyte], Literal[0]], 8]
|
||||
@c.record
|
||||
class struct_vfio_device_bind_iommufd(c.Struct):
|
||||
SIZE = 16
|
||||
SIZE = 24
|
||||
argsz: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
iommufd: Annotated[Annotated[int, ctypes.c_int32], 8]
|
||||
out_devid: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
token_uuid_ptr: Annotated[Annotated[int, ctypes.c_uint64], 16]
|
||||
@c.record
|
||||
class struct_vfio_device_attach_iommufd_pt(c.Struct):
|
||||
SIZE = 12
|
||||
SIZE = 16
|
||||
argsz: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
pt_id: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
pasid: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
@c.record
|
||||
class struct_vfio_device_detach_iommufd_pt(c.Struct):
|
||||
SIZE = 8
|
||||
SIZE = 12
|
||||
argsz: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
pasid: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
@c.record
|
||||
class struct_vfio_device_feature_migration(c.Struct):
|
||||
SIZE = 8
|
||||
@@ -274,6 +278,19 @@ class struct_vfio_device_feature_bus_master(c.Struct):
|
||||
SIZE = 4
|
||||
op: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
@c.record
|
||||
class struct_vfio_region_dma_range(c.Struct):
|
||||
SIZE = 16
|
||||
offset: Annotated[Annotated[int, ctypes.c_uint64], 0]
|
||||
length: Annotated[Annotated[int, ctypes.c_uint64], 8]
|
||||
@c.record
|
||||
class struct_vfio_device_feature_dma_buf(c.Struct):
|
||||
SIZE = 16
|
||||
region_index: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
open_flags: Annotated[Annotated[int, ctypes.c_uint32], 4]
|
||||
flags: Annotated[Annotated[int, ctypes.c_uint32], 8]
|
||||
nr_ranges: Annotated[Annotated[int, ctypes.c_uint32], 12]
|
||||
dma_ranges: Annotated[c.Array[struct_vfio_region_dma_range, Literal[0]], 16]
|
||||
@c.record
|
||||
class struct_vfio_iommu_type1_info(c.Struct):
|
||||
SIZE = 24
|
||||
argsz: Annotated[Annotated[int, ctypes.c_uint32], 0]
|
||||
@@ -398,7 +415,7 @@ VFIO_SPAPR_TCE_IOMMU = 2 # type: ignore
|
||||
VFIO_TYPE1v2_IOMMU = 3 # type: ignore
|
||||
VFIO_DMA_CC_IOMMU = 4 # type: ignore
|
||||
VFIO_EEH = 5 # type: ignore
|
||||
VFIO_TYPE1_NESTING_IOMMU = 6 # type: ignore
|
||||
__VFIO_RESERVED_TYPE1_NESTING_IOMMU = 6 # type: ignore
|
||||
VFIO_SPAPR_TCE_v2_IOMMU = 7 # type: ignore
|
||||
VFIO_NOIOMMU_IOMMU = 8 # type: ignore
|
||||
VFIO_UNMAP_ALL = 9 # type: ignore
|
||||
@@ -508,8 +525,11 @@ VFIO_DEVICE_FEATURE_GET = (1 << 16) # type: ignore
|
||||
VFIO_DEVICE_FEATURE_SET = (1 << 17) # type: ignore
|
||||
VFIO_DEVICE_FEATURE_PROBE = (1 << 18) # type: ignore
|
||||
VFIO_DEVICE_FEATURE = _IO(VFIO_TYPE, VFIO_BASE + 17) # type: ignore
|
||||
VFIO_DEVICE_BIND_FLAG_TOKEN = (1 << 0) # type: ignore
|
||||
VFIO_DEVICE_BIND_IOMMUFD = _IO(VFIO_TYPE, VFIO_BASE + 18) # type: ignore
|
||||
VFIO_DEVICE_ATTACH_PASID = (1 << 0) # type: ignore
|
||||
VFIO_DEVICE_ATTACH_IOMMUFD_PT = _IO(VFIO_TYPE, VFIO_BASE + 19) # type: ignore
|
||||
VFIO_DEVICE_DETACH_PASID = (1 << 0) # type: ignore
|
||||
VFIO_DEVICE_DETACH_IOMMUFD_PT = _IO(VFIO_TYPE, VFIO_BASE + 20) # type: ignore
|
||||
VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) # type: ignore
|
||||
VFIO_MIGRATION_STOP_COPY = (1 << 0) # type: ignore
|
||||
@@ -528,6 +548,7 @@ VFIO_DEVICE_FEATURE_MIG_DATA_SIZE = 9 # type: ignore
|
||||
VFIO_DEVICE_FEATURE_CLEAR_MASTER = 0 # type: ignore
|
||||
VFIO_DEVICE_FEATURE_SET_MASTER = 1 # type: ignore
|
||||
VFIO_DEVICE_FEATURE_BUS_MASTER = 10 # type: ignore
|
||||
VFIO_DEVICE_FEATURE_DMA_BUF = 11 # type: ignore
|
||||
VFIO_IOMMU_INFO_PGSIZES = (1 << 0) # type: ignore
|
||||
VFIO_IOMMU_INFO_CAPS = (1 << 1) # type: ignore
|
||||
VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 # type: ignore
|
||||
|
||||
Reference in New Issue
Block a user