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typos
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@@ -8,7 +8,7 @@ def preprocessing_op(x,w,C):
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#print(x.shape, w.shape)
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if C.bs > 1 and C.py > 0:
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# explictly add y-padding for batched inputs
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# explicitly add y-padding for batched inputs
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# N C H W
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xs = [(0, 0) for _ in x.shape]
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xs[2] = (C.py, C.py)
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@@ -18,7 +18,7 @@ def get_conv_args(x_shape, w_shape, stride=1, groups=1, padding=0, dilation=1, o
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bs,cin_,iy,ix = x_shape
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# this can change px_ and py_ to make the out_shape right
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# TOOD: copy padding names from http://nvdla.org/hw/v1/ias/unit_description.html
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# TODO: copy padding names from http://nvdla.org/hw/v1/ias/unit_description.html
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if out_shape is not None:
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py_ = (out_shape[2] - 1) * sy + 1 + dy * (H-1) - iy - py
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px_ = (out_shape[3] - 1) * sx + 1 + dx * (W-1) - ix - px
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@@ -141,7 +141,7 @@ def _realize_binaryops(self:LazyBuffer) -> Tuple[DeviceBuffer, List[DeviceBuffer
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earlycode = "acc"
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conv_args : Optional[ConvArgs] = None
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# if there's *one* processing or reduce op in here, we can corealize it. we can corealize binary op sibilings as well
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# if there's *one* processing or reduce op in here, we can corealize it. we can corealize binary op siblings as well
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# NOTE: if it references the same conv multiple times, they should already be merged by the dictionary
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psrcs : List[Tuple[LazyBuffer, LazyBuffer]] = [(k,x) for k,x in zip(real_srcs.keys(), map(get_movementroot_contiguous, real_srcs.keys())) if x.optype in [ProcessingOps,ReduceOps] and x.realized is None and len(x.children) <= 1 and len(k.children) <= 1]
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if len(psrcs) == 1 and MERGE_ONE_REDUCE_INTO_ELEMENTWISE:
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@@ -61,7 +61,7 @@ class Tensor:
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def detach(self): return Tensor(self.lazydata, device=self.device, requires_grad=False)
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def numpy(self): return np.array(self.lazydata.toCPU())
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# TOOD: this keeps the legacy behavior working, remove it after refactor
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# TODO: this keeps the legacy behavior working, remove it after refactor
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@property
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def data(self): return self.numpy()
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