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671 lines
38 KiB
Python
671 lines
38 KiB
Python
# Generate AMD ISA autogen files from PDF documentation
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# Combines format/enum generation (previously in dsl.py) and pseudocode compilation (previously in pcode.py)
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# Usage: python -m extra.assembly.amd.pdf [--arch rdna3|rdna4|cdna|all]
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import re, functools
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from pathlib import Path
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from concurrent.futures import ProcessPoolExecutor
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PDF_URLS = {
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"rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content",
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"rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content",
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"cdna": ["https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf",
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"https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"],
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}
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# Field type mappings and ordering
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FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src',
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'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField',
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'VDATA': 'VGPRField', 'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField',
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'SIMM16': 'SImm', 'OFFSET': 'Imm', 'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src',
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'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'}
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FIELD_ORDER = {
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'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'],
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'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'],
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'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'],
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'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'],
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'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'],
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'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'],
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'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'],
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'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
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'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
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'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'],
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'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'],
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'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'],
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'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'],
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'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']}
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SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'}
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FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO',
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'4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'}
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INST_PATTERN = re.compile(r'^([SVD]S?_[A-Z0-9_]+)\s+(\d+)\s*$', re.M)
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# Patterns that can't be handled by the DSL (require special handling in emu.py)
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UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS',
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'vscnt', 'vmcnt', 'expcnt', 'lgkmcnt',
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'CVT_OFF_TABLE', 'ThreadMask',
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'S1[i', 'C.i32',
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'if n.', 'DST.u32', 'addrd = DST', 'addr = DST',
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'BARRIER_STATE', 'ReallocVgprs',
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'GPR_IDX', 'VSKIP', 'specified in', 'TTBL',
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'fp6', 'bf6'] # Malformed pseudocode from PDF
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# ═══════════════════════════════════════════════════════════════════════════════
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# COMPILER: pseudocode -> Python (minimal transforms)
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# ═══════════════════════════════════════════════════════════════════════════════
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def compile_pseudocode(pseudocode: str) -> str:
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"""Compile pseudocode to Python. Transforms are minimal - most syntax just works."""
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pseudocode = re.sub(r'\bpass\b', 'pass_', pseudocode) # 'pass' is Python keyword
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raw_lines = pseudocode.strip().split('\n')
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joined_lines: list[str] = []
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for line in raw_lines:
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line = line.strip()
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if joined_lines and (joined_lines[-1].rstrip().endswith(('||', '&&', '(', ',')) or
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(joined_lines[-1].count('(') > joined_lines[-1].count(')'))):
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joined_lines[-1] = joined_lines[-1].rstrip() + ' ' + line
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else:
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joined_lines.append(line)
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lines = []
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indent, need_pass, in_first_match_loop = 0, False, False
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declared_arrays: dict[str, int] = {} # Track declared arrays: name -> size
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for line in joined_lines:
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line = line.strip()
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if not line or line.startswith('//'): continue
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if line.startswith('if '):
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lines.append(' ' * indent + f"if {_expr(line[3:].rstrip(' then'), declared_arrays)}:")
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indent += 1
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need_pass = True
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elif line.startswith('elsif '):
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if need_pass: lines.append(' ' * indent + "pass")
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indent -= 1
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lines.append(' ' * indent + f"elif {_expr(line[6:].rstrip(' then'), declared_arrays)}:")
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indent += 1
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need_pass = True
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elif line == 'else':
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if need_pass: lines.append(' ' * indent + "pass")
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indent -= 1
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lines.append(' ' * indent + "else:")
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indent += 1
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need_pass = True
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elif line.startswith('endif'):
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if need_pass: lines.append(' ' * indent + "pass")
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indent -= 1
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need_pass = False
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elif line.startswith('endfor'):
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if need_pass: lines.append(' ' * indent + "pass")
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indent -= 1
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need_pass, in_first_match_loop = False, False
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elif m := re.match(r'declare\s+(\w+)\s*:\s*\d+\'[FBU]\[(\d+)\]', line):
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# Handle array declarations: declare in : 32'F[3] or declare S : 32'B[3]
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arr_name, arr_size = m[1], int(m[2])
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declared_arrays[arr_name] = arr_size
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py_name = f"{arr_name}_" if arr_name == 'in' else arr_name # 'in' is Python keyword
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if arr_name == 'S':
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lines.append(' ' * indent + f"{py_name} = [S0, S1, S2]") # Map to source registers
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else:
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lines.append(' ' * indent + f"{py_name} = [Reg(0) for _ in range({arr_size})]")
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elif line.startswith('declare '):
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pass # Ignore other declare statements
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elif m := re.match(r'for (\w+) in (.+?)\s*:\s*(.+?) do', line):
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start, end = _expr(m[2].strip(), declared_arrays), _expr(m[3].strip(), declared_arrays)
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lines.append(' ' * indent + f"for {m[1]} in range({start}, int({end})+1):")
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indent += 1
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need_pass, in_first_match_loop = True, True
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elif '=' in line and not line.startswith('=='):
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need_pass = False
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line = line.rstrip(';')
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if m := re.match(r'\{\s*D1\.[ui]1\s*,\s*D0\.[ui]64\s*\}\s*=\s*(.+)', line):
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rhs = _expr(m[1], declared_arrays)
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lines.append(' ' * indent + f"_full = {rhs}")
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lines.append(' ' * indent + f"D0.u64 = int(_full) & 0xffffffffffffffff")
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lines.append(' ' * indent + f"D1 = Reg((int(_full) >> 64) & 1)")
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elif any(op in line for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^=')):
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for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^='):
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if op in line:
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lhs, rhs = line.split(op, 1)
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lhs_s = _expr(lhs.strip(), declared_arrays) # Transform LHS too for array access
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lines.append(' ' * indent + f"{lhs_s} {op} {_expr(rhs.strip(), declared_arrays)}")
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break
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else:
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lhs, rhs = line.split('=', 1)
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lhs_s, rhs_s = lhs.strip(), rhs.strip()
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lhs_t = _expr(lhs_s, declared_arrays) # Transform LHS for array access
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stmt = _assign(lhs_t, _expr(rhs_s, declared_arrays), declared_arrays)
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if in_first_match_loop and rhs_s == 'i' and (lhs_s == 'tmp' or lhs_s == 'D0.i32'):
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stmt += "; break"
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lines.append(' ' * indent + stmt)
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if need_pass: lines.append(' ' * indent + "pass")
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return '\n'.join(lines)
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def _assign(lhs: str, rhs: str, declared_arrays: dict[str, int] | None = None) -> str:
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# Check for array element assignment: in_[i] should not wrap in Reg()
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if declared_arrays and re.match(r'\w+_?\[\w+\]', lhs):
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return f"{lhs} = {rhs}"
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if lhs in ('tmp', 'SCC', 'VCC', 'EXEC', 'D0', 'D1', 'saveexec', 'PC'):
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return f"{lhs} = Reg({rhs})"
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return f"{lhs} = {rhs}"
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def _expr(e: str, declared_arrays: dict[str, int] | None = None) -> str:
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e = e.strip()
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# Handle OPSEL_HI.u3[i] and OPSEL.u3[i] - bit extraction from opsel fields
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e = re.sub(r'(OPSEL(?:_HI)?)\.u\d+\[(\w+)\]', r'((\1 >> \2) & 1)', e)
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# Rename 'in' to 'in_' to avoid Python keyword conflict
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e = re.sub(r'\bin\[', 'in_[', e)
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e = e.replace('&&', ' and ').replace('||', ' or ').replace('<>', ' != ')
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e = re.sub(r'!([^=])', r' not \1', e)
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e = re.sub(r'\{\s*(\w+\.u32)\s*,\s*(\w+\.u32)\s*\}', r'_pack32(\1, \2)', e)
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def pack(m):
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hi, lo = _expr(m[1].strip(), declared_arrays), _expr(m[2].strip(), declared_arrays)
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return f'_pack({hi}, {lo})'
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e = re.sub(r'\{\s*([^,{}]+)\s*,\s*([^,{}]+)\s*\}', pack, e)
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e = re.sub(r"1201'B\(2\.0\s*/\s*PI\)", "TWO_OVER_PI_1201", e)
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e = re.sub(r"\d+'([0-9a-fA-Fx]+)[UuFf]*", r'\1', e)
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e = re.sub(r"\d+'[FIBU]\(", "(", e)
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e = re.sub(r'\bB\(', '(', e)
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e = re.sub(r'([0-9a-fA-Fx])ULL\b', r'\1', e)
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e = re.sub(r'([0-9a-fA-Fx])LL\b', r'\1', e)
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e = re.sub(r'([0-9a-fA-Fx])U\b', r'\1', e)
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e = re.sub(r'(\d\.?\d*)F\b', r'\1', e)
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e = re.sub(r'(\[laneId\])\.[uib]\d+', r'\1', e)
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e = e.replace('+INF', 'INF').replace('-INF', '(-INF)')
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e = re.sub(r'NAN\.f\d+', 'float("nan")', e)
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def convert_verilog_slice(m):
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start, width = m.group(1).strip(), m.group(2).strip()
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return f'[({start}) + ({width}) - 1 : ({start})]'
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e = re.sub(r'\[([^:\[\]]+)\s*\+:\s*([^:\[\]]+)\]', convert_verilog_slice, e)
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def process_brackets(s):
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result, i = [], 0
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while i < len(s):
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if s[i] == '[':
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depth, start = 1, i + 1
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j = start
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while j < len(s) and depth > 0:
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if s[j] == '[': depth += 1
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elif s[j] == ']': depth -= 1
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j += 1
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inner = _expr(s[start:j-1], declared_arrays)
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result.append('[' + inner + ']')
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i = j
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else:
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result.append(s[i])
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i += 1
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return ''.join(result)
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e = process_brackets(e)
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while '?' in e:
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depth, bracket, q = 0, 0, -1
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for i, c in enumerate(e):
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if c == '(': depth += 1
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elif c == ')': depth -= 1
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elif c == '[': bracket += 1
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elif c == ']': bracket -= 1
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elif c == '?' and depth == 0 and bracket == 0: q = i; break
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if q < 0: break
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depth, bracket, col = 0, 0, -1
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for i in range(q + 1, len(e)):
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if e[i] == '(': depth += 1
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elif e[i] == ')': depth -= 1
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elif e[i] == '[': bracket += 1
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elif e[i] == ']': bracket -= 1
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elif e[i] == ':' and depth == 0 and bracket == 0: col = i; break
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if col < 0: break
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cond, t, f = e[:q].strip(), e[q+1:col].strip(), e[col+1:].strip()
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e = f'(({t}) if ({cond}) else ({f}))'
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return e
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# ═══════════════════════════════════════════════════════════════════════════════
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# PDF PARSING WITH PAGE CACHING
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# ═══════════════════════════════════════════════════════════════════════════════
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class CachedPDF:
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"""PDF wrapper with page text/table caching for faster repeated access."""
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def __init__(self, pdf):
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self._pdf, self._text_cache, self._table_cache = pdf, {}, {}
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def __len__(self): return len(self._pdf.pages)
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def text(self, i):
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if i not in self._text_cache: self._text_cache[i] = self._pdf.pages[i].extract_text() or ''
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return self._text_cache[i]
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def tables(self, i):
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if i not in self._table_cache: self._table_cache[i] = [t.extract() for t in self._pdf.pages[i].find_tables()]
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return self._table_cache[i]
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def _parse_bits(s: str) -> tuple[int, int] | None:
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return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None
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def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]:
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fields = []
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for row in table[1:]:
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if not row or not row[0]: continue
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name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip()
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if not (bits := _parse_bits(bits_str)): continue
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enc_val, hi, lo = None, bits[0], bits[1]
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if name == 'ENCODING' and row[2]:
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if m := re.search(r"(?:'b|Must be:\s*)([01_]+)", row[2]):
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enc_bits = m.group(1).replace('_', '')
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enc_val, declared_width, actual_width = int(enc_bits, 2), hi - lo + 1, len(enc_bits)
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if actual_width > declared_width: lo = hi - actual_width + 1
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ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper())
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fields.append((name, hi, lo, enc_val, ftype))
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return fields
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def _parse_single_pdf(url: str):
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"""Parse a single PDF and return (formats, enums, src_enum, doc_name, instructions)."""
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import pdfplumber
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from tinygrad.helpers import fetch
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pdf = CachedPDF(pdfplumber.open(fetch(url)))
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total_pages = len(pdf)
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# Auto-detect document type
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first_page = pdf.text(0)
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is_cdna4, is_cdna3 = 'CDNA4' in first_page or 'CDNA 4' in first_page, 'CDNA3' in first_page or 'MI300' in first_page
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is_cdna, is_rdna4 = is_cdna3 or is_cdna4, 'RDNA4' in first_page or 'RDNA 4' in first_page
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is_rdna35, is_rdna3 = 'RDNA3.5' in first_page or 'RDNA 3.5' in first_page, 'RDNA3' in first_page and 'RDNA3.5' not in first_page
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doc_name = "CDNA4" if is_cdna4 else "CDNA3" if is_cdna3 else "RDNA4" if is_rdna4 else "RDNA3.5" if is_rdna35 else "RDNA3" if is_rdna3 else "Unknown"
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# Find Microcode Formats section (for formats/enums)
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microcode_start = next((i for i in range(int(total_pages * 0.2), total_pages)
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if re.search(r'\d+\.\d+\.\d+\.\s+SOP2\b|Chapter \d+\.\s+Microcode Formats', pdf.text(i))), int(total_pages * 0.9))
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# Find Instructions section (for pseudocode)
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instr_start = next((i for i in range(int(total_pages * 0.1), int(total_pages * 0.5))
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if re.search(r'Chapter \d+\.\s+Instructions\b', pdf.text(i))), total_pages // 3)
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instr_end = next((i for start in [int(total_pages * 0.6), int(total_pages * 0.5), instr_start]
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for i in range(start, min(start + 100, total_pages))
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if re.search(r'Chapter \d+\.\s+Microcode Formats', pdf.text(i))), total_pages)
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# Parse src enum from SSRC encoding table
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src_enum = dict(SRC_EXTRAS)
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for i in range(microcode_start, min(microcode_start + 10, total_pages)):
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text = pdf.text(i)
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if 'SSRC0' in text and 'VCC_LO' in text:
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for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M):
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val, name = int(m.group(1)), m.group(2).rstrip('.:')
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if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name]
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elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name
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break
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# Parse opcode tables
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full_text = '\n'.join(pdf.text(i) for i in range(microcode_start, min(microcode_start + 50, total_pages)))
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enums: dict[str, dict[int, str]] = {}
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for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S):
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if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}:
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enums[m.group(1) + "Op"] = ops
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if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S):
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if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}:
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enums["VOPDOp"] = ops
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enum_names = set(enums.keys())
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# Parse instruction formats
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|
def is_fields_table(t): return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '')
|
|
def has_encoding(fields): return any(f[0] == 'ENCODING' for f in fields)
|
|
def has_header_before_fields(text): return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos]))
|
|
|
|
format_headers = []
|
|
for i in range(50):
|
|
if microcode_start + i >= total_pages: break
|
|
text = pdf.text(microcode_start + i)
|
|
for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start()))
|
|
for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text):
|
|
fmt_name = m.group(1)
|
|
if is_cdna and fmt_name.isupper() and len(fmt_name) >= 2: format_headers.append((fmt_name, i, m.start()))
|
|
elif m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < 50:
|
|
next_text = pdf.text(microcode_start + i + 1).lstrip()
|
|
if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]):
|
|
format_headers.append((fmt_name, i, m.start()))
|
|
|
|
formats: dict[str, list] = {}
|
|
for fmt_name, rel_idx, header_pos in format_headers:
|
|
if fmt_name in formats: continue
|
|
page_idx = microcode_start + rel_idx
|
|
text = pdf.text(page_idx)
|
|
field_pos = text.find('Field Name', header_pos)
|
|
fields = None
|
|
for offset in range(3):
|
|
if page_idx + offset >= total_pages: break
|
|
if offset > 0 and has_header_before_fields(pdf.text(page_idx + offset)): break
|
|
for t in pdf.tables(page_idx + offset) if offset > 0 or field_pos > header_pos else []:
|
|
if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f): fields = f; break
|
|
if fields: break
|
|
if not fields and field_pos > header_pos:
|
|
for t in pdf.tables(page_idx):
|
|
if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)): fields = f; break
|
|
if not fields: continue
|
|
field_names = {f[0] for f in fields}
|
|
for pg_offset in range(1, 3):
|
|
if page_idx + pg_offset >= total_pages or has_header_before_fields(pdf.text(page_idx + pg_offset)): break
|
|
for t in pdf.tables(page_idx + pg_offset):
|
|
if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra):
|
|
for ef in extra:
|
|
if ef[0] not in field_names: fields.append(ef); field_names.add(ef[0])
|
|
break
|
|
formats[fmt_name] = fields
|
|
|
|
# Fix known PDF errors
|
|
if 'SMEM' in formats:
|
|
formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t)
|
|
for n, h, l, e, t in formats['SMEM']]
|
|
if doc_name in ('RDNA3', 'RDNA3.5'):
|
|
if 'SOPPOp' in enums: assert 8 not in enums['SOPPOp']; enums['SOPPOp'][8] = 'S_WAITCNT_DEPCTR'
|
|
if 'DSOp' in enums:
|
|
for k, v in {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'}.items():
|
|
assert k not in enums['DSOp']; enums['DSOp'][k] = v
|
|
if 'FLATOp' in enums:
|
|
for k, v in {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}.items():
|
|
assert k not in enums['FLATOp']; enums['FLATOp'][k] = v
|
|
|
|
# Extract pseudocode for instructions
|
|
all_text = '\n'.join(pdf.text(i) for i in range(instr_start, instr_end))
|
|
matches = list(INST_PATTERN.finditer(all_text))
|
|
raw_pseudocode: dict[tuple[str, int], str] = {}
|
|
for i, match in enumerate(matches):
|
|
name, opcode = match.group(1), int(match.group(2))
|
|
start, end = match.end(), matches[i + 1].start() if i + 1 < len(matches) else match.end() + 2000
|
|
snippet = all_text[start:end].strip()
|
|
if pseudocode := _extract_pseudocode(snippet): raw_pseudocode[(name, opcode)] = pseudocode
|
|
|
|
return {"formats": formats, "enums": enums, "src_enum": src_enum, "doc_name": doc_name, "pseudocode": raw_pseudocode, "is_cdna": is_cdna}
|
|
|
|
def _extract_pseudocode(text: str) -> str | None:
|
|
"""Extract pseudocode from an instruction description snippet."""
|
|
lines, result, depth, in_lambda = text.split('\n'), [], 0, 0
|
|
for line in lines:
|
|
s = line.strip()
|
|
if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue
|
|
if s.startswith(('Notes', 'Functional examples')): break
|
|
if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue
|
|
if '= lambda(' in s: in_lambda += 1; continue
|
|
if in_lambda > 0:
|
|
if s.endswith(');'): in_lambda -= 1
|
|
continue
|
|
if s.startswith('if '): depth += 1
|
|
elif s.startswith('endif'): depth = max(0, depth - 1)
|
|
if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue
|
|
if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue
|
|
is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =',
|
|
'D0[', 'D1[', 'S0[', 'S1[', 'S2[', 'MEM[', 'RETURN_DATA', 'DATA.', 'DATA0', 'DATA1', 'ADDR']) or
|
|
s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or
|
|
re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s))
|
|
if is_code: result.append(s)
|
|
return '\n'.join(result) if result else None
|
|
|
|
def _merge_results(results: list[dict]) -> dict:
|
|
"""Merge multiple PDF parse results into a superset."""
|
|
merged = {"formats": {}, "enums": {}, "src_enum": dict(SRC_EXTRAS), "doc_names": [], "pseudocode": {}, "is_cdna": False}
|
|
for r in results:
|
|
merged["doc_names"].append(r["doc_name"])
|
|
merged["is_cdna"] = merged["is_cdna"] or r["is_cdna"]
|
|
for val, name in r["src_enum"].items():
|
|
if val in merged["src_enum"]: assert merged["src_enum"][val] == name
|
|
else: merged["src_enum"][val] = name
|
|
for enum_name, ops in r["enums"].items():
|
|
if enum_name not in merged["enums"]: merged["enums"][enum_name] = {}
|
|
for val, name in ops.items():
|
|
if val in merged["enums"][enum_name]: assert merged["enums"][enum_name][val] == name
|
|
else: merged["enums"][enum_name][val] = name
|
|
for fmt_name, fields in r["formats"].items():
|
|
if fmt_name not in merged["formats"]: merged["formats"][fmt_name] = list(fields)
|
|
else:
|
|
existing = {f[0]: (f[1], f[2]) for f in merged["formats"][fmt_name]}
|
|
for f in fields:
|
|
if f[0] in existing: assert existing[f[0]] == (f[1], f[2])
|
|
else: merged["formats"][fmt_name].append(f)
|
|
for key, pc in r["pseudocode"].items():
|
|
if key not in merged["pseudocode"]: merged["pseudocode"][key] = pc
|
|
return merged
|
|
|
|
# ═══════════════════════════════════════════════════════════════════════════════
|
|
# CODE GENERATION
|
|
# ═══════════════════════════════════════════════════════════════════════════════
|
|
|
|
def _generate_enum_py(enums, src_enum, doc_name) -> str:
|
|
"""Generate enum.py content (just enums, no dsl.py dependency)."""
|
|
def enum_lines(name, items): return [f"class {name}(IntEnum):"] + [f" {n} = {v}" for v, n in sorted(items.items())] + [""]
|
|
lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit", "from enum import IntEnum", ""]
|
|
lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], [])
|
|
return '\n'.join(lines)
|
|
|
|
def _generate_ins_py(formats, enums, src_enum, doc_name) -> str:
|
|
"""Generate ins.py content (instruction formats and helpers, imports dsl.py and enum.py)."""
|
|
def field_key(f, order): return order.index(f[0].lower()) if f[0].lower() in order else 1000
|
|
lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit",
|
|
"# ruff: noqa: F401,F403", "from typing import Annotated",
|
|
"from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField",
|
|
"from extra.assembly.amd.autogen.{arch}.enum import *",
|
|
"import functools", ""]
|
|
format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}}
|
|
lines.append("# instruction formats")
|
|
for fmt_name, fields in sorted(formats.items()):
|
|
base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32"
|
|
order = FIELD_ORDER.get(fmt_name, [])
|
|
lines.append(f"class {fmt_name}({base}):")
|
|
if enc := next((f for f in fields if f[0] == 'ENCODING'), None):
|
|
lines.append(f" encoding = bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f" encoding = bits[{enc[1]}] == {enc[3]}")
|
|
if defaults := format_defaults.get(fmt_name): lines.append(f" _defaults = {defaults}")
|
|
for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=lambda f: field_key(f, order)):
|
|
ann = f":Annotated[BitField, {ftype}]" if ftype and ftype.endswith('Op') else f":{ftype}" if ftype else ""
|
|
lines.append(f" {name.lower()}{ann} = bits[{hi}]" if hi == lo else f" {name.lower()}{ann} = bits[{hi}:{lo}]")
|
|
lines.append("")
|
|
lines.append("# instruction helpers")
|
|
for cls_name, ops in sorted(enums.items()):
|
|
fmt = cls_name[:-2]
|
|
for op_val, name in sorted(ops.items()):
|
|
seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt, "")
|
|
tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}")
|
|
if fmt in formats or fmt in ("GLOBAL", "SCRATCH"):
|
|
suffix = "_e32" if fmt in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt == "VOP3" and op_val < 512 else ""
|
|
if name in ('V_FMAMK_F32', 'V_FMAMK_F16'):
|
|
lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
|
|
elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'):
|
|
lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
|
|
else: lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})")
|
|
src_names = {name for _, name in src_enum.items()}
|
|
lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in {'DPP8', 'DPP16'}]
|
|
if "NULL" in src_names: lines.append("OFF = NULL\n")
|
|
return '\n'.join(lines)
|
|
|
|
def _generate_gen_pcode_py(enums, pseudocode, arch) -> str:
|
|
"""Generate gen_pcode.py content (compiled pseudocode functions)."""
|
|
# Get op enums for this arch (import from .ins which re-exports from .enum)
|
|
import importlib
|
|
autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}.ins")
|
|
OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp', 'DSOp'] if hasattr(autogen, name)]
|
|
|
|
# Build defined ops mapping
|
|
defined_ops: dict[tuple, list] = {}
|
|
for enum_cls in OP_ENUMS:
|
|
for op in enum_cls:
|
|
if op.name.startswith(('S_', 'V_', 'DS_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op))
|
|
|
|
enum_names = [e.__name__ for e in OP_ENUMS]
|
|
lines = [f'''# autogenerated by pdf.py - do not edit
|
|
# to regenerate: python -m extra.assembly.amd.pdf --arch {arch}
|
|
# ruff: noqa: E501,F405,F403
|
|
# mypy: ignore-errors
|
|
from extra.assembly.amd.autogen.{arch}.enum import {", ".join(enum_names)}
|
|
from extra.assembly.amd.pcode import *
|
|
''']
|
|
|
|
instructions: dict = {cls: {} for cls in OP_ENUMS}
|
|
for key, pc in pseudocode.items():
|
|
if key in defined_ops:
|
|
for enum_cls, enum_val in defined_ops[key]: instructions[enum_cls][enum_val] = pc
|
|
|
|
for enum_cls in OP_ENUMS:
|
|
cls_name = enum_cls.__name__
|
|
if not instructions.get(enum_cls): continue
|
|
fn_entries = []
|
|
for op, pc in instructions[enum_cls].items():
|
|
if any(p in pc for p in UNSUPPORTED): continue
|
|
try:
|
|
code = compile_pseudocode(pc)
|
|
code = _apply_pseudocode_fixes(op, code)
|
|
fn_name, fn_code = _generate_function(cls_name, op, pc, code)
|
|
lines.append(fn_code)
|
|
fn_entries.append((op, fn_name))
|
|
except Exception as e: print(f" Warning: Failed to compile {op.name}: {e}")
|
|
if fn_entries:
|
|
lines.append(f'{cls_name}_FUNCTIONS = {{')
|
|
for op, fn_name in fn_entries: lines.append(f" {cls_name}.{op.name}: {fn_name},")
|
|
lines.append('}\n')
|
|
|
|
# Add V_WRITELANE_B32 if VOP3Op exists
|
|
if 'VOP3Op' in enum_names:
|
|
lines.append('''
|
|
# V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode)
|
|
def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0):
|
|
wr_lane = s1 & 0x1f
|
|
return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)}
|
|
VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32
|
|
''')
|
|
|
|
lines.append('COMPILED_FUNCTIONS = {')
|
|
for enum_cls in OP_ENUMS:
|
|
if instructions.get(enum_cls): lines.append(f' {enum_cls.__name__}: {enum_cls.__name__}_FUNCTIONS,')
|
|
lines.append('}\n\ndef get_compiled_functions(): return COMPILED_FUNCTIONS')
|
|
return '\n'.join(lines)
|
|
|
|
def _apply_pseudocode_fixes(op, code: str) -> str:
|
|
"""Apply known fixes for PDF pseudocode bugs."""
|
|
if op.name == 'V_DIV_FMAS_F32':
|
|
code = code.replace('D0.f32 = 2.0 ** 32 * fma(S0.f32, S1.f32, S2.f32)',
|
|
'D0.f32 = (2.0 ** 64 if exponent(S2.f32) > 127 else 2.0 ** -64) * fma(S0.f32, S1.f32, S2.f32)')
|
|
if op.name == 'V_DIV_FMAS_F64':
|
|
code = code.replace('D0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)',
|
|
'D0.f64 = (2.0 ** 128 if exponent(S2.f64) > 1023 else 2.0 ** -128) * fma(S0.f64, S1.f64, S2.f64)')
|
|
if op.name == 'V_DIV_SCALE_F32':
|
|
code = code.replace('D0.f32 = float("nan")', 'VCC = Reg(0x1); D0.f32 = float("nan")')
|
|
code = code.replace('elif S1.f32 == DENORM.f32:\n D0.f32 = ldexp(S0.f32, 64)', 'elif False:\n pass')
|
|
code += '\nif S1.f32 == DENORM.f32:\n D0.f32 = float("nan")'
|
|
code = code.replace('elif exponent(S2.f32) <= 23:\n D0.f32 = ldexp(S0.f32, 64)', 'elif exponent(S2.f32) <= 23:\n VCC = Reg(0x1); D0.f32 = ldexp(S0.f32, 64)')
|
|
code = code.replace('elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)\n if S0.f32 == S2.f32:\n D0.f32 = ldexp(S0.f32, 64)', 'elif S2.f32 / S1.f32 == DENORM.f32:\n VCC = Reg(0x1)')
|
|
if op.name == 'V_DIV_SCALE_F64':
|
|
code = code.replace('D0.f64 = float("nan")', 'VCC = Reg(0x1); D0.f64 = float("nan")')
|
|
code = code.replace('elif S1.f64 == DENORM.f64:\n D0.f64 = ldexp(S0.f64, 128)', 'elif False:\n pass')
|
|
code += '\nif S1.f64 == DENORM.f64:\n D0.f64 = float("nan")'
|
|
code = code.replace('elif exponent(S2.f64) <= 52:\n D0.f64 = ldexp(S0.f64, 128)', 'elif exponent(S2.f64) <= 52:\n VCC = Reg(0x1); D0.f64 = ldexp(S0.f64, 128)')
|
|
code = code.replace('elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)\n if S0.f64 == S2.f64:\n D0.f64 = ldexp(S0.f64, 128)', 'elif S2.f64 / S1.f64 == DENORM.f64:\n VCC = Reg(0x1)')
|
|
if op.name == 'V_DIV_FIXUP_F32':
|
|
code = code.replace('D0.f32 = ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))',
|
|
'D0.f32 = ((-OVERFLOW_F32) if (sign_out) else (OVERFLOW_F32)) if isNAN(S0.f32) else ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))')
|
|
if op.name == 'V_DIV_FIXUP_F64':
|
|
code = code.replace('D0.f64 = ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))',
|
|
'D0.f64 = ((-OVERFLOW_F64) if (sign_out) else (OVERFLOW_F64)) if isNAN(S0.f64) else ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))')
|
|
if op.name == 'V_TRIG_PREOP_F64':
|
|
code = code.replace('result = F((TWO_OVER_PI_1201[1200 : 0] << shift.u32) & 0x1fffffffffffff)',
|
|
'result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff)')
|
|
return code
|
|
|
|
def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]:
|
|
"""Generate a single compiled pseudocode function."""
|
|
has_d1 = '{ D1' in pc
|
|
is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc
|
|
is_div_scale = 'DIV_SCALE' in op.name
|
|
has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale)
|
|
has_opsel = 'OPSEL' in pc # FMA_MIX and similar instructions need OPSEL/OPSEL_HI
|
|
combined = code + pc
|
|
|
|
fn_name = f"_{cls_name}_{op.name}"
|
|
# Function accepts Reg objects directly (uppercase names), laneId is passed directly as int
|
|
params = "S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None"
|
|
if has_opsel: params += ", OPSEL=0, OPSEL_HI=0"
|
|
lines = [f"def {fn_name}({params}):"]
|
|
|
|
# Registers that need special handling (not passed directly)
|
|
# Only init if used but not first assigned as `name = Reg(...)` in the compiled code
|
|
def needs_init(name): return name in combined and not re.search(rf'^\s*{name}\s*=\s*Reg\(', code, re.MULTILINE)
|
|
special_regs = [('D1', 'Reg(0)'), ('SIMM16', 'Reg(literal)'), ('SIMM32', 'Reg(literal)'),
|
|
('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)')]
|
|
if needs_init('tmp'): special_regs.insert(0, ('tmp', 'Reg(0)'))
|
|
if needs_init('saveexec'): special_regs.insert(0, ('saveexec', 'Reg(EXEC._val)'))
|
|
used = {name for name, _ in special_regs if name in combined}
|
|
|
|
# Detect which registers are modified (not just read) - look for assignments
|
|
modifies_d0 = is_div_scale or bool(re.search(r'\bD0\b[.\[]', combined))
|
|
modifies_exec = is_cmpx or bool(re.search(r'EXEC\.(u32|u64|b32|b64)\s*=', combined))
|
|
modifies_vcc = has_sdst or bool(re.search(r'VCC\.(u32|u64|b32|b64)\s*=|VCC\.u64\[laneId\]\s*=', combined))
|
|
modifies_scc = bool(re.search(r'\bSCC\s*=', combined))
|
|
modifies_pc = bool(re.search(r'\bPC\s*=', combined))
|
|
|
|
# Build init code for special registers
|
|
init_lines = []
|
|
if is_div_scale: init_lines.append(" D0 = Reg(S0._val)")
|
|
for name, init in special_regs:
|
|
if name in used: init_lines.append(f" {name} = {init}")
|
|
if 'EXEC_LO' in code: init_lines.append(" EXEC_LO = SliceProxy(EXEC, 31, 0)")
|
|
if 'EXEC_HI' in code: init_lines.append(" EXEC_HI = SliceProxy(EXEC, 63, 32)")
|
|
if 'VCCZ' in code and not re.search(r'^\s*VCCZ\s*=', code, re.MULTILINE): init_lines.append(" VCCZ = Reg(1 if VCC._val == 0 else 0)")
|
|
if 'EXECZ' in code and not re.search(r'^\s*EXECZ\s*=', code, re.MULTILINE): init_lines.append(" EXECZ = Reg(1 if EXEC._val == 0 else 0)")
|
|
code_lines = [line for line in code.split('\n') if line.strip()]
|
|
if init_lines:
|
|
lines.extend(init_lines)
|
|
if code_lines: lines.append(" # --- compiled pseudocode ---")
|
|
for line in code_lines:
|
|
lines.append(f" {line}")
|
|
|
|
# Build result dict - only include registers that are modified
|
|
result_items = []
|
|
if modifies_d0: result_items.append("'D0': D0")
|
|
if modifies_scc: result_items.append("'SCC': SCC")
|
|
if modifies_vcc: result_items.append("'VCC': VCC")
|
|
if modifies_exec: result_items.append("'EXEC': EXEC")
|
|
if has_d1: result_items.append("'D1': D1")
|
|
if modifies_pc: result_items.append("'PC': PC")
|
|
lines.append(f" return {{{', '.join(result_items)}}}\n")
|
|
return fn_name, '\n'.join(lines)
|
|
|
|
# ═══════════════════════════════════════════════════════════════════════════════
|
|
# MAIN GENERATION
|
|
# ═══════════════════════════════════════════════════════════════════════════════
|
|
|
|
def generate_arch(arch: str) -> dict:
|
|
"""Generate enum.py, ins.py and gen_pcode.py for a single architecture."""
|
|
urls = PDF_URLS[arch]
|
|
if isinstance(urls, str): urls = [urls]
|
|
|
|
print(f"\n{'='*60}\nGenerating {arch}...")
|
|
print(f"Parsing {len(urls)} PDF(s)...")
|
|
results = [_parse_single_pdf(url) for url in urls]
|
|
merged = _merge_results(results) if len(results) > 1 else results[0]
|
|
doc_name = "+".join(merged["doc_names"]) if len(results) > 1 else merged["doc_name"]
|
|
|
|
base_path = Path(f"extra/assembly/amd/autogen/{arch}")
|
|
base_path.mkdir(parents=True, exist_ok=True)
|
|
(base_path / "__init__.py").touch()
|
|
|
|
# Write enum.py (enums only, no dsl.py dependency)
|
|
enum_path = base_path / "enum.py"
|
|
enum_content = _generate_enum_py(merged["enums"], merged["src_enum"], doc_name)
|
|
enum_path.write_text(enum_content)
|
|
print(f"Generated {enum_path}: SrcEnum ({len(merged['src_enum'])}) + {len(merged['enums'])} enums")
|
|
|
|
# Write ins.py (instruction formats and helpers, imports dsl.py and enum.py)
|
|
ins_path = base_path / "ins.py"
|
|
ins_content = _generate_ins_py(merged["formats"], merged["enums"], merged["src_enum"], doc_name).replace("{arch}", arch)
|
|
ins_path.write_text(ins_content)
|
|
print(f"Generated {ins_path}: {len(merged['formats'])} formats")
|
|
|
|
# Write gen_pcode.py (needs enum.py to exist first for imports)
|
|
pcode_path = base_path / "gen_pcode.py"
|
|
pcode_content = _generate_gen_pcode_py(merged["enums"], merged["pseudocode"], arch)
|
|
pcode_path.write_text(pcode_content)
|
|
print(f"Generated {pcode_path}: {len(merged['pseudocode'])} instructions")
|
|
|
|
return merged
|
|
|
|
def _generate_arch_wrapper(arch: str):
|
|
"""Wrapper for multiprocessing - returns arch name for ordering."""
|
|
generate_arch(arch)
|
|
return arch
|
|
|
|
def generate_all():
|
|
"""Generate all architectures in parallel."""
|
|
with ProcessPoolExecutor() as executor:
|
|
list(executor.map(_generate_arch_wrapper, PDF_URLS.keys()))
|
|
|
|
if __name__ == "__main__":
|
|
import argparse
|
|
parser = argparse.ArgumentParser(description="Generate AMD ISA autogen files from PDF documentation")
|
|
parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3")
|
|
args = parser.parse_args()
|
|
if args.arch == "all": generate_all()
|
|
else: generate_arch(args.arch)
|