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GP-6007: Updated NDS32 analyzer and elf relocation handler and test

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fixups
This commit is contained in:
ghidorahrex
2025-09-22 14:37:16 +00:00
parent fa7c3b1fec
commit 71cd33572c
21 changed files with 671 additions and 842 deletions
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8
Ghidra/Extensions/SleighDevTools/pcodetest/c_src/misc_BODY.c
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@@ -16,6 +16,14 @@
#include "pcode_test.h"
#include "big_struct.h"
#ifdef HAS_LIBC
#include <string.h>
#else
void *memset(void *b, int c, size_t len);
void *memcpy(void *dst, const void *src, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
#endif
static i4 int_expectedValue;
static i4 int_actualValue;

12
Ghidra/Extensions/SleighDevTools/pcodetest/defaults.py
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@@ -47,12 +47,14 @@ pcodeTestDefaults.has_vector = 0
pcodeTestDefaults.small_build = 0
pcodeTestDefaults.ld_library_path = ''
pcodeTestDefaults.toolchain_type = 'gcc'
pcodeTestDefaults.compile_exe = 'bin/gcc'
pcodeTestDefaults.objdump_exe = 'bin/objdump'
pcodeTestDefaults.compile_exe = 'gcc'
pcodeTestDefaults.objdump_exe = 'objdump'
pcodeTestDefaults.objdump_option = ''
pcodeTestDefaults.readelf_exe = 'bin/readelf'
pcodeTestDefaults.nm_exe = 'bin/nm'
pcodeTestDefaults.strip_exe = 'bin/strip'
pcodeTestDefaults.readelf_exe = 'readelf'
pcodeTestDefaults.exec_dir = 'bin/'
pcodeTestDefaults.exec_prefix = ''
pcodeTestDefaults.nm_exe = 'nm'
pcodeTestDefaults.strip_exe = 'strip'
pcodeTestDefaults.variants = {'O0': '-O0', 'O3': '-O3'}
pcodeTestDefaults.proc_test = ''
pcodeTestDefaults.force = False

15
Ghidra/Extensions/SleighDevTools/pcodetest/pcode_defs.py
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@@ -436,7 +436,7 @@ PCodeTest({
'name': 'NDS32BE',
'build_all': 1,
'toolchain': 'NDS32/nds32be-elf',
'ccflags': '',
'ccflags': '-mbig-endian',
'cclibs': '-lgcc',
'language_id': 'NDS32:BE:32:default',
})
@@ -444,9 +444,20 @@ PCodeTest({
PCodeTest({
'name': 'NDS32LE',
'build_all': 1,
'toolchain': 'NDS32/nds32le-elf',
'toolchain': 'NDS32/nds32le-elf',#'NDS32/nds32le-linux-glibc-v5d',
'ccflags': '-mlittle-endian -EL',
'cclibs': '-lgcc',
'language_id': 'NDS32:LE:32:default',
})
PCodeTest({
'name': 'NDS32AS',
'build_all': 1,
'toolchain': 'NDS32/nds32le-elf-mculib-v3s',
'exec_prefix': 'nds32le-elf-',
'ccflags': '',
'cclibs': '-lgcc',
'gcc_version': '12.2.0',
'language_id': 'NDS32:LE:32:default',
})

9
Ghidra/Extensions/SleighDevTools/pcodetest/pcodetest.py
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@@ -88,7 +88,13 @@ class PCodeTestBuild(BuildUtil):
def main(self):
# make sure compiler exists and runnable
self.config.compile_exe = self.config.exec_dir + self.config.exec_prefix + self.config.compile_exe
self.config.build_exe = self.config.exec_dir + str(self.config.exec_prefix) + str(self.config.build_exe)
self.config.strip_exe = self.config.exec_dir + str(self.config.exec_prefix) + str(self.config.strip_exe)
self.config.objdump_exe = self.config.exec_dir + str(self.config.exec_prefix) + str(self.config.objdump_exe)
self.config.readelf_exe = self.config.exec_dir + str(self.config.exec_prefix) + str(self.config.readelf_exe)
self.config.nm_exe = self.config.exec_dir + str(self.config.exec_prefix) + str(self.config.nm_exe)
if not self.is_executable_file(self.which('compile_exe')):
self.log_err(self.config.format('build the Toolchain before compilation'))
return
@@ -427,6 +433,7 @@ class PCodeBuildGCC(PCodeTestBuild):
self.set_library_path(self.config.ld_library_path)
# Construct the compile/link command line and execute it
cmp = self.which('compile_exe')
cmd = [cmp] + input_files + self.cflags(output_file) + [opt_cflag, '-B', self.dirname(cmp), '-o', output_file]
out, err = self.run(cmd)

15
Ghidra/Processors/NDS32/build.gradle
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@@ -1,3 +1,18 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"

13
Ghidra/Processors/NDS32/certification.manifest Normal file
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@@ -0,0 +1,13 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
data/languages/lsmw.sinc||GHIDRA||||END|
data/languages/nds32.cspec||GHIDRA||||END|
data/languages/nds32.dwarf||GHIDRA||||END|
data/languages/nds32.ldefs||GHIDRA||||END|
data/languages/nds32.opinion||GHIDRA||||END|
data/languages/nds32.pspec||GHIDRA||||END|
data/languages/nds32.sinc||GHIDRA||||END|
data/languages/nds32be.slaspec||GHIDRA||||END|
data/languages/nds32le.slaspec||GHIDRA||||END|
data/patterns/nds32_patterns.xml||GHIDRA||||END|
data/patterns/patternconstraints.xml||GHIDRA||||END|

50
Ghidra/Processors/NDS32/data/buildLanguage.xml
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@@ -1,50 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
+ Compile sleigh languages within this module.
+ Sleigh compiler options are read from the sleighArgs.txt file.
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
-->
<project name="privateBuildDeveloper" default="sleighCompile">
<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
<import file="../.antProperties.xml" optional="false" />
<target name="sleighCompile">
<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>
<path id="sleigh.class.path">
<fileset dir="${framework.path}/SoftwareModeling/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Generic/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Utility/lib">
<include name="*.jar"/>
</fileset>
</path>
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
<fail unless="sleigh.compile.exists" />
<java classname="${sleigh.compile.class}"
classpathref="sleigh.class.path"
fork="true"
failonerror="true">
<jvmarg value="-Xmx2048M"/>
<arg value="-i"/>
<arg value="sleighArgs.txt"/>
<arg value="-a"/>
<arg value="./languages"/>
</java>
</target>
</project>

687
Ghidra/Processors/NDS32/data/languages/lsmw.sinc
View File

@@ -1,576 +1,139 @@
macro Lmwbi(reg) {
reg = *mult_addr;
mult_addr = mult_addr + 4;
}
macro Lmwbd(reg) {
reg = *mult_addr;
mult_addr = mult_addr - 4;
}
macro Lmwai(reg) {
mult_addr = mult_addr + 4;
reg = *mult_addr;
}
macro Lmwad(reg) {
mult_addr = mult_addr - 4;
reg = *mult_addr;
}
macro Smwbi(reg) {
*mult_addr = reg;
mult_addr = mult_addr + 4;
}
macro Smwbd(reg) {
*mult_addr = reg;
mult_addr = mult_addr - 4;
}
macro Smwai(reg) {
mult_addr = mult_addr + 4;
*mult_addr = reg;
}
Dreg: a0 is a0 & regNum=0 { export a0; }
Dreg: a1 is a1 & regNum=1 { export a1; }
Dreg: a2 is a2 & regNum=2 { export a2; }
Dreg: a3 is a3 & regNum=3 { export a3; }
Dreg: a4 is a4 & regNum=4 { export a4; }
Dreg: a5 is a5 & regNum=5 { export a5; }
Dreg: s0 is s0 & regNum=6 { export s0; }
Dreg: s1 is s1 & regNum=7 { export s1; }
Dreg: s2 is s2 & regNum=8 { export s2; }
Dreg: s3 is s3 & regNum=9 { export s3; }
Dreg: s4 is s4 & regNum=10 { export s4; }
Dreg: s5 is s5 & regNum=11 { export s5; }
Dreg: s6 is s6 & regNum=12 { export s6; }
Dreg: s7 is s7 & regNum=13 { export s7; }
Dreg: s8 is s8 & regNum=14 { export s8; }
Dreg: ta is ta & regNum=15 { export ta; }
Dreg: t0 is t0 & regNum=16 { export t0; }
Dreg: t1 is t1 & regNum=17 { export t1; }
Dreg: t2 is t2 & regNum=18 { export t2; }
Dreg: t3 is t3 & regNum=19 { export t3; }
Dreg: t4 is t4 & regNum=20 { export t4; }
Dreg: t5 is t5 & regNum=21 { export t5; }
Dreg: t6 is t6 & regNum=22 { export t6; }
Dreg: t7 is t7 & regNum=23 { export t7; }
Dreg: t8 is t8 & regNum=24 { export t8; }
Dreg: t9 is t9 & regNum=25 { export t9; }
Dreg: p0 is p0 & regNum=26 { export p0; }
Dreg: p1 is p1 & regNum=27 { export p1; }
Dreg: fp is fp & regNum=28 { export fp; }
Dreg: gp is gp & regNum=29 { export gp; }
Dreg: lp is lp & regNum=30 { export lp; }
Dreg: sp is sp & regNum=31 { export sp; }
macro Smwad(reg) {
mult_addr = mult_addr - 4;
*mult_addr = reg;
}
Lmwbi.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwbi(a0); }
Lmwbi.a0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwbi(a1); }
Lmwbi.a1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwbi(a2); }
Lmwbi.a2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwbi(a3); }
Lmwbi.a3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwbi(a4); }
Lmwbi.a4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwbi(a5); }
Lmwbi.a5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwbi(s0); }
Lmwbi.s0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwbi(s1); }
Lmwbi.s1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwbi(s2); }
Lmwbi.s2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwbi(s3); }
Lmwbi.s3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwbi(s4); }
Lmwbi.s4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwbi(s5); }
Lmwbi.s5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwbi(s6); }
Lmwbi.s6: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwbi(s7); }
Lmwbi.s7: is LsmwRb_ & LsmwRe_ { }
Lmwbi.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwbi(s8); }
Lmwbi.s8: is LsmwRb_ & LsmwRe_ { }
Lmwbi.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwbi(ta); }
Lmwbi.ta: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwbi(t0); }
Lmwbi.t0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwbi(t1); }
Lmwbi.t1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwbi(t2); }
Lmwbi.t2: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwbi(t3); }
Lmwbi.t3: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwbi(t4); }
Lmwbi.t4: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwbi(t5); }
Lmwbi.t5: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwbi(t6); }
Lmwbi.t6: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwbi(t7); }
Lmwbi.t7: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwbi(t8); }
Lmwbi.t8: is LsmwRb_ & LsmwRe_ { }
Lmwbi.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwbi(t9); }
Lmwbi.t9: is LsmwRb_ & LsmwRe_ { }
Lmwbi.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwbi(p0); }
Lmwbi.p0: is LsmwRb_ & LsmwRe_ { }
Lmwbi.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwbi(p1); }
Lmwbi.p1: is LsmwRb_ & LsmwRe_ { }
Lmwbi.fp: fp is Enable4_fp=1 & fp { Lmwbi(fp); }
Lmwbi.fp: is Enable4_fp=0 { }
Lmwbi.gp: gp is Enable4_gp=1 & gp { Lmwbi(gp); }
Lmwbi.gp: is Enable4_gp=0 { }
Lmwbi.lp: lp is Enable4_lp=1 & lp { Lmwbi(lp); }
Lmwbi.lp: is Enable4_lp=0 { }
Lmwbi.sp: sp is Enable4_sp=1 & sp { Lmwbi(sp); }
Lmwbi.sp: is Enable4_sp=0 { }
macro LmwOp(reg) {
reg = *mult_addr;
}
Lmwbd.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwbd(a0); }
Lmwbd.a0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwbd(a1); }
Lmwbd.a1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwbd(a2); }
Lmwbd.a2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwbd(a3); }
Lmwbd.a3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwbd(a4); }
Lmwbd.a4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwbd(a5); }
Lmwbd.a5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwbd(s0); }
Lmwbd.s0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwbd(s1); }
Lmwbd.s1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwbd(s2); }
Lmwbd.s2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwbd(s3); }
Lmwbd.s3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwbd(s4); }
Lmwbd.s4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwbd(s5); }
Lmwbd.s5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwbd(s6); }
Lmwbd.s6: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwbd(s7); }
Lmwbd.s7: is LsmwRb_ & LsmwRe_ { }
Lmwbd.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwbd(s8); }
Lmwbd.s8: is LsmwRb_ & LsmwRe_ { }
Lmwbd.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwbd(ta); }
Lmwbd.ta: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwbd(t0); }
Lmwbd.t0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwbd(t1); }
Lmwbd.t1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwbd(t2); }
Lmwbd.t2: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwbd(t3); }
Lmwbd.t3: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwbd(t4); }
Lmwbd.t4: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwbd(t5); }
Lmwbd.t5: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwbd(t6); }
Lmwbd.t6: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwbd(t7); }
Lmwbd.t7: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwbd(t8); }
Lmwbd.t8: is LsmwRb_ & LsmwRe_ { }
Lmwbd.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwbd(t9); }
Lmwbd.t9: is LsmwRb_ & LsmwRe_ { }
Lmwbd.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwbd(p0); }
Lmwbd.p0: is LsmwRb_ & LsmwRe_ { }
Lmwbd.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwbd(p1); }
Lmwbd.p1: is LsmwRb_ & LsmwRe_ { }
Lmwbd.fp: fp is Enable4_fp=1 & fp { Lmwbd(fp); }
Lmwbd.fp: is Enable4_fp=0 { }
Lmwbd.gp: gp is Enable4_gp=1 & gp { Lmwbd(gp); }
Lmwbd.gp: is Enable4_gp=0 { }
Lmwbd.lp: lp is Enable4_lp=1 & lp { Lmwbd(lp); }
Lmwbd.lp: is Enable4_lp=0 { }
Lmwbd.sp: sp is Enable4_sp=1 & sp { Lmwbd(sp); }
Lmwbd.sp: is Enable4_sp=0 { }
macro SmwOp(reg) {
*mult_addr = reg;
}
Lmwai.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwai(a0); }
Lmwai.a0: is LsmwRb_ & LsmwRe_ { }
Lmwai.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwai(a1); }
Lmwai.a1: is LsmwRb_ & LsmwRe_ { }
Lmwai.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwai(a2); }
Lmwai.a2: is LsmwRb_ & LsmwRe_ { }
Lmwai.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwai(a3); }
Lmwai.a3: is LsmwRb_ & LsmwRe_ { }
Lmwai.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwai(a4); }
Lmwai.a4: is LsmwRb_ & LsmwRe_ { }
Lmwai.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwai(a5); }
Lmwai.a5: is LsmwRb_ & LsmwRe_ { }
Lmwai.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwai(s0); }
Lmwai.s0: is LsmwRb_ & LsmwRe_ { }
Lmwai.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwai(s1); }
Lmwai.s1: is LsmwRb_ & LsmwRe_ { }
Lmwai.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwai(s2); }
Lmwai.s2: is LsmwRb_ & LsmwRe_ { }
Lmwai.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwai(s3); }
Lmwai.s3: is LsmwRb_ & LsmwRe_ { }
Lmwai.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwai(s4); }
Lmwai.s4: is LsmwRb_ & LsmwRe_ { }
Lmwai.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwai(s5); }
Lmwai.s5: is LsmwRb_ & LsmwRe_ { }
Lmwai.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwai(s6); }
Lmwai.s6: is LsmwRb_ & LsmwRe_ { }
Lmwai.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwai(s7); }
Lmwai.s7: is LsmwRb_ & LsmwRe_ { }
Lmwai.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwai(s8); }
Lmwai.s8: is LsmwRb_ & LsmwRe_ { }
Lmwai.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwai(ta); }
Lmwai.ta: is LsmwRb_ & LsmwRe_ { }
Lmwai.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwai(t0); }
Lmwai.t0: is LsmwRb_ & LsmwRe_ { }
Lmwai.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwai(t1); }
Lmwai.t1: is LsmwRb_ & LsmwRe_ { }
Lmwai.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwai(t2); }
Lmwai.t2: is LsmwRb_ & LsmwRe_ { }
Lmwai.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwai(t3); }
Lmwai.t3: is LsmwRb_ & LsmwRe_ { }
Lmwai.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwai(t4); }
Lmwai.t4: is LsmwRb_ & LsmwRe_ { }
Lmwai.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwai(t5); }
Lmwai.t5: is LsmwRb_ & LsmwRe_ { }
Lmwai.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwai(t6); }
Lmwai.t6: is LsmwRb_ & LsmwRe_ { }
Lmwai.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwai(t7); }
Lmwai.t7: is LsmwRb_ & LsmwRe_ { }
Lmwai.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwai(t8); }
Lmwai.t8: is LsmwRb_ & LsmwRe_ { }
Lmwai.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwai(t9); }
Lmwai.t9: is LsmwRb_ & LsmwRe_ { }
Lmwai.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwai(p0); }
Lmwai.p0: is LsmwRb_ & LsmwRe_ { }
Lmwai.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwai(p1); }
Lmwai.p1: is LsmwRb_ & LsmwRe_ { }
Lmwai.fp: fp is Enable4_fp=1 & fp { Lmwai(fp); }
Lmwai.fp: is Enable4_fp=0 { }
Lmwai.gp: gp is Enable4_gp=1 & gp { Lmwai(gp); }
Lmwai.gp: is Enable4_gp=0 { }
Lmwai.lp: lp is Enable4_lp=1 & lp { Lmwai(lp); }
Lmwai.lp: is Enable4_lp=0 { }
Lmwai.sp: sp is Enable4_sp=1 & sp { Lmwai(sp); }
Lmwai.sp: is Enable4_sp=0 { }
macro MwDec() { mult_addr = mult_addr - 4; }
macro MwInc() { mult_addr = mult_addr + 4; }
Lmwad.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Lmwad(a0); }
Lmwad.a0: is LsmwRb_ & LsmwRe_ { }
Lmwad.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Lmwad(a1); }
Lmwad.a1: is LsmwRb_ & LsmwRe_ { }
Lmwad.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Lmwad(a2); }
Lmwad.a2: is LsmwRb_ & LsmwRe_ { }
Lmwad.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Lmwad(a3); }
Lmwad.a3: is LsmwRb_ & LsmwRe_ { }
Lmwad.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Lmwad(a4); }
Lmwad.a4: is LsmwRb_ & LsmwRe_ { }
Lmwad.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Lmwad(a5); }
Lmwad.a5: is LsmwRb_ & LsmwRe_ { }
Lmwad.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Lmwad(s0); }
Lmwad.s0: is LsmwRb_ & LsmwRe_ { }
Lmwad.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Lmwad(s1); }
Lmwad.s1: is LsmwRb_ & LsmwRe_ { }
Lmwad.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Lmwad(s2); }
Lmwad.s2: is LsmwRb_ & LsmwRe_ { }
Lmwad.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Lmwad(s3); }
Lmwad.s3: is LsmwRb_ & LsmwRe_ { }
Lmwad.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Lmwad(s4); }
Lmwad.s4: is LsmwRb_ & LsmwRe_ { }
Lmwad.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Lmwad(s5); }
Lmwad.s5: is LsmwRb_ & LsmwRe_ { }
Lmwad.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Lmwad(s6); }
Lmwad.s6: is LsmwRb_ & LsmwRe_ { }
Lmwad.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Lmwad(s7); }
Lmwad.s7: is LsmwRb_ & LsmwRe_ { }
Lmwad.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Lmwad(s8); }
Lmwad.s8: is LsmwRb_ & LsmwRe_ { }
Lmwad.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Lmwad(ta); }
Lmwad.ta: is LsmwRb_ & LsmwRe_ { }
Lmwad.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Lmwad(t0); }
Lmwad.t0: is LsmwRb_ & LsmwRe_ { }
Lmwad.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Lmwad(t1); }
Lmwad.t1: is LsmwRb_ & LsmwRe_ { }
Lmwad.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Lmwad(t2); }
Lmwad.t2: is LsmwRb_ & LsmwRe_ { }
Lmwad.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Lmwad(t3); }
Lmwad.t3: is LsmwRb_ & LsmwRe_ { }
Lmwad.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Lmwad(t4); }
Lmwad.t4: is LsmwRb_ & LsmwRe_ { }
Lmwad.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Lmwad(t5); }
Lmwad.t5: is LsmwRb_ & LsmwRe_ { }
Lmwad.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Lmwad(t6); }
Lmwad.t6: is LsmwRb_ & LsmwRe_ { }
Lmwad.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Lmwad(t7); }
Lmwad.t7: is LsmwRb_ & LsmwRe_ { }
Lmwad.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Lmwad(t8); }
Lmwad.t8: is LsmwRb_ & LsmwRe_ { }
Lmwad.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Lmwad(t9); }
Lmwad.t9: is LsmwRb_ & LsmwRe_ { }
Lmwad.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Lmwad(p0); }
Lmwad.p0: is LsmwRb_ & LsmwRe_ { }
Lmwad.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Lmwad(p1); }
Lmwad.p1: is LsmwRb_ & LsmwRe_ { }
Lmwad.fp: fp is Enable4_fp=1 & fp { Lmwad(fp); }
Lmwad.fp: is Enable4_fp=0 { }
Lmwad.gp: gp is Enable4_gp=1 & gp { Lmwad(gp); }
Lmwad.gp: is Enable4_gp=0 { }
Lmwad.lp: lp is Enable4_lp=1 & lp { Lmwad(lp); }
Lmwad.lp: is Enable4_lp=0 { }
Lmwad.sp: sp is Enable4_sp=1 & sp { Lmwad(sp); }
Lmwad.sp: is Enable4_sp=0 { }
Lsmw_id: is LsmwId=0 { MwInc(); }
Lsmw_id: is LsmwId=1 { MwDec(); }
Smwbi.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwbi(a0); }
Smwbi.a0: is LsmwRb_ & LsmwRe_ { }
Smwbi.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwbi(a1); }
Smwbi.a1: is LsmwRb_ & LsmwRe_ { }
Smwbi.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwbi(a2); }
Smwbi.a2: is LsmwRb_ & LsmwRe_ { }
Smwbi.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwbi(a3); }
Smwbi.a3: is LsmwRb_ & LsmwRe_ { }
Smwbi.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwbi(a4); }
Smwbi.a4: is LsmwRb_ & LsmwRe_ { }
Smwbi.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwbi(a5); }
Smwbi.a5: is LsmwRb_ & LsmwRe_ { }
Smwbi.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwbi(s0); }
Smwbi.s0: is LsmwRb_ & LsmwRe_ { }
Smwbi.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwbi(s1); }
Smwbi.s1: is LsmwRb_ & LsmwRe_ { }
Smwbi.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwbi(s2); }
Smwbi.s2: is LsmwRb_ & LsmwRe_ { }
Smwbi.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwbi(s3); }
Smwbi.s3: is LsmwRb_ & LsmwRe_ { }
Smwbi.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwbi(s4); }
Smwbi.s4: is LsmwRb_ & LsmwRe_ { }
Smwbi.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwbi(s5); }
Smwbi.s5: is LsmwRb_ & LsmwRe_ { }
Smwbi.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwbi(s6); }
Smwbi.s6: is LsmwRb_ & LsmwRe_ { }
Smwbi.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwbi(s7); }
Smwbi.s7: is LsmwRb_ & LsmwRe_ { }
Smwbi.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwbi(s8); }
Smwbi.s8: is LsmwRb_ & LsmwRe_ { }
Smwbi.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwbi(ta); }
Smwbi.ta: is LsmwRb_ & LsmwRe_ { }
Smwbi.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwbi(t0); }
Smwbi.t0: is LsmwRb_ & LsmwRe_ { }
Smwbi.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwbi(t1); }
Smwbi.t1: is LsmwRb_ & LsmwRe_ { }
Smwbi.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwbi(t2); }
Smwbi.t2: is LsmwRb_ & LsmwRe_ { }
Smwbi.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwbi(t3); }
Smwbi.t3: is LsmwRb_ & LsmwRe_ { }
Smwbi.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwbi(t4); }
Smwbi.t4: is LsmwRb_ & LsmwRe_ { }
Smwbi.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwbi(t5); }
Smwbi.t5: is LsmwRb_ & LsmwRe_ { }
Smwbi.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwbi(t6); }
Smwbi.t6: is LsmwRb_ & LsmwRe_ { }
Smwbi.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwbi(t7); }
Smwbi.t7: is LsmwRb_ & LsmwRe_ { }
Smwbi.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwbi(t8); }
Smwbi.t8: is LsmwRb_ & LsmwRe_ { }
Smwbi.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwbi(t9); }
Smwbi.t9: is LsmwRb_ & LsmwRe_ { }
Smwbi.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwbi(p0); }
Smwbi.p0: is LsmwRb_ & LsmwRe_ { }
Smwbi.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwbi(p1); }
Smwbi.p1: is LsmwRb_ & LsmwRe_ { }
Smwbi.fp: fp is Enable4_fp=1 & fp { Smwbi(fp); }
Smwbi.fp: is Enable4_fp=0 { }
Smwbi.gp: gp is Enable4_gp=1 & gp { Smwbi(gp); }
Smwbi.gp: is Enable4_gp=0 { }
Smwbi.lp: lp is Enable4_lp=1 & lp { Smwbi(lp); }
Smwbi.lp: is Enable4_lp=0 { }
Smwbi.sp: sp is Enable4_sp=1 & sp { Smwbi(sp); }
Smwbi.sp: is Enable4_sp=0 { }
Lmw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { LmwOp(fp); build Lsmw_id; }
Lmw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; LmwOp(fp); }
Lmw.fp: is Enable4_fp=0 { }
Lmw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { LmwOp(gp); build Lsmw_id; }
Lmw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; LmwOp(gp); }
Lmw.gp: is Enable4_gp=0 { }
Lmw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { LmwOp(lp); build Lsmw_id; }
Lmw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; LmwOp(lp); }
Lmw.lp: is Enable4_lp=0 { }
Lmw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { LmwOp(sp); build Lsmw_id; }
Lmw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; LmwOp(sp); }
Lmw.sp: is Enable4_sp=0 { }
Smwbd.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwbd(a0); }
Smwbd.a0: is LsmwRb_ & LsmwRe_ { }
Smwbd.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwbd(a1); }
Smwbd.a1: is LsmwRb_ & LsmwRe_ { }
Smwbd.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwbd(a2); }
Smwbd.a2: is LsmwRb_ & LsmwRe_ { }
Smwbd.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwbd(a3); }
Smwbd.a3: is LsmwRb_ & LsmwRe_ { }
Smwbd.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwbd(a4); }
Smwbd.a4: is LsmwRb_ & LsmwRe_ { }
Smwbd.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwbd(a5); }
Smwbd.a5: is LsmwRb_ & LsmwRe_ { }
Smwbd.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwbd(s0); }
Smwbd.s0: is LsmwRb_ & LsmwRe_ { }
Smwbd.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwbd(s1); }
Smwbd.s1: is LsmwRb_ & LsmwRe_ { }
Smwbd.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwbd(s2); }
Smwbd.s2: is LsmwRb_ & LsmwRe_ { }
Smwbd.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwbd(s3); }
Smwbd.s3: is LsmwRb_ & LsmwRe_ { }
Smwbd.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwbd(s4); }
Smwbd.s4: is LsmwRb_ & LsmwRe_ { }
Smwbd.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwbd(s5); }
Smwbd.s5: is LsmwRb_ & LsmwRe_ { }
Smwbd.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwbd(s6); }
Smwbd.s6: is LsmwRb_ & LsmwRe_ { }
Smwbd.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwbd(s7); }
Smwbd.s7: is LsmwRb_ & LsmwRe_ { }
Smwbd.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwbd(s8); }
Smwbd.s8: is LsmwRb_ & LsmwRe_ { }
Smwbd.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwbd(ta); }
Smwbd.ta: is LsmwRb_ & LsmwRe_ { }
Smwbd.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwbd(t0); }
Smwbd.t0: is LsmwRb_ & LsmwRe_ { }
Smwbd.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwbd(t1); }
Smwbd.t1: is LsmwRb_ & LsmwRe_ { }
Smwbd.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwbd(t2); }
Smwbd.t2: is LsmwRb_ & LsmwRe_ { }
Smwbd.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwbd(t3); }
Smwbd.t3: is LsmwRb_ & LsmwRe_ { }
Smwbd.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwbd(t4); }
Smwbd.t4: is LsmwRb_ & LsmwRe_ { }
Smwbd.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwbd(t5); }
Smwbd.t5: is LsmwRb_ & LsmwRe_ { }
Smwbd.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwbd(t6); }
Smwbd.t6: is LsmwRb_ & LsmwRe_ { }
Smwbd.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwbd(t7); }
Smwbd.t7: is LsmwRb_ & LsmwRe_ { }
Smwbd.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwbd(t8); }
Smwbd.t8: is LsmwRb_ & LsmwRe_ { }
Smwbd.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwbd(t9); }
Smwbd.t9: is LsmwRb_ & LsmwRe_ { }
Smwbd.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwbd(p0); }
Smwbd.p0: is LsmwRb_ & LsmwRe_ { }
Smwbd.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwbd(p1); }
Smwbd.p1: is LsmwRb_ & LsmwRe_ { }
Smwbd.fp: fp is Enable4_fp=1 & fp { Smwbd(fp); }
Smwbd.fp: is Enable4_fp=0 { }
Smwbd.gp: gp is Enable4_gp=1 & gp { Smwbd(gp); }
Smwbd.gp: is Enable4_gp=0 { }
Smwbd.lp: lp is Enable4_lp=1 & lp { Smwbd(lp); }
Smwbd.lp: is Enable4_lp=0 { }
Smwbd.sp: sp is Enable4_sp=1 & sp { Smwbd(sp); }
Smwbd.sp: is Enable4_sp=0 { }
# Terminating condition
LmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; LmwOp(Dreg); MwInc(); }
LmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; LmwOp(Dreg); MwDec(); }
Smwai.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwai(a0); }
Smwai.a0: is LsmwRb_ & LsmwRe_ { }
Smwai.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwai(a1); }
Smwai.a1: is LsmwRb_ & LsmwRe_ { }
Smwai.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwai(a2); }
Smwai.a2: is LsmwRb_ & LsmwRe_ { }
Smwai.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwai(a3); }
Smwai.a3: is LsmwRb_ & LsmwRe_ { }
Smwai.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwai(a4); }
Smwai.a4: is LsmwRb_ & LsmwRe_ { }
Smwai.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwai(a5); }
Smwai.a5: is LsmwRb_ & LsmwRe_ { }
Smwai.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwai(s0); }
Smwai.s0: is LsmwRb_ & LsmwRe_ { }
Smwai.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwai(s1); }
Smwai.s1: is LsmwRb_ & LsmwRe_ { }
Smwai.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwai(s2); }
Smwai.s2: is LsmwRb_ & LsmwRe_ { }
Smwai.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwai(s3); }
Smwai.s3: is LsmwRb_ & LsmwRe_ { }
Smwai.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwai(s4); }
Smwai.s4: is LsmwRb_ & LsmwRe_ { }
Smwai.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwai(s5); }
Smwai.s5: is LsmwRb_ & LsmwRe_ { }
Smwai.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwai(s6); }
Smwai.s6: is LsmwRb_ & LsmwRe_ { }
Smwai.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwai(s7); }
Smwai.s7: is LsmwRb_ & LsmwRe_ { }
Smwai.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwai(s8); }
Smwai.s8: is LsmwRb_ & LsmwRe_ { }
Smwai.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwai(ta); }
Smwai.ta: is LsmwRb_ & LsmwRe_ { }
Smwai.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwai(t0); }
Smwai.t0: is LsmwRb_ & LsmwRe_ { }
Smwai.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwai(t1); }
Smwai.t1: is LsmwRb_ & LsmwRe_ { }
Smwai.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwai(t2); }
Smwai.t2: is LsmwRb_ & LsmwRe_ { }
Smwai.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwai(t3); }
Smwai.t3: is LsmwRb_ & LsmwRe_ { }
Smwai.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwai(t4); }
Smwai.t4: is LsmwRb_ & LsmwRe_ { }
Smwai.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwai(t5); }
Smwai.t5: is LsmwRb_ & LsmwRe_ { }
Smwai.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwai(t6); }
Smwai.t6: is LsmwRb_ & LsmwRe_ { }
Smwai.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwai(t7); }
Smwai.t7: is LsmwRb_ & LsmwRe_ { }
Smwai.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwai(t8); }
Smwai.t8: is LsmwRb_ & LsmwRe_ { }
Smwai.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwai(t9); }
Smwai.t9: is LsmwRb_ & LsmwRe_ { }
Smwai.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwai(p0); }
Smwai.p0: is LsmwRb_ & LsmwRe_ { }
Smwai.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwai(p1); }
Smwai.p1: is LsmwRb_ & LsmwRe_ { }
Smwai.fp: fp is Enable4_fp=1 & fp { Smwai(fp); }
Smwai.fp: is Enable4_fp=0 { }
Smwai.gp: gp is Enable4_gp=1 & gp { Smwai(gp); }
Smwai.gp: is Enable4_gp=0 { }
Smwai.lp: lp is Enable4_lp=1 & lp { Smwai(lp); }
Smwai.lp: is Enable4_lp=0 { }
Smwai.sp: sp is Enable4_sp=1 & sp { Smwai(sp); }
Smwai.sp: is Enable4_sp=0 { }
LmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); LmwOp(Dreg); }
LmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); LmwOp(Dreg); }
Smwad.a0: a0 is LsmwRb_<=0 & LsmwRe_>=0 & a0 { Smwad(a0); }
Smwad.a0: is LsmwRb_ & LsmwRe_ { }
Smwad.a1: a1 is LsmwRb_<=1 & LsmwRe_>=1 & a1 { Smwad(a1); }
Smwad.a1: is LsmwRb_ & LsmwRe_ { }
Smwad.a2: a2 is LsmwRb_<=2 & LsmwRe_>=2 & a2 { Smwad(a2); }
Smwad.a2: is LsmwRb_ & LsmwRe_ { }
Smwad.a3: a3 is LsmwRb_<=3 & LsmwRe_>=3 & a3 { Smwad(a3); }
Smwad.a3: is LsmwRb_ & LsmwRe_ { }
Smwad.a4: a4 is LsmwRb_<=4 & LsmwRe_>=4 & a4 { Smwad(a4); }
Smwad.a4: is LsmwRb_ & LsmwRe_ { }
Smwad.a5: a5 is LsmwRb_<=5 & LsmwRe_>=5 & a5 { Smwad(a5); }
Smwad.a5: is LsmwRb_ & LsmwRe_ { }
Smwad.s0: s0 is LsmwRb_<=6 & LsmwRe_>=6 & s0 { Smwad(s0); }
Smwad.s0: is LsmwRb_ & LsmwRe_ { }
Smwad.s1: s1 is LsmwRb_<=7 & LsmwRe_>=7 & s1 { Smwad(s1); }
Smwad.s1: is LsmwRb_ & LsmwRe_ { }
Smwad.s2: s2 is LsmwRb_<=8 & LsmwRe_>=8 & s2 { Smwad(s2); }
Smwad.s2: is LsmwRb_ & LsmwRe_ { }
Smwad.s3: s3 is LsmwRb_<=9 & LsmwRe_>=9 & s3 { Smwad(s3); }
Smwad.s3: is LsmwRb_ & LsmwRe_ { }
Smwad.s4: s4 is LsmwRb_<=10 & LsmwRe_>=10 & s4 { Smwad(s4); }
Smwad.s4: is LsmwRb_ & LsmwRe_ { }
Smwad.s5: s5 is LsmwRb_<=11 & LsmwRe_>=11 & s5 { Smwad(s5); }
Smwad.s5: is LsmwRb_ & LsmwRe_ { }
Smwad.s6: s6 is LsmwRb_<=12 & LsmwRe_>=12 & s6 { Smwad(s6); }
Smwad.s6: is LsmwRb_ & LsmwRe_ { }
Smwad.s7: s7 is LsmwRb_<=13 & LsmwRe_>=13 & s7 { Smwad(s7); }
Smwad.s7: is LsmwRb_ & LsmwRe_ { }
Smwad.s8: s8 is LsmwRb_<=14 & LsmwRe_>=14 & s8 { Smwad(s8); }
Smwad.s8: is LsmwRb_ & LsmwRe_ { }
Smwad.ta: ta is LsmwRb_<=15 & LsmwRe_>=15 & ta { Smwad(ta); }
Smwad.ta: is LsmwRb_ & LsmwRe_ { }
Smwad.t0: t0 is LsmwRb_<=16 & LsmwRe_>=16 & t0 { Smwad(t0); }
Smwad.t0: is LsmwRb_ & LsmwRe_ { }
Smwad.t1: t1 is LsmwRb_<=17 & LsmwRe_>=17 & t1 { Smwad(t1); }
Smwad.t1: is LsmwRb_ & LsmwRe_ { }
Smwad.t2: t2 is LsmwRb_<=18 & LsmwRe_>=18 & t2 { Smwad(t2); }
Smwad.t2: is LsmwRb_ & LsmwRe_ { }
Smwad.t3: t3 is LsmwRb_<=19 & LsmwRe_>=19 & t3 { Smwad(t3); }
Smwad.t3: is LsmwRb_ & LsmwRe_ { }
Smwad.t4: t4 is LsmwRb_<=20 & LsmwRe_>=20 & t4 { Smwad(t4); }
Smwad.t4: is LsmwRb_ & LsmwRe_ { }
Smwad.t5: t5 is LsmwRb_<=21 & LsmwRe_>=21 & t5 { Smwad(t5); }
Smwad.t5: is LsmwRb_ & LsmwRe_ { }
Smwad.t6: t6 is LsmwRb_<=22 & LsmwRe_>=22 & t6 { Smwad(t6); }
Smwad.t6: is LsmwRb_ & LsmwRe_ { }
Smwad.t7: t7 is LsmwRb_<=23 & LsmwRe_>=23 & t7 { Smwad(t7); }
Smwad.t7: is LsmwRb_ & LsmwRe_ { }
Smwad.t8: t8 is LsmwRb_<=24 & LsmwRe_>=24 & t8 { Smwad(t8); }
Smwad.t8: is LsmwRb_ & LsmwRe_ { }
Smwad.t9: t9 is LsmwRb_<=25 & LsmwRe_>=25 & t9 { Smwad(t9); }
Smwad.t9: is LsmwRb_ & LsmwRe_ { }
Smwad.p0: p0 is LsmwRb_<=26 & LsmwRe_>=26 & p0 { Smwad(p0); }
Smwad.p0: is LsmwRb_ & LsmwRe_ { }
Smwad.p1: p1 is LsmwRb_<=27 & LsmwRe_>=27 & p1 { Smwad(p1); }
Smwad.p1: is LsmwRb_ & LsmwRe_ { }
Smwad.fp: fp is Enable4_fp=1 & fp { Smwad(fp); }
Smwad.fp: is Enable4_fp=0 { }
Smwad.gp: gp is Enable4_gp=1 & gp { Smwad(gp); }
Smwad.gp: is Enable4_gp=0 { }
Smwad.lp: lp is Enable4_lp=1 & lp { Smwad(lp); }
Smwad.lp: is Enable4_lp=0 { }
Smwad.sp: sp is Enable4_sp=1 & sp { Smwad(sp); }
Smwad.sp: is Enable4_sp=0 { }
LmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { LmwOp(Dreg); MwInc(); build LmwReg; }
LmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { LmwOp(Dreg); MwDec(); build LmwReg; }
Lmw.regs: is LsmwBa=0 & LsmwId=0 & Lmwbi.sp & Lmwbi.lp & Lmwbi.gp & Lmwbi.fp & Lmwbi.p1 & Lmwbi.p0 & Lmwbi.t9 & Lmwbi.t8 & Lmwbi.t7 & Lmwbi.t6 & Lmwbi.t5 & Lmwbi.t4 & Lmwbi.t3 & Lmwbi.t2 & Lmwbi.t1 & Lmwbi.t0 & Lmwbi.ta & Lmwbi.s8 & Lmwbi.s7 & Lmwbi.s6 & Lmwbi.s5 & Lmwbi.s4 & Lmwbi.s3 & Lmwbi.s2 & Lmwbi.s1 & Lmwbi.s0 & Lmwbi.a5 & Lmwbi.a4 & Lmwbi.a3 & Lmwbi.a2 & Lmwbi.a1 & Lmwbi.a0 { }
Lmw.regs: is LsmwBa=0 & LsmwId=1 & Lmwbd.a0 & Lmwbd.a1 & Lmwbd.a2 & Lmwbd.a3 & Lmwbd.a4 & Lmwbd.a5 & Lmwbd.s0 & Lmwbd.s1 & Lmwbd.s2 & Lmwbd.s3 & Lmwbd.s4 & Lmwbd.s5 & Lmwbd.s6 & Lmwbd.s7 & Lmwbd.s8 & Lmwbd.ta & Lmwbd.t0 & Lmwbd.t1 & Lmwbd.t2 & Lmwbd.t3 & Lmwbd.t4 & Lmwbd.t5 & Lmwbd.t6 & Lmwbd.t7 & Lmwbd.t8 & Lmwbd.t9 & Lmwbd.p0 & Lmwbd.p1 & Lmwbd.fp & Lmwbd.gp & Lmwbd.lp & Lmwbd.sp { }
Lmw.regs: is LsmwBa=1 & LsmwId=0 & Lmwai.sp & Lmwai.lp & Lmwai.gp & Lmwai.fp & Lmwai.p1 & Lmwai.p0 & Lmwai.t9 & Lmwai.t8 & Lmwai.t7 & Lmwai.t6 & Lmwai.t5 & Lmwai.t4 & Lmwai.t3 & Lmwai.t2 & Lmwai.t1 & Lmwai.t0 & Lmwai.ta & Lmwai.s8 & Lmwai.s7 & Lmwai.s6 & Lmwai.s5 & Lmwai.s4 & Lmwai.s3 & Lmwai.s2 & Lmwai.s1 & Lmwai.s0 & Lmwai.a5 & Lmwai.a4 & Lmwai.a3 & Lmwai.a2 & Lmwai.a1 & Lmwai.a0 { }
Lmw.regs: is LsmwBa=1 & LsmwId=1 & Lmwad.a0 & Lmwad.a1 & Lmwad.a2 & Lmwad.a3 & Lmwad.a4 & Lmwad.a5 & Lmwad.s0 & Lmwad.s1 & Lmwad.s2 & Lmwad.s3 & Lmwad.s4 & Lmwad.s5 & Lmwad.s6 & Lmwad.s7 & Lmwad.s8 & Lmwad.ta & Lmwad.t0 & Lmwad.t1 & Lmwad.t2 & Lmwad.t3 & Lmwad.t4 & Lmwad.t5 & Lmwad.t6 & Lmwad.t7 & Lmwad.t8 & Lmwad.t9 & Lmwad.p0 & Lmwad.p1 & Lmwad.fp & Lmwad.gp & Lmwad.lp & Lmwad.sp { }
Smw.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
Smw.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
Smw.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
Smw.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }
Lmwa.regs: is LsmwBa=0 & LsmwId=0 & Lmwbi.sp & Lmwbi.lp & Lmwbi.gp & Lmwbi.fp & Lmwbi.p1 & Lmwbi.p0 & Lmwbi.t9 & Lmwbi.t8 & Lmwbi.t7 & Lmwbi.t6 & Lmwbi.t5 & Lmwbi.t4 & Lmwbi.t3 & Lmwbi.t2 & Lmwbi.t1 & Lmwbi.t0 & Lmwbi.ta & Lmwbi.s8 & Lmwbi.s7 & Lmwbi.s6 & Lmwbi.s5 & Lmwbi.s4 & Lmwbi.s3 & Lmwbi.s2 & Lmwbi.s1 & Lmwbi.s0 & Lmwbi.a5 & Lmwbi.a4 & Lmwbi.a3 & Lmwbi.a2 & Lmwbi.a1 & Lmwbi.a0 { }
Lmwa.regs: is LsmwBa=0 & LsmwId=1 & Lmwbd.a0 & Lmwbd.a1 & Lmwbd.a2 & Lmwbd.a3 & Lmwbd.a4 & Lmwbd.a5 & Lmwbd.s0 & Lmwbd.s1 & Lmwbd.s2 & Lmwbd.s3 & Lmwbd.s4 & Lmwbd.s5 & Lmwbd.s6 & Lmwbd.s7 & Lmwbd.s8 & Lmwbd.ta & Lmwbd.t0 & Lmwbd.t1 & Lmwbd.t2 & Lmwbd.t3 & Lmwbd.t4 & Lmwbd.t5 & Lmwbd.t6 & Lmwbd.t7 & Lmwbd.t8 & Lmwbd.t9 & Lmwbd.p0 & Lmwbd.p1 & Lmwbd.fp & Lmwbd.gp & Lmwbd.lp & Lmwbd.sp { }
Lmwa.regs: is LsmwBa=1 & LsmwId=0 & Lmwai.sp & Lmwai.lp & Lmwai.gp & Lmwai.fp & Lmwai.p1 & Lmwai.p0 & Lmwai.t9 & Lmwai.t8 & Lmwai.t7 & Lmwai.t6 & Lmwai.t5 & Lmwai.t4 & Lmwai.t3 & Lmwai.t2 & Lmwai.t1 & Lmwai.t0 & Lmwai.ta & Lmwai.s8 & Lmwai.s7 & Lmwai.s6 & Lmwai.s5 & Lmwai.s4 & Lmwai.s3 & Lmwai.s2 & Lmwai.s1 & Lmwai.s0 & Lmwai.a5 & Lmwai.a4 & Lmwai.a3 & Lmwai.a2 & Lmwai.a1 & Lmwai.a0 { }
Lmwa.regs: is LsmwBa=1 & LsmwId=1 & Lmwad.a0 & Lmwad.a1 & Lmwad.a2 & Lmwad.a3 & Lmwad.a4 & Lmwad.a5 & Lmwad.s0 & Lmwad.s1 & Lmwad.s2 & Lmwad.s3 & Lmwad.s4 & Lmwad.s5 & Lmwad.s6 & Lmwad.s7 & Lmwad.s8 & Lmwad.ta & Lmwad.t0 & Lmwad.t1 & Lmwad.t2 & Lmwad.t3 & Lmwad.t4 & Lmwad.t5 & Lmwad.t6 & Lmwad.t7 & Lmwad.t8 & Lmwad.t9 & Lmwad.p0 & Lmwad.p1 & Lmwad.fp & Lmwad.gp & Lmwad.lp & Lmwad.sp { }
Smwa.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
Smwa.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
Smwa.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
Smwa.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }
LmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { MwInc(); LmwOp(Dreg); build LmwReg; }
LmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { MwDec(); LmwOp(Dreg); build LmwReg; }
# Initial conditions
Lmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }
Lmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; build LmwReg; }
Lmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }
Lmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }
Lmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }
Lmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; build LmwReg; }
Lmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; }
Lmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; }
Smw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { SmwOp(fp); build Lsmw_id; }
Smw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; SmwOp(fp); }
Smw.fp: is Enable4_fp=0 { }
Smw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { SmwOp(gp); build Lsmw_id; }
Smw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; SmwOp(gp); }
Smw.gp: is Enable4_gp=0 { }
Smw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { SmwOp(lp); build Lsmw_id; }
Smw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; SmwOp(lp); }
Smw.lp: is Enable4_lp=0 { }
Smw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { SmwOp(sp); build Lsmw_id; }
Smw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; SmwOp(sp); }
Smw.sp: is Enable4_sp=0 { }
# Terminating condition
SmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); }
SmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); }
SmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); }
SmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); }
SmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); build SmwReg; }
SmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); build SmwReg; }
SmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); build SmwReg; }
SmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); build SmwReg; }
# Initial conditions
Smw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }
Smw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; build SmwReg; }
Smw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }
Smw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }
Smwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }
Smwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; build SmwReg; }
Smwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; }
Smwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; }
#Smw.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
#Smw.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
#Smw.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
#Smw.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }
#Lmwa.regs: is LsmwBa=0 & LsmwId & Lmwbi.sp & Lmwbi.lp & Lmwbi.gp & Lmwbi.fp & Lmwbi.p1 & Lmwbi.p0 & Lmwbi.t9 & Lmwbi.t8 & Lmwbi.t7 & Lmwbi.t6 & Lmwbi.t5 & Lmwbi.t4 & Lmwbi.t3 & Lmwbi.t2 & Lmwbi.t1 & Lmwbi.t0 & Lmwbi.ta & Lmwbi.s8 & Lmwbi.s7 & Lmwbi.s6 & Lmwbi.s5 & Lmwbi.s4 & Lmwbi.s3 & Lmwbi.s2 & Lmwbi.s1 & Lmwbi.s0 & Lmwbi.a5 & Lmwbi.a4 & Lmwbi.a3 & Lmwbi.a2 & Lmwbi.a1 & Lmwbi.a0 { }
#Lmwa.regs: is LsmwBa=0 & LsmwId=1 & Lmwbd.a0 & Lmwbd.a1 & Lmwbd.a2 & Lmwbd.a3 & Lmwbd.a4 & Lmwbd.a5 & Lmwbd.s0 & Lmwbd.s1 & Lmwbd.s2 & Lmwbd.s3 & Lmwbd.s4 & Lmwbd.s5 & Lmwbd.s6 & Lmwbd.s7 & Lmwbd.s8 & Lmwbd.ta & Lmwbd.t0 & Lmwbd.t1 & Lmwbd.t2 & Lmwbd.t3 & Lmwbd.t4 & Lmwbd.t5 & Lmwbd.t6 & Lmwbd.t7 & Lmwbd.t8 & Lmwbd.t9 & Lmwbd.p0 & Lmwbd.p1 & Lmwbd.fp & Lmwbd.gp & Lmwbd.lp & Lmwbd.sp { }
#Lmwa.regs: is LsmwBa=1 & LsmwId=0 & Lmwai.sp & Lmwai.lp & Lmwai.gp & Lmwai.fp & Lmwai.p1 & Lmwai.p0 & Lmwai.t9 & Lmwai.t8 & Lmwai.t7 & Lmwai.t6 & Lmwai.t5 & Lmwai.t4 & Lmwai.t3 & Lmwai.t2 & Lmwai.t1 & Lmwai.t0 & Lmwai.ta & Lmwai.s8 & Lmwai.s7 & Lmwai.s6 & Lmwai.s5 & Lmwai.s4 & Lmwai.s3 & Lmwai.s2 & Lmwai.s1 & Lmwai.s0 & Lmwai.a5 & Lmwai.a4 & Lmwai.a3 & Lmwai.a2 & Lmwai.a1 & Lmwai.a0 { }
#Lmwa.regs: is LsmwBa=1 & LsmwId=1 & Lmwad.a0 & Lmwad.a1 & Lmwad.a2 & Lmwad.a3 & Lmwad.a4 & Lmwad.a5 & Lmwad.s0 & Lmwad.s1 & Lmwad.s2 & Lmwad.s3 & Lmwad.s4 & Lmwad.s5 & Lmwad.s6 & Lmwad.s7 & Lmwad.s8 & Lmwad.ta & Lmwad.t0 & Lmwad.t1 & Lmwad.t2 & Lmwad.t3 & Lmwad.t4 & Lmwad.t5 & Lmwad.t6 & Lmwad.t7 & Lmwad.t8 & Lmwad.t9 & Lmwad.p0 & Lmwad.p1 & Lmwad.fp & Lmwad.gp & Lmwad.lp & Lmwad.sp { }
#Smwa.regs: is LsmwBa=0 & LsmwId=0 & Smwbi.sp & Smwbi.lp & Smwbi.gp & Smwbi.fp & Smwbi.p1 & Smwbi.p0 & Smwbi.t9 & Smwbi.t8 & Smwbi.t7 & Smwbi.t6 & Smwbi.t5 & Smwbi.t4 & Smwbi.t3 & Smwbi.t2 & Smwbi.t1 & Smwbi.t0 & Smwbi.ta & Smwbi.s8 & Smwbi.s7 & Smwbi.s6 & Smwbi.s5 & Smwbi.s4 & Smwbi.s3 & Smwbi.s2 & Smwbi.s1 & Smwbi.s0 & Smwbi.a5 & Smwbi.a4 & Smwbi.a3 & Smwbi.a2 & Smwbi.a1 & Smwbi.a0 { }
#Smwa.regs: is LsmwBa=0 & LsmwId=1 & Smwbd.a0 & Smwbd.a1 & Smwbd.a2 & Smwbd.a3 & Smwbd.a4 & Smwbd.a5 & Smwbd.s0 & Smwbd.s1 & Smwbd.s2 & Smwbd.s3 & Smwbd.s4 & Smwbd.s5 & Smwbd.s6 & Smwbd.s7 & Smwbd.s8 & Smwbd.ta & Smwbd.t0 & Smwbd.t1 & Smwbd.t2 & Smwbd.t3 & Smwbd.t4 & Smwbd.t5 & Smwbd.t6 & Smwbd.t7 & Smwbd.t8 & Smwbd.t9 & Smwbd.p0 & Smwbd.p1 & Smwbd.fp & Smwbd.gp & Smwbd.lp & Smwbd.sp { }
#Smwa.regs: is LsmwBa=1 & LsmwId=0 & Smwai.sp & Smwai.lp & Smwai.gp & Smwai.fp & Smwai.p1 & Smwai.p0 & Smwai.t9 & Smwai.t8 & Smwai.t7 & Smwai.t6 & Smwai.t5 & Smwai.t4 & Smwai.t3 & Smwai.t2 & Smwai.t1 & Smwai.t0 & Smwai.ta & Smwai.s8 & Smwai.s7 & Smwai.s6 & Smwai.s5 & Smwai.s4 & Smwai.s3 & Smwai.s2 & Smwai.s1 & Smwai.s0 & Smwai.a5 & Smwai.a4 & Smwai.a3 & Smwai.a2 & Smwai.a1 & Smwai.a0 { }
#Smwa.regs: is LsmwBa=1 & LsmwId=1 & Smwad.a0 & Smwad.a1 & Smwad.a2 & Smwad.a3 & Smwad.a4 & Smwad.a5 & Smwad.s0 & Smwad.s1 & Smwad.s2 & Smwad.s3 & Smwad.s4 & Smwad.s5 & Smwad.s6 & Smwad.s7 & Smwad.s8 & Smwad.ta & Smwad.t0 & Smwad.t1 & Smwad.t2 & Smwad.t3 & Smwad.t4 & Smwad.t5 & Smwad.t6 & Smwad.t7 & Smwad.t8 & Smwad.t9 & Smwad.p0 & Smwad.p1 & Smwad.fp & Smwad.gp & Smwad.lp & Smwad.sp { }

11
Ghidra/Processors/NDS32/data/languages/nds32.cspec
View File

@@ -50,8 +50,17 @@
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="a5"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="a1" piece2="a0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="a3" piece2="a2"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="a5" piece2="a4"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="24" space="stack"/>
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">

190
Ghidra/Processors/NDS32/data/languages/nds32.sinc
View File

@@ -17,7 +17,14 @@ define register offset=0x100 size=8
define register offset=0x100 size=4
[d0.hi d0.lo d1.hi d1.lo];
define register offset=0x1000 size=4
[ itb ];
define register offset=0x1000 size=8 contextreg;
define context contextreg
counter = (22,26)
regNum = (27,31) # register for load/store multiple instructions
;
define token instr32(32)
OpSz = (31, 31)
@@ -31,7 +38,10 @@ define token instr32(32)
Rs = (5, 9)
Sub5 = (0, 4)
Sub6 = (0, 5)
Sub7 = (0, 6)
Sub8 = (0, 7)
Sub3 = (7, 9)
Imm8u = (7,14)
Imm5u = (10, 14)
Imm5s = (10, 14) signed
Br1t = (14, 14)
@@ -295,7 +305,7 @@ AddrRaRbsv: [Ra + OffsetRbsv] is Ra & OffsetRbsv { addr:4 = Ra + OffsetRbsv; exp
### Load / Store Multiple Word Instruction ###
# TODO : this is ugly
@include "lsmw.sinc"
LsmwBa_: "b" is LsmwBa=0 { }
@@ -308,14 +318,14 @@ LsmwM_: "" is LsmwRa & LsmwM=0 { }
LsmwM_: "m" is LsmwRa & LsmwM=1 { LsmwRa = mult_addr; }
:lmw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is $(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00 & Lmw.regs
:lmw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Lmw.regs
{
mult_addr = LsmwRa;
build Lmw.regs;
build LsmwM_;
}
:smw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is $(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00 & Smw.regs
:smw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Smw.regs
{
mult_addr = LsmwRa;
build Smw.regs;
@@ -551,8 +561,6 @@ SetendBE: "b" is Toggle=1 { setend(1:1); }
### 32-bit Baseline V2 instructions ###
@if defined(BASELINE_V2)
### ALU Instructions ###
:addi.gp is $(I32) & $(SBGP) & Rt & GpSub1=0b1 & Imm19s { Rt = gp + Imm19s; }
@@ -563,25 +571,16 @@ SetendBE: "b" is Toggle=1 { setend(1:1); }
:mulr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101001 & Rtl & Rth
{
res:8 = zext(Ra) * zext(Rb);
@if ENDIAN == "big"
Rtl = res(4);
Rth = res:4;
@else
Rtl = res:4;
Rth = res(4);
@endif
Rtl = res[32,32];
Rth = res[0,32];
}
:mulsr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101000 & Rtl & Rth
{
res:8 = sext(Ra) * sext(Rb);
@if ENDIAN == "big"
Rtl = res(4);
Rth = res:4;
@else
Rtl = res:4;
Rth = res(4);
@endif
Rtl = res[32,32];
Rth = res[0,32];
}
:maddr32 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b110011 { Rt = Rt + (Ra * Rb); }
@@ -605,16 +604,15 @@ GpWordAddress: [+ off] is Imm17s [ off = Imm17s << 2; ] { addr:4 = gp + off; exp
:shi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b10 & GpHalfAddress { local tmp = Rt; *GpHalfAddress = tmp:2; }
:swi.gp Rt, GpWordAddress is $(I32) & $(HWGP) & Rt & GpSub3=0b111 & GpWordAddress { *GpWordAddress = Rt; }
# TODO : same as lmw/smw, this is horrible
:lmwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is $(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01 & Lmwa.regs
:lmwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Lmwa.regs
{
mult_addr = LsmwRa;
build Lmwa.regs;
build LsmwM_;
}
:smwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is $(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01 & Smwa.regs
:smwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Smwa.regs
{
mult_addr = LsmwRa;
build Smwa.regs;
@@ -624,14 +622,10 @@ GpWordAddress: [+ off] is Imm17s [ off = Imm17s << 2; ] { addr:4 = gp + off; exp
:lbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00100000 { local tmp:1 = *AddrRaRbsv; Rt = zext(tmp); }
:sbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00101000 { local tmp = Rt; *AddrRaRbsv = tmp:1; }
@endif
### 32-bit Baseline V3 instructions ###
@if defined(BASELINE_V3)
### ALU Instructions with Shift Operation (v3) ###
:add_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00000 { Rt = Ra + (Rb << sh); }
@@ -664,15 +658,11 @@ Rel8: addr is Imm8s [ addr = inst_start + (Imm8s << 1); ] { export *:4 addr; }
# TODO: Add CCTL L1D_WBALL, level
@endif
### 32-bit ISA extension ###
### ALU Instruction (Performance) ###
@if defined(PERFORMANCE_V1)
:abs Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Rb=0 & $(ALU2Z) & Sub6=0b000011
{
@@ -767,12 +757,9 @@ Rel8: addr is Imm8s [ addr = inst_start + (Imm8s << 1); ] { export *:4 addr; }
Rt = countTmp;
}
@endif
### Performance Extension V2 ###
@if defined(PERFORMANCE_V2)
# TODO : arithmetic functions: bs*
:bse is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b001100 unimpl
@@ -806,10 +793,105 @@ macro add_abs_diff(dst, src1, src2, shift)
add_abs_diff(Rt, Ra, Rb, 24);
}
# 32-bit String Extension
:ffb Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001110 {
match:1 = Rb[0,8];
m1:1 = (Ra[0,8] == match);
m2:1 = (Ra[8,8] == match);
m3:1 = (Ra[16,8] == match);
m4:1 = (Ra[24,8] == match);
Rt = -4;
if (m1) goto inst_next;
Rt = -3;
if (m2) goto inst_next;
Rt = -2;
if (m3) goto inst_next;
Rt = -1;
if (m4) goto inst_next;
Rt = 0;
# choosery method
# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
}
:ffbi Rt, Ra, Imm8u is $(I32) & $(ALU_2) & Rt & Ra & Imm8u & Sub7=0b1001110 {
match:1 = Imm8u;
m1:1 = (Ra[0,8] == match);
m2:1 = (Ra[8,8] == match);
m3:1 = (Ra[16,8] == match);
m4:1 = (Ra[24,8] == match);
Rt = -4;
if (m1) goto inst_next;
Rt = -3;
if (m2) goto inst_next;
Rt = -2;
if (m3) goto inst_next;
Rt = -1;
if (m4) goto inst_next;
Rt = 0;
}
:ffmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001111 {
match:1 = Rb[0,8];
m1:1 = (Ra[0,8] != Rb[0,8]);
m2:1 = (Ra[8,8] != Rb[8,8]);
m3:1 = (Ra[16,8] != Rb[16,8]);
m4:1 = (Ra[24,8] != Rb[24,8]);
@if ENDIAN == "little"
Rt = -4;
if (m1) goto inst_next;
Rt = -3;
if (m2) goto inst_next;
Rt = -2;
if (m3) goto inst_next;
Rt = -1;
if (m4) goto inst_next;
Rt = 0;
# choosery method
# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
@else
Rt = -4;
if (m4) goto inst_next;
Rt = -3;
if (m3) goto inst_next;
Rt = -2;
if (m2) goto inst_next;
Rt = -1;
if (m1) goto inst_next;
Rt = 0;
@endif
}
:flmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b1001111 {
match:1 = Rb[0,8];
m1:1 = (Ra[0,8] != Rb[0,8]);
m2:1 = (Ra[8,8] != Rb[8,8]);
m3:1 = (Ra[16,8] != Rb[16,8]);
m4:1 = (Ra[24,8] != Rb[24,8]);
@if ENDIAN == "little"
Rt = -1;
if (m4) goto inst_next;
Rt = -2;
if (m3) goto inst_next;
Rt = -3;
if (m2) goto inst_next;
Rt = -4;
if (m1) goto inst_next;
Rt = 0;
# choosery method
# rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1);
@else
Rt = -1;
if (m1) goto inst_next;
Rt = -2;
if (m2) goto inst_next;
Rt = -3;
if (m3) goto inst_next;
Rt = -4;
if (m4) goto inst_next;
Rt = 0;
@endif
}
########### 16b ############
@@ -832,8 +914,13 @@ define token instr16(16)
rt3b = (8, 10)
ra3 = (3, 5)
rb3 = (0, 2)
bit5 = (5,5)
bit6 = (6,6)
bit7 = (7,7)
bit8 = (8,8)
imm3u = (0, 2)
imm3ub = (3, 5)
imm4u = (5, 8)
imm5u = (0, 4)
imm5s = (0, 4) signed
imm6u = (0, 5)
@@ -978,14 +1065,13 @@ rel8: addr is imm8s [ addr = inst_start + (imm8s << 1); ] { export *:4 addr; }
### Misc Instruction ###
:break16 swid9 is $(I16) & opc6=0b110101 & swid9 { break(swid9:4); }
:nop16 is $(I16) & opc6=0b001001 & rt4=0b0000 & imm5u=0b00000 { }
# V3 doesn't allow break16 with SWID greater than 31
:break16 swid9 is $(I16) & opc6=0b110101 & imm4u=0 & swid9 { break(swid9:4); }
:nop16 is $(I16) & opc6=0b001001 & rt4=0 & imm5u=0 { }
### ALU Instructions (V2) ###
@if defined(BASELINE_V2)
:addi10.sp imm10s is $(I16) & opc5=0b11011 & imm10s { sp = sp + imm10s; }
@@ -996,14 +1082,10 @@ sp_rel7w: [+ rel7w] is rel7w { addr:4 = sp + rel7w; export addr; }
:lwi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=0 & sp_rel7w { rt3b = *sp_rel7w; }
:swi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=1 & sp_rel7w { *sp_rel7w = rt3b; }
@endif
### 16-bit Baseline V3 instructions ###
@if defined(BASELINE_V3)
### ALU Instructions (V3 16-bit) ###
imm6u_: imm8 is imm6u [ imm8 = imm6u << 2; ] { export *[const]:4 imm8; }
@@ -1056,11 +1138,11 @@ push25_re: re2 is re2 & re2=3 { push25_s8(); }
<end>
}
macro pop25_special() { Lmwbi(fp); Lmwbi(gp); Lmwbi(lp); }
macro pop25_s0() { Lmwbi(s0); }
macro pop25_s2() { pop25_s0(); Lmwbi(s1); Lmwbi(s2); }
macro pop25_s4() { pop25_s2(); Lmwbi(s3); Lmwbi(s4); }
macro pop25_s8() { pop25_s4(); Lmwbi(s5); Lmwbi(s6); Lmwbi(s7); Lmwbi(s8); }
macro pop25_special() { LmwOp(fp); LmwOp(gp); LmwOp(lp); }
macro pop25_s0() { LmwOp(s0); }
macro pop25_s2() { pop25_s0(); LmwOp(s1); LmwOp(s2); }
macro pop25_s4() { pop25_s2(); LmwOp(s3); LmwOp(s4); }
macro pop25_s8() { pop25_s4(); LmwOp(s5); LmwOp(s6); LmwOp(s7); LmwOp(s8); }
pop25_re: re2 is re2 & re2=0 { pop25_s0(); }
pop25_re: re2 is re2 & re2=1 { pop25_s2(); }
@@ -1076,6 +1158,16 @@ pop25_re: re2 is re2 & re2=3 { pop25_s8(); }
}
@endif
# EX9.IT
imm9u_: imm9 is imm5u & imm4u [ imm9 = (imm4u << 5) | imm5u; ] { export *[const]:4 imm9; }
define pcodeop ex9;
# TODO: Depending on the value of ITB.HW the address is either set by hardware or set by ITB.Addr
:ex9.it imm9u_ is $(I16) & opc6=0b110101 & (bit5=1 | bit6=1 | bit7=1 | bit8=1) & imm9u_ {
ex9(imm9u_);
}
:ex9.it imm5u is $(I16) & opc10=0b1011101010 & imm5u {
ex9(imm5u:4);
}

4
Ghidra/Processors/NDS32/data/languages/nds32be.slaspec
View File

@@ -1,7 +1,3 @@
@define BASELINE_V2 "yes"
@define BASELINE_V3 "yes"
@define PERFORMANCE_V1 "yes"
@define PERFORMANCE_V2 "yes"
@define ENDIAN "big"
@include "nds32.sinc"

4
Ghidra/Processors/NDS32/data/languages/nds32le.slaspec
View File

@@ -1,7 +1,3 @@
@define BASELINE_V2 "yes"
@define BASELINE_V3 "yes"
@define PERFORMANCE_V1 "yes"
@define PERFORMANCE_V2 "yes"
@define ENDIAN "little"
@include "nds32.sinc"

6
Ghidra/Processors/NDS32/data/sleighArgs.txt
View File

@@ -1,6 +0,0 @@
# Add sleigh compiler options to this file (one per line) which will
# be used when compiling each language within this module.
# All options should start with a '-' character.
#
# IMPORTANT: The -a option should NOT be specified
#

53
Ghidra/Processors/NDS32/src/main/java/ghidra/app/plugin/core/analysis/NDS32Analyzer.java
View File

@@ -1,3 +1,18 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.plugin.core.analysis;
import java.math.BigInteger;
@@ -29,16 +44,12 @@ import ghidra.util.task.TaskMonitor;
public class NDS32Analyzer extends ConstantPropagationAnalyzer {
private final static String PROCESSOR_NAME = "NDS32";
private static final String SWITCH_OPTION_NAME = "Switch Table Recovery";
private static final String SWITCH_OPTION_DESCRIPTION = "Turn on to recover switch tables (not implemented yet !)";
private static final boolean SWITCH_OPTION_DEFAULT_VALUE = false;
private static final String RECOVER_GP_OPTION_NAME = "Recover global GP register writes";
private static final String RECOVER_GP_OPTION_DESCRIPTION = "Reads the global GP value from the symbol _SDA_BASE_";
private static final boolean RECOVER_GP_OPTION_DEFAULT_VALUE = true;
private boolean recoverSwitchTables = SWITCH_OPTION_DEFAULT_VALUE;
//private boolean recoverSwitchTables = SWITCH_OPTION_DEFAULT_VALUE;
private boolean recoverGp = RECOVER_GP_OPTION_DEFAULT_VALUE;
private Address gpAssumptionValue = null;
@@ -67,10 +78,6 @@ public class NDS32Analyzer extends ConstantPropagationAnalyzer {
public void optionsChanged(Options options, Program program) {
super.optionsChanged(options, program);
options.registerOption(SWITCH_OPTION_NAME, recoverSwitchTables, null,
SWITCH_OPTION_DESCRIPTION);
recoverSwitchTables = options.getBoolean(SWITCH_OPTION_NAME, recoverSwitchTables);
options.registerOption(RECOVER_GP_OPTION_NAME, recoverGp, null,
RECOVER_GP_OPTION_DESCRIPTION);
recoverGp = options.getBoolean(RECOVER_GP_OPTION_NAME, recoverGp);
@@ -88,7 +95,9 @@ public class NDS32Analyzer extends ConstantPropagationAnalyzer {
/**
* Check for a global GP register symbol or discovered symbol
* @param program
* @param set
* @param monitor
*/
private void checkForGlobalGP(Program program, AddressSetView set, TaskMonitor monitor) {
if (!recoverGp) {
@@ -139,7 +148,7 @@ public class NDS32Analyzer extends ConstantPropagationAnalyzer {
}
}
ContextEvaluator eval = new ConstantPropagationContextEvaluator(trustWriteMemOption) {
ContextEvaluator eval = new ConstantPropagationContextEvaluator(monitor, trustWriteMemOption) {
@Override
public boolean evaluateDestination(VarnodeContext context, Instruction instruction) {
FlowType flowtype = instruction.getFlowType();
@@ -147,13 +156,6 @@ public class NDS32Analyzer extends ConstantPropagationAnalyzer {
return false;
}
if (recoverSwitchTables) {
String mnemonic = instruction.getMnemonicString();
if (mnemonic.equals("jr")) {
fixJumpTable(program, instruction, monitor);
}
}
return false;
}
};
@@ -167,21 +169,4 @@ public class NDS32Analyzer extends ConstantPropagationAnalyzer {
return resultSet;
}
/**
* @param program
* @param startInstr
* @param monitor
*/
private void fixJumpTable(Program program, Instruction startInstr, TaskMonitor monitor) {
/* TODO: implement switch recovery ?
* We are looking for tables like this :
*
* slti45 a0,0x4 <- table size
* beqzs8 LAB_005159ea <- default jump
* sethi ta, 0x515
* ori ta, ta, 0x9a0
* lw a0, [ta + (a0 << 0x2)] <- ref to table
* jr a0 <- table jump
*/
}
}

74
Ghidra/Processors/NDS32/src/main/java/ghidra/app/util/bin/format/elf/relocation/NDS32_ElfRelocationConstants.java
View File

@@ -1,74 +0,0 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
public class NDS32_ElfRelocationConstants {
public static final int R_NDS32_NONE = 0;
public static final int R_NDS32_16_RELA = 19;
public static final int R_NDS32_32_RELA = 20;
public static final int R_NDS32_9_PCREL_RELA = 22;
public static final int R_NDS32_15_PCREL_RELA = 23;
public static final int R_NDS32_17_PCREL_RELA = 24;
public static final int R_NDS32_25_PCREL_RELA = 25;
public static final int R_NDS32_HI20_RELA = 26;
public static final int R_NDS32_LO12S3_RELA = 27;
public static final int R_NDS32_LO12S2_RELA = 28;
public static final int R_NDS32_LO12S1_RELA = 29;
public static final int R_NDS32_LO12S0_RELA = 30;
public static final int R_NDS32_SDA15S3_RELA = 31;
public static final int R_NDS32_SDA15S2_RELA = 32;
public static final int R_NDS32_SDA15S1_RELA = 33;
public static final int R_NDS32_SDA15S0_RELA = 34;
public static final int R_NDS32_GOT20 = 37;
public static final int R_NDS32_25_PLTREL = 38;
public static final int R_NDS32_COPY = 39;
public static final int R_NDS32_GLOB_DAT = 40;
public static final int R_NDS32_JMP_SLOT = 41;
public static final int R_NDS32_RELATIVE = 42;
public static final int R_NDS32_GOTOFF = 43;
public static final int R_NDS32_GOTPC20 = 44;
public static final int R_NDS32_GOT_HI20 = 45;
public static final int R_NDS32_GOT_LO12 = 46;
public static final int R_NDS32_GOTPC_HI20 = 47;
public static final int R_NDS32_GOTPC_LO12 = 48;
public static final int R_NDS32_GOTOFF_HI20 = 49;
public static final int R_NDS32_GOTOFF_LO12 = 50;
public static final int R_NDS32_INSN16 = 51;
public static final int R_NDS32_LABEL = 52;
public static final int R_NDS32_LONGCALL1 = 53;
public static final int R_NDS32_LONGCALL2 = 54;
public static final int R_NDS32_LONGCALL3 = 55;
public static final int R_NDS32_LONGJUMP1 = 56;
public static final int R_NDS32_LONGJUMP2 = 57;
public static final int R_NDS32_LONGJUMP3 = 58;
public static final int R_NDS32_LOADSTORE = 59;
public static final int R_NDS32_9_FIXED_RELA = 60;
public static final int R_NDS32_15_FIXED_RELA = 61;
public static final int R_NDS32_17_FIXED_RELA = 62;
public static final int R_NDS32_25_FIXED_RELA = 63;
public static final int R_NDS32_PLTREL_HI20 = 64;
public static final int R_NDS32_PLTREL_LO12 = 65;
public static final int R_NDS32_PLT_GOTREL_HI20 = 66;
public static final int R_NDS32_PLT_GOTREL_LO12 = 67;
public static final int R_NDS32_LO12S0_ORI_RELA = 72;
public static final int R_NDS32_DWARF2_OP1_RELA = 77;
public static final int R_NDS32_DWARF2_OP2_RELA = 78;
public static final int R_NDS32_DWARF2_LEB_RELA = 79;
public static final int R_NDS32_WORD_9_PCREL_RELA = 94;
public static final int R_NDS32_LONGCALL4 = 107;
public static final int R_NDS32_RELA_NOP_MIX = 192;
public static final int R_NDS32_RELA_NOP_MAX = 255;
}

77
Ghidra/Processors/NDS32/src/main/java/ghidra/app/util/bin/format/elf/relocation/NDS32_ElfRelocationHandler.java
View File

@@ -4,9 +4,9 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -16,21 +16,22 @@
package ghidra.app.util.bin.format.elf.relocation;
import java.util.Map;
import ghidra.app.util.bin.format.elf.ElfConstants;
import ghidra.app.util.bin.format.elf.ElfHeader;
import ghidra.app.util.bin.format.elf.ElfLoadHelper;
import ghidra.app.util.bin.format.elf.ElfRelocation;
import ghidra.app.util.bin.format.elf.ElfRelocationTable;
import ghidra.app.util.bin.format.elf.ElfSymbol;
import ghidra.app.util.bin.format.elf.*;
import ghidra.app.util.importer.MessageLog;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressOutOfBoundsException;
import ghidra.program.model.listing.Program;
import ghidra.program.model.mem.Memory;
import ghidra.program.model.mem.MemoryAccessException;
import ghidra.util.exception.NotFoundException;
import ghidra.program.model.reloc.RelocationResult;
import ghidra.program.model.reloc.Relocation.Status;
public class NDS32_ElfRelocationHandler extends AbstractElfRelocationHandler<NDS32_ElfRelocationType, ElfRelocationContext<?>> {
public NDS32_ElfRelocationHandler() {
super(NDS32_ElfRelocationType.class);
}
public class NDS32_ElfRelocationHandler extends ElfRelocationHandler {
@Override
public boolean canRelocate(ElfHeader elf) {
@@ -38,35 +39,26 @@ public class NDS32_ElfRelocationHandler extends ElfRelocationHandler {
}
@Override
public NDS32_ElfRelocationContext createRelocationContext(ElfLoadHelper loadHelper,
ElfRelocationTable relocationTable, Map<ElfSymbol, Address> symbolMap) {
return new NDS32_ElfRelocationContext(this, loadHelper, relocationTable, symbolMap);
public int getRelrRelocationType() {
return NDS32_ElfRelocationType.R_NDS32_RELATIVE.typeId;
}
@Override
public void relocate(ElfRelocationContext elfRelocationContext, ElfRelocation relocation, Address relocationAddress)
throws MemoryAccessException, NotFoundException {
ElfHeader elf = elfRelocationContext.getElfHeader();
if (elf.e_machine() != ElfConstants.EM_NDS32) {
return;
}
protected RelocationResult relocate(ElfRelocationContext<?> elfRelocationContext,
ElfRelocation relocation, NDS32_ElfRelocationType type, Address relocationAddress,
ElfSymbol sym, Address symbolAddr, long symbolValue, String symbolName)
throws MemoryAccessException {
if (!elf.is32Bit()) {
return;
}
NDS32_ElfRelocationContext nds32RelocationContext =
(NDS32_ElfRelocationContext) elfRelocationContext;
ElfRelocationContext<?> nds32RelocationContext = elfRelocationContext;
int type = relocation.getType();
int symbolIndex = relocation.getSymbolIndex();
doRelocate(nds32RelocationContext, type, symbolIndex, relocation, relocationAddress);
return doRelocate(nds32RelocationContext, type, symbolIndex, relocation, relocationAddress);
}
private void doRelocate(NDS32_ElfRelocationContext nds32RelocationContext, int relocType,
private RelocationResult doRelocate(ElfRelocationContext<?> nds32RelocationContext, NDS32_ElfRelocationType type,
int symbolIndex, ElfRelocation relocation, Address relocationAddress)
throws MemoryAccessException, NotFoundException, AddressOutOfBoundsException {
throws MemoryAccessException {
Program program = nds32RelocationContext.getProgram();
Memory memory = program.getMemory();
MessageLog log = nds32RelocationContext.getLog();
@@ -84,28 +76,21 @@ public class NDS32_ElfRelocationHandler extends ElfRelocationHandler {
int value = 0;
int newValue = 0;
switch(relocType) {
case NDS32_ElfRelocationConstants.R_NDS32_HI20_RELA:
int byteLength = 4;
switch(type) {
case R_NDS32_HI20_RELA:
value = (int)(symbolValue + addend);
newValue = (oldValue & 0xfff00000) | (value >> 12);
memory.setInt(relocationAddress, newValue, true);
break;
case NDS32_ElfRelocationConstants.R_NDS32_LO12S0_RELA:
return new RelocationResult(Status.APPLIED, byteLength);
case R_NDS32_LO12S0_RELA:
value = (int)(symbolValue + addend);
newValue = (oldValue & 0xfffff000) | (value & 0xfff);
memory.setInt(relocationAddress, newValue, true);
break;
return new RelocationResult(Status.APPLIED, byteLength);
default:
markAsUnhandled(program, relocationAddress, relocType, symbolIndex, symbolName, log);
}
}
private static class NDS32_ElfRelocationContext extends ElfRelocationContext {
protected NDS32_ElfRelocationContext(ElfRelocationHandler handler, ElfLoadHelper loadHelper,
ElfRelocationTable relocationTable, Map<ElfSymbol, Address> symbolMap) {
super(handler, loadHelper, relocationTable, symbolMap);
return RelocationResult.UNSUPPORTED;
}
}
}

195
Ghidra/Processors/NDS32/src/main/java/ghidra/app/util/bin/format/elf/relocation/NDS32_ElfRelocationType.java Normal file
View File

@@ -0,0 +1,195 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.app.util.bin.format.elf.relocation;
public enum NDS32_ElfRelocationType implements ElfRelocationType {
/* REL relocations. */
R_NDS32_16(1),
R_NDS32_32(2),
R_NDS32_20(3),
R_NDS32_9_PCREL(4),
R_NDS32_15_PCREL(5),
R_NDS32_17_PCREL(6),
R_NDS32_25_PCREL(7),
R_NDS32_HI20(8),
R_NDS32_LO12S3(9),
R_NDS32_LO12S2(10),
R_NDS32_LO12S1(11),
R_NDS32_LO12S0(12),
R_NDS32_SDA15S3(13),
R_NDS32_SDA15S2(14),
R_NDS32_SDA15S1(15),
R_NDS32_SDA15S0(16),
R_NDS32_GNU_VTINHERIT(17),
R_NDS32_GNU_VTENTRY(18),
/* RELA relocations. */
R_NDS32_16_RELA(19),
R_NDS32_32_RELA(20),
R_NDS32_20_RELA(21),
R_NDS32_9_PCREL_RELA(22),
R_NDS32_15_PCREL_RELA(23),
R_NDS32_17_PCREL_RELA(24),
R_NDS32_25_PCREL_RELA(25),
R_NDS32_HI20_RELA(26),
R_NDS32_LO12S3_RELA(27),
R_NDS32_LO12S2_RELA(28),
R_NDS32_LO12S1_RELA(29),
R_NDS32_LO12S0_RELA(30),
R_NDS32_SDA15S3_RELA(31),
R_NDS32_SDA15S2_RELA(32),
R_NDS32_SDA15S1_RELA(33),
R_NDS32_SDA15S0_RELA(34),
R_NDS32_RELA_GNU_VTINHERIT(35),
R_NDS32_RELA_GNU_VTENTRY(36),
/* GOT and PLT. */
R_NDS32_GOT20(37),
R_NDS32_25_PLTREL(38),
R_NDS32_COPY(39),
R_NDS32_GLOB_DAT(40),
R_NDS32_JMP_SLOT(41),
R_NDS32_RELATIVE(42),
R_NDS32_GOTOFF(43),
R_NDS32_GOTPC20(44),
R_NDS32_GOT_HI20(45),
R_NDS32_GOT_LO12(46),
R_NDS32_GOTPC_HI20(47),
R_NDS32_GOTPC_LO12(48),
R_NDS32_GOTOFF_HI20(49),
R_NDS32_GOTOFF_LO12(50),
/* 32_to_16 relaxations. */
R_NDS32_INSN16(51),
/* Alignment tag. */
R_NDS32_LABEL(52),
R_NDS32_LONGCALL1(53), /* This is obsoleted. */
R_NDS32_LONGCALL2(54), /* This is obsoleted. */
R_NDS32_LONGCALL3(55), /* This is obsoleted. */
R_NDS32_LONGJUMP1(56), /* This is obsoleted. */
R_NDS32_LONGJUMP2(57), /* This is obsoleted. */
R_NDS32_LONGJUMP3(58), /* This is obsoleted. */
R_NDS32_LOADSTORE(59), /* This is obsoleted. */
R_NDS32_9_FIXED_RELA(60),
R_NDS32_15_FIXED_RELA(61),
R_NDS32_17_FIXED_RELA(62),
R_NDS32_25_FIXED_RELA(63),
R_NDS32_PLTREL_HI20(64), /* This is obsoleted. */
R_NDS32_PLTREL_LO12(65), /* This is obsoleted. */
R_NDS32_PLT_GOTREL_HI20(66),
R_NDS32_PLT_GOTREL_LO12(67),
R_NDS32_SDA12S2_DP_RELA(68),
R_NDS32_SDA12S2_SP_RELA(69),
R_NDS32_LO12S2_DP_RELA(70),
R_NDS32_LO12S2_SP_RELA(71),
R_NDS32_LO12S0_ORI_RELA(72),
R_NDS32_SDA16S3_RELA(73),
R_NDS32_SDA17S2_RELA(74),
R_NDS32_SDA18S1_RELA(75),
R_NDS32_SDA19S0_RELA(76),
R_NDS32_DWARF2_OP1_RELA(77), /* This is obsoleted. */
R_NDS32_DWARF2_OP2_RELA(78), /* This is obsoleted. */
R_NDS32_DWARF2_LEB_RELA(79), /* This is obsoleted. */
R_NDS32_UPDATE_TA_RELA(80), /* This is obsoleted. */
R_NDS32_9_PLTREL(81),
R_NDS32_PLT_GOTREL_LO20(82),
R_NDS32_PLT_GOTREL_LO15(83),
R_NDS32_PLT_GOTREL_LO19(84),
R_NDS32_GOT_LO15(85),
R_NDS32_GOT_LO19(86),
R_NDS32_GOTOFF_LO15(87),
R_NDS32_GOTOFF_LO19(88),
R_NDS32_GOT15S2_RELA(89),
R_NDS32_GOT17S2_RELA(90),
R_NDS32_5_RELA(91),
R_NDS32_10_UPCREL_RELA(92), /* This is obsoleted. */
R_NDS32_SDA_FP7U2_RELA(93),
R_NDS32_WORD_9_PCREL_RELA(94),
R_NDS32_25_ABS_RELA(95),
R_NDS32_17IFC_PCREL_RELA(96), /* This is obsoleted. */
R_NDS32_10IFCU_PCREL_RELA(97), /* This is obsoleted. */
/* TLS support. */
R_NDS32_TLS_LE_HI20(98),
R_NDS32_TLS_LE_LO12(99),
R_NDS32_TLS_IE_HI20(100),
R_NDS32_TLS_IE_LO12S2(101),
R_NDS32_TLS_TPOFF(102),
R_NDS32_TLS_LE_20(103),
R_NDS32_TLS_LE_15S0(104),
R_NDS32_TLS_LE_15S1(105),
R_NDS32_TLS_LE_15S2(106),
R_NDS32_LONGCALL4(107),
R_NDS32_LONGCALL5(108),
R_NDS32_LONGCALL6(109),
R_NDS32_LONGJUMP4(110),
R_NDS32_LONGJUMP5(111),
R_NDS32_LONGJUMP6(112),
R_NDS32_LONGJUMP7(113),
/* Reserved numbers: 114. */
/* TLS support */
R_NDS32_TLS_IE_LO12(115),
R_NDS32_TLS_IEGP_HI20(116),
R_NDS32_TLS_IEGP_LO12(117),
R_NDS32_TLS_IEGP_LO12S2(118),
R_NDS32_TLS_DESC(119),
R_NDS32_TLS_DESC_HI20(120),
R_NDS32_TLS_DESC_LO12(121),
R_NDS32_TLS_DESC_20(122),
R_NDS32_TLS_DESC_SDA17S2(123),
/* Reserved numbers: 124-191. */
/* These used only for relaxations */
R_NDS32_RELAX_ENTRY(192),
R_NDS32_GOT_SUFF(193),
R_NDS32_GOTOFF_SUFF(194),
R_NDS32_PLT_GOT_SUFF(195),
R_NDS32_MULCALL_SUFF(196), /* This is obsoleted. */
R_NDS32_PTR(197),
R_NDS32_PTR_COUNT(198),
R_NDS32_PTR_RESOLVED(199),
R_NDS32_PLTBLOCK(200), /* This is obsoleted. */
R_NDS32_RELAX_REGION_BEGIN(201),
R_NDS32_RELAX_REGION_END(202),
R_NDS32_MINUEND(203),
R_NDS32_SUBTRAHEND(204),
R_NDS32_DIFF8(205),
R_NDS32_DIFF16(206),
R_NDS32_DIFF32(207),
R_NDS32_DIFF_ULEB128(208),
R_NDS32_DATA(209),
R_NDS32_TRAN(210),
/* TLS support */
R_NDS32_TLS_LE_ADD(211),
R_NDS32_TLS_LE_LS(212),
R_NDS32_EMPTY(213),
R_NDS32_TLS_DESC_ADD(214),
R_NDS32_TLS_DESC_FUNC(215),
R_NDS32_TLS_DESC_CALL(216),
R_NDS32_TLS_DESC_MEM(217),
R_NDS32_RELAX_REMOVE(218),
R_NDS32_RELAX_GROUP(219),
R_NDS32_TLS_IEGP_LW(220),
R_NDS32_LSI(221),
R_NDS32_RELA_NOP_MAX(255);
public final int typeId;
private NDS32_ElfRelocationType(int typeId) {
this.typeId = typeId;
}
@Override
public int typeId() {
return typeId;
}
}

41
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_BE_O0_EmulatorTest.java Normal file
View File

@@ -0,0 +1,41 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class NDS32_BE_O0_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "NDS32:BE:32:default";
private static final String COMPILER_SPEC_ID = "default";
private static final String[] REG_DUMP_SET = new String[] {};
public NDS32_BE_O0_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "NDS32BE_GCC_O0";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(NDS32_BE_O0_EmulatorTest.class);
}
}

41
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_BE_O3_EmulatorTest.java Normal file
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@@ -0,0 +1,41 @@
/* ###
* IP: GHIDRA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ghidra.test.processors;
import ghidra.test.processors.support.ProcessorEmulatorTestAdapter;
import junit.framework.Test;
public class NDS32_BE_O3_EmulatorTest extends ProcessorEmulatorTestAdapter {
private static final String LANGUAGE_ID = "NDS32:BE:32:default";
private static final String COMPILER_SPEC_ID = "default";
private static final String[] REG_DUMP_SET = new String[] {};
public NDS32_BE_O3_EmulatorTest(String name) throws Exception {
super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET);
}
@Override
protected String getProcessorDesignator() {
return "NDS32BE_GCC_O3";
}
public static Test suite() {
return ProcessorEmulatorTestAdapter.buildEmulatorTestSuite(NDS32_BE_O3_EmulatorTest.class);
}
}

4
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_LE_O0_EmulatorTest.java
View File

@@ -4,9 +4,9 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

4
Ghidra/Processors/NDS32/src/test.processors/java/ghidra/test/processors/NDS32_LE_O3_EmulatorTest.java
View File

@@ -4,9 +4,9 @@
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*
* http://www.apache.org/licenses/LICENSE-2.0
*
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.