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Fix riscv asm parser.

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chriseth
2023-04-05 16:29:51 +02:00
parent 9d9dc52808
commit 135eda01d4
1 changed files with 1 additions and 1 deletions
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src/riscv/riscv_asm.lalrpop
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@@ -69,7 +69,7 @@ Register: Register = {
r"s[2-9]" => Register(16 + <>[1..].parse::<u8>().unwrap()),
r"s1[0-1]" => Register(16 + <>[1..].parse::<u8>().unwrap()),
r"t[0-2]" => Register(5 + <>[1..].parse::<u8>().unwrap()),
r"t[3-6]" => Register(28 + <>[1..].parse::<u8>().unwrap()),
r"t[3-6]" => Register(25 + <>[1..].parse::<u8>().unwrap()),
}
OffsetRegister: Argument = {