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Author SHA1 Message Date
Nicolas Sarlin
b4066df77f chore(ci): run cargo audit 2025-09-16 12:03:32 +02:00
Pedro Alves
6b94872a00 fix(gpu): add an assert to be sure the carry part has correct size in expand 2025-09-15 12:57:11 -03:00
Nicolas Sarlin
d88caff6dd fix(ci): fix serde root crate in tfhe-lints 2025-09-15 15:18:58 +02:00
Thomas Montaigu
75a265f93b fix(integer): fix aggregate_one_hot_vector 
`aggregate_one_hot_vector`` was modified when the KVStore was
added to support inputs where information in the blocks was not packed.
And to detect if blocks where packed it was relying on the degree value.

However, the inputs may come from LUTs that had precise degree, and
could lead to believe the inputs were not packed.

To fix this we split in 2 fn:
* aggregate_one_hot_vector
* aggregate_and_unpack_one_hot_vector

And use the correct one when we know if the inputs are packed
 2025-09-15 10:27:24 +02:00
Nicolas Sarlin
bfbf638fed fix(zk): add a size check for the public key 2025-09-12 11:10:06 +02:00
David Testé
01651d6fb2 chore(ci): update lattice estimator version 2025-09-12 11:07:25 +02:00
Pedro Alves
b2624d1a76 chore(gpu): refactor the indexing logic for the LWE expand 2025-09-11 13:10:18 -03:00
tmontaigu
9fb7b56629 feat(integer): add KVStore 
The KVStore is a Hash Table, with homomorphic capabilities

The keys are meant to be clear integers, values are meant to be
Radix/SignedRadix

The ServerKey now has functions to be able to do operations that modify
an existing key,value pair using an encrypted key.
 2025-09-11 13:55:42 +02:00
Arthur Meyre
24feeb8609 chore(ci): avoid backward compat workflow cancel 
- re-use formulas from the integer workflow which also executes on main
 2025-09-11 10:43:23 +02:00
pgardratzama
757c2fc828 chore(hpu): make hpu integer bench fast by default 2025-09-10 22:24:31 +02:00
pgardratzama
4ff0d6cac2 feat(hpu): integer bench update (adds mod, div -> div_mod), erc20_simd simd batch size read from iop prototype 2025-09-10 22:24:31 +02:00
pgardratzama
1530f52c79 feat(hpu): adds support of ERC20 SIMD in hpu ERC20 bench 2025-09-10 22:24:31 +02:00
David Testé
9918dacd6a chore(ci): change workflow jobs naming convention 
The term "bpr" means Branch Protection Rule. It helps one to
identify any job that must pass before being able to merge to the
base branch.
 2025-09-10 15:36:45 +02:00
tmontaigu
2b503acf18 chore(shortint): add consts for MetaParameters 2025-09-10 15:15:06 +02:00
tmontaigu
57cc326a64 feat(shortint): MetaParameters struct 
There are a lot of different parameter types in tfhe-rs, related to
different but linked features. Thus when some PBS parameters are
selected, compatible compression parameters must be selected from the
possible parameters.

To make things easier, the MetaParameters struct is added, this stores
in one place parameters that can be used together.
 2025-09-10 15:15:06 +02:00
Arthur Meyre
84eb8aeb63 test(shortint): add BR + DP + KS + MS noise checks 
- sanity check, noise measurement and pfail are done
 2025-09-10 14:50:28 +02:00
Arthur Meyre
f09acfa581 chore: rename test files to remove redundant name fragment 2025-09-10 14:50:28 +02:00
Arthur Meyre
8335a6b6b5 chore(ci): run backward compat tests on merge to main 
- this is to prime cache and check backward data on merge to main
 2025-09-10 14:49:50 +02:00
tmontaigu
f80fd157ae fix(c-api): add missing safe_deser for ServerKey 2025-09-10 13:40:44 +02:00
Agnes Leroy
0ed97cfba8 chore(gpu): update sxm5 cost 2025-09-10 10:49:25 +02:00
Agnes Leroy
daee3f1850 chore(gpu): fix out of memory error in 4090 doc tests 2025-09-10 10:46:04 +02:00
tmontaigu
e8dc403ebd feat(integer): add flip operation 
Add the flip(condition: BooleanBlock, a: T, b: T) -> (T, T)
operation that homomorphically flip/swap two values if the
given encrypted boolean encrypts true
 2025-09-10 09:44:28 +02:00
Pedro Alves
63e5504c80 doc(gpu): add a section about noise squashing 2025-09-09 13:10:23 -03:00
Nicolas Sarlin
d664e4ada6 docs(safe_ser): document panics if max size is too large 2025-09-09 17:03:23 +02:00
Pedro Alves
c78cc2d2e9 chore(gpu): add a benchmark for 128-bit multi-bit noise squashing 
- Also, remove the lut indexes concept from the 128-bit multi-bit pbs. It's assumed not to exist by the entire backend (as it doesn't for classical PBS). So to keep it here would be a bit error prone.
 2025-09-09 07:51:35 -03:00
Pedro Alves
b566d78621 chore(gpu): improve the 128-bit multi-bit PBS core crypto test 2025-09-09 07:51:35 -03:00
Pedro Alves
7da6786d59 feat(gpu): add support to the 128-bit multi-bit PBS on HL's noise squashing 2025-09-09 07:51:35 -03:00
Himess
6edf6b9e26 chore: gate backward_compatibility_tests.rs with shortint feature 2025-09-09 09:35:59 +02:00
Himess
6fde90ad9c chore(clap): Replace use of deprecated attributes 
Replace deprecated #[clap(...)] attributes to #[arg]/#[command] and remove redundant use of value_parser
 2025-09-09 09:35:59 +02:00
Agnes Leroy
5d70ae4232 fix(gpu): add missing broadcast lut 2025-09-09 08:47:53 +02:00
David Testé
89b36ebca0 chore(bench): remove 2-bits size for full precision bench on gpu 
GPU backend cannot accept less than 2 blocks for integer
benchmarks. Since 2-bits precision benchmarks are run with
*_MESSAGE_2_CARRY_2_* parameters, it will create only one block of
ciphertext, thus making the benchmarks unsuitable for GPU backend.
 2025-09-08 12:24:24 +02:00
dependabot[bot]
bfc97385f4 chore(deps): bump actions/stale from 9.1.0 to 10.0.0 
Bumps [actions/stale](https://github.com/actions/stale) from 9.1.0 to 10.0.0.
- [Release notes](https://github.com/actions/stale/releases)
- [Changelog](https://github.com/actions/stale/blob/main/CHANGELOG.md)
- [Commits](5bef64f19d...3a9db7e6a4)

---
updated-dependencies:
- dependency-name: actions/stale
  dependency-version: 10.0.0
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>
 2025-09-08 10:39:56 +02:00
dependabot[bot]
7ab763abba chore(deps): bump codecov/codecov-action from 5.5.0 to 5.5.1 
Bumps [codecov/codecov-action](https://github.com/codecov/codecov-action) from 5.5.0 to 5.5.1.
- [Release notes](https://github.com/codecov/codecov-action/releases)
- [Changelog](https://github.com/codecov/codecov-action/blob/main/CHANGELOG.md)
- [Commits](fdcc847654...5a1091511a)

---
updated-dependencies:
- dependency-name: codecov/codecov-action
  dependency-version: 5.5.1
  dependency-type: direct:production
  update-type: version-update:semver-patch
...

Signed-off-by: dependabot[bot] <support@github.com>
 2025-09-08 10:39:41 +02:00
dependabot[bot]
a05db18ba3 chore(deps): bump actions/setup-node from 4.4.0 to 5.0.0 
Bumps [actions/setup-node](https://github.com/actions/setup-node) from 4.4.0 to 5.0.0.
- [Release notes](https://github.com/actions/setup-node/releases)
- [Commits](49933ea528...a0853c2454)

---
updated-dependencies:
- dependency-name: actions/setup-node
  dependency-version: 5.0.0
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>
 2025-09-08 10:39:27 +02:00
Guillermo Oyarzun
a3168eb1b5 feat(gpu): enable lut generation with preallocated buffers 2025-09-08 10:01:34 +02:00
Arthur Meyre
7fccb851d7 fix(csprng): harmonize behavior for UnixSeeder between small and big endian 
- bytes are generated in a given order and endianness needs to be given
to the buffer for the generated number to make sense
- Seed(pub u128) exposes that endianness so it needs to be consistent to
outside users
 2025-09-08 09:40:00 +02:00
Arthur Meyre
a78d5cc57b fix(csprng): make Seed interface less confusing wrt endianness 
- From a user perspective giving the same u128 seed e.g. 1u128 should have
the same behavior no matter the endianness of the system
 2025-09-08 09:40:00 +02:00
Nicolas Sarlin
9c0d078e1a chore(zk): bump tfhe-zk-pok to 0.7.2 tfhe-zk-pok-0.7.2 2025-09-08 09:30:34 +02:00
Nicolas Sarlin
6016755f9d fix(js): bump wasm bindgen version 2025-09-05 17:55:33 +02:00
Nicolas Sarlin
adcf9bc1f3 fix(zk): handle limit cases in the four_squares algorithm 2025-09-05 15:34:44 +02:00
pgardratzama
0a1651adf3 fix(hpu): update firmware in bitstream to allow SIMD operations 2025-09-05 10:42:36 +02:00
pgardratzama
11b540c456 chore(hpu): adds cost of hpu setups 2025-09-05 10:42:36 +02:00
pgardratzama
bd7df4a03b chore(hpu): enable hpu hlapi workflow and throughput bench in integer workflow 2025-09-05 10:42:36 +02:00
pgardratzama
2279d0deb8 chore(hpu): update hpu firmware (fix 2 bits operations issue) 2025-09-05 10:42:36 +02:00
pgardratzama
6fe24c6ab3 chore(hpu): update hpu integer bench scalar op names 2025-09-05 10:42:36 +02:00
pgardratzama
46c6adb0dc feat(hpu): create a new workflow to launch HLAPI benches for HPU 2025-09-05 10:42:36 +02:00
pgardratzama
c6aa1adbe7 chore(hpu): update benches to run new operations 2025-09-05 10:42:36 +02:00
Helder Campos
d3a867ecfe feat(hpu): High bandwidth HPU 2025-09-05 10:42:36 +02:00
Helder Campos
a83c92f28f feat(hpu): Soft Reset Support and fix some runtime registers 2025-09-05 10:42:36 +02:00
Helder Campos
3b48ef301e feat(hpu): Made two SIMD IOPs, ADD and ERC20. 2025-09-05 10:42:36 +02:00